120 mA, Current Sinking,
10-Bit, I2C® DAC
AD5821
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
120 mA current sink
Available in 3 × 3 array WLCSP package
2-wire (I2C-compatible) 1.8 V serial interface
10-bit resolution
Integrated current sense resistor
2.7 V to 5.5 V power supply
Guaranteed monotonic over all codes
Power-down to 0.5 μA typical
Internal reference
Ultralow noise preamplifier
Power-down function
Power-on reset
CONSUMER APPLICATIONS
Lens autofocus
Image stabilization
Optical zoom
Shutters
Iris/exposure
Neutral density (ND) filters
Lens covers
Camera phones
Digital still cameras
Camera modules
Digital video cameras/camcorders
Camera-enabled devices
Security cameras
Web/PC cameras
INDUSTRIAL APPLICATIONS
Heater controls
Fan controls
Cooler (Peltier) controls
Solenoid controls
Valve controls
Linear actuator controls
Light controls
Current loop controls
GENERAL DESCRIPTION
The AD5821 is a single 10-bit digital-to-analog converter with
120 mA output current sink capability. It features an internal
reference and operates from a single 2.7 V to 5.5 V supply.
The DAC is controlled via a 2-wire (I2C-compatible) serial
interface that operates at clock rates up to 400 kHz.
The AD5821 incorporates a power-on reset circuit that ensures
that the DAC output powers up to 0 V and remains there until
a valid write takes place. It has a power-down feature that reduces
the current consumption of the device to 1 µA maximum.
The AD5821 is designed for autofocus, image stabilization, and
optical zoom applications in camera phones, digital still cameras,
and camcorders.
The AD5821 also has many industrial applications, such as
controlling temperature, light, and movement, over the range of
−40°C to +85°C without derating.
The I2C address for the AD5821 is 0x18.
FUNCTIONAL BLOCK DIAGRAM
R
SENSE
3.3Ω
R
AD5821
D1
10-BIT
CURRENT
OUTPUT DAC
05950-001
SDA
AGND
XSHUTDOWN
V
DD
DGND
SCL I
SINK
DGND
V
DD
I
2
C SERIAL
INTERFACE
REFERENCE
POWER-ON
RESET
Figure 1.
AD5821
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Consumer Applications ................................................................... 1
Industrial Applications .................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 4
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ..............................................7
Ter mi nol og y .................................................................................... 10
Theory of Operation ...................................................................... 11
Serial Interface ............................................................................ 11
I2C Bus Operation ...................................................................... 11
Data Format ................................................................................ 11
Power Supply Bypassing and Grounding................................ 12
Applications Information.............................................................. 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
1/07—Revision 0: Initial Version
AD5821
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications TMIN to TMAX,
unless otherwise noted.
Table 1.
B Version1
Parameter Min Typ Max Unit Test Conditions/Comments
DC PERFORMANCE VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V
with reduced performance
Resolution 10 Bits 117 μA/LSB
Relative Accuracy2 ±1.5 ±4 LSB
Differential Nonlinearity2, 3 ±1 LSB Guaranteed monotonic over all codes
Zero-Code Error2, 40 1 5 mA All 0s loaded to DAC
Offset Error @ Code 162 0.5 mA
Gain Error2 ±0.6 % of FSR @ 25°C
Offset Error Drift4, 5 10 μA/°C
Gain Error Drift2, 5 ±0.2 ±0.5 LSB/°C
OUTPUT CHARACTERISTICS
Minimum Sink Current4 3 mA
Maximum Sink Current 120 mA
Output Current During XSHUTDOWN 80 nA XSHUTDOWN = 0
Output Compliance50.6 VDD V Output voltage range over which maximum 120 mA
sink current is available
Output Compliance50.48 VDD V Output voltage range over which 90 mA sink current
is available
Power-Up Time 20 μs To 10% of FS, coming out of power-down mode; VDD = 5 V
LOGIC INPUTS (XSHUTDOWN)5
Input Current ±1 μA
Input Low Voltage, VINL 0.54 V VDD = 2.7 V to 5.5 V
Input High Voltage, VINH 1.3 V VDD = 2.7 V to 5.5 V
Pin Capacitance 3 pF
LOGIC INPUTS (SCL, SDA)5
Input Low Voltage, VINL −0.3 +0.54 V VDD = 2.7 V to 3.6 V
Input High Voltage, VINH 1.26 VDD + 0.3 V VDD = 2.7 V to 3.6 V
Input Low Voltage, VINL −0.3 +0.54 V VDD = 3.6 V to 5.5 V
Input High Voltage, VINH 1.4 VDD + 0.3 V VDD = 3.6 V to 5.5 V
Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD
Input Hysteresis, VHYST 0.05 VDD V
Digital Input Capacitance, CIN 6 pF
Glitch Rejection6 50 ns Pulse width of spike suppressed
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode) IDD specification is valid for all DAC codes
VDD = 2.7 V to 3.6 V 2.5 4 mA VINH = 1.8 V, VINL = GND, VDD = 3.6 V
IDD (Power-Down Mode)7 0.5 μA VINH = 1.8 V, VINL = GND
1 Temperature range is as follows: B Version = −30°C to +85°C.
2 See the section. Terminology
3 Linearity is tested using a reduced code range: Code 32 to Code 1023.
4 To achieve near zero output current, use the power-down feature.
5 Guaranteed by design and characterization; not production tested. XSHUTDOWN is active low. SDA and SCL pull-up resistors are tied to 1.8 V.
6 Input filtering on both the SCL and the SDA inputs suppresses noise spikes that are less than 50 ns.
7 XSHUTDOWN is active low.
AD5821
Rev. 0 | Page 4 of 16
AC SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted.
Table 2.
B Version1, 2
Parameter Min Typ Max Unit Test Conditions/Comments
Output Current Settling Time 250 μs VDD = 3.6 V, RL = 25 Ω, LL = 680 μH, ¼ scale to ¾ scale change (0x100 to 0x300)
Slew Rate 0.3 mA/μs
Major Code Change Glitch Impulse 0.15 nA-s 1 LSB change around major carry
Digital Feedthrough3 0.06 nA-s
1 Temperature range is as follows: B Version = −40°C to +85°C.
2 Guaranteed by design and characterization; not production tested.
3 See the section. Terminology
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version
Parameter1Limit at TMIN, TMAX Unit Description
fSCL 400 kHz max SCL clock frequency
t12.5 μs min SCL cycle time
t20.6 μs min tHIGH, SCL high time
t31.3 μs min tLOW, SCL low time
t40.6 μs min tHD, STA, start/repeated start condition hold time
t5100 ns min tSU, DAT, data setup time
t620.9 μs max tHD, DAT, data hold time
0 μs min
t70.6 μs min tSU, STA, setup time for repeated start
t80.6 μs min tSU, STO, stop condition setup time
t91.3 μs min tBUF, bus free time between a stop condition and a start condition
t10 300 ns max tR, rise time of both SCL and SDA when receiving
0 ns min May be CMOS driven
t11 250 ns max tF, fall time of SDA when receiving
300 ns max tF, fall time of both SCL and SDA when transmitting
20 + 0.1 CB3ns min
CB400 pF max Capacitive load for each bus line
1 Guaranteed by design and characterization; not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VINH MIN of the SCL signal) to bridge the undefined region of the SCL falling edge.
3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
Timing Diagram
05950-002
S
DA
t
9
SCL
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
1
t
8
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
AD5821
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to AGND –0.3 V to +5.5 V
VDD to DGND –0.3 V to VDD + 0.3 V
AGND to DGND –0.3 V to +0.3 V
SCL, SDA to DGND –0.3 V to VDD + 0.3 V
XSHUTDOWN to DGND –0.3 V to VDD + 0.3 V
ISINK to AGND –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −30°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ MAX) 150°C
WLFCSP Power Dissipation (TJ MAX − TA)/θJA
θJA Thermal Impedance1
Mounted on 4-Layer Board 95°C/W
Lead Temperature, Soldering
Maximum Peak Reflow Temperature2260°C (±5°C)
1 To achieve the optimum θJA, it is recommended that the AD5821
be soldered on a 4-layer board.
2 As per JEDEC J-STD-020C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5821
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05950-021
A
12
VIEW FROM BALL SIDE
3
B
C
Figure 3. 9-Ball WLCSP Pin Configuration
Table 5. 9-Ball WLCSP Pin Function Description
Ball Number Mnemonic Description
A1 ISINK Output Current Sink.
A2 NC No Connection.
A3 XSHUTDOWN Power-Down. Asynchronous power-down signal, active low.
B1 AGND Analog Ground Pin.
B2 DGND Digital Ground Pin.
B3 SDA I2C Interface Signal.
C1 DGND Digital Ground Pin.
C2 VDD Digital Supply Voltage.
C3 SCL I2C Interface Signal.
NC
DGND
2
SDA
3
SCL
4
DGND
5
V
DD
6
AGND
7
I
SINK
8
XSHUTDOWN
1
1690µ
m
1515µm
05950-030
Figure 4. Metallization Photo
Dimensions shown in microns (μm)
AD5821
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
–0.5
0
0.5
1.0
1.5
INL V
DD
= 3.8V
TEMP = 25°C
1008
1023
952
896
840
784
728
672
616
560
504
448
392
336
280
224
168
112
56
0
05034-004
CODE
INL (LSB)
Figure 5. Typical INL vs. Code Plot
1008
1023
952
896
840
784
728
672
616
560
504
448
392
336
280
224
168
112
56
0
0.6
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
05034-005
CODE
DNL (LSB)
DNL V
DD
= 3.8V
TEMP = 25°C
Figure 6. Typical DNL vs. Code Plot
91.5
92.0
91.0
90.5
90.0
89.5
89.0
88.5
88.0
300.0
–6
333.1
–6
250.0
–6
200.0
–6
150.0
–6
100.0
–6
53.5
–6
05034-006
TIME
OUTPUT CURRENT (mA)
Figure 7. ¼ to ¾ Scale Settling Time (VDD = 3.6 V)
05034-007
CH3 M50.0μs
VERT = 50μs/DIV
HORIZ = 468μA/DIV
3
Figure 8. Settling Time for a 4-LSB Step (VDD = 3.6 V)
05034-008
CH1 M2.0s
VERT = 2μA/DIV 4.8μA p-p
HORIZ = 2s/DIV
1
Figure 9. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V)
1008
1023
952
896
840
784
728
672
616
560
504
448
392
336
280
224
168
112
56
0
0.14
0.12
I
OUT
@ +25°C
I
OUT
@ +85°C
I
OUT
@ –40°C
0.10
0.08
0.06
0.04
0.02
0
05034-009
CODE
I
OUT
(A)
Figure 10. Sink Current vs. Code vs. Temperature (VDD = 3.6 V)
AD5821
Rev. 0 | Page 8 of 16
2000
1800
1600
1400
1200
1000
800
600
400
200
0
10 100 1k 100k10k
05034-010
FREQUENCY
μA/V
Figure 11. AC Power Supply Rejection (VDD = 3.6 V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
85–40–30–20–100 15253545556575
–1.0
05034-011
TEMPERATURE (°C)
INL (LSB)
POSITIVE INL (V
DD
= 3.6V)
POSITIVE INL (V
DD
= 4.5V)POSITIVE INL (V
DD
= 3.8V)
NEGATIVE INL (V
DD
= 3.6V)
NEGATIVE INL (V
DD
= 4.5V)
NEGATIVE INL (V
DD
= 3.8V)
Figure 12. INL vs. Temperature vs. Supply Voltage
1.0
85–40–30–20–100 15253545556575
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
05034-012
TEMPERATURE (°C)
DNL (LSB)
POSITIVE DNL (V
DD
= 3.6V)
POSITIVE DNL (V
DD
= 4.5V)
POSITIVE DNL (V
DD
= 3.8V)
NEGATIVE DNL (V
DD
= 3.6V)
NEGATIVE DNL (V
DD
= 4.5V)
NEGATIVE DNL (V
DD
= 3.8V)
Figure 13. DNL vs. Temperature vs. Supply Voltage
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.05
0.10
85–40 –30 –20 –10 0 15 25 35 45 55 65 75
0
05950-013
TEMPERATURE (°C)
ZERO-CODE ERROR (mA)
VDD = 3.6V
VDD = 3.8V
VDD = 4.5V
Figure 14. Zero-Code Error vs. Supply Voltage vs. Temperature
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
85–40 –30 –20 –10 0 15 25 35 45 55 65 75
–2.0
05950-014
TEMPERATURE (°C)
FULL-SCALE ERROR (mA)
VDD = 3.6V
VDD = 3.8V
VDD = 4.5V
Figure 15. Full-Scale Error vs. Temperature vs. Supply Voltage
1.4
1.3
1.1
1.0
0.9
0.8
0.7
0.5
0.6
0.4
–50 –30 9070503010–10
05950-024
TEMPERATURE (°C)
VOLTAG E (V)
1.2
VDD = 2.7V
VDD = 3.6V
VDD = 5.5V
VDD = 4.5V
Figure 16. SCL and SDA Logic High Level (VINH) vs.
Supply Voltage and Temperature
AD5821
Rev. 0 | Page 9 of 16
1.4
1.3
1.1
1.0
0.9
0.8
0.7
0.5
0.6
0.4
–50 –30 9070503010–10
05950-026
TEMPERATURE (°C)
VOLTAG E (V)
1.2
VDD = 2.7V
VDD = 3.6V
VDD = 5.5V VDD = 4.5V
Figure 17. SCL and SDA Logic Low Level (VINL) vs.
Supply Voltage and Temperature
1.4
1.3
1.1
1.0
0.9
0.8
0.7
0.5
0.6
0.4
–50 –30 9070503010–10
05950-025
TEMPERATURE (°C)
VOLTAG E (V)
1.2
VDD = 2.7V
VDD = 3.6V
VDD = 5.5V
VDD = 4.5V
Figure 18. XSHUTDOWN Logic High Level (VINH) vs.
Supply Voltage and Temperature
1.4
1.3
1.1
1.0
0.9
0.8
0.7
0.5
0.6
0.4
–50 –30 9070503010–10
05950-027
TEMPERATURE (°C)
VOLTAG E (V)
1.2
VDD = 2.7V
VDD = 3.6V
VDD = 5.5V
VDD = 4.5V
Figure 19. DNL vs. XSHUTDOWN Logic Low Level (VINL) vs.
Supply Voltage and Temperature
AD5821
Rev. 0 | Page 10 of 16
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSB, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 5.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in Figure 6.
Zero-Code Error
Zero-code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
is 0 mA. The zero-code error is always positive in the AD5821
because the output of the DAC cannot go below 0 mA. This is
due to a combination of the offset errors in the DAC and output
amplifier. Zero-code error is expressed in milliamperes (mA).
Gain Error
Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal, expressed as a percent of the full-scale range.
Gain Error Drift
Gain error drift is a measurement of the change in gain error
with changes in temperature. It is expressed in LSB/°C.
Digital-to-Analog Glitch Impulse
This is the impulse injected into the analog output when the
input code in the DAC register changes state. It is normally
specified as the area of the glitch in nanoamperes per second
(nA-s) and is measured when the digital input code is changed
by 1 LSB at the major carry transition.
Digital Feedthrough
Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
It is specified in nanoamperes per second (nA-s) and measured
with a full-scale code change on the data bus, that is, from all 0s
to all 1s and vice versa.
Offset Error
Offset error is a measurement of the difference between ISINK
(actual) and IOUT (ideal) in the linear region of the transfer
function, expressed in milliamperes (mA). Offset error is
measured on the AD5821 with Code 16 loaded into the DAC
register.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in microvolts per
degree Celsius (µV/°C).
AD5821
Rev. 0 | Page 11 of 16
THEORY OF OPERATION
The AD5821 is a fully integrated, 10-bit digital-to-analog
converter (DAC) with 120 mA output current sink capability.
It is intended for driving voice coil actuators in applications
such as lens autofocus, image stabilization, and optical zoom.
The circuit diagram is shown in Figure 20. A 10-bit current
output DAC coupled with Resistor R generates the voltage that
drives the noninverting input of the operational amplifier. This
voltage also appears across the RSENSE resistor and generates the
sink current required to drive the voice coil.
Resistor R and Resistor RSENSE are interleaved and matched.
Therefore, the temperature coefficient and any nonlinearities
over temperature are matched, and the output drift over tempera-
ture is minimized. Diode D1 is an output protection diode.
R
SENSE
3.3Ω
R
AD5821
D1
10-BIT
CURRENT
OUTPUT DAC
05950-001
SDA
AGND
XSHUTDOWN
V
DD
DGND
SCL I
SINK
DGND
V
DD
I
2
C SERIAL
INTERFACE
REFERENCE
POWER-ON
RESET
Figure 20. Block Diagram Showing Connection to Voice Coil
SERIAL INTERFACE
The AD5821 is controlled using the industry-standard I2C
2-wire serial protocol. Data can be written to or read from the
DAC at data rates of up to 400 kHz. After a read operation, the
contents of the input register are reset to all 0s.
I2C BUS OPERATION
An I2C bus operates with one or more master devices that
generate the serial clock (SCL) and read and write data on the
serial data line (SDA) to and from slave devices such as the
AD5821. All devices on an I2C bus have their SDA pin connected
to the SDA line and their SCL pin connected to the SCL line of
the master device. I2C devices can only pull the bus lines low;
pulling high is achieved by pull-up resistors, RP. The value of RP
depends on the data rate, bus capacitance, and the maximum load
current that the I2C device can sink (3 mA for a standard device).
0
5950-016
SCL
SDA
I
2
C MASTER
DEVICE AD5821
I
2
C SLAVE
DEVICE
I
2
C SLAVE
DEVICE
R
P
R
P
1.8V
Figure 21. Typical I2C Bus
When the bus is idle, SCL and SDA are both high. The master
device initiates a serial bus operation by generating a start
condition, which is defined as a high-to-low transition on the
SDA low while SCL is high. The slave device connected to the
bus responds to the start condition and shifts in the next eight
data bits under control of the serial clock. These eight data bits
consist of a 7-bit address, plus a read/write (R/W) bit that is 0 if
data is to be written to a device, and 1 if data is to be read from a
device. Each slave device on an I2C bus must have a unique address.
The address of the AD5821 is 0001100; however, 0001101,
0001110, and 0001111 address the part because the last two bits
are unused/don’t cares (see Figure 22 and Figure 23). Because the
address plus the R/W bit always equals eight bits of data, the write
address of the AD5821 is 00011000 (0x18) and the read address
is 00011001 (0x19) (see Figure 22 and Figure 23).
At the end of the address data, after the R/W bit, the slave
device that recognizes its own address responds by generating
an acknowledge (ACK) condition. This is defined as the slave
device pulling SDA low while SCL is low before the ninth clock
pulse and keeping it low during the ninth clock pulse. Upon
receiving ACK, the master device can clock data into the AD5821
in a write operation, or it can clock it out in a read operation.
Data must change either during the low period of the clock
(because SDA transitions during the high period define a start
condition, as described previously), or during a stop condition,
as described in the Data Format section.
I2C data is divided into blocks of eight bits, and the slave generates
an ACK at the end of each block. Because the AD5821 requires
10 bits of data, two data-words must be written to it when a
write operation occurs, or read from it when a read operation
occurs. At the end of a read or write operation, the AD5821
acknowledges the second data byte. The master generates a stop
condition, defined as a low-to-high transition on SDA while SCL
is high, to end the transaction.
DATA FORMAT
Data is written to the AD5821 high byte first, MSB first, and is
shifted into the 16-bit input register. After all data is shifted in,
data from the input register is transferred to the DAC register.
Because the DAC requires only 10 bits of data, not all bits of the
input register data are used. The MSB is reserved for an active-
high, software-controlled, power-down function. Bit 14 is unused;
Bit 13 to Bit 4 correspond to the DAC data bits, Bit 9 to Bit 0.
Bit 3 to Bit 0 are unused.
During a read operation, data is read in the same bit order.
AD5821
Rev. 0 | Page 12 of 16
05950-017
PD XD9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
00
SCL
SDA
START BY
MASTER
ACK BY
AD5821
1191
ACK BY
AD5821
ACK BY
AD5821
STOP BY
MASTER
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 1
SERIAL BUS
ADDRESS BYTE
01 11 1R/W
9
Figure 22. Write Operation
05950-018
PD XD9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
00
SCL
SDA
START BY
MASTER
ACK BY
AD5821
1191
ACK BY
AD5821
ACK BY
AD5821
STOP BY
MASTER
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 1
SERIAL BUS
ADDRESS BYTE
01 11 1R/W
9
Figure 23. Read Operation
Table 6. Data Format1
Serial Data-Words High Byte Low Byte
Serial Data Bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
Input Register R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Function XSHUTDOWN X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
1 XSHUTDOWN = soft power-down; X = unused/don’t care; and D9 to D0 = DAC data.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in an application, it is beneficial to
consider power supply and ground return layout on the PCB.
The PCB for the AD5821 should have separate analog and digital
power supply sections. Where shared AGND and DGND is
necessary, the connection of grounds should be made at only
one point, as close as possible to the AD5821.
Special attention should be paid to the layout of the AGND return
path and, and it should be tracked between the voice coil motor
and ISINK to minimize any series resistance. Figure 24 shows the
output current sink of the AD5821 and illustrates the importance
of reducing the effective series impedance of AGND and the track
resistance between the motor and ISINK. The voice coil is modeled
as Inductor LC and Resistor RC. The current through the voice coil
is effectively a dc current that results in a voltage drop, VC, when
the AD5821 is sinking current. The effect of any series inductance
is minimal.
05950-019
AGND
AD5821
Q1
GROUND
RETURN
I
SINK
V
DROP
R
SENSE
R
R
G
L
G
V
COIL
V
BATTERY
R
T
R
C
L
C
TRACE
RESISTANCE
VOICE
COIL
SDA
SCL
X
SHUTDOWN
DGND
DGND
V
DD
Figure 24. Effect of PCB Trace Resistance and Inductance
AD5821
Rev. 0 | Page 13 of 16
When sinking the maximum current of 120 mA, the maximum
voltage drop allowed across RSENSE is 400 mV, and the minimum
drain to source voltage of Q1 is 200 mV. This means that the
AD5821 output has a compliance voltage of 600 mV. If VDROP
falls below 600 mV, the output transistor, Q1, can no longer
operate properly and ISINK may not be maintained as a constant.
When sinking 90 mA, the maximum voltage drop allowed
across RSENSE is 300 mV, and the minimum drain to source
voltage of Q1 is 180 mV. This means that the AD5821 output
has a compliance voltage of 480 mV. If VDROP falls below 480 mV,
the output transistor, Q1, can no longer operate properly and
ISINK may not be maintained as a constant. As ISINK decreases, the
voltage required across the transistor, Q1, also decreases and,
therefore, lower supplies can be used with the voice coil motor.
As the current increases to 120 mA through the voice coil,
VC increases. VDROP decreases and eventually approaches the
minimum specified compliance voltage of 600 mV (or 480 mV,
if ISINK = 90 mA). The ground return path is modeled by the
components RG and LG. The track resistance between the voice
coil and the AD5821 is modeled as RT. The inductive effects of
LG influence RSENSE and RC equally, and because the current is
maintained as a constant, it is not as critical as the purely resistive
component of the ground return path. When the maximum sink
current is flowing through the motor, the resistive elements, RT and
RG, may have an impact on the voltage headroom of Q1 and
could, in turn, limit the maximum value of RC because of
voltage compliance.
For example, if
VBATTERY = 3.6 V
RG = 0.5 Ω
RT = 0.5 Ω
ISINK = 120 mA
VDROP = 600 mV (the compliance voltage)
Then the largest value of resistance of the voice coil, RC, is
=
×+×+−
=
SINK
GSINK
T
SINKDROP
BAT
CI
RIRIVV
R)]()([
24
mA120
)]0.5mA(1202mV[600V3.6 =
××+−
Using another example, if
VBATTERY = 3.6 V
RG = 0.5 Ω
RT = 0.5 Ω
ISINK = 90 mA
VDROP = 480 mV (the compliance voltage specification at 90 mA)
Then the largest value of resistance of the voice coil, RC, is
=
×
+×
+
−
=
SINK
GSINK
T
SINKDROP
BAT
CI
RIRIVV
R)]()([
33.66
mA90
)]0.5mA(902mV[480V3.6 =
××
+
−
For this reason, it is important to minimize any series impedance
on both the ground return path and interconnect between the
AD5821 and the motor. It is also important to note that for
lower values of ISINK, the compliance voltage of the output stage
also decreases. This decrease allows the user to either use voice
coil motors with high resistance values or decrease the power
supply voltage on the voice coil motor. The compliance voltage
decreases as the ISINK current decreases.
The power supply of the AD5821, or the regulator used to supply
the AD5821, should be decoupled. Best practice power supply
decoupling recommends that the power supply be decoupled
with a 10 µF capacitor. Ideally, this 10 µF capacitor should be of
a tantalum bead type. However, if the power supply or regulator
supply is well regulated and clean, such decoupling may not be
required. The AD5821 should be decoupled locally with a 0.1 µF
ceramic capacitor, and this 0.1 F capacitor should be located as
close as possible to the VDD pin. The 0.1 µF capacitor should be
ceramic with a low effective series resistance and effective series
inductance. The 0.1 µF capacitor provides a low impedance path
to ground for high transient currents.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground.
Avoid crossover of digital and analog signals, if possible. When
traces cross on opposite sides of the board, they should run at
right angles to each other to reduce feedthrough effects through
the board. The best technique is to use a multilayer board with
ground and power planes, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
AD5821
Rev. 0 | Page 14 of 16
APPLICATIONS INFORMATION
The AD5821 is designed to drive both spring-preloaded and
nonspring linear motors used in applications such as lens auto-
focus, image stabilization, or optical zoom. The operation principle
of the spring-preloaded motor is that the lens position is controlled
by the balancing of a voice coil and spring. Figure 25 shows the
transfer curve of a typical spring-preloaded linear motor for
autofocus. The key points of this transfer function are displace-
ment or stroke, which is the actual distance the lens moves in
millimeters (mm) and the current through the motor, measured
in milliamps (mA).
A start current is associated with spring-preloaded linear
motors, which is a threshold current that must be exceeded for
any displacement in the lens to occur. The start current is usually
20 mA or greater; the rated stroke or displacement is usually
0.25 mm to 0.4 mm; and the slope of the transfer curve is
approximately 10 µm/mA or less.
The AD5821 is designed to sink up to 120 mA, which is more
than adequate for available commercial linear motors or voice
coils. Another factor that makes the AD5821 the ideal solution
for these applications is the monotonicity of the device, ensuring
that lens positioning is repeatable for the application of a given
digital word.
Figure 26 shows a typical application circuit for the AD5821.
10 50 60 8070 90 100403020 110 120
0.1
0.5
0.4
0.3
0.2
START
CURRENT
SINK CURRENT (mA)
STROKE (mm)
05950-029
Figure 25. Spring-Preloaded Voice Coil Stroke vs. Sink Current
05950-028
7
2
1
XSHUTDOWN
8
VOICE
COIL
I
SINK
R
SENSE
REFERENCE
R
AD5821
5
SCL
SDA
I
2
C MASTER
DEVICE
I
2
C SLAVE
DEVICE
R
P
R
P
V
DD
V
CC
V
DD
D1
0.1µF
I
2
C SERIAL
INTERFACE
3
4
6
POWER-ON
RESET
0.1µF 10µF
10µF +
+
V
CC
V
DD
10-BIT
CURRENT
OUTPUT DAC
Figure 26. Typical Application Circuit
AD5821
Rev. 0 | Page 15 of 16
OUTLINE DIMENSIONS
SEATING
PLANE
0.50 BSC
BALL PITCH
1.575
1.515
1.455
1.750
1.690
1.630
0.28
0.24
0.20
0.36
0.32
0.28
0.65
0.59
0.53
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
A
123
B
C
BALL 1
IDENTIFIER
110405-0
Figure 27. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD5821BCBZ-REEL71−40°C to +85°C 9-Ball Wafer Level Chip Scale Package (WLCSP) CB-9-1 D82
AD5821BCBZ-REEL1−40°C to +85°C 9-Ball Wafer Level Chip Scale Package (WLCSP) CB-9-1 D82
AD5821-WAFER −40°C to +85°C Bare Die Wafer
AD5821D-WAFER −40°C to +85°C Bare Die Wafer on Film
EVAL-AD5821EBZ1 Evaluation Board
1 Z = Pb-free part.
AD5821
Rev. 0 | Page 16 of 16
T
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05950-0-1/07(0)
TTT
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Authorized Distributor
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