oH Y U N BAL pyszvecs 8Mx8 bit Synchronous DRAM Series 010/ HY57V648020/ HY57V658010/ HY57V658020 HY57V648011/ HY57V648021/ HY57V658011/ HY57V658021 DESCRIPTION HY57V648010_ || 4Mbit x 2bank x 8 /O, LVTTL HY57V648020 || 2Mbit x 4bank x 8 I/O, LVTTL HY57V658010 || 4Mbit x 2bank x 8 I/O, LVTTL HY57V658020 || 2Mbit x 4bank x 8 VO, LVTTL HY57V648011_ || 4Mbit x 2bank x 8 /O, SSTL HY57V648021_ || 2Mbit x 4bank x 8 I/O, SSTL HY57V658011 || 4Mbit x 2bank x 8 VO, SSTL HY57V658021_ || 2Mbit x dbank x 8 1/0, SSTL The HY57V648010, HY57V648020, HY57V658010, HY57V658020, HY57V648011, HY57V648021, H57V658011, HY57V658021 are high speed 3.3V Synchronous DRAMs and fabricated with the Hyundai CMOS process. Each bank shares the same chip inputs and outputs but can be independently operated. The Synchronous devices are compatible with the JEDEC functional FEATURES Fully synchronous ; all inputs referenced to positive edge of system clock e Internai 2 or 4 banks with single pulsed RAS e Auto Precharge/Precharge all banks by A10 flag Single 3.3V0.3V power supply All device pins are compatible with LVTTL or High speed I/O interface(SSTL) * 400mil 54pin TSOP(I!) with 0.8mm of lead pitch (Lead-On-Chip) e 4096 refresh cycles every 64ms or 8192 refresh cycles every 128ms Possible to assert random column address every clock cycle ORDERING INFORMATION PRELIMINARY description and pinout, offering fully synchronous Operation. All address, data and control inputs are latched on the rising edge of the master clock input. The data paths are internally pipelined to achieve very high bandwidth. Programmable options include the length of pipeline(Read latency of 1,2, or 3), the number of consecutive read or write cycles initiated by a single control command(Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle.(This pipelined design is not restricted by a 2N rule.) The Synchronous DRAM also allows both auto refresh and self refresh. All input and output voltage levels are compatible with LVTTL or High speed I/O interface(SSTL). e Programmable Burst lengths and Sequences - 1,2,4,8,full page for Sequential type - 1,2,4,8 for Interleave type Programmable CAS latency ; 1,2,3 clocks e Support clock suspend/Power down mode by CKE e Data mask function by DQM e Mode register set programming Burst termination command Meet all the other JEDEC specifications e Self refresh provides minimum power, full internal refresh control e Interleaved Auto refresh mode Part NO. Max. Frequency Package Remark HY57V648010TC - 10/12/15 100/83/66 MHz 400mil TSOP-II x8, 2bank, 8K ref., LVTTL HY57V648020TC - 10/12/15 100/83/66 MHz 400mil TSOP-II x8, 4bank, 8K ref., LVTTL HY57V658010TC - 10/12/15 100/83/66 MHz 400mil TSOP-I! x8, 2bank, 4K ref., LVTTL HY57V658020TC - 10/12/15 100/83/66 MHz 400mil TSOP-I] x8, 4bank, 4K ref., LVTTL HY57V648011TC - 7/8/10 150/125/100 MHz 400mil TSOP-I x8, 2bank, 8K ref., SSTL HY57V648021TC - 7/8/10 150/125/100 MHz 400mil TSOP-Ii x8, 4bank, 8K ref., SSTL HY57V658011TC - 7/8/10 150/125/100 MHz 400mil TSOP-II x8, 2bank, 4K ref., SSTL HY57V658021TC - 7/8/10 150/125/100 MHz 400mil TSOP-Ii x8, 4bank, 4K ref., SSTL This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. MH 4675088 0005249 663 99 18E11-02-NOV96 K=r =HYUNDAI 8Mx8bit Synchronous DRAM Series PIN CONNECTION 2bank 4bank voD 10 10 ooo 2 2 Voda 3 3 NO 4 4 oa 5 50 VSSQ 6 6 49 NC 7 7 48 von 5 HY57V648010 5 HY57V648020 7 No HY57V658010 HY57V658020 4, __ 0 HY57V648011 HY57V648021 44 HY57V658011 Hy57Vv658021 voD 4 Nc 40 ME 39 KE re 3 KS 36 A13(BAD) 3% Al2 34 AIDIAP) 33 AO 2 3 2 28 PIN DESCRIPTION Pin Numbers Pin Name Type Description System Clock Input; All other inputs except CKE are 38 CLK Input registered to the SDRAM on the rising edge of CLK. Clock Enable; Controls internal clock signal and when 37 CKE Input | deactivated, the SDRAM will be one of the states among power down, suspend, or self refresh. 2bank: 20 A13 Input Bank select address(BA) ; Select either one of dual banks 4bank: 20,21 A13, A12 pu during both RAS andGag activity. 2bank: Address Inputs; 21-26, 29-35 | A0-A12 Row&Column address : A0Q-A8 : Input | Row address only : 2bank[A9-A12], 4bank[A9-A11] 4bank: Precharge flag : A10 22-26, 29-35 | A0-A11 Opcode for mode register set : A0-A13 19 cs Input | Chip Select; Functions command mask(NOP). 18 RAS input | Row Enable; See functional truth table for details. 17 CAS Input {| Column Enable; See functional truth table for details. 16 W_ Input | Write Enable; See functional truth table for details. 39 DQM Input | Data Input / Output Mask 2,5,8,11, Input / . . . 44,47,50,53 DQ0-DQ7 Output Data Input / Output; Include inputs, outputs, or Hi-Z state. 3,9,43,49 Voba Supply . 6,12,46,52 | Vssa for DQ | PQ Power Supplies 1,27 Vob Supply | Power Supplies; 3.3V +0.3V 28,54 Vss Supply | Ground Me 4675086 0005250 S85 100 1SE11-02-NOV96HYUNDAI 8Mx8bit Synchronous DRAM Series FUNCTIONAL BLOCK DIAGRAM 4Mbit x 2bank x 8 I/O Synchronous DRAM - Self Refresh Counter o 3 oO & Bie Refresh Refresh 3 Interval Timer Counter yl s 8 4Mx8 < g)Oo Bank 0 a nN = ra KIS & oe Bilge a oo, 3 Bs Ps 45) 3 35 Address[0:12] B ig & : __ 2 ee L_+|Sense AMP & /O gates xx Coiumn Decoder CLK + a] oS Precharge ,| Address <| | CKE > a Register 4 5 + Dao ! Row Active || p BA(A13)>| + DQ1 as Column Active en eens < > DQ2 8 atc ounter Ble pas RA ) @ Overflow Q a Burst Length 3 <> DO4 el CA |@ Counter a le DAS E g w z| & |++ Das DemM baz Column Decoder [___*|Sense AMP & I/O gates o i. Lora Qu ao ~ 7g er 8 x = a a) ol Bi 5 o = 5 a}/yz ran) =/90 5 g = LI S| 3 4Mx8 46s s @|/a Bank 1 wl BF = =| Q el s Sia Oo o SB z oO oO 3. a a = Oo fs we Mode Register Test Mode VO Control MH 4675088 0005251 411. 1SE11-02-NOV96 101HYUNDAI 8Mx8bit Synchronous DRAM Series 2Mbit x 4bank x 8 /O Synchronous DRAM 2 2Mx8 +|" Self Refresh Counter 8 Bank 2 o 3 o oO Ble _ a Refresh Refresh a|3 Interval Timer Counter / 38 2Mx8 c r*| @/a Bank 0 % ov .| 2 = 15 5 3s 3/& eS 2 Eos = BS = Sense AMP & I/O gates| Address[O:11] < Column Decoder _ 5 ee L__,|Sense AMP & I/O gates 4X Column Decoder CLK > a xa [| gs g CKE Precharge ,| Address |_ q| < ++ DQO ___ | Register o| BA(A13) Row Active > 2 le> DQ1 a r } BA(A12)+} = |_| Column Active Column Addr. are pae 8 Latch & Counter a i> DQ3 CcsS |S v Ss 2 Overflow Q kt DOQ4 RA ) & Burst Length 2 Counter a = |e 005 0 ~ cA > se} s & le DAS _ Ss ft a w 3 ++ DQ7 Vv pamM Column Decoder o [_* [Sense AMP & I/O gates Ll > 3 Column Decoder x = S Sense AMP & I/O gates 6 a 3 a jas a) | Sl 3 1818 2Mx8 a 3 3 &|a Bank 1 uf Fs 2 =|3 aq gl s Ble S| 2 3 a qs $ 3 o Ss] a & = 2Mx8 & Bank 3 Made Register Test Mode /O Control me 4675088 0005252 356 102 1SE11-02-NOV96HYUNDAI 8Mx8bit Synchronous DRAM Series ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating Unit TA Ambient Temperature 0 to 70 c TsTG Storage Temperature -55 to 125 c VIN, VOUT Voltage on Any Pin relative to Vss -1.0 to 4.6 Vv VbD Voltage on VDD relative to Vss -1.0 to 4.6 Vv los Short Circuit Output Current 50 mA Pb Power Dissipation 1 Ww TSOLDER Soldering Temperature Time 260 + 10 T - sec Note : Operation at above Absolute Maximum Ratings can adversely affect device reliability. RECOMMENDED DC OPERATING CONDITIONS: (Ta=OT to 70) Symbol Parameter Min. Typ. Max. Unit Note Vpb, VDDQ | Power Supply Voltage 3.0 3.3 3.6 Vv Vss, VssqQ | Power Supply Voltage 0 0 0 Vv VIH Input High Voltage 2.0 : Vop + 0.4 Vs LVTTL VREF + 0.2 - Vop + 0.3 Vv SSTL Vit Input Low Voltage -0.3 - 0.8 Vv LVTTL -0.3 - VREF - 0.2 Vv SSTL VREF Reference Voltage - Vona x 0.45 - Vv SSTL RT Termination Resistor - 50 - Q SSTL Rs Series Resistor - 20 - R SSTL RECOMMENDED AC OPERATING CONDITIONS. (TA=0C to 70, VoD=3.3V+10%, Vss=0V) Symbol Parameter Value Unit | Note . 2.4/0.4 LVTTL VIH/ ViL | AC Input High/Low Level Voltage VREFO S/VREF-03 Vv SSTL . 1.4 LVTTL Vtrip Input Timing Measurement Reference Level Voltage VREE Vv SSTL tr/tf Input Rise/Fall Time 1 ns Voutref | Output Reference Voltage 14 Vv LVTTL VREF SSTL CL Output Load Capacitance for Access Time Measurement Note pF Note : Output toad to measure access times is equivalent to two TTL gates and one capacitance(50pF). CAPACITANCE (TA=25 C, f= 1MHz) Symbol Parameter Pin Max. | Unit cn Input Capacitance A0-A13 5 pF Cl2 Input Capacitance CLK, CKE, GS, RAS, CAS ,WE , DQM 5 pF Co Data Input/Output Capacitance | DQ0-DQ7 7 pF Note: * DC Output Load Circuit AC Output Load Circuit Quo > 70 Vit=1.4V Output Z0=500 Se vite av 1SE11-02-NOV96 LL i MB 4675088 0005253 214 103WYUNDAI 8Mx8bit Synchronous DRAM Series DC CHARACTERISTICS(I) (Ta=0 to 70C, VDD=3.3V+10%, Vss=0V) Symbol Parameter Test Condition Min. Max. Unit Note tu Input Leakage Current ping | a oe avcoy -1 1 LA Lo Output Leakage Current voen to geales. -1 1 LA IREF VREF Current - -1 1 LA Vot Output Low Voltage lo=2.0MA - 0.4 Vv LVTTL lo=16mMA - VtTT-0.4 Vv SSTL VoH Output High Voltage lo=-2.0MA 2.4 - Vv LVTTL lo=-16mMA VTT+0.4 - Vv SSTL DC CHARACTERISTICS(Il) (Ta=0 to 70, Vop=3.3V+10%, Vss=0V) Symbol Parameter Test Condition Max.| Unit} Note Burst Length=1, One bank active 7ns | 100 tRAS = tRAS(min), 8ns | 85 Ipb1 Operating current tRP=tRP(min), 10ns| 85 |} mA} Note 2 to=O0mA 12ns; 70 15ns; 60 Ipp2P | Precharge Standby Current | CKE = ViL(max) 2 |mA in Power Down Mode lpp2n | Precharge Standby Current | CKE= Vix(min), All other pins = VpbD-0.2V or 12 | mAILVTTL' =0.2V in Non Power Down Mode CKE=VreF+0.2V,All other pins 2 VREF+0.2V or | 12 | mA] SSTL SVREF-0.2V lop3P {| Active Standby Current CKE = Vit(max), All bank active 3 | mA in Power Down Mode IpD3n_ | Active Standby Current CKE 2 ViH(min), All other pins = Vop-0.2V or 35 | mA/LVTTL' =0.2V, All bank active in Non Power Down Mode CKE=VRreF+0.2V,All other pins = VREF+0.2V or | 35 | mA] SSTL <=VreF-0.2V, All bank active tcLK=tcLk(min), 7ns | 200 lop4 Operating Current tRAS 2 tRAS(min), &ns | 180 (Burst Mode) lo=0mA, 10ns| 150 | mAj Note 2 CAS Latency=3 12ns| 120 15ns| 100 7ns | 125 tRc =trRc(min), Two bank active 8ns | 110 (8K/128ms) 10ns| 110 | mA| Note 2 12ns| 90 IDD5 Refresh Current 15ns| 75 7ns | 180 tRc = trc(min), Four bank active 8ns | 160 (4K/64ms) 10ns {| 160 | mA} Note 2 12ns| 130 15ns | 105 IDo6 Self Refresh Current CKE=0.2V 2 | mA 500 | HA | L-part Note : 1. It depends on the number of each pins transition. It is assumed there is no transition to measure this current. 2. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition this |p01 is measured on condition that addresses are changed only one time during tcLK(Min.) M 4675088 0005254 120 104 1SE11-02-NOV96NYUNDAI 8Mx8bit Synchronous DRAM Series AC CHARACTERISTICS Synchronous Characteristics(I) Parameter 150MHz 125MHz 100MHz 83MHz 66MHz Unit (7ns (8ns (10ns) (12ns) (15ns CAS Latency 3 | 2] 1 3 | 2] 1 3 {241 372 {1 3 | 2 | 1 | Latency Frequency 150| 83 | 33 | 125] 83 | 33 100 | 83 | 33 | 83 | 66} 33] - | 66 | 33 MHz Clock Cycle Time | 7 | 12 | 30; 8 | 12; 30] 70/12130112/15]301 - | 15/30 ns tRCD 3/2]; 71;,3/,2;);1]/3]/2;);%4;)3!]2 44 - | 2 | 1 | CLKG) tRAS 6|4,2;6)/4;215]/4:i2't4j;4]21-]4)]2 CLK(s) tRP 4/3 /,1};3/3),1/3/3;)4/)3)2)41 - | 2] 1 CLK(s) {RC 10; 7{3}10}7;3]}8|)/7)3;7{/6/3]-]e6f[3 CLK(s) tRRD 312/71); 3]/2}/1/3]/2})1})/2]/2]/2]-]e2T2 CLK(s) tDPL 1/14/1441] 1 1}, 4] 4) d)].4)4 - | 14] 1 | CLK(s) {DAL S/3{/2/4]}/3]}]2;4/3);2/13/3]21-]37 2 CLK(s) {SRE 1; 1]/1]1]1 i ee es eee ee - {| 1] 1 =| CLK(s) tT 1 1 1 1 1 ns Refresh Cycle 8K/128ms, 4K/64ms Cycles Characteristic 50ns Par ns Note : tRRD -Bank Active to Active Command tDPL -DiN to Precharge Command tDAL -DIN to Active(Ref.) Command (After Write with Autoprecharge) tsreE -Self Refresh Exit Time Synchronous Characteristics(ll) [LVTTL Part] Symbol Parameter -10 -12 -15 Unit | Note Min. | Max. | Min. | Max. | Min. | Max. tac Access Time from CLK |CAS Lat.=3 - 8 - 9 - 10 | ns CAS Lat.=2 - - - - - 10 | ns tcH CLK High Level Width 3.5 - 3.5 - 3.5 - ns te CLK Low Level Width 3.5 - 3.5 - 3.5 - ns toH Data-out Hold Time 3 - 3 - 3 - ns to1z Data-out Low-Impedance Time 3 - 3 - 3 - ns toHZ | Data-out High-Impedance Time 0 8 0 9 0 10 ns tps Data-in Set-up Time 3 - 3 - 3 - ns tDH Data-in Hold Time 1 - 1 - 1 - ns tas Address Set-up Time 3 - 3 - 3 - ns tAH Address Hold Time 1 - 1 - 1 - ns tcxs | CKE Set-up Time 3 - 3 - 3 - ns tCKH | CKE Hold Time 1 - 1 - 1 - ns tcs Command Set-up Time 3 - 3 - 3 - ns tcH Command Hold Time 1 - 1 - 1 - ns tPDE | Power Down Exit Set-up Time 3 - 3 - 3 - ns MM 4675066 0005255 Ob? 1SE11-02-NOV96 108 KerHYUNDAI 8Mx8bit Synchronous DRAM Series [SSTL Part] Symbol Parameter -7 -8 -10 Unit | Note Min. | Max. | Min. | Max. | Min. | Max. tac___| Access Time from CLK [CAS Lat=3 | - 5 - : 8 ns CAS Lat.=2 - - - - - ns {cH CLK High Level Width 2.5 - 3 3.5 - ns tCL CLK Low Level Width 2.5 - 3 3.5 - ns {OH Data-out Hold Time 2 - 2 3 - ns toLz Data-out Low-Impedance Time 2 - 2 3 - ns toHz | Data-out High-lmpedance Time 0 5 0 0 8 ns tbs Data-in Set-up Time 2 - 2 3 - ns {DH Data-in Hold Time 1 - 1 1 - ns tas Address Set-up Time 2 - 2 3 - ns {AH Address Hold Time 1 - 1 1 - ns tcxs | CKE Set-up Time 2 - 2 3 - ns tCKH | CKE Hold Time 1 - 1 1 - ns tcs Command Set-up Time 2 - 2 3 - ns tCH Command Hold Time 1 - 1 1 - ns tPDE | Power Down Exit Set-up Time 2 - 2 3 - ns Latency Symbol Parameter Latency tcKED CKE to CLK Suspend / Power Down Mode Entry 1 tbqmoz DQM to Data Output in Hi-z 2 tDQmMiM DQM to Data input Mask 0 tWTL Write Command to Data Input Valid 0 CAS Latency=1 1 tPROZ Precharge Command to Data Output in Hi-z CAS Latency=2 2 CAS Latency=3 3 tMRD Mode Register Set to New Command 1 tccD Min. Column Address to Column Address Delay 1 tPPD Min. Precharge to Precharge Time 1 Notes: 1. All voltage referenced Vss(Ground). 2. An initial pause of 100 4S is required after power-on followed by Power On Sequence & Auto Refresh before proper device operation is achieved. 3. AC measurements assume tT=1ns. 4. Reference level for measuring timing of input signals is 1.40V for LVTTL and VrRer for SSTL. Transition times are measured between ViIH and VIL. 5. An access time is measured at 1.40V for LVTTL and VreF for SSTL. 106 Mm 4675086 OOOSeSb TTI 1SE11-02-NOV96HYUNDAI 8Mx8bit Synchronous DRAM Series STATE AND FUNCTIONAL TRUTH TABLE, OPERATIONS INVOLVING ALL BANKS CLK T Current State CKE os|ras|cas| wel pa |ato| AA2, Action Prev. | Curr. AI/AI2 L L X| X x xX Xx X X Maintain Power Down Power Down L H Lj H H H x X Exit Power Down Idle L H H} X x Xx Xx X xX Exit Power Down Idle L L xX} X x x xX X x Maintain Self Refresh SelfRefresh | L | H |L] H|H | HI] Xx | x X Exit Self Refresh Idle L | H |H| xX Xx xX X | X xX H L L | H H H X xX Xx Enter Power Down H L Hj} X x Xx X x Xx Enter Power Down All Banks Idie H L Ly Ll L H xX x x Enter Self Refresh H H }L{ H H H xX | X Xx NOP H H HH} X Xx xX Xx Xx xX Deselect H H Lik L L OPCODE Mode Register Access H H Ly] L L H x X Xx Auto Refresh CLK Suspend L L xX] X x X x x x Maintain CLK Suspend L H X1 X xX X x x x Exit CLK Suspend Auto Refresh H H LY} H H H x x Aer te. Banks tate H H H| X X x Xx xX Deselect rranapoe | H | Lx] x [x | x | x |x| x | Seezend Sock next eve Write DOM Latency is 0, DQM H x x) x x x x x x Read DOM Latency is 2. Note: 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. In case of 2bank : AO-A9, A11,A12 in case of 4bank : A0-AS9, A11 1SE11-02-NOV96 Mi 46750866 0005257? 93T 107HYUNDAI 8Mx8bit Synchronous DRAM Series STATE AND FUNCTIONAL TRUTH TABLE, SELECTED BANK Current State of CLK Tf Action to Selected Bank Selected Bank | |RAS |CAS| WE| BA | Ato | A0-A9,A11/A12| (Unless otherwise noted) L L L L OPCODE Mode Register Access L H H H X xX x NOP Idle H x x x X xX X Deselect L L H L BA X Xx NOP L L L H Xx X x Auto or Self Refresh L L H H BA | RA RA Activate Row L L L xX X-| X x ILLEGAL L H H H x X x NOP H x Xx x Xx X x Deselect L L H L BA L Xx Precharge Selected Bank Row Active L L H L x H Xx Precharge All Banks L H L L BA L CA Begin Write L H L L BA H CA Begin Write/Auto Precharge L H L H BA L CA Begin Read L H L H BA H CA Begin Read/Auto Precharge NOP(Continue burst to end L|}H]H)H| xX | Xx x Row Active) H xX xX X Xx X XK Deselect L L H L BA L Xx Precharge Selected Bank L L H L x H Xx Precharge All banks L L L X Xx xX X ILLEGAL Read L H L L | BAT L CA Begin Write* L H L L BA H CA Begin Write/Auto Precharge L H L H BA L CA Begin New Read Begin New Read/Auto L H L H BA H CA Precharge L H H L Xx X X Term Burst > Row Active NOP(Continue burst to end lL H H H x x x Row Active) H xX x Xx x x X Deselect L L H L BA L X Precharge Selected Bank L L H L x H X Precharge All banks L L L X x x xX ILLEGAL Write L H L L BA L CA Begin New Write Begin New Write/Auto L H L L BA H CA Precharge L H L H BA L CA Begin New Read Begin New Read/Auto L H L H BA H CA Precharge L H H L X Xx xX Term Burst > Row Active NOP, Continue burst to end L H H H Xx xX x Precharge H x X x xX X X Deselect Read with L L H L BA L X ILLEGAL Auto L L H L X H X ILLEGAL Precharging L H L L BA L CA ILLEGAL L H L L BA H CA ILLEGAL L H L H BA L CA ILLEGAL L H L H BA H CA ILLEGAL L H H L x X Xx ILLEGAL L L L X Xx Xx x ILLEGAL 108 Mm 4675086 0005256 47b ml 1SE11-02-NOV96HYUNDAI 8Mx8bit Synchronous DRAM Series Current State of CLK t Action to Selected Bank Selected Bank CS |RAS |CAS| WE! BA | A10 | A0-A9,A11/A12 | (Unless otherwise noted) NOP, Continue burst to end ee ee x x x Precharge H x x x x xX x Deselect Write with L L H L BA L Xx ILLEGAL Auto Precharging |_L L H L x H x ILLEGAL L H L L BA L CA ILLEGAL L H L L BA H CA ILLEGAL L H L H BA L CA ILLEGAL L H L H BA H CA ILLEGAL L H H L x xX Xx ILLEGAL L L L Xx x xX Xx ILLEGAL L H H H Xx x Xx NOP Idle after trp H | X X x Xx x x Deselect L L H L BA L Xx NOP Precharging L L H L x H X NOP L H L L BA L CA ILLEGAL L H L L BA H CA ILLEGAL L H L H BA L CA ILLEGAL L H L H BA H CA ILLEGAL L H H L xX x x ILLEGAL L H H H X x Xx NOP Row active after tRco H x xX Xx xX x Xx Deselect Row Activating L L H L BA L x ILLEGAL L L H L x H xX ILLEGAL L H L L BA Xx CA ILLEGAL L H L H BA xX CA ILLEGAL L H H L x Xx x ILLEGAL L L L Xx xX Xx x ILLEGAL L H H H x x xX NOP H x x x x Xx 4 Deselect Mode Register L L H H x xX Xx ILLEGAL Accessing L H L H x Xx X ILLEGAL L H L L x xX X ILLEGAL L H H L x x x ILLEGAL Notes: 1. Assume CKE high on the previous and current clock cycles. 2. Read burst must terminate one cycle before the start of a write sequence. This can be accomplished in one of two ways. First, if the last bit of the burst is output two cycles before the start of the write sequence, the burst will terminate. And the output will tristate, the internal read pipeline will be flushed during the cycle before the write command is issued. Second, the burst can be terminated by bringing DQM high and issuing a terminate burst command two cycles before the write command. This will also guarantee that the output will tristate and the read pipeline will be flushed during the cycle before the write command is issued. 3. While either bank is executing a Read or Write burst sequence with Auto Precharge selected, no Read or Write commands are allowed to the opposite bank. 4. X=Don't care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code, NOP=No Operation 5. In case of 2bank : AO-A9, A11,A12 In case of 4bank : A0-A9, A11 1SE11-02-NOV96 M@ 46750488 0005259 702 om 109HYUNDAI 8Mx8bit Synchronous DRAM Series STATE DIAGRAM(SIMPLIFIED) POWER | EEN ee eee WRITE WITH AUTOPRE- CHARGE Q Cc AD a 4 w Cc 7d a oe POWER APPLIED Notes: ~ ___ By command Input vrrteee ese eeess > Automatic sequence after finishing the command Me 4675088 0005260 42h 110 1SE11-02-NOV96HYUNDAI 8Mx8bit Synchronous DRAM Series PROGRAMMABLE MODE REGISTER MODE REGISTER SET(WRITE) A13 | A12 | Ai1 | A10 | AQ A8 AT A6 AS A4 A3 A2 Al AO 0) 0 i) 0 0 0 i) CAS Latency BT Burst Length Vv A3 Burst Type 0 Sequential (Wrap round, Binary-up) 1 Interleave (Wrap round) v y AG AS A4 | CAS Latency A2 Al AO Burst Length 0 0 0 Reserved 0 0 0 1 0 0 1 1 0 0 1 2 0 1 0 2 0 1 0 4 cr 0 1 1 3 0 1 1 8 E 1 0 0 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 0 Reserved 1 1 1 Reserved 1 1 1 Full page Note : 1. Full page burst supports only sequential type. TEST MODE A1i| A10| AQ | A&8 | A7 |] AGB | AS | Ad} AB | A2 1] A1 | AO Address 0 0 0 0 1 x x x x X x x Refresh Counter Test Note: Test Mode - Used to test the counter of Auto Refresh. - Exit test mode using Precharge All. bank . M@ 4675088 OOOS2b1] 3b0 1SE11-02-NOV96 111HYUNDAI 8Mx8bit Synchronous DRAM Series BURTS LENGTH AND SEQUENCE Burst Length Initial Address Burst Type A2 A1 AO Sequential Interleave 2 Xx X 0 0,1 0,1 X X 1 1,0 1,0 4 X 0 0 0,1,2,3 0,1,2,3 X 0 1 1,2,3,0 1,0,3,2 X 10 2,3,0,1 2,3,0,1 xX 11 3,0,1,2 3,2,1,0 8 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 0,1,2,3,4,,m Full page Note 1,2,3,45, 0 Not supported m,0,1,2,3,"",m-4 Table 1. Address sequence for different burst lengths Note : 8Mbit x 2bank x 41/0 - initial address: A9-A0, Page length: 1024, m=1023 4Mbit x 4bank x 4I/O - Initial address: A9-A0, Page length: 1024, m=1023 MH 4675088 0005262 2T? 112 1SE11-02-NOV96HYUNDAI 8Mx8bit Synchronous DRAM Series PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package Unit : mm(Inch) RRR ABA RRA RRA RRR RRA RAAB ! O HEGHEBHRHEHHE OHHH BARB AHH BEE 11.938(0.4700 11.735(0.4620 10,262(0.4040 10.058(0.3960 22.327(0.8790 22.149(0.8720) 1 GAGE PLANE BASE PLANE o~5"\ . / 4 o.g0(0.0315}8s 0,400(0,016 ! T SEATING PLANE } 0.300(0.012 .0.150(0.0059 0.597(0.0235 0.210(0.0083) 1.194(0.0470 RETR 0.406(0.0160 0.120(6.0047 0.991(0.0390 Ker z E MB 4675068 0005263 133 1SE11-02-NOV96 113