Wireless Components
ASK Single Conversion Receiver 390MHz
TDA 5204 E1
Version 1.0
Specification December 2000
preliminary
Edition 12.00
Published by Infineon Technologies AG,
Balanstraße 73,
81541 München
© Infineon Technologies AG December 2000.
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Revision History
Current Version: 1.0 as of 12.01.01
Previous Version: none
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Product Info
Product Info
Wireless Components
Specification, December 2000
Package
TDA 5204 E1
preliminary
Product Info
General Description The IC is a very low power consump-
tion single chip ASK Single Conver-
sion Receiver for receive frequencies
between 385 and 406MHz. The
Receiver offers a high level of integra-
tion and needs only a few external
components. The device contains a
low noise amplifier (LNA), a double
balanced mixer, a fully integrated
VCO, a PLL synthesiser, a crystal
oscillator, a limiter with RSSI genera-
tor, a data filter, a data comparator
(slicer) and a peak detector. Addition-
ally there is a power down feature to
save battery life.
Features
Low supply current
(Is = 4.8mA typ.)
Supply voltage range 5V ±10%
Temperature range -40°C...+85°C
Power down mode with very low
supply current (50nA typ)
Fully integrated VCO and PLL
Synthesiser
RF input sensitivity < –110dBm
390MHz band
Selectable reference frequency
Limiter with RSSI generation,
operating at 10.7MHz
2nd order low pass data filter with
external capacitors
Data slicer with self-adjusting
threshold
Application
Keyless Entry Systems
Remote Control Systems
Fire Alarm Systems
Low Bitrate Communication
Systems
Ordering Information
Type Ordering Code Package
TDA 5204 Q67037-A1169 P-TSSOP-28-1
available on tape and reel
1Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.6 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.7 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.8 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1 LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3 Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2Product Description
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Contents of this Chapter
Product Description
2 - 2
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
2.1 Overview
The IC is a very low power consumption single chip ASK Superheterodyne
Receiver (SHR) for the frequency band 390MHz. The SHR offers a high level
of integration and needs only a few external components. The device contains
a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a
PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter,
a data comparator (slicer) and a peak detector. Additionally there is a power
down feature to save battery life.
2.2 Application
Keyless Entry Systems
Remote Control Systems
Fire Alarm Systems
Low Bitrate Communication Systems
2.3 Features
Low supply current (Is = 4.8mA typ.)
Supply voltage range 5V ±10%
Power down mode with very low supply current (50nA typ.)
Fully integrated VCO and PLL Synthesiser
RF input sensitivity < –110dBm
frequency band 390MHz
Selectable reference frequency
Limiter with RSSI generation, operating at 10.7MHz
2nd order low pass data filter with external capacitors
Data slicer with self-adjusting threshold
Temperature range -40°C...+85°C
Product Description
2 - 3
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
2.4 Possible Receive Ranges
385...406MHz (high-side injected)
406...428MHz (low-side injected)
781...823MHz (high-side injected)
803...844MHz (low-side injected)
2.5 Package Outlines
P_TSSOP_28.EPS
Figure 2-1 P-TSSOP-28-1 package outlines
3Functional Description
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Contents of this Chapter
Functional Description
3 - 2
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
3.1 Pin Configuration
Pin_Configuration.wmf
Figure 3-1 IC Pin Configuration
CRST2
PWDN
PDO
DATA
3VOUT
THRES
FFB
OPP
SLN
SLP
LIMX
LIM
CSEL
LF
TDA5204
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CRST1
VCC
LNI
TAGC
AGND
LNO
VCC
MI
MIX
AGND
FSEL
IFO
DGND
VDD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Functional Description
3 - 3
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No. Symbol Equivalent I/O-Schematic Function
1CRST1 External Crystal Connector 1
2VCC 5V Supply
3LNI LNA Input
4TAGC AGC Time Constant Control
5AGND Analogue Ground Return
6LNO LNA Output
7VCC 5V Supply
1
4.15V
3
1k
4
1k
4.3V
1.7V
4uA
1.5uA
1k
6
Functional Description
3 - 4
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
8
9
MI
MIX
Mixer Input
Complementary Mixer Input
10 AGND Analogue Ground Return
11 FSEL 390MHz:
not applicable - has to be left
open
12 IFO 10.7 MHz IF Mixer Output
13 DGND Digital Ground Return
14 VDD 5V Supply (PLL Counter Cir-
cuitry)
15 LF PLL Filter Access Point
(Loop Filter)
8
2k 2k
9
1.7V
40k
11
1.2V
60
12
300uA
2.2V
4.5k
100
2.4V
30uA
30uA
4.8V
200
15
Functional Description
3 - 5
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
16 CSEL 6.xx or 12.xx MHz Quartz
Selector
17
18
LIM
LIMX
Limiter Input
Complementary Limiter Input
19 SLP Data Filter Output
Data Slicer Positive Input
Peak Detector Input
20 SLN Data Slicer Negative Input
21 OPP OpAmp Noninverting Input
80k
16
1.2V
330
2.4V
17
18
15k
15k
19
100
40u
10k
10k
20
10k
21
200
Functional Description
3 - 6
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
22 FFB Data Filter Feedback Pin
23 THRES AGC Threshold Input
24 3VOUT 3V Reference Output
25 DATA Data Output
22
100k
23
10k
24
3V
25
200
80k
Functional Description
3 - 7
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
26 PDO Peak Detector Output
27 PDWN Power Down Input
Vs --> Power ON
GND---> Power Down
28 CRST2 External Crystal Connector 2
26
200
27
220k
220k
28
4.15V
Functional Description
3 - 8
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
3.3 Functional Block Diagram
Function_5204.wmf
Figure 3-2 Main Block Diagram
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
IF
Filter
VDD
VCC
LNO MI MIX IFO LIM LIMX FFB OPP SLP SLN
DATA
PDO
SLICERRSSI
THRES
LNA
RF
TAGC
DGND
VCC AGND FSEL CSEL PDWN
Crystal
Loop
Filter
Bandgap
Reference
U
REF
TDA 5204
AGC
Reference
3VOUT
3
4
14
13
2/7 5/10 11 15
LF
16 1 28 27
24
23
26
25
201921
22
181712
9
86
Crystal
OSC
Φ
DET
: 128/64VCO: 1/2
Functional Description
3 - 9
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) 390MHz to
the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately
21dB. A low pass filter with a corner frequency of 20MHz is built on chip in order
to suppress RF signals to appear at the IF output ( IFO pin). The IF output is
internally consisting of an emitter follower that has a source impedance of
approximately 330Ω=to facilitate interfacing the pin directly to a standard
10.7MHz ceramic filter without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. It’s nominal centre frequency is 800MHz. The FSEL pin (Pin 11) has to
be left open. No additional components are necessary. The oscillator signal is
fed both to the synthesiser divider chain and to the downconverting mixer. The
VCO signal is divided by two before it is fed to the mixer. The loop filter is also
realised fully on-chip.
3.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in
the 6 and 12MHz range as the overall division ratio of the PLL can be switched
between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
Table 3-2 CSEL Pin Operating States
CSEL Crystal Frequency
Open 6.xx MHz
Shorted to ground 12.xx MHz
Functional Description
3 - 10
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80dB that has a bandpass-characteristic centred around
10.7MHz. It has an input impedance of 330 Ω=to allow for easy interfacing to a
10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength
Indicator (RSSI) generator which produces a DC voltage that is directly propor-
tional to the input signal level as can be seen in Figure 4.1. This signal is used
to demodulate the ASK receive signal in the subsequent baseband circuitry and
to turn down the LNA gain by approximately 18dB in case the input signal
strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ=on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.7 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of approximately 120kBaud. The maximum
achievable data rate also depends on the IF Filter bandwidth and the local oscil-
lator tolerance values. Both inputs are accessible. The output delivers a digital
data signal (CMOS-like levels) for the detector. The self-adjusting threshold on
pin SLN (pin 20) its generated by RC-term or peak detector depending on the
baseband coding scheme. The data slicer threshold generation alternatives are
described in more detail in Section 4.5.
3.4.8 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The out-
put can be used as an indicator for the signal strength and also as a reference
for the data slicer. The maximum output current is approx. 900µA.
Functional Description
3 - 11
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
3.4.9 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Table 3-3 PDWN Pin Operating States
PDWN Operating State
Open or tied to ground Powerdown Mode
Tied to Vs Receiver On
4Applications
4.1 LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Contents of this Chapter
Applications
4 - 2
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
4.1 LNA and Automatic Gain Control (AGC)
The AGC extends the dynamic range of the receiver.
The automatic gain control in the TDA5204 is a narrow-band control loop which
compares the receive signal strength signal (RSSI, 0.8V to 2.8V) from the lim-
iter with a fixed threshold voltage applied to pin 23 (THRES).
In the following figure the internal circuitry of the LNA automatic gain control is
shown.
LNA_autom.wmf
Figure 4-1 LNA Automatic Gain Control Circuitry
The fixed voltage on pin 23 is generated on the external voltage divider. The
comparator is a transimpedance amplifier (OTA), which creates a positive cur-
rent (+4.2uA) in the case the RSSI level is larger than the threshold voltage.
Otherwise the current is -1.5uA. This leads to an asymmetric fast-attack and
slow-release behaviour and thus to fast reaction to the low gain mode and slow
reaction to the high gain mode.
This current is converted into a control voltage over an external capacitor C
attached to pin 4 (TAGC) which defines the gain of the LNA. The limits of the
control voltages for the LNA on pin4 are 1.67V for high gain mode and Vcc-0.7V
for low gain mode.
Pins: 24 23
4
LNA
R4 R5
U
threshold
RSSI (0.8 - 2.8V)
VCC
Gain control
voltage
OTA
+3V
I
load
RSSI > U
threshold
: I
load
=4.2µA
RSSI < U
threshold
: I
load
= -1.5µA
U
C
C
U
c
:< 2.6V : Gain high
U
c
:> 2.6V : Gain low
U
cmax
= V
CC
- 0.7V
U
cmin
= 1.67V
Applications
4 - 3
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
RSSI-AGC.wmf
Figure 4-2 RSSI Level an Permissive AGC Threhold Level
The value of the capacitor defines the response time of the AGC. For a stable
control loop the capacitor value should be at least 47nF.
The AGC can be disabled by tying the THRES-pin either to GND or to VCC as
show here:
LNA high gain: - pin 23 (THRES) shorted to VCC
LNA low gain: - pin 23 (THRES) shorted to GND
In these cases capacitor and voltage divider are not necessary.
LNA always
in high gain mode
0
0.5
1
1.5
2
2.5
3
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30
Input Level at LNA Input [dBm]
U
THRES
Voltage Range
RSSI Level Range LNA always
in low gain mode
RSSI Level
Applications
4 - 4
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
Filter_Design.wmf
Figure 4-3 Data Filter Design
(1) (2)
with
(3) the quality factor of the poles
where
in case of a Bessel filter a = 1.3617, b = 0.618
and thus Q = 0.577
and in case of a Butterworth filter a = 1.41, b = 1
and thus Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Pins: 22 21 19
RR
100k 100k
C
1
C
2
C12Qb⋅
R2πf3dB
⋅
-------------------------=C2 b
4Q R πf3dB
⋅⋅
----------------------------------=
Qb
a
-------=
Applications
4 - 5
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
quartz specifications given by the quartz manufacturer.
Quartz_load.wmf
Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator
The quartz oscillator input impedance consists of a negative resistance and an
inductance L.
Crystal specified with load capacitance
with CL the load capacitance (refer to the quartz crystal specification).
Examples with typ. values:
6.26 MHz: CL = 12 pF L=21uH CS = 8.6 pF
12.52 MHz: CL = 12 pF L=19uH CS = 5 pF
These values may be obtained by putting two capacitors in series to the quartz.
C
S
Crystal Input
impedance
Z
1-28
TDA5204
Pin 28
Pin 1
()
Lf
C
C
L
S2
2
1
1
π
+
=
Applications
4 - 6
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
4.4 Quartz Frequency Calculation
The quartz frequency is calculated by using the following formula:
ƒQU = (ƒRF ± 10.7MHz) / r (1),
with ƒRF .... receive frequency
+/- ... high-side / low-side injected
ƒLO .... local oscillator (PLL) frequency (ƒRF ± 10.7)
ƒQU .... quartz oscillator frequency
r .... ratio of local oscillator (PLL) frequency and quartz
frequency as shown in the subsequent table.
Example: fRF=390MHz
fQU=(390MHz+10.7MHz) / 64 = 6.2609375MHz
fQU=(390MHz+10.7MHz) / 32 = 12.521875MHz
Table 4-1
frequency range
fRF
high-side
injected
low-side
injected
FSEL
Pin11
385...406MHz Xopen
406...428MHz Xopen
781...823MHz XGND
803...844MHz XGND
Table 4-3
FSEL CSEL Ratio r
(fLO/fQU)
open open 64
open GND 32
GND open 128
GND GND 64
Table 4-2
quartz crystal
range
CSEL
Pin16
6.xx MHz open
12.xx MHz GND
Applications
4 - 7
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated in two ways, depending on
the signal coding scheme used. In case of a signal coding scheme without DC
content such as Manchester coding the threshold can be generated using an
external R-C integrator as shown in the following . The cut-off frequency of the
R-C integrator has to be lower than the lowest frequency appearing in the data
signal. In order to keep distortion low, the minimum value for R is 20kΩ.
Data_slice1.wmf
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in con-
nection with two resistors and one capacitor as shown in the following figure.
The component values are depending on the coding scheme and the protocol
used.
Data_slice2.wmf
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector
Pins: 2019
R
C
25
data out
U
threshold
data slicer
data
filter
Pins: 20
19 25
data out
U
threshold
data slicer
data
filter
26
peak detector
C
R
R
5 Reference
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Contents of this Chapter
Reference
5 - 2
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C
#Parameter Symbol Limit Values Unit Remarks
min max
1Supply Voltage Vs-0.3 5.5 V
2Junction Temperature Tj-40 +125 °C
3Storage Temperature Ts-60 +150 °C
4Thermal Resistance RthJA 114 K/W
5ESD integrity, all pins VESD -1 +1 kV HBM
according to
MIL STD
883D,
method
3015.7
Reference
5 - 3
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
5.1.2 Operating Range
Within the operating range the IC operates as explained in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C
#Parameter Symbol Limit Values Unit Test Conditions L Item
min max
1Supply Current IS 6.4 mA fRF = 390MHz
2Power Down Current IPWDN 250 nA
3Receiver Input Level RFin -110 -13 dBm @ source impedance 50Ω,
BER 2E-3, average power
level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth, with AGC
4Receive Frequency fRF 385 406 MHz
This value is guaranteed by design.
Reference
5 - 4
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
5.1.3 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the spec-
ified voltage and ambient temp. range. Typical characteristics are the median
of the production. The device performance parameters marked with
were
measured on an Infineon evaluation board as desdribed in Section 5.2. Cur-
rents flowing into the device are denoted as positive currents and vice versa.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
#Parameter Symbol Limit Values Unit Test Conditions L Item
min typ max
Supply
Supply Current
1Supply current,
standby mode
IS PDWN 50 150 nA Pin 27 (PDWN)
open or tied to 0 V
2Supply current IS4.8 5.5 mA
LNA
Signal Input LNI (PIN 3), high gain mode
1Average Power Level
at BER = 2E-3
(Sensitivity)
RFin -112 dBm Manchester
encoded datarate
4kBit, 280kHz IF
Bandwidth
2Input impedance,
fRF = 390 MHz
S11 LNA 0.879 / -31 deg
3Input level @ 1dB C.P.
fRF=390 MHz
P1dBLNA -14 dBm
4Input 3rd order intercept
point fRF = 390 MHz
IIP3LNA -10 dBm fin = 390MHz
5LO signal feedthrough at
antenna port
LOLNI -119 dBm
Signal Output LNO (PIN 6), high gain mode
1Gain fRF = 390 MHz S21 LNA 1.578 / 141.8deg
2Output impedance,
fRF = 390 MHz
S22 LNA 0.8822 / -12.13deg
3Voltage Gain Antenna to
MI fRF = 390 MHz
GAntMI 21 dB
4Noise Figure NFLNA 2dB excluding matching
network loss - see
Appendix
Signal Input LNI, low gain mode
1Input impedance,
fRF = 390 MHz
S11 LNA 0.903 / -31.8deg
2Input level @ 1dB C. P.
fRF = 390 MHz
P1dBLNA -7 dBm matched input
Reference
5 - 5
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter Symbol Limit Values Unit Test Conditions LItem
min typ max
Signal Input LNI, VTHRES = GND, low gain mode
3Input 3rd order intercept
point fRF = 390 MHz
IIP3LNA -13 dBm fin = 390MHz
Signal Output LNO, VTHRES = GND, low gain mode
1Gain fRF = 390 MHz S21 LNA 0.1834 / 144deg
2Output impedance,
fRF = 390 MHz
S22 LNA 0.897 / -12.4deg
3Voltage Gain Antenna to
MI fRF = 390 MHz
GAntMI 2dB
Signal 3VOUT (PIN 24)
1Output voltage V3VOUT 2.9 3 3.1 V
2Load current out I3VOUT -50 µA
Signal THRES (PIN 23)
1Input Voltage range VTHRES 0 VSVsee chapter 4.1
2LNA low gain mode VTHRES 00.5 V
3LNA high gain mode VTHRES 3.3 VSV
4Current in ITHRES_in -5 nA
Signal TAGC (PIN 4)
1Current out,
LNA low gain state
ITAGC_out -2.5 -4.2 -5.5 µA RSSI > VTHRES
2Current in,
LNA high gain state
ITAGC_in 0.5 1.5 4µARSSI < VTHRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1Input impedance,
fRF = 390 MHz
S11 MIX 0.9413 / -13.1deg
2Input 3rd order intercept
point
IIP3MIX -25 dBm
Signal Output IFO (PIN 12)
1Output impedance ZIFO 330 Ω
2Conversion Voltage Gain
fRF=390 MHz
GMIX +21 dB
3Noise Figure, SSB
(~DSB NF+3dB)
NFMIX 13 dB
4RF to IF isolation ARF-IF 46 dB
Reference
5 - 6
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter Symbol Limit Values Unit Test Conditions LItem
min typ max
LIMITER
Signal Input LIM/X (PINS 17/18)
1 Input Impedance ZLIM 264 330 396 Ω
2RSSI dynamic range DRRSSI 60 70 80 dB
3RSSI linearity LINRSSI ±1dB
4Operating frequency (3dB
points)
fLIM 5 10.7 23 MHz
5RSSI Level at Data Filter
Output SLP
RSSIlow 0.4 0.8 1.2 V Limiter_in: 10uV
6RSSI Level at Data Filter
Output SLP
RSSIhigh 2.3 2.8 3.2 V Limiter_in: 100mV
DATA FILTER
1Max. useable bandwidth BWBB
FILT
100 kHz
SLICER
Signal Output DATA (PIN 25)
1Max. useable bandwith BWBB
SLIC
100 kHz
2LOW output voltage VSLIC_L 0100 mV
3HIGH output voltage VSLIC_H Vs-1.2 VS-1 Vs-0.7 V
4Output current ISLIC_out -400 -800 -1100 µA high level drive
5Output impedance Rout 60 80 100 kΩlow level drive
PEAK DETECTOR
Signal Output PDO (PIN 26)
1Load current Iload -500 -950 -1200 µA
2Leakage current Ileakage 07002000 nA
Reference
5 - 7
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter Symbol Limit Values Unit Test Conditions LItem
min typ max
CRYSTAL OSCILLATOR
Signals CRSTL1, CRISTL 2, (PINS 1/28)
1Operating frequency fCRSTL 114 MHz fundamental mode,
series resonance
2Negative Resistance
@ ~6MHz
Re{Z1-28}-750 Ω
3Negatve Resitance
@ ~12MHz
Re{Z1-28}-450 Ω
4Input Indutance
@ ~6MHz
Im{Z1-28}/
2π f
21 uH
5Input Inductance
@ ~12MHz
Im{Z1-28}/
2π f
19 uH
PLL
Signal LF (PIN 15)
1Tuning voltage relative to
Vs
VTUNE 0.5 1.05 2V
POWER DOWN Pin
Signal PDWN (PIN 27)
1Powerdown Mode On PWDNON 00.8 V
2Powerdown Mode Off PWDNOff 2.8 VSV
3Input bias current IPWD 19 uA Power On Mode
4Start-up Time until valid IF
signal is detected
TSU 1ms
PLL DIVIDER
Signal CSEL (PIN 16)
1fCRSTL range 6.xxMHz VCSEL 1.4 4Vor open
2 fCRSTL range 12.xxMHz VCSEL 00.2 V
3Bias current CSEL ICSEL -5 µA CSEL tied to GND
Measured only in lab.
Reference
5 - 8
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
5.2 Test Circuit
The device performance parameters marked with
in Section 5.1.3 were mea-
sured on an Infineon evaluation board. This evaluation board can be obtained
together with evaluation boards of the accompanying transmitter device
TDA51xx in an evaluation kit that may be ordered on the INFINEON RKE
Webpage www.infineon.com/rke
Test_circuit.wmf
Figure 5-1 Schematic of the Evaluation Board
Infineon Technologies Design Center Graz
TITLE: TDA5200 /-01 /-02 Evaluation Board
FILE: -10 V 2.0
DATE: Jul.19, 1999
Reference
5 - 9
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
5.3 Test Board Layouts
Figure 5-2 Top Side of the Evaluation Board (TDA5210 Testboard is the same)
Figure 5-3 Bottom Side of the Evaluation Board
Reference
5 - 10
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
Figure 5-4 Component Placement on the Evaluation Board
Reference
5 - 11
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5204 at
390MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials
Ref Value Specification
R1 100kΩ0805, ± 5%
R2 100kΩ0805, ± 5%
R3 820kΩ0805, ± 5%
R4 120kΩ0805, ± 5%
R5 180kΩ0805, ± 5%
R6 10kΩ0805, ± 5%
L1 15nH Toko, PTL2012-F15N0G
L2 10pF a0805,COG, ± 2%
C1 1.8pF 0805, COG, ± 0.1pF
C2 6.8pF 0805, COG, ± 0.1pF
C3 6.8pF 0805, COG, ± 0.1pF
C4 100pF 0805, COG, ± 5%
C5 47nF 1206, X7R, ± 10%
C6 12nH b Toko, PTL2012-F15N0G
C7 100pF 0805, COG, ± 5%
C8 33pF 0805, COG, ± 5%
C9 100pF 0805, COG, ± 5%
C10 10nF 0805, X7R, ± 10%
C11 10nF 0805, X7R, ± 10%
C12 220pF 0805, COG, ± 5%
C13 47nF 0805, X7R, ± 10%
C14 470pF 0805, COG, ± 5%
C15 47nF 0805, X7R, ± 10%
C16 12pF 0805, COG, ± 0.1pF
C17 12pF 0805, COG, ± 2%
Q2 (390MHz + 10.7MHz)/32 HC49/U, fundamental mode, CL = 12pF,
12.521875 MHz: Jauch Q12.521875-S11-1252-12-10/20
F1 SFE10.7MA5-A Murata
X2, X3 142-0701-801 Johnson
X1, X4, S1, S5 2-pole pin connector
S4 3-pole pin connector, or not equipped
IC1 TDA 5204 Infineon
a. / b. The coil is at the place of the capacity and vice versa.
Reference
5 - 12
TDA 5204 E1
preliminary
Wireless Components
Specification, January 2001
The following components are necessary in addition to the above mentioned
ones for evaluation of the TDA5204 in conjunction with a Microchip HCS515
decoder.
Table 5-5 Bill of Materials Addendum
Ref Value Specification
R21 22kΩ0805, ± 5%
R22 100kΩ0805, ± 5%
R23 22kΩ0805, ± 5%
R24 820kΩ0805, ± 5%
R25 560kΩ0805, ± 5%
C21 100nF 1206, X7R, ± 10%
C22 100nF 1206, X7R, ± 10%
IC2 HCS515 Microchip
T1 BC 847B Infineon
D1 LS T670-JL Infineon
List of Figures
List of Figures - 1
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
List of Figures
Figure 2-1 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 4-1 LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Figure 4-2 RSSI Level an Permissive AGC Threhold Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . 4-5
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . 4-7
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . 4-7
Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Figure 5-2 Top Side of the Evaluation Board (TDA5210 Testboard is the same) . . . . . . . . . . . . . . 5-9
Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
List of Tables
List of Tables - 1
TDA 5204 E1
preliminary
Wireless Components
Specification, December 2000
List of Tables
Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Table 3-3 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C . . . . . . . . . 5-2
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C . . . . . . . . . . . . . . . . . 5-3
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . 5-4
Table 5-4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-5 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12
