DS07-13748-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90860E Series
MB90867E(S), MB90F867E(S),
MB90V340E-101/102
■DESCRIPTION
MB90860E-series with Flash ROM is especially designed for automotive and other industrial applications. With
the new 0.35 µm CMOS technology, Fujitsu now offers on-chip Flash ROM program memory up to 512 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
MB90860E Series
2
■FEATURES
• CPU
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes(23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Serial interface
• UART (LIN/SCI) : up to 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
•I
2C interface* : up to 2 channels
• Up to 400 Kbits/s transfer rate
• Interrupt controller
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• Automatic data transfer function independent of CPU
• Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
• 8/10-bit A/D converter
• 8/10-bit A/D converter : 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 16 channels, or 16-bit × 8 channels
• 16-bit reload timer : 4 channels
• 16-bit input/output timer
- 16-bit free run timer : 2 channel
(FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16-bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
MB90860E Series
3
• Variety of mode
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (time-base timer mode that is transferred from main clock mode)
• PLL timer mode (time-base timer mode that is transferred from PLL clock mode)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Technology
•0.35 µm CMOS technology
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-
ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
MB90860E Series
4
■PRODUCT LINEUP
(Continued)
MB90867E(S) MB90F867E(S) MB90V340E-101/102
CPU F2MC-16LX CPU
Type MASK ROM product Flash memory product Evaluation product
System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
ROM MASK ROM
128 Kbytes
Flash memory
128 Kbytes External
RAM 6 Kbytes 6 Kbytes 30 Kbytes
Emulator-specific
power supply*1⎯Yes
Technology
0.35 µm CMOS with on-chip
voltage regulator for internal
power supply
0.35 µm CMOS with on-chip
voltage regulator for internal
power supply + Flash memory
with on-chip charge pump for
programming voltage
0.35 µm CMOS with on-chip
voltage regulator for internal
power supply
Operating
voltage range
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
5 V ± 10%
Temperature range −40 °C to +105 °C⎯
Package QFP-100, LQFP-100 PGA-299
UART
4 channels 5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbps) 2 channels
8/10-bit
A/D converter
24 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit reload timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
16-bit
I/O timer
(2 channels)
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (ch.0, ch.4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit output
compare
(8 channels)
Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit input capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
Part Number
Parameter
MB90860E Series
5
(Continued)
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
MB90867E(S) MB90F867E(S) MB90V340E-101/102
8/16-bit
programmable pulse
generator
(8 channels)
Supports 8-bit and 16-bit operation modes
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
CAN interface ⎯3 channels
External interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A converter ⎯2 channels
Up to 100 kHz
sub clock for low
power operation
Devices without ‘S’-suffix Only for MB90V340E-
102
I/O ports
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable in pin-wise of 8 as CMOS schmitt trigger/automotive inputs (default)
TTL input level settable for external bus (32-pin only for external bus)
Flash memory
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
⎯
Part Number
Parameter
MB90860E Series
6
■PIN ASSIGNMENTS
• MB90V340E-101/102
(Continued)
(TOP VIEW)
(FPT-100P-M06)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15/SCK4
P16/AD14/SOT4
P15/AD13/SIN4
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
301 8
P75/AN21/INT5
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
MD0
MD1
MD2
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P56/AN14/DA00
P55/AN13
P54/AN12/TOT3
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
QFP - 100
21201716 19181514131211 2625242322 27 2829435629710
80515871 70 67 6669 6865 64 6362 6176 75 74 7372777879 54 535556 5259 5760
P57/AN15/DA01
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P60/AN0/PPG0(1)
P61/AN1/PPG2(3)
P62/AN2/PPG4(5)
P63/AN3/PPG6(7)
P64/AN4/PPG8(9)
P65/AN5/PPGA(B)
P66/AN6/PPGC(D)
P67/AN7/PPGE(F)
Vss
P70/AN16/INT0
P71/AN17/INT1
AVcc
AVRH
AVRL
AVss
RST
P31/RD/IN5
P32/WRL/WR/RX2/INT10R
P33/WRH/TX2
P35/HAK/OUT5
MB90860E Series
7
(Continued)
(TOP VIEW)
(FPT-100P-M05)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
75
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15/SCK4
P16/AD14/SOT4
P15/AD13/SIN4
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15/DA01
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
MD0
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
LQFP - 100
99P24/A20/IN0
100P25/A21/IN1
28P56/AN14/DA00
27 P55/AN13
26 P54/AN12/TOT3
49 MD2
50 MD1
78P03/AD03/INT11
77P02/AD02/INT10
76P01/AD01/INT9
74 7372 71 70 69 6867 66 65 64 6362 61 60 5859 555657 54 5352 51
123456789 1011121314 15 16 1817 212019 22 2324 25
RST
P31/RD/IN5
P32/WRL/WR/RX2/INT10R
P33/WRH/TX2
P35/HAK/OUT5
MB90860E Series
8
• MB90867E(S)/MB90F867E(S)
(Continued)
(TOP VIEW)
(FPT-100P-M06)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P75/AN21/INT5
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1
PA0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
MD0
MD1
MD2
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P56/AN14
P55/AN13
P54/AN12/TOT3
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7
P42/IN6/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
QFP - 100
80797877 76 75 74 7372 71 70 69 6867 66 65 64 6362 61 60 59 5857 56 55 54 5352 51
123456789 1011121314 15 16 17 1819 20 21 22 2324 25 26 27 2829 30
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P61/AN1/PPG2(3)
AVss
P57/AN15
AVcc
P60/AN0/PPG0(1)
AVRL
AVRH
Vss
P62/AN2/PPG4(5)
P63/AN3/PPG6(7)
RST
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
P32/WRL/WR/INT10R
* : X0A, X1A : MB90867E, MB90F867E
P40, P41 : MB90867ES/MB90F867ES
MB90860E Series
9
(Continued)
(TOP VIEW)
(FPT-100P-M05)
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P00/AD00/INT8
PA1
PA0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
MD0
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7
P42/IN6/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
99P24/A20/IN0
100P25/A21/IN1
28P56/AN14
27 P55/AN13
26 P54/AN12/TOT3
49 MD2
50 MD1
78P03/AD03/INT11
77P02/AD02/INT10
76P01/AD01/INT9
LQFP - 100
75 74 7372 71 70 69 6867 66 65 64 6362 61 60 59 5857 56 55 54 5352 51
123456789 1011121314 15 16 17 1819 20 21 22 2324 25
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
RST
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
P32/WRL/WR/INT10R
* : X0A, X1A : MB90867E, MB90F867E
P40, P41 : MB90867ES, MB90F867ES
MB90860E Series
10
■PIN DESCRIPTION
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3
Function
QFP100*1LQFP100*2
1 to 4 99 to 2
P24 to P27
G
General purpose I/O pins. The register can be set to select
whether to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding bit
in the external address output control register (HACR) is 1.
A20 to A23
Output pins of the external address bus. When the corresponding
bit in the external address output control register (HACR) is 0, the
pins are enabled as high address output pins (A20 to A23).
IN0 to IN3 Trigger input pins for input captures 0 to 3.
53
P30
G
General purpose I/O pin.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
ALE Address latch enable output pin. This function is enabled when
the external bus is enabled.
IN4 Trigger input pin for input capture 4.
64
P31
G
General purpose I/O pin.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
RD External read strobe output pin. This function is enabled when the
external bus is enabled.
IN5 Trigger input pin for input capture 5.
75
P32
G
General purpose I/O pin. The register can be set to select whether
to use a pull-up resistor. This function is enabled either in single-
chip mode or with the WR/WRL pin output disabled.
WR / WRL
Write strobe output pin for the external data bus. This function is
enabled when both the external bus and the WR/WRL pin output
are enabled. WRL is used to write-strobe 8 lower bits of the data
bus in 16-bit access while WR is used to write-strobe 8 bits of the
data bus in 8-bit access.
INT10R External interrupt request input pin (sub) .
86
P33
G
General purpose I/O pin. The register can be set to select whether
to use a pull-up resistor.This function is enabled either in single-
chip mode or with the WRH pin output disabled.
WRH
Write strobe output pin for the 8 higher bits of the external data
bus. This function is enabled when the external bus is enabled,
when the external bus 16-bit mode is selected, and when the
WRH output pin is enabled.
MB90860E Series
11
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3
Function
QFP100*1LQFP100*2
97
P34
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the hold function disabled.
HRQ Hold request input pin. This function is enabled when both the
external bus and the hold function are enabled.
OUT4 Waveform output pin for output compare 4.
10 8
P35
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the hold function disabled.
HAK Hold acknowledge output pin. This function is enabled when
both the external bus and the hold function are enabled.
OUT5 Waveform output pin for output compare 5.
11 9
P36
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the external ready function disabled.
RDY External ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
OUT6 Waveform output pin for output compare 6.
12 10
P37
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the clock output disabled.
CLK Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
OUT7 Waveform output pin for output compare 7.
13, 14 11, 12
P40, P41 F General purpose I/O pins.
(devices with S-suffix)
X0A , X1A B Input pins for sub-clock
(devices without S-suffix)
15 13 VCC ⎯Power (3.5 V to 5.5 V) input pin
16 14 VSS ⎯GND pin
17 15 C K
This is the power supply stabilization capacitor pin. It should be
connected to a higher than or equal to 0.1 µF ceramic
capacitor.
18 16
P42
F
General purpose I/O pin.
IN6 Trigger input pin for input capture 6.
INT9R External interrupt request input pin (sub)
MB90860E Series
12
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3
Function
QFP100*1LQFP100*2
19 17 P43 FGeneral purpose I/O pin.
IN7 Trigger input pin for input capture 7.
20 18
P44
H
General purpose I/O pin.
SDA0 Serial data I/O pin for I2C 0
FRCK0 Input pin for the 16-bit I/O Timer 0
21 19
P45
H
General purpose I/O pin.
SCL0 Serial clock I/O pin for I2C 0
FRCK1 Input pin for the 16-bit I/O Timer
22 20 P46 HGeneral purpose I/O pin.
SDA1 Serial data I/O pin for I2C 1
23 21 P47 HGeneral purpose I/O pin.
SCL1 Serial clock I/O pin for I2C 1
24 22
P50
O
General purpose I/O pin.
AN8 Analog input pin for the A/D converter
SIN2 Serial data input pin for UART2
25 23
P51
I
General purpose I/O pin.
AN9 Analog input pin for the A/D converter
SOT2 Serial data output pin for UART2
26 24
P52
I
General purpose I/O pin.
AN10 Analog input pin for the A/D converter
SCK2 Clock I/O pin for UART2
27 25
P53
I
General purpose I/O pin.
AN11 Analog input pin for the A/D converter
TIN3 Event input pin for the reload timer 3
28 26
P54
I
General purpose I/O pin.
AN12 Analog input pin for the A/D converter
TOT3 Output pin for the reload timer 3
29 27 P55 IGeneral purpose I/O pin.
AN13 Analog input pin for the A/D converter
30, 31 28, 29 P56, P57 JGeneral purpose I/O pins.
AN14, AN15 Analog input pin for the A/D converter
32 30 AVCC K Power input pin for the A/D Converter analog
MB90860E Series
13
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3
Function
QFP100*1LQFP100*2
33 31 AVRH L
Reference voltage input pin for the A/D Converter. This power
supply must be turned on or off while a voltage higher than or
equal to AVRH is applied to AVCC.
34 32 AVRL K Lower reference voltage input pin for the A/D Converter
35 33 AVSS K GND pin for the A/D Converter analog
36 to 43 34 to 41
P60 to P67
I
General purpose I/O pins.
AN0 to AN7 Analog input pins for the A/D converter
PPG0, 2, 4, 6,
8, A, C, E Output pins for PPGs
44 42 VSS ⎯GND pin
45 to 50 43 to 48
P70 to P75
I
General purpose I/O pins.
AN16 to AN21 Analog input pins for the A/D converter
INT0 to INT5 External interrupt request input pins
51 49 MD2 D Input pin for specifying the operating mode.
52, 53 50, 51 MD1, MD0 C Input pins for specifying the operating mode.
54 52 RST E Reset input
55, 56 53, 54
P76, P77
I
General purpose I/O pins.
AN22, AN23 Analog input pins for the A/D converter
INT6, INT7 External interrupt request input pins
57 55
P80
F
General purpose I/O pin.
TIN0 Event input pin for the reload timer 0
ADTG Trigger input pin for the A/D converter
INT12R External interrupt request input pin (sub)
58 56
P81
F
General purpose I/O pin.
TOT0 Output pin for the reload timer 0
CKOT Output pin for the clock monitor
INT13R External interrupt request input pin (sub)
59 57
P82
M
General purpose I/O pin.
SIN0 Serial data input pin for UART0
TIN2 Event input pin for the reload timer 2
INT14R External interrupt request input pin (sub)
60 58
P83
F
General purpose I/O pin.
SOT0 Serial data output pin for UART0
TOT2 Output pin for the reload timer 2
61 59
P84
F
General purpose I/O pin.
SCK0 Clock I/O pin for UART0
INT15R External interrupt request input pin (sub)
MB90860E Series
14
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3
Function
QFP100*1LQFP100*2
62 60 P85 MGeneral purpose I/O pin.
SIN1 Serial data input pin for UART1
63 61 P86 FGeneral purpose I/O pin.
SOT1 Serial data output pin for UART1
64 62 P87 FGeneral purpose I/O pin.
SCK1 Clock I/O pin for UART1
65 63 VCC ⎯Power (3.5 V to 5.5 V) input pins
66 64 VSS ⎯GND pins
67 to 70 65 to 68 P90 to P93 FGeneral purpose I/O pin
PPG1, 3, 5, 7 Output pins for PPGs
71 to 74 69 to 72
P94 to P97
F
General purpose I/O pin
OUT0 to
OUT3
Waveform output pins for output compares 0 to 3. This function
is enabled when the OCU enables waveform output.
75 73 PA0 FGeneral purpose I/O pin.
INT8R External interrupt request input pin (sub)
76 74 PA1 F General purpose I/O pin.
77 to 84 75 to 82
P00 to P07
G
General purpose I/O pins. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
INT8 to INT15 External interrupt request input pins.
85 83
P10
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD08 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
TIN1 Event input pin for the reload timer 1
86 84
P11
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD09 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
TOT1 Output pin for the reload timer 1
MB90860E Series
15
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3
Function
QFP100*1LQFP100*2
87 85
P12
N
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD10 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
SIN3 Serial data input pin for UART3
INT11R External interrupt request input pin (sub)
88 86
P13
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD11 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
SOT3 Serial data output pin for UART3
89 87
P14
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD12 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
SCK3 Clock I/O pin for UART3
90 88 VCC ⎯Power (3.5 V to 5.5 V) input pin
91 89 VSS ⎯GND pin
92 90 X1 AMain clock output pin
93 91 X0 Main clock input pin
94 92
P15
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD13 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
95 93
P16
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD14 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
96 94
P17
G
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
AD15 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
MB90860E Series
16
(Continued)
*1 : FPT-100P-M06
*2 : FPT-100P-M05
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
Pin No.
Pin name
I/O
Circuit
type*3
Function
QFP100*1LQFP100*2
97 to 100 95 to 98
P20 to P23
G
General purpose I/O pins. The register can be set to select
whether to use a pull-up resistor.In external bus mode, the pin
is enabled as a general-purpose I/O port when the
corresponding bit in the external address output control
register (HACR) is 1.
A16 to A19
Output pins of the external address bus. When the
corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A16 to A19).
PPG9,PPGB,
PPGD,PPGF Output pins for PPGs
MB90860E Series
17
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
• Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 MΩ
B
• Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 MΩ
C
• Mask ROM and evaluation device:
CMOS Hysteresis input pin
• Flash device:
CMOS input pin
D
• Mask ROM and evaluation device:
CMOS Hysteresis input pin
Pull-down resistor value: approx. 50 kΩ
• Flash memory device:
CMOS input pin
No Pull-down
E
CMOS Hysteresis input pin
Pull-up resistor value: approx. 50 kΩ
Standby control signal
X1
X0
Xout
Standby control signal
X1A
X0A
Xout
Hysteresis
inputs
R
Pull-down
Resistor
Hysteresis
inputs
R
Pull-up
Resistor
Hysteresis
inputs
R
MB90860E Series
18
(Continued)
Type Circuit Remarks
F
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
G
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
• Programmable pull-up resistor: 50 kΩ
approx.
H
• CMOS level output (IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
Pull-up control
Hysteresis inputs
Automotive inputs
TTL input
Standby control for
input shutdown
Pout
Nout
R
N-ch
P-ch
P-ch
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
MB90860E Series
19
(Continued)
Type Circuit Remarks
I
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time in-
put shutdown function)
• A/D converter analog input
J
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• D/A analog output
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time in-
put shutdown function)
• A/D converter analog input
K
Power supply input protection circuit
L
• A/D converter reference voltage power
supply input pin, with the protection circuit
• Flash devices do not have a protection
circuit against VCC for pin AVRH
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
Pout
Nout
R
N-ch
P-ch
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
Analog output
Pout
Nout
R
P-ch
N-ch
P-ch
N-ch
ANE
AVR
ANE
P-ch
N-ch
MB90860E Series
20
(Continued)
Type Circuit Remarks
M
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
N
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
Programmable pull-up registor:50 kΩ
approx
O
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• A/D converter analog input
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
Pull-up control
CMOS inputs
Automotive inputs
TTL input
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
P-ch
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
Pout
Nout
R
P-ch
N-ch
MB90860E Series
21
■HANDLING DEVICES
1. Preventing latch-up
CMOS IC may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device
4. Mode Pin (MD0 to MD2)
Connect the mode pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection.
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90860E
Series
Vcc Vss
Vcc
Vss
MB90860E Series
22
5. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable) .
6. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
7. Crystal Oscillator Circuit
X0, X1 pins and X0A, X1A pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic oscillator)
and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other
circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
8. Pull-up/down resistors
The MB90860E Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
9. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
10. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
11. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the MB90860 series attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
12. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V)
X0
X1
MB90860E Series
Open
MB90860E Series
23
13. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For the reference, stabilize the supply voltage by setting the following value.
•V
CC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the
standard VCC supply voltage
• The coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
14. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
15. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, in spite of reset input, there is a possibility that
output signal of Port 0 to Port 3 might be unstable.
16. Flash security Function
The security bit is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
Flash memory size Address for security bit
MB90F867E(S) Embedded 1 Mbit Flash Memory FE0001H
Port 0 to Port 3 outputs
might be unstable
Port 0 to Port 3 outputs = Hi-Z
Port 0 to Port 3
VCC
1/2VCC
MB90860E Series
24
■BLOCK DIAGRAMS
• MB90V340E-101/102
RAM
UART
Prescaler
8/10-bit
24 channels
16-bit Reload
Timer
I/O Timer 0
Clock
Controller
Input
Capture
8 channels
Output
Compare
8 channels
CAN
Controller
External
Interrupt
16LX
CPU
F2MC-16 Bus
X0,X1
RST
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
TIN3 to TIN0
TOT3 to TOT0
IN7 to IN0
OUT7 to OUT0
RX2 to RX0
TX2 to TX0
INT15 to INT8
External
Bus
Interface
AD15 to AD00
A23 to A16
ALE
RD
WR/WRL
WRH
HRQ
HAK
RDY
CLK
X0A,X1A*
5 channels
10-bit
DAC
2 channels
DA01, DA00
I/O Timer 1
FRCK0
FRCK1
8/16-bit
PPG
16 channels
PPGF to PPG0
I2C
Interface
SDA1, SDA0
SCL1, SCL0
3 channels
5 channels
2 channels
DMAC
* : Only for MB90V340E-102
Clock
Monitor CKOT
(INT15R to INT8R)
INT7 to INT0
ADC
16 channels
30 Kbytes
4 channels
MB90860E Series
25
• MB90867E(S), MB90F867E(S)
RAM
ROM/Flash
UART
Prescaler
8/10-bit
24 channels
16-bit Reload
Timer
I/O Timer 0
Clock
Controller
Input
Capture
8 channels
Output
Compare
8 channels
External
Interrupt
16LX
CPU
F2MC-16 Bus
X0,X1
RST
SOT3 to SOT0
SCK3 to SCK0
SIN3 to SIN0
AVCC
AVSS
AN15 to AN0
AVRH
AVRL
ADTG
TIN3 to TIN0
TOT3 to TOT0
IN7 to IN0
OUT7 to OUT0
INT15 to INT8
External
Bus
Interface
AD15 to AD00
A23 to A16
ALE
RD
WR/WRL
WRH
HRQ
HAK
RDY
CLK
X0A,X1A*
128 Kbytes
4 channels
I/O Timer 1
FRCK0
FRCK1
8/16-bit
PPG
16 channels
PPGF to PPG0
4 channels
I2C
Interface
SDA1, SDA0
SCL1, SCL0
2 channels
AN23 to AN16
6 Kbytes
DMAC
* : Only for devices without ‘S’ Suffix
Clock
Monitor CKOT
(INT15R to INT8R)
INT7 to INT0
ADC
16 channels
4 channels
MB90860E Series
26
■MEMORY MAP
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
MB90V340E-101/102
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
FDFFFF
H
FD0000
H
FCFFFF
H
FC0000
H
FBFFFF
H
FB0000
H
FAFFFF
H
FA0000
H
F9FFFF
H
F90000
H
F8FFFF
H
F80000
H
00FFFF
H
008000
H
007FFF
H
007900
H
0078FF
H
000100
H
0000EF
H
000000
H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM
(image of FF bank)
Peripheral
RAM 30 Kbytes
Peripheral
External access area
: No access
MB90867E(S)
MB90F867E(S)
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
0000EF
H
000000
H
00FFFF
H
007FFF
H
007900
H
003FFF
H
000100
H
008000
H
External
access area
ROM (image
of FF bank)
Peripheral
RAM 6 Kbytes
External access area
Peripheral
ROM (FF bank)
ROM (FE bank)
External access area
MB90860E Series
27
■I/O MAP
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
000000HPort 0 Data Register PDR0 R/W Port 0 XXXXXXXXB
000001HPort 1 Data Register PDR1 R/W Port 1 XXXXXXXXB
000002HPort 2 Data Register PDR2 R/W Port 2 XXXXXXXXB
000003HPort 3 Data Register PDR3 R/W Port 3 XXXXXXXXB
000004HPort 4 Data Register PDR4 R/W Port 4 XXXXXXXXB
000005HPort 5 Data Register PDR5 R/W Port 5 XXXXXXXXB
000006HPort 6 Data Register PDR6 R/W Port 6 XXXXXXXXB
000007HPort 7 Data Register PDR7 R/W Port 7 XXXXXXXXB
000008HPort 8 Data Register PDR8 R/W Port 8 XXXXXXXXB
000009HPort 9 Data Register PDR9 R/W Port 9 XXXXXXXXB
00000AHPort A Data Register PDRA R/W Port A XXXXXXXXB
00000BHPort 5 Analog Input Enable Register ADER5 R/W Port 5, A/D 11111111B
00000CHPort 6 Analog Input Enable Register ADER6 R/W Port 6, A/D 11111111B
00000DHPort 7 Analog Input Enable Register ADER7 R/W Port 7, A/D 11111111B
00000EHInput Level Select Register 0 ILSR0 R/W Ports XXXXXXXXB
00000FHInput Level Select Register 1 ILSR1 R/W Ports XXXX0XXXB
000010HPort 0 Direction Register DDR0 R/W Port 0 00000000B
000011HPort 1 Direction Register DDR1 R/W Port 1 00000000B
000012HPort 2 Direction Register DDR2 R/W Port 2 00000000B
000013HPort 3 Direction Register DDR3 R/W Port 3 00000000B
000014HPort 4 Direction Register DDR4 R/W Port 4 00000000B
000015HPort 5 Direction Register DDR5 R/W Port 5 00000000B
000016HPort 6 Direction Register DDR6 R/W Port 6 00000000B
000017HPort 7 Direction Register DDR7 R/W Port 7 00000000B
000018HPort 8 Direction Register DDR8 R/W Port 8 00000000B
000019HPort 9 Direction Register DDR9 R/W Port 9 00000000B
00001AHPort A Direction Register DDRA R/W Port A 00000100B
00001BHReserved
00001CHPort 0 Pull-up Control Register PUCR0 R/W Port 0 00000000B
00001DHPort 1 Pull-up Control Register PUCR1 R/W Port 1 00000000B
00001EHPort 2 Pull-up Control Register PUCR2 R/W Port 2 00000000B
00001FHPort 3 Pull-up Control Register PUCR3 W, R/W Port 3 00000000B
MB90860E Series
28
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
000020HSerial Mode Register 0 SMR0 W,R/W
UART0
00000000B
000021HSerial Control Register 0 SCR0 W,R/W 00000000B
000022HReception/Transmission Data Register 0 RDR0/
TDR0 R/W 00000000B
000023HSerial Status Register 0 SSR0 R,R/W 00001000B
000024HExtended Communication Control
Register 0 ECCR0 R,W,
R/W 000000XXB
000025HExtended Status/Control Register 0 ESCR0 R/W 00000100B
000026HBaud Rate Generator Register 00 BGR00 R/W 00000000B
000027HBaud Rate Generator Register 01 BGR01 R/W 00000000B
000028HSerial Mode Register 1 SMR1 W,R/W
UART1
00000000B
000029HSerial Control Register 1 SCR1 W,R/W 00000000B
00002AHReception/Transmission Data Register 1 RDR1/
TDR1 R/W 00000000B
00002BHSerial Status Register 1 SSR1 R,R/W 00001000B
00002CHExtended Communication Control
Register 1 ECCR1 R,W,
R/W 000000XXB
00002DHExtended Status/Control Register 1 ESCR1 R/W 00000100B
00002EHBaud Rate Generator Register 10 BGR10 R/W 00000000B
00002FHBaud Rate Generator Register 11 BGR11 R/W 00000000B
000030HPPG 0 Operation Mode Control Register PPGC0 W,R/W
16-bit PPG 0/1
0X000XX1B
000031HPPG 1 Operation Mode Control Register PPGC1 W,R/W 0X000001B
000032HPPG 0/PPG 1 Count Clock Select Register PPG01 R/W 000000X0B
000033HReserved
000034HPPG 2 Operation Mode Control Register PPGC2 W,R/W
16-bit PPG 2/3
0X000XX1B
000035HPPG 3 Operation Mode Control Register PPGC3 W,R/W 0X000001B
000036HPPG 2/PPG 3 Count Clock Select Register PPG23 R/W 000000X0B
000037HReserved
000038HPPG 4 Operation Mode Control Register PPGC4 W,R/W
16-bit PPG 4/5
0X000XX1B
000039HPPG 5 Operation Mode Control Register PPGC5 W,R/W 0X000001B
00003AHPPG 4/PPG 5 Clock Select Register PPG45 R/W 000000X0B
00003BHAddress Detect Control Register 1 PACSR1 R/W Address Match
Detection 1 00000000B
00003CHPPG 6 Operation Mode Control Register PPGC6 W,R/W
16-bit PPG 6/7
0X000XX1B
00003DHPPG 7 Operation Mode Control Register PPGC7 W,R/W 0X000001B
00003EHPPG 6/PPG 7 Count Clock Control Register PPG67 R/W 000000X0B
00003FHReserved
MB90860E Series
29
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
000040HPPG 8 Operation Mode Control Register PPGC8 W,R/W
16-bit PPG 8/9
0X000XX1B
000041HPPG 9 Operation Mode Control Register PPGC9 W,R/W 0X000001B
000042HPPG 8/PPG 9 Count Clock Control
Register PPG89 R/W 000000X0B
000043HReserved
000044HPPG A Operation Mode Control Register PPGCA W,R/W
16-bit PPG A/B
0X000XX1B
000045HPPG B Operation Mode Control Register PPGCB W,R/W 0X000001B
000046HPPG A/PPG B Count Clock Select
Register PPGAB R/W 000000X0B
000047HReserved
000048HPPG C Operation Mode Control Register PPGCC W,R/W
16-bit PPG C/D
0X000XX1B
000049HPPG D Operation Mode Control Register PPGCD W,R/W 0X000001B
00004AHPPG C/PPG D Count Clock Select
Register PPGCD R/W 000000X0B
00004BHReserved
00004CHPPG E Operation Mode Control Register PPGCE W,R/W
16-bit PPG E/F
0X000XX1B
00004DHPPG F Operation Mode Control Register PPGCF W,R/W 0X000001B
00004EHPPG E/PPG F Count Clock Select
Register PPGEF R/W 000000X0B
00004FHReserved
000050HInput Capture Control Status 0/1 ICS01 R/W Input Capture 0/1 00000000B
000051HInput Capture Edge 0/1 ICE01 R/W, R XXX0X0XXB
000052HInput Capture Control Status 2/3 ICS23 R/W Input Capture 2/3 00000000B
000053HInput Capture Edge 2/3 ICE23 R XXXXXXXXB
000054HInput Capture Control Status 4/5 ICS45 R/W Input Capture 4/5 00000000B
000055HInput Capture Edge 4/5 ICE45 R XXXXXXXXB
000056HInput Capture Control Status 6/7 ICS67 R/W Input Capture 6/7 00000000B
000057HInput Capture Edge 6/7 ICE67 R/W, R XXX000XXB
000058HOutput Compare Control Status 0 OCS0 R/W Output Compare 0/1 0000XX00B
000059HOutput Compare Control Status 1 OCS1 R/W 0XX00000B
00005AHOutput Compare Control Status 2 OCS2 R/W Output Compare 2/3 0000XX00B
00005BHOutput Compare Control Status 3 OCS3 R/W 0XX00000B
00005CHOutput Compare Control Status 4 OCS4 R/W Output Compare 4/5 0000XX00B
00005DHOutput Compare Control Status 5 OCS5 R/W 0XX00000B
00005EHOutput Compare Control Status 6 OCS6 R/W Output Compare 6/7 0000XX00B
00005FHOutput Compare Control Status 7 OCS7 R/W 0XX00000B
MB90860E Series
30
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
000060HTimer Control Status 0 TMCSR0 R/W 16-bit Reload
Timer 0
00000000B
000061HTimer Control Status 0 TMCSR0 R/W XXXX0000B
000062HTimer Control Status 1 TMCSR1 R/W 16-bit Reload
Timer 1
00000000B
000063HTimer Control Status 1 TMCSR1 R/W XXXX0000B
000064HTimer Control Status 2 TMCSR2 R/W 16-bit Reload
Timer 2
00000000B
000065HTimer Control Status 2 TMCSR2 R/W XXXX0000B
000066HTimer Control Status 3 TMCSR3 R/W 16-bit Reload
Timer 3
00000000B
000067HTimer Control Status 3 TMCSR3 R/W XXXX0000B
000068HA/D Control Status 0 ADCS0 R/W
A/D Converter
000XXXX0B
000069HA/D Control Status 1 ADCS1 R/W 0000000XB
00006AHA/D Data 0 ADCR0 R 00000000B
00006BHA/D Data 1 ADCR1 R XXXXXX00B
00006CHADC Setting 0 ADSR0 R/W 00000000B
00006DHADC Setting 1 ADSR1 R/W 00000000B
00006EHReserved
00006FHROM Mirror Function Select ROMM W ROM Mirror XXXXXXX1B
000070H
to
00009AH
Reserved
00009BHDMA Descriptor Channel Specified
Register DCSR R/W
DMA
00000000B
00009CHDMA Status L Register DSRL R/W 00000000B
00009DHDMA Status H Register DSRH R/W 00000000B
00009EHAddress Detect Control Register 0 PACSR0 R/W Address Match
Detection 0 00000000B
00009FHDelayed Interrupt/release DIRR R/W Delayed Interrupt XXXXXXX0B
0000A0HLow-power Mode Control Register LPMCR W,R/W Low Power
Control Circuit 00011000B
0000A1HClock Selection Register CKSCR R,R/W Low Power
Control Circuit 11111100B
0000A2H,
0000A3HReserved
0000A4HDMA Stop Status Register DSSR R/W DMA 00000000B
0000A5HAutomatic Ready Function Select Register ARSR W
External Memory
Access
0011XX00B
0000A6HExternal Address Output Control Register HACR W 00000000B
0000A7HBus Control Signal Selection Register ECSR W 0000000XB
0000A8HWatchdog Control Register WDTC R,W Watchdog Timer XXXXX111B
MB90860E Series
31
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
0000A9HTime Base Timer Control Register TBTC W,R/W Time Base Timer 1XX00100B
0000AAHWatch Timer Control Register WTC R,R/W Watch Timer 1X001000B
0000ABHReserved
0000ACHDMA Enable L Register DERL R/W DMA 00000000B
0000ADHDMA Enable H Register DERH R/W 00000000B
0000AEH
Flash Control Status Register
(Flash Devices only.
Otherwise reserved)
FMCS R,R/W Flash Memory 000X0000B
0000AFHReserved
0000B0HInterrupt Control Register 00 ICR00 W,R/W
Interrupt Control
00000111B
0000B1HInterrupt Control Register 01 ICR01 W,R/W 00000111B
0000B2HInterrupt Control Register 02 ICR02 W,R/W 00000111B
0000B3HInterrupt Control Register 03 ICR03 W,R/W 00000111B
0000B4HInterrupt Control Register 04 ICR04 W,R/W 00000111B
0000B5HInterrupt Control Register 05 ICR05 W,R/W 00000111B
0000B6HInterrupt Control Register 06 ICR06 W,R/W 00000111B
0000B7HInterrupt Control Register 07 ICR07 W,R/W 00000111B
0000B8HInterrupt Control Register 08 ICR08 W,R/W 00000111B
0000B9HInterrupt Control Register 09 ICR09 W,R/W 00000111B
0000BAHInterrupt Control Register 10 ICR10 W,R/W 00000111B
0000BBHInterrupt Control Register 11 ICR11 W,R/W 00000111B
0000BCHInterrupt Control Register 12 ICR12 W,R/W 00000111B
0000BDHInterrupt Control Register 13 ICR13 W,R/W 00000111B
0000BEHInterrupt Control Register 14 ICR14 W,R/W 00000111B
0000BFHInterrupt Control Register 15 ICR15 W,R/W 00000111B
0000C0HD/A Converter Data 0 Register DAT0 R/W
D/A Converter
XXXXXXXXB
0000C1HD/A Converter Data 1 Register DAT1 R/W XXXXXXXXB
0000C2HD/A Control 0 Register DACR0 R/W XXXXXXX0B
0000C3HD/A Control 1 Register DACR1 R/W XXXXXXX0B
0000C4H,
0000C5HReserved
0000C6HExternal Interrupt Enable 0 ENIR0 R/W
External Interrupt 0
00000000B
0000C7HExternal Interrupt Source 0 EIRR0 R/W XXXXXXXXB
0000C8HExternal Interrupt Level Setting 0 ELVR0 R/W 00000000B
0000C9HExternal Interrupt Level Setting 0 ELVR0 R/W 00000000B
MB90860E Series
32
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
0000CAHExternal Interrupt Enable 1 ENIR1 R/W
External Interrupt 1
00000000B
0000CBHExternal Interrupt Source 1 EIRR1 R/W XXXXXXXXB
0000CCHExternal Interrupt Level Setting 1 ELVR1 R/W 00000000B
0000CDHExternal Interrupt Level Setting 1 ELVR1 R/W 00000000B
0000CEHExternal Interrupt Source Select EISSR R/W 00000000B
0000CFHPLL/Sub Clock Control Register PSCCR W PLL XXXX0000B
0000D0HDMA Buffer Address Pointer L Register BAPL R/W
DMA
XXXXXXXXB
0000D1HDMA Buffer Address Pointer M Register BAPM R/W XXXXXXXXB
0000D2HDMA Buffer Address Pointer H Register BAPH R/W XXXXXXXXB
0000D3HDMA Control Register DMACS R/W XXXXXXXXB
0000D4HI/O Register Address Pointer L
Register IOAL R/W XXXXXXXXB
0000D5HI/O Register Address Pointer H
Register IOAH R/W XXXXXXXXB
0000D6HData Counter L Register DCTL R/W XXXXXXXXB
0000D7HData Counter H Register DCTH R/W XXXXXXXXB
0000D8HSerial Mode Register 2 SMR2 W,R/W
UART2
00000000B
0000D9HSerial Control Register 2 SCR2 W,R/W 00000000B
0000DAHReception/Transmission Data
Register 2
RDR2/
TDR2 R/W 00000000B
0000DBHSerial Status Register 2 SSR2 R,R/W 00001000B
0000DCHExtended Communication Control
Register 2 ECCR2 R,W,
R/W 000000XXB
0000DDHExtended Status Control Register 2 ESCR2 R/W 00000100B
0000DEHBaud Rate Generator Register 20 BGR20 R/W 00000000B
0000DFHBaud Rate Generator Register 21 BGR21 R/W 00000000B
0000E0H
to
0000FFH
External area
007900HReload Register L0 PRLL0 R/W
16-bit PPG 0/1
XXXXXXXXB
007901HReload Register H0 PRLH0 R/W XXXXXXXXB
007902HReload Register L1 PRLL1 R/W XXXXXXXXB
007903HReload Register H1 PRLH1 R/W XXXXXXXXB
007904HReload Register L2 PRLL2 R/W
16-bit PPG 2/3
XXXXXXXXB
007905HReload Register H2 PRLH2 R/W XXXXXXXXB
007906HReload Register L3 PRLL3 R/W XXXXXXXXB
007907HReload Register H3 PRLH3 R/W XXXXXXXXB
MB90860E Series
33
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
007908HReload Register L4 PRLL4 R/W
16-bit PPG 4/5
XXXXXXXXB
007909HReload Register H4 PRLH4 R/W XXXXXXXXB
00790AHReload Register L5 PRLL5 R/W XXXXXXXXB
00790BHReload Register H5 PRLH5 R/W XXXXXXXXB
00790CHReload Register L6 PRLL6 R/W
16-bit PPG 6/7
XXXXXXXXB
00790DHReload Register H6 PRLH6 R/W XXXXXXXXB
00790EHReload Register L7 PRLL7 R/W XXXXXXXXB
00790FHReload Register H7 PRLH7 R/W XXXXXXXXB
007910HReload Register L8 PRLL8 R/W
16-bit PPG 8/9
XXXXXXXXB
007911HReload Register H8 PRLH8 R/W XXXXXXXXB
007912HReload Register L9 PRLL9 R/W XXXXXXXXB
007913HReload Register H9 PRLH9 R/W XXXXXXXXB
007914HReload Register LA PRLLA R/W
16-bit PPG A/B
XXXXXXXXB
007915HReload Register HA PRLHA R/W XXXXXXXXB
007916HReload Register LB PRLLB R/W XXXXXXXXB
007917HReload Register HB PRLHB R/W XXXXXXXXB
007918HReload Register LC PRLLC R/W
16-bit PPG C/D
XXXXXXXXB
007919HReload Register HC PRLHC R/W XXXXXXXXB
00791AHReload Register LD PRLLD R/W XXXXXXXXB
00791BHReload Register HD PRLHD R/W XXXXXXXXB
00791CHReload Register LE PRLLE R/W
16-bit PPG E/F
XXXXXXXXB
00791DHReload Register HE PRLHE R/W XXXXXXXXB
00791EHReload Register LF PRLLF R/W XXXXXXXXB
00791FHReload Register HF PRLHF R/W XXXXXXXXB
007920HInput Capture 0 IPCP0 R
Input Capture 0/1
XXXXXXXXB
007921HInput Capture 0 IPCP0 R XXXXXXXXB
007922HInput Capture 1 IPCP1 R XXXXXXXXB
007923HInput Capture 1 IPCP1 R XXXXXXXXB
007924HInput Capture 2 IPCP2 R
Input Capture 2/3
XXXXXXXXB
007925HInput Capture 2 IPCP2 R XXXXXXXXB
007926HInput Capture 3 IPCP3 R XXXXXXXXB
007927HInput Capture 3 IPCP3 R XXXXXXXXB
007928HInput Capture 4 IPCP4 R
Input Capture 4/5
XXXXXXXXB
007929HInput Capture 4 IPCP4 R XXXXXXXXB
00792AHInput Capture 5 IPCP5 R XXXXXXXXB
00792BHInput Capture 5 IPCP5 R XXXXXXXXB
MB90860E Series
34
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
00792CHInput Capture 6 IPCP6 R
Input Capture 6/7
XXXXXXXXB
00792DHInput Capture 6 IPCP6 R XXXXXXXXB
00792EHInput Capture 7 IPCP7 R XXXXXXXXB
00792FHInput Capture 7 IPCP7 R XXXXXXXXB
007930HOutput Compare 0 OCCP0 R/W
Output Compare 0/1
XXXXXXXXB
007931HOutput Compare 0 OCCP0 R/W XXXXXXXXB
007932HOutput Compare 1 OCCP1 R/W XXXXXXXXB
007933HOutput Compare 1 OCCP1 R/W XXXXXXXXB
007934HOutput Compare 2 OCCP2 R/W
Output Compare 2/3
XXXXXXXXB
007935HOutput Compare 2 OCCP2 R/W XXXXXXXXB
007936HOutput Compare 3 OCCP3 R/W XXXXXXXXB
007937HOutput Compare 3 OCCP3 R/W XXXXXXXXB
007938HOutput Compare 4 OCCP4 R/W
Output Compare 4/5
XXXXXXXXB
007939HOutput Compare 4 OCCP4 R/W XXXXXXXXB
00793AHOutput Compare 5 OCCP5 R/W XXXXXXXXB
00793BHOutput Compare 5 OCCP5 R/W XXXXXXXXB
00793CHOutput Compare 6 OCCP6 R/W
Output Compare 6/7
XXXXXXXXB
00793DHOutput Compare 6 OCCP6 R/W XXXXXXXXB
00793EHOutput Compare 7 OCCP7 R/W XXXXXXXXB
00793FHOutput Compare 7 OCCP7 R/W XXXXXXXXB
007940HTimer Data 0 TCDT0 R/W
I/O Timer 0
00000000B
007941HTimer Data 0 TCDT0 R/W 00000000B
007942HTimer Control Status 0 TCCSL0 R/W 00000000B
007943HTimer Control Status 0 TCCSH0 R/W 0XXXXXXXB
007944HTimer Data 1 TCDT1 R/W
I/O Timer 1
00000000B
007945HTimer Data 1 TCDT1 R/W 00000000B
007946HTimer Control Status 1 TCCSL1 R/W 00000000B
007947HTimer Control Status 1 TCCSH1 R/W 0XXXXXXXB
007948HTimer 0/Reload 0 TMR0/
TMRLR0
R/W 16-bit Reload
Timer 0
XXXXXXXXB
007949HR/W XXXXXXXXB
00794AHTimer 1/Reload 1 TMR1/
TMRLR1
R/W 16-bit Reload
Timer 1
XXXXXXXXB
00794BHR/W XXXXXXXXB
00794CHTimer 2/Reload 2 TMR2/
TMRLR2
R/W 16-bit Reload
Timer 2
XXXXXXXXB
00794DHR/W XXXXXXXXB
00794EHTimer 3/Reload 3 TMR3/
TMRLR3
R/W 16-bit Reload
Timer 3
XXXXXXXXB
00794FHR/W XXXXXXXXB
MB90860E Series
35
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
007950HSerial Mode Register 3 SMR3 W,R/W
UART3
00000000B
007951HSerial Control Register 3 SCR3 W,R/W 00000000B
007952HReception/Transmission Data
Register 3
RDR3/
TDR3 R/W 00000000B
007953HSerial Status Register 3 SSR3 R,R/W 00001000B
007954HExtended Communication Control
Register 3 ECCR3 R,W,
R/W 000000XXB
007955HExtended Status Control Register ESCR3 R/W 00000100B
007956HBaud Rate Generator Register 30 BGR30 R/W 00000000B
007957HBaud Rate Generator Register 31 BGR31 R/W 00000000B
007958HSerial Mode Register 4 SMR4 W,R/W
UART4
00000000B
007959HSerial Control Register 4 SCR4 W,R/W 00000000B
00795AHReception/Transmission Data
Register 4
RDR4/
TDR4 R/W 00000000B
00795BHSerial Status Register 4 SSR4 R,R/W 00001000B
00795CHExtended Communication Control
Register 4 ECCR4 R,W,
R/W 000000XXB
00795DHExtended Status Control Register ESCR4 R/W 00000100B
00795EHBaud Rate Generator Register 40 BGR40 R/W 00000000B
00795FHBaud Rate generator Register 41 BGR41 R/W 00000000B
007960H
to
00796BH
Reserved
00796CHClock Output Enable Register CLKR R/W Clock Monitor XXXX0000B
00796DH
to
00796FH
Reserved
007970HI2C Bus Status Register 0 IBSR0 R
I2C Interface 0
00000000B
007971HI2C bus Control Register 0 IBCR0 W,R/W 00000000B
007972HI2C 10-bit Slave Address Register 0 ITBAL0 R/W 00000000B
007973HITBAH0 R/W 00000000B
007974HI2C 10-bit Slave Address Mask
Register 0
ITMKL0 R/W 11111111B
007975HITMKH0 R/W 00111111B
007976HI2C 7-bit Slave Address Register 0 ISBA0 R/W 00000000B
007977HI2C 7-bit Slave Address Mask Register 0 ISMK0 R/W 01111111B
007978HI2C Data Register 0 IDAR0 R/W 00000000B
007979H,
00797AHReserved
MB90860E Series
36
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
00797BHI2C Clock Control Register 0 ICCR0 R/W I2C Interface 0 00011111B
00797CH
to
00797FH
Reserved
007980HI2C Bus Status Register 1 IBSR1 R
I2C Interface 1
00000000B
007981HI2C Bus Control Register 1 IBCR1 W,R/W 00000000B
007982HI2C 10-bit Slave Address Register 1 ITBAL1 R/W 00000000B
007983HITBAH1 R/W 00000000B
007984HI2C 10-bit Slave Address Mask
Register 1
ITMKL1 R/W 11111111B
007985HITMKH1 R/W 00111111B
007986HI2C 7-bit Slave Address Register 1 ISBA1 R/W 00000000B
007987HI2C 7-bit Slave Address Mask Register 1 ISMK1 R/W 01111111B
007988HI2C Data Register 1 IDAR1 R/W 00000000B
007989H,
00798AHReserved
00798BHI2C Clock Control Register 1 ICCR1 R/W I2C Interface 1 00011111B
00798CH
to
0079C1H
Reserved
0079C2HClock modulator control register
(setting prohibited) CMCR R, R/W Clock modulator
(using prohibited) 0001X000B
0079C3H
to
0079DFH
Reserved
0079E0HDetect Address Setting 0 PADR0 R/W
Address Match
Detection 0
XXXXXXXXB
0079E1HDetect Address Setting 0 PADR0 R/W XXXXXXXXB
0079E2HDetect Address Setting 0 PADR0 R/W XXXXXXXXB
0079E3HDetect Address Setting 1 PADR1 R/W XXXXXXXXB
0079E4HDetect Address Setting 1 PADR1 R/W XXXXXXXXB
0079E5HDetect Address Setting 1 PADR1 R/W XXXXXXXXB
0079E6HDetect Address Setting 2 PADR2 R/W XXXXXXXXB
0079E7HDetect Address Setting 2 PADR2 R/W XXXXXXXXB
0079E8HDetect Address Setting 2 PADR2 R/W XXXXXXXXB
0079E9H
to
0079EFH
Reserved
MB90860E Series
37
(Continued)
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
Address Register Abbrevia-
tion Access Resource name Initial value
0079F0HDetect Address Setting 3 PADR3 R/W
Address Match
Detection 1
XXXXXXXXB
0079F1HDetect Address Setting 3 PADR3 R/W XXXXXXXXB
0079F2HDetect Address Setting 3 PADR3 R/W XXXXXXXXB
0079F3HDetect Address Setting 4 PADR4 R/W XXXXXXXXB
0079F4HDetect Address Setting 4 PADR4 R/W XXXXXXXXB
0079F5HDetect Address Setting 4 PADR4 R/W XXXXXXXXB
0079F6HDetect Address Setting 5 PADR5 R/W XXXXXXXXB
0079F7HDetect Address Setting 5 PADR5 R/W XXXXXXXXB
0079F8HDetect Address Setting 5 PADR5 R/W XXXXXXXXB
0079F9H
to
007FFFH
Reserved
MB90860E Series
38
■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
(Continued)
Interrupt cause EI2OS
clear
DMA ch
number
Interrupt vector Interrupt control
register
Number Address Number Address
Reset N ⎯#08 FFFFDCH⎯⎯
INT9 instruction N ⎯#09 FFFFD8H⎯⎯
Exception N ⎯#10 FFFFD4H⎯⎯
(Reserved) N ⎯#11 FFFFD0HICR00 0000B0H
(Reserved) N ⎯#12 FFFFCCH
Input Capture 6 Y1 ⎯#13 FFFFC8HICR01 0000B1H
Input Capture 7 Y1 ⎯#14 FFFFC4H
I2C0 N ⎯#15 FFFFC0HICR02 0000B2H
(Reserved) N ⎯#16 FFFFBCH
16-bit Reload Timer 0 Y1 0 #17 FFFFB8HICR03 0000B3H
16-bit Reload Timer 1 Y1 1 #18 FFFFB4H
16-bit Reload Timer 2 Y1 2 #19 FFFFB0HICR04 0000B4H
16-bit Reload Timer 3 Y1 ⎯#20 FFFFACH
PPG 0/1/4/5 N ⎯#21 FFFFA8HICR05 0000B5H
PPG 2/3/6/7 N ⎯#22 FFFFA4H
PPG 8/9/C/D N ⎯#23 FFFFA0HICR06 0000B6H
PPG A/B/E/F N ⎯#24 FFFF9CH
Time Base Timer N ⎯#25 FFFF98HICR07 0000B7H
External Interrupt 0 to 3, 8 to 11 Y1 3 #26 FFFF94H
Watch Timer N ⎯#27 FFFF90HICR08 0000B8H
External Interrupt 4 to 7, 12 to 15 Y1 4 #28 FFFF8CH
8/10-bit A/D Converter Y1 5 #29 FFFF88HICR09 0000B9H
I/O Timer 0, I/O Timer 1 N ⎯#30 FFFF84H
Input Capture 4/5, I2C1 Y1 6 #31 FFFF80HICR10 0000BAH
Output Compare 0/1/4/5 Y1 7 #32 FFFF7CH
Input Capture 0 to 3 Y1 8 #33 FFFF78HICR11 0000BBH
Output Compare 2/3/6/7 Y1 9 #34 FFFF74H
UART 0 Reception Y2 10 #35 FFFF70HICR12 0000BCH
UART 0 Transmission Y1 11 #36 FFFF6CH
UART 1 Reception /
UART 3 Reception Y2 12 #37 FFFF68H
ICR13 0000BDH
UART 1 Transmission /
UART 3 Transmission Y1 13 #38 FFFF64H
MB90860E Series
39
(Continued)
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : •The peripheral resources sharing the ICR register have the same interrupt level.
•When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
•When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
Interrupt cause EI2OS
clear
DMA ch
number
Interrupt vector Interrupt control
register
Number Address Number Address
UART 2 Reception /
UART 4 Reception Y2 14 #39 FFFF60H
ICR14 0000BEH
UART 2 Transmission /
UART 4 Transmission Y1 15 #40 FFFF5CH
Flash Memory N ⎯#41 FFFF58HICR15 0000BFH
Delayed interrupt N ⎯#42 FFFF54H
MB90860E Series
40
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC*2
AVRH,
AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
Input voltage*1VIVSS − 0.3 VSS + 6.0 V *3
Output voltage*1VOVSS − 0.3 VSS + 6.0 V *3
Maximum Clamp Current ICLAMP −4.0 +4.0 mA *5
Total Maximum Clamp Current Σ|ICLAMP|⎯40 mA *5
“L” level maximum output current IOL ⎯15 mA *4
“L” level average output current IOLAV ⎯4mA*4
“L” level maximum overall output current ΣIOL ⎯100 mA *4
“L” level average overall output current ΣIOLAV ⎯50 mA *4
“H” level maximum output current IOH ⎯−15 mA *4
“H” level average output current IOHAV ⎯−4mA*4
“H” level maximum overall output current ΣIOH ⎯−100 mA *4
“H” level average overall output current ΣIOHAV ⎯−50 mA *4
Power consumption PD⎯340 mW
Operating temperature TA−40 +105 °C
Storage temperature TSTG −55 +150 °C
MB90860E Series
41
(Continued)
*5 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P57 (evaluation device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87,
P90 to P97, PA0 to PA1
•Use within recommended operating conditions.
•Use at DC voltage (current)
•The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
•The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
•Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
•Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
•Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
•Care must be taken not to leave the +B input pin open.
•Sample recommended circuits:
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
• Input/output equivalent circuits
+B input (0 V to 16 V)
Limiting
resistance
Protective diode
MB90860E Series
42
2. Recommended Conditions
(VSS = AVSS = 0 V)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Typ Max
Power supply voltage VCC,
AVCC
4.0 5.0 5.5 V Under normal operation
3.5 5.0 5.5 V
Under normal operation, when not
using the A/D converter and not
Flash programming.
4.5 5.0 5.5 V When External bus is used.
3.0 ⎯5.5 V Maintains RAM data in stop mode
Smooth capacitor CS0.1 ⎯1.0 µF
Use a ceramic capacitor or capac-
itor of better AC characteristics.
Capacitor at the VCC should be
greater than this capacitor.
Operating temperature TA−40 ⎯+105 °C
C
CS
C Pin Connection Diagram
MB90860E Series
43
3. DC Characteristics
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(Continued)
Parameter Sym-
bol Pin Condition Value Unit Remarks
Min Typ Max
Input H
voltage
(At VCC =
5 V ± 10%)
VIHS ⎯⎯0.8 VCC ⎯VCC + 0.3 V
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P44, P45, P46,
P47, P50, P82, P83)
VIHA ⎯⎯0.8 VCC ⎯VCC + 0.3 V
Port inputs if
Automotive input levels
are selected
VIHT ⎯⎯2.0 ⎯VCC + 0.3 V Port inputs if TTL input
levels are selected
VIHS ⎯⎯0.7 VCC ⎯VCC + 0.3 V
P12, P50, P82, P85
inputs if CMOS input
levels are selected
VIHI ⎯⎯0.7 VCC ⎯VCC + 0.3 V
P44, P45, P46, P47 in-
puts if CMOS hysteresis
input levels are selected
VIHR ⎯⎯0.8 VCC ⎯VCC + 0.3 V RST input pin (CMOS
hysteresis)
VIHM ⎯⎯VCC − 0.3 ⎯VCC + 0.3 V MD input pin
Input L
voltage
(At VCC =
5 V ± 10%)
VILS ⎯⎯VSS − 0.3 ⎯0.2 VCC V
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P44, P45, P46,
P47, P50, P82, P83)
VILA ⎯⎯VSS − 0.3 ⎯0.5 VCC V
Port inputs if
Automotive input levels
are selected
VILT ⎯⎯VSS − 0.3 ⎯0.8 V Port inputs if TTL
input levels are selected
VILS ⎯⎯VSS − 0.3 ⎯0.3 VCC V
P12, P50, P82, P85
inputs if CMOS input
levels are selected
VILI ⎯⎯VSS − 0.3 ⎯0.3 VCC V
P44, P45, P46, P47 in-
puts if CMOS hysteresis
input levels are selected
VILR ⎯⎯VSS − 0.3 ⎯0.2 VCC VRST input pin (CMOS
hysteresis)
VILM ⎯⎯VSS − 0.3 ⎯VSS + 0.3 V MD input pin
Output H
voltage VOH Normal
outputs
VCC = 4.5 V,
IOH = −4.0 mA VCC − 0.5 ⎯⎯V
Output H
voltage VOHI I2C current
outputs
VCC = 4.5 V,
IOH = −3.0 mA VCC − 0.5 ⎯⎯V
Output L
voltage VOL Normal
outputs
VCC = 4.5 V,
IOL = 4.0 mA ⎯⎯0.4 V
Output L
voltage VOLI I2C current
outputs
VCC = 4.5 V,
IOL = 3.0 mA ⎯⎯0.4 V
MB90860E Series
44
(Continued)
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
* : The power supply current is measured with an external clock.
Parameter Sym-
bol Pin Condition Value Unit Remarks
Min Typ Max
Input leak current IIL ⎯VCC = 5.5 V, VSS < VI < VCC −1⎯ + 1 µA
Pull-up
resistance RUP
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
⎯25 50 100 kΩ
Pull-down
resistance RDOWN MD2 ⎯25 50 100 kΩExcept
Flash
devices
Power supply
current*
ICC
VCC
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
⎯55 70 mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing FLASH memory.
⎯70 85 mA Flash
devices
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing FLASH memory.
⎯75 90 mA Flash
devices
ICCS
VCC = 5.0 V,
Internal frequency : 24 MHz,
At Sleep mode.
⎯25 35 mA
ICTS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At Main Timer mode
⎯0.3 0.8 mA
ICTSPLL6
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency = 4 MHz
⎯47mA
ICCL
VCC = 5.0 V
Internal frequency : 8 kHz,
At sub operation
TA = +25°C
⎯70 140 µA
ICCLS
VCC = 5.0 V
Internal frequency : 8 kHz,
At sub sleep
TA = +25°C
⎯20 50 µA
ICCT
VCC = 5.0 V
Internal frequency : 8 kHz,
At watch mode
TA = +25°C
⎯10 35 µA
ICCH
VCC = 5.0 V,
At Stop mode,
TA = +25°C
⎯725µA
Input capacity CIN
Other than C,
AVCC, AVSS,
AVRH, AVRL,
VCC, VSS,
⎯⎯515pF
MB90860E Series
45
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as
mentioned in “Relation among external clock frequency and machine clock frequency”.
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Clock frequency fC
X0, X1 3 ⎯16 MHz When using an oscillation
circuit
X0, X1 3 ⎯24 MHz When using an external
clock*
fCL X0A, X1A — 32.768 100 kHz
Clock cycle time tCYL
X0, X1 62.5 ⎯333 ns When using an oscillation
circuit
X0, X1 41.67 ⎯333 ns When using an external
clock
tCYLL X0A, X1A 10 30.5 — µs
Input clock pulse width PWH, PWL X0 10 ⎯⎯ns Duty ratio is about 30% to
70%.
PWHL, PWLL X0A 5 15.2 ⎯µs
Input clock rise and fall time tCR, tCF X0 ⎯⎯ 5 ns When using external clock
Internal operating clock
frequency (machine clock)
fCP ⎯1.5 ⎯24 MHz When using main clock
fCPL ⎯⎯8.192 50 kHz When using sub clock
Internal operating clock
cycle time (machine clock)
tCP ⎯41.67 ⎯666 ns When using main clock
tCPL ⎯20 122.1 ⎯µs When using sub clock
X0
t
CYL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WH
P
WL
X0A
t
CYLL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WHL
P
WLL
Clock Timing
MB90860E Series
46
• Guaranteed PLL operation range
Guaranteed operation range of MB90860E series
* : When using crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
24
5.5
3.5
1.5 4
Power supply voltage
VCC (V)
Guaranteed operation range
Guaranteed PLL operation range
4.0
Guaranteed A/D Converter
operation range
Machine clock fCP (MHz)
24
4.0
16
12
3412 24
Internal clock
fCP (MHz)
External clock fC (MHz) *
× 4 × 3 × 2 × 1
× 1/2
(PLL off)
8
8
Guaranteed oscillation frequency range
1.5
16
× 6
MB90860E Series
47
(2) Reset Standby Input
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Parameter Symbol Pin Value Unit Remarks
Min Max
Reset input
time tRSTL RST
500 ⎯ns Under normal operation
Oscillation time of oscillator*
+ 100 µs⎯ns
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
100 ⎯µs In Time Timer mode
tRSTL
0.2 VCC 0.2 VCC
100 µs
RST
X0
90% of
amplitude
Instruction execution
Oscillation stabilization
waiting time
Oscillation time
of oscillator
Internal operation
clock
Internal reset
0.2 VCC
RST
tRSTL
0.2 VCC
Under normal operation:
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode, Power-on:
MB90860E Series
48
(3) Power On Reset
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
(4) Clock Output Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Power on rise time tRVCC ⎯0.05 30 ms
Power off time tOFF VCC 1⎯ms Due to repetitive operation
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Cycle time tCYC CLK ⎯62.5 ⎯ns fCP = 16 MHz
41.76 ⎯ns fCP = 24 MHz
CLK ↑ → CLK ↓tCHCL CLK ⎯20 ⎯ns fCP = 16 MHz
13 ⎯ns fCP = 24 MHz
VCC
VCC
VSS
3 V
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
Holds RAM data
If you change the power supply voltage too rapidly, a power on reset may occur. We
recommend that you startup smoothly by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below. Perform while
not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate
We recommend a rise of
50 mV/ms maximum.
CLK
2.4 V
tCYC
2.4 V
0.8 V
tCHCL
MB90860E Series
49
(5) Bus Timing (Read)
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Parameter Sym-
bol Pin Condition Value Unit
Min Max
ALE pulse width tLHLL ALE
⎯
tCP/2 − 10 ⎯ns
Valid address → ALE ↓ time tAVLL ALE, A23 to A16,
AD15 to AD00 tCP/2 − 20 ⎯ns
ALE ↓ → Address valid time tLLAX ALE, AD15 to AD00 tCP/2 − 15 ⎯ns
Valid address → RD ↓ time tAVRL A23 to A16,
AD15 to AD00, RD tCP − 15 ⎯ns
Valid address → Valid data input tAVDV A23 to A16,
AD15 to AD00 ⎯5 tCP/2 − 60 ns
RD pulse width tRLRH RD 3 tCP/2 − 20 ⎯ns
RD ↓ → Valid data input tRLDV RD, AD15 to AD00 ⎯3 tCP/2 − 50 ns
RD ↑ → Data hold time tRHDX RD, AD15 to AD00 0 ⎯ns
RD ↓ → ALE ↑ time tRHLH RD, ALE tCP/2 − 15 ⎯ns
RD ↑ → Address valid time tRHAX RD, A23 to A16 tCP/2 − 10 ⎯ns
Valid address → CLK ↑ time tAVCH A23 to A16,
AD15 to AD00, CLK tCP/2 − 16 ⎯ns
RD ↓ → CLK ↑ time tRLCH RD, CLK tCP/2 − 15 ⎯ns
ALE ↓ → RD ↓ time tLLRL ALE, RD tCP/2 − 15 ⎯ns
A23 to A16
0.8 V
2.4 V
2.4 V
0.8 V
tRHAX
AD15 to AD00
0.8 V
2.4 V 2.4 V
0.8 V Address VIL
VIH VIH
VIL
Read data
tRHDX
tRLDV
tAVDV
CLK
tAVCH
2.4 V
tRLCH
2.4 V
ALE 2.4 V
tLHLL
2.4 V
tRHLH
0.8 V
tLLAX
2.4 V
tAVLL
RD
tLLRL
tRLRH
0.8 V
2.4 V
tAVRL
MB90860E Series
50
(6) Bus Timing (Write)
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Parameter Symbol Pin Condition Value Unit
Min Max
Valid address → WR ↓ time tAVWL
A23 to A16,
AD15 to AD00,
WR
⎯
tCP−15 ⎯ns
WR pulse width tWLWH WR 3 tCP/2 − 20 ⎯ns
Valid data output → WR ↑ time tDVWH AD15 to AD00,
WR 3 tCP/2 − 20 ⎯ns
WR ↑ → Data hold time tWHDX AD15 to AD00,
WR 15 ⎯ns
WR ↑ → Address valid time tWHAX A23 to A16, WR tCP/2 − 10 ⎯ns
WR ↑ → ALE ↑ time tWHLH WR, ALE tCP/2 − 15 ⎯ns
WR ↓ → CLK ↑ time tWLCH WR, CLK tCP/2 − 15 ⎯ns
CLK
tWLCH
2.4 V
ALE
tWHLH
2.4 V
WR (WRL, WRH)
tWLWH
0.8 V
2.4 V
tAVWL
A23 to A16
0.8 V
2.4 V
2.4 V
0.8 V
tWHAX
AD15 to AD00 2.4 V
0.8 V Address 0.8 V
2.4 V
Write data
tDVWH
0.8 V
2.4 V
tWHDX
MB90860E Series
51
(7) Ready Input Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Note : If the RDY setup time is insufficient, use the auto-ready function.
Parameter Sym-
bol Pin Test
Condition
Rated Value Units Remarks
Min Max
RDY setup time tRYHS RDY ⎯
45 ⎯ns fCP = 16 MHz
32 ⎯ns fCP = 24 MHz
RDY hold time tRYHH RDY 0 ⎯ns
CLK 2.4 V
ALE
RD/WR
RDY
When WAIT is not used.
VIH VIH
tRYHH
RDY
When WAIT is used.
tRYHS
VIL
MB90860E Series
52
(8) Hold Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
Parameter Symbol Pin Condition Value Units
Min Max
Pin floating → HAK ↓ time tXHAL HAK ⎯30 tCP ns
HAK ↑ time → Pin valid time tHAHV HAK tCP 2 tCP ns
HAK
Each pin
High-Z
tHAHV
tXHAL
2.4 V
0.8 V
2.4 V 2.4 V
0.8 V 0.8 V
MB90860E Series
53
(9) UART0/1/2/3/4
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Notes : •AC characteristic in CLK synchronized mode.
•CL is load capacity value of pins when testing.
Parameter Symbol Pin Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK4
Internal clock
operation output pins
are
CL = 80 pF + 1 TTL.
8 tCP ⎯ns
SCK ↓ → SOT delay time tSLOV SCK0 to SCK4,
SOT0 to SOT4 −80 +80 ns
Valid SIN → SCK ↑tIVSH SCK0 to SCK4,
SIN0 to SIN4 100 ⎯ns
SCK ↑ → Valid SIN hold time tSHIX SCK0 to SCK4,
SIN0 to SIN4 60 ⎯ns
Serial clock “H” pulse width tSHSL SCK0 to SCK4
External clock
operation output pins
are
CL = 80 pF + 1 TTL.
4 tCP ⎯ns
Serial clock “L” pulse width tSLSH SCK0 to SCK4 4 tCP ⎯ns
SCK ↓ → SOT delay time tSLOV SCK0 to SCK4,
SOT0 to SOT4 ⎯150 ns
Valid SIN → SCK ↑tIVSH SCK0 to SCK4,
SIN0 to SIN4 60 ⎯ns
SCK ↑ → Valid SIN hold time tSHIX SCK0 to SCK4,
SIN0 to SIN4 60 ⎯ns
Internal Shift Clock Mode
SCK 2.4 V
tSCYC
0.8 V
SOT
0.8 V
2.4 V
0.8 V
tSLOV
SIN VIL
VIH
tIVSH
VIL
VIH
tSHIX
MB90860E Series
54
(10) Trigger Input Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0.0 V)
Parameter Symbol Pin Condition Value Unit
Min Max
Input pulse width tTRGH
tTRGL
INT0 to INT15,
INT0R to INT15R,
ADTG
⎯5 tCP ⎯ns
External Shift Clock Mode
SCK VIH
tSLSH
VIL
SOT
0.8 V
2.4 V
tSLOV
SIN VIL
VIH
tIVSH
VIL
VIH
tSHIX
VIH
VIL
tSHSL
VIL
VIH
tTRGH
VIL
VIH
tTRGL
INT0 to INT15,
INT0R to INT15R,
ADTG
MB90860E Series
55
(11) Timer Related Resource Input Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
(12) Timer Related Resource Output Timing
(TA = –40°C to +105°C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0.0 V)
Parameter Symbol Pin Condition Value Unit
Min Max
Input pulse width tTIWH TIN0 to TIN3,
IN0 to IN7 ⎯4 tCP ⎯ns
tTIWL
Parameter Symbol Pin Condition Value Unit
Min Max
CLK ↑ → TOUT change time tTO TOT0 to TOT3,
PPG0 to PPGF ⎯30 ⎯ns
VIL
VIH
tTIWH
VIL
VIH
tTIWL
TIN0 to TIN3,
IN0 to IN7
CLK 2.4 V
0.8 V
2.4 V
tTO
TOT0 to TOT3,
PPG0 to PPGF
MB90860E Series
56
(13) I2C Timing
(TA = –40°C to +105°C, VCC = 5.0 V ± 10%, VSS = 0.0 V)
*1 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
Parameter Symbol Condition Standard-mode Fast-mode*1
Unit
Min Max Min Max
SCL clock frequency fSCL
R = 1.7 kΩ,
C = 50 pF*2
0 100 0 400 kHz
Hold time (repeated) START condition
SDA ↓ → SCL ↓tHDSTA 4.0 ⎯0.6 ⎯µs
“L” width of the SCL clock tLOW 4.7 ⎯1.3 ⎯µs
“H” width of the SCL clock tHIGH 4.0 ⎯0.6 ⎯µs
Set-up time for a repeated START condition
SCL ↑ → SDA ↓tSUSTA 4.7 ⎯0.6 ⎯µs
Data hold time
SCL ↓ → SDA ↓ ↑tHDDAT 0 3.45*300.9*
4µs
Data set-up time
SDA ↓ ↑ → SCL ↑tSUDAT 250 ⎯100 ⎯ns
Set-up time for STOP condition
SCL ↑ → SDA ↑tSUSTO 4.0 ⎯0.6 ⎯µs
Bus free time between a STOP and START
condition tBUS 4.7 ⎯1.3 ⎯µs
SDA
SCL
tLOW tSUDAT tHDSTA tBUS
tHDSTA tHDDAT tHIGH tSUSTA tSUSTO
MB90860E Series
57
5. A/D Converter
(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
* : IF A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as AVRH − AVRL becomes smaller.
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Resolution ⎯⎯ ⎯ ⎯ 10 bit
Total error ⎯⎯ ⎯ ⎯ ±3.0 LSB
Nonlinearity error ⎯⎯ ⎯ ⎯ ±2.5 LSB
Differential
nonlinearity error ⎯⎯ ⎯ ⎯ ±1.9 LSB
Zero reading
voltage VOT AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB
Full scale reading
voltage VFST AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
Compare time ⎯⎯ 1.0 ⎯16500 µs4.5 V ≤ AVCC ≤ 5.5 V
2.0 4.0 V ≤ AVCC < 4.5 V
Sampling time ⎯⎯ 0.5 ⎯∞µs4.5 V ≤ AVCC ≤ 5.5 V
1.2 4.0 V ≤ AVCC < 4.5 V
Analog port input
current IAIN AN0 to AN23 −0.3 ⎯+0.3 µA
Analog input
voltage range VAIN AN0 to AN23 AVRL ⎯AVRH V
Reference
voltage range
⎯AVRH AVRL + 2.7 ⎯AVCC V
⎯AVRL 0 ⎯AVRH − 2.7 V
Power supply
current
IAAVCC ⎯3.5 7.5 mA
IAH AVCC ⎯⎯ 5µA*
Reference
voltage current
IRAVRH ⎯600 900 µA
IRH AVRH ⎯⎯ 5µA*
Offset between
input channels ⎯AN0 to AN23 ⎯⎯ 4LSB
MB90860E Series
58
6. Definition of A/D Converter Terms
(Continued)
Resolution : Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
Total error : Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Zero reading
voltage
: Input voltage which results in the minimum conversion value.
Full scale
reading voltage
: Input voltage which results in the maximum conversion value.
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVRL AVRH
VNT
1.5 LSB
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
Actual conversion
characteristics
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
Digital output
Analog input
Total error
Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB [LSB]
1 LSB (Ideal value) = AVRH − AVRL
1024 [V]
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
MB90860E Series
59
(Continued)
3FF
H
3FE
H
3FD
H
004
H
003
H
002
H
001
H
AVRL AVRH AVRL AVRH
N + 1
H
N
H
N − 1
H
N − 2
H
V
OT
(actual measurement value)
{1 LSB × (N − 1)
+ V
OT
}
Actual conversion
characteristics
V
FST
(actual
measurement
value)
V
NT
(actual
measurement value)
Actual conversion
characteristics
Ideal characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Ideal
characteristics
Digital output
Digital output
Analog inputAnalog input
V
NT
(actual measurement value)
V
(N + 1) T
(actual measurement
value)
Non linearity error Differential linearity error
Non linearity error of digital output N =VNT − {1 LSB × (N − 1) + VOT}
1 LSB [LSB]
Differential linearity error of digital output N =V (N+1) T − VNT
1 LSB −1 LSB [LSB]
VFST − VOT
1022 [V]
1 LSB =
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
MB90860E Series
60
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period ≤ 0.5 µs)
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.
8. Flash Memory Program/Erase Characteristics
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase time
TA = +25 °C
VCC = 5.0 V
⎯115s
Excludes programming
prior to erasure
Chip erase time ⎯9⎯sExcludes programming
prior to erasure
Word (16-bit width)
programming time ⎯16 3600 µsExcept for the over head
time of the system
Programs/Erase cycle ⎯10000 ⎯⎯cycle
Flash Data Retention
Time
Average
TA = +85 °C20 ⎯⎯Year *
C
Comparator
Analog input R
4.5 V ≤ AVCC ≤ 5.5 V : R := 2.52 kΩ, C := 10.7 pF
4.0 V ≤ AVCC < 4.5 V : R := 13.6 kΩ, C := 10.7 pF
• Analog input circuit model
Note : Use the values in the figure only as a guideline.
MB90860E Series
61
■EXAMPLE CHARACTERISTICS
• MB90F867E, MB90F867ES
ICC − VCC ICCL − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICCS − VCC ICCLS − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICTS − VCC ICCT − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICTSPLL6 − VCC ICCH − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency TA = +25 °C, at stop
ICC (mA)
70
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL ( A)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
ICCS (mA)
35
15
5
10
VCC (V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCLS ( A)
50
15
5
10
VCC (V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
ICTS ( A)
400
150
50
100
VCC (V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
ICCT ( A)
20
10
6
8
VCC (V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
ICCH ( A)
10
5
1
2
VCC (V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
MB90860E Series
62
• MB90867E, MB90867ES
ICC − VCC ICCL − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICCS − VCC ICCLS − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICTS − VCC ICCT − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICTSPLL6 − VCC ICCH − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency TA = +25 °C, at stop
ICC (mA)
70
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL (µA)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
ICCS (mA)
35
15
5
10
VCC (V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCLS (µA)
50
15
5
10
VCC
(
V
)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
ICTS (µA)
400
150
50
100
VCC (V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
ICCT (µA)
20
10
6
8
VCC (V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
ICCH (µA)
10
5
1
2
VCC (V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
MB90860E Series
63
• I/O characteristics
(VCC−VOH) − IOH VOL − IOL
TA = +25 °C, VCC = 4.5 V TA = +25 °C, VCC = 4.5 V
Automotive VIN − VCC CMOS VIN − VCC
TA = +25 °C
UART-SIN pin, other than I2C pin
TA = +25 °C
TTL VIN − VCC CMOS VIN − VCC
TA = +25 °C
UART-SIN pin, I2C pin
TA = +25 °C
VCC VOH (mV)
800
300
100
200
IOH (mA)
0
400
500
600
024 7 10
700
13 6589
VOL (mV)
1000
300
100
200
IOL (mA)
0
400
500
600
900
700
800
024 7 1013 6589
VIN (V)
5.0
1.5
0.5
1.0
VCC (V)
0.0
2.0
3.0
3.5
2.5
2.5 3.5 4.5 5.5 6.53.0 4.0 5.0 6.0 7.0
4.0
4.5 VIHA
VILA
VIN (V)
5.0
2.5
1.5
2.0
VCC (V)
0.0
3.0
4.0
2.5 3.5 4.5 5.5 6.5
4.5
3.5
1.0
0.5
VIHS
VILS
3.0 4.0 5.0 6.0 7.0
VIN (V)
2.5
0.8
0.3
0.5
VCC (V)
0.0
1.0
2.0
2.5 3.5 4.5 5.5 6.5
2.3
1.5
1.3
1.8
3.0 4.0 5.0 6.0 7.0
VIHT
VILT
VIN (V)
5.0
2.5
0.5
1.0
VCC (V)
0.0
3.0
4.0
4.5
3.5
1.5
2.0
2.5 3.5 4.5 5.5 6.53.0 4.0 5.0 6.0 7.0
VIHS
VILS
MB90860E Series
64
■ORDERING INFORMATION
Part number Package Remarks
MB90F867EPF 100-pin Plastic QFP
(FPT-100P-M06)
Flash memory product
MB90F867ESPF
MB90F867EPFV 100-pin Plastic LQFP
(FPT-100P-M05)
MB90F867ESPFV
MB90867EPF 100-pin Plastic QFP
(FPT-100P-M06)
MASK ROM product
MB90867ESPF
MB90867EPFV 100-pin Plastic LQFP
(FPT-100P-M05)
MB90867ESPFV
MB90V340E-101 299-pin Ceramic PGA
(PGA-299C-A01) Evaluation product
MB90V340E-102
MB90860E Series
65
■PACKAGE DIMENSIONS
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
100-pin plastic QFP Lead pitch 0.65 mm
Package width ×
package length 14.00 × 20.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference) P-QFP100-14×20-0.65
100-pin plastic QFP
(FPT-100P-M06)
(
FPT-100P-M06
)
C
2002 FUJITSU LIMITED F100008S-c-5-5
130
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002) M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00 +0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
0~8˚
*
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB90860E Series
66
(Continued)
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
100-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 14.0 × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.65g
Code
(Reference) P-LFQFP100-14×14-0.50
100-pin plastic LQFP
(FPT-100P-M05)
(FPT-100P-M05)
C
2003 FUJITSU LIMITED F100007S-c-4-6
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020) 0.20±0.05
(.008±.002) M
0.08(.003)0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX .059 –.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0˚~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB90860E Series
F0610
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
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