TBD62089APG
2016-12-21
1
©2016 Toshiba Corporation
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TBD62089APG
8-ch Sink Type DMOS Transistor Array with D-type Flip-Flop
The TBD62089APG is an 8-ch DMOS transistor array with
D-type flip-flop. Please be careful about thermal conditions during use.
Features
• Built-in 8 circuits
• High output voltage
:
VOUT = 50 V (max)
• High output current
:
IOUT = 500 mA/ch (max)
• Package
:
DIP20-P-300-2.54A
Pin assignment (top view)
DIP20-P-300-2.54A
Weight: 1.4 g (typ.)
/CLR
CLK
D3
D1
D2
D4
D5
D6
D7
D8
GND
/Y8
VDD
/Y7
/Y6
/Y5
/Y4
/Y3
/Y2
/Y1
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Pin description
Pin No. Pin name Function
/CLR
Clear signal input pin
D1
Data signal input pin
D2
Data signal input pin
D3
Data signal input pin
D4
Data signal input pin
D5
Data signal input pin
D6
Data signal input pin
D7
Data signal input pin
D8
Data signal input pin
CLK
Clock signal input pin
GND
Ground pin
/Y8
Output pin
/Y7
Output pin
/Y6
Output pin
/Y5
Output pin
/Y4
Output pin
/Y3
Output pin
/Y2
Output pin
/Y1
Output pin
VDD
Power supply pin
Block diagram
Equivalent circuit may be omitted or simplified for explanatory purpose.
Function table
INPUT
OUTPUT: /Y
/CLR
CLK
D
L
X
X
H
H
↑
L
H
H
↑
H
L
H
L
X
Y0
H
↓
X
Y0
↑: ”L” to ”H”
↓: ”H” to ”L”
H: High level
L: Low level
X: Don’t care
Y0: /Y level just before inputting conditions in the table are fixed
*: Operating conditions in the table: OUTPUT is connected to the power supply through resistors.
VDD
CLK
/CLR
100kΩ
(typ.)
100kΩ
(typ.)
CK
D Q
R
D1
/Y1
100kΩ
(typ.)
CK
D
Q
R
D2
100kΩ
(typ.)
CK
D Q
R
D3
100kΩ
(typ.)
CK
D Q
R
D4
100kΩ
(typ.)
CK
D Q
R
D5
100kΩ
(typ.)
CK
D Q
R
D6
100kΩ
(typ.)
CK
D Q
R
D7
100kΩ
(typ.)
CK
D Q
R
D8
100kΩ
(typ.)
GND
/Y2
/Y3
/Y4
/Y5
/Y6
/Y7
/Y8
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Absolute maximum ratings (Ta = 25°C)
Characteristics Symbol Rating Unit
Output voltage VOUT 50 V
Power supply voltage VDD −0.5 to 6 V
Output current IOUT 500 mA/ch
Input voltage VIN −0.5 to 6 V
Power dissipation PD
(Note1) 1.76 (Note2) W
Operating temperature Topr −40 to 85 °C
Storage temperature Tstg −55 to 150 °C
Note1: In mounting on a board, based on JEDEC 2s2p standards
Note2: When Ta exceeds 25 °C, derating with 14.1 mW/°C is necessary.
Operating range (Ta = - 40 to 85°C, unless otherwi se specified)
Characteristics
Symbol
Tes t conditions
Min
Typ.
Max
Unit
Output voltage VOUT ― ― ― 50 V
Power supply voltage VDD ― 3 ―
5.5
V
Output current (per channel)
(Note) IOUT
1 channel ON, Ta = 25 °C 0 ―
400
mA
tpw = 25 ms
8 channels ON
Ta = 85°C
Tj = 120°C
Duty = 10 % 0 ― 400
Duty = 50 % 0 ― 195
Input voltage (Output on) VIN (ON) ― 0.7×VDD ― VDD V
Input voltage (Output off) VIN (OFF) ― 0 ― 0.3×VDD V
Voltage rising time of CLK input tr VDD = 3 V to 5.5 V 0 ― 500 ns
Voltage falling time of CLK input
tf VDD = 3 V to 5.5 V 0 ― 500 ns
Setup time tsu VDD = 3 V to 5.5 V
Setup time of D input for CLK input 10 ― ― ns
Hold time th VDD = 3 V to 5.5 V
Hold time of D input for CLK input 10 ― ― ns
Pulse width (CLK, /CLR) tw VDD = 3 V to 5.5 V 30 ― ― ns
Logic clock frequency fCLK VDD = 3 V to 5.5 V ― ― 20 MHz
Note: In mounting on a board, based on JEDEC 2s2p standards
Timing chart
Timing charts may be omitted or simplified for explanatory purposes.
CLK
D
th
tsu
tw
50%
50%
50%
50%
10%
90%
tr
tf
90%
10%
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Electrical characteristics (Ta = 25°C and VDD = 5 V, unless otherwise specified)
Characteristics Symbol Te st
Circuit
Tes t c onditions Min Typ. Max Unit
Output leakage current Ileak 1 VOUT = 50 V, Ta = 85 °C
VIN = 0 V ― ― 1.0 μA
Output voltage
(Output ON-resistance)
VDS
(RON) 2
IOUT = 350 mA ― 0.56
(1.6)
1.14
(3.25)
V
(Ω)
IOUT = 200 mA ― 0.32
(1.6)
0.65
(3.25)
IOUT = 100 mA ― 0.16
(1.6)
0.325
(3.25)
Input current (Output on) IIN (ON) 3 VIN = 5.5 V, VDD = 5.5 V ― ― 80 μA
Input current (Output off) IIN (OFF) 4 VIN = 0 V, VDD = 5.5 V ― ― 1.0 μA
Power supply current
(per channel)
ICC (ON) 3 VIN = 5.5 V, VDD = 5.5 V ― ― 75 μA
ICC (OFF) 4 VIN = 0 V, VDD = 5.5 V ― ― 1.0 μA
Propagation delay time
tpHL (CLK) 5
CLK (50 %) to /Y (50 %)
/Y: H to L
CL = 30 pF
RL = 240 Ω, pull-up to 24 V
VDD = 4.5 to 5.5 V ― 270 430
ns
VDD = 3.0 to 3.6 V ― 470 670
tpLH (CLK) 5
CLK (50 %) to /Y (50 %)
/Y: L to H
CL = 30 pF
RL = 240 Ω, pull-up to 24 V
VDD = 4.5 to 5.5 V ― 350 510
ns
VDD = 3.0 to 3.6 V ― 350 510
tpLH
(/CLR) 5
/CLR (50 %) to /Y (50 %)
/Y: L to H
CL = 30 pF
RL = 240 Ω, pull-up to 24 V
VDD = 4.5 to 5.5 V ― 350 510
ns
VDD = 3.0 to 3.6 V ― 350 510
Turn-on delay time tor 5
/Y waveform: 10 % to 90 %
CL = 30 pF
RL = 240 Ω, pull-up to 24 V
VDD = 4.5 to 5.5 V ― 280 400
ns
VDD = 3.0 to 3.6 V ― 280 400
Turn-off delay time tof 5
/Y waveform: 90 % to 10 %
CL = 30 pF
RL = 240 Ω, pull-up to 24 V
VDD = 4.5 to 5.5 V ― 330 480
ns
VDD = 3.0 to 3.6 V ― 620 860
Timing chart
Timing charts may be omitted or simplified for explanatory purposes.
tpHL(CLK)
CLK
/Y
50%
50%
50%
50%
tpLH(CLK)
90%
10%
10%
90%
tof
tor
/CLR
/Y
50%
50%
tpLH(/CLR)
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Test circuit
1. Ileak 2. VDS (RON)
3. IIN (ON) and ICC (ON) 4. IIN (OFF) and ICC (OFF)
5. tpHL (CLK), tpLH (CLK), tpLH (/CLR), tor, and tof
Test circuits may be omitted or simplified for explanatory purposes.
VDD
/Y
D
GND
VDD
CLK
/CLR
IIN(ON)
IIN(ON)
IIN(ON)
VIN
VIN
VIN
VDD
/Y
D
GND
VDD
CLK
/CLR
IIN(OFF)
IIN(OFF)
IIN(OFF)
VIN
VIN
VIN
VDD
/Y
D
GND
VOUT
VDD
CLK
/CLR
PG
RL
CL
VDD
/Y
D
GND
VOUT
Ileak
VDD
CLK
/CLR
PG
(/Y = H)
RON = VDS / IOUT
VDD
/Y
D
GND
VDS
IOUT
VDD
CLK
/CLR
PG
(/Y = L)
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Package dimensions
DIP20-P-300-2.54A Unit: mm
Weight: 1.4 g (typ.)
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Notes on Contents
1. Block diagram
Block diagram may be simplified for explanatory purpose.
2. Test circuit
Test circuit may be simplified for explanatory purpose.
3. Timing chart
Timing charts may be simplified for explanatory purposes.
IC Usage Considerations
Notes on handling of ICs
(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for
a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause device breakdown, damage or
deterioration, and may result in injury by explosion or combustion.
(2) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals
of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute
maximum rating, and exceeding the rating(s) may cause device breakdown, damage or deterioration, and may
result in injury by explosion or combustion. In addition, do not use any device inserted in the wrong orientation
or incorrectly to which current is applied even just once.
(3) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in the case of
overcurrent and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute
maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the
wiring or load, causing a large current to continuously flow and the breakdown can lead to smoke or ignition. To
minimize the effects of the flow of a large current in the case of breakdown, appropriate settings, such as fuse
capacity, fusing time and insertion circuit location, are required.
(4) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to
prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON
or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause
injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power
supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause
injury, smoke or ignition.
(5) Carefully select external components (such as inputs and negative feedback capacitors) and load components
(such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as
from input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is
connected to a speaker with low input withstand voltage, overcurrent or IC failure may cause smoke or ignition.
(The overcurrent may cause smoke or ignition from the IC itself.) In particular, please pay attention when using
a Bridge Tied Load (BTL) connection-type IC that inputs output DC voltage to a speaker directly.
Points to remember on handling of ICs
Heat Radiation Design
When using an IC with large current flow such as power amp, regulator or driver, design the device so that heat is
appropriately radiated, in order not to exceed the specified junction temperature (TJ) at any time or under any condition.
These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life,
deterioration of IC characteristics or IC breakdown. In addition, when designing the device, take into consideration the
effect of IC heat radiation with peripheral components.
Back-EMF
When a motor rotates in the reverse direction, stops or slows abruptly, current flows back to the motor’s power supply
owing to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power
supply and output pins might be exposed to conditions beyond the absolute maximum ratings. To avoid this problem, take
the effect of back-EMF into consideration in system design.
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RESTRICTIONS ON PRODUCT USE
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