WM8903 w Ultra Low Power CODEC for Portable Audio Applications DESCRIPTION FEATURES The WM8903 is a high performance ultra-low power stereo CODEC optimised for portable audio applications. * The device features stereo ground-referenced headphone amplifiers using the Wolfson `Class-W' amplifier techniques - incorporating an innovative dual-mode charge pump architecture - to optimise efficiency and power consumption during playback. The ground-referenced outputs eliminate headphone coupling capacitors. Both headphone and line outputs include common mode feedback paths to reject ground noise. Control sequences for audio path setup can be pre-loaded and executed by an integrated sequencer to reduce software driver development and eliminate pops and clicks via Wolfson's SilentSwitchTM technology. The analogue input stage can be configured for single ended, pseudo-differential or fully differential inputs. Up to 3 stereo microphone or line inputs may be connected. The input impedance is constant with PGA gain setting. A stereo digital microphone interface is provided, which can also be mixed with the mic/line signals at the output mixers. A dynamic range controller provides compression and level control to support a wide range of portable recording applications. Anti-clip and quick release features offer good performance in the presence of loud impulsive noises. Common audio sampling frequencies are supported from a range of external clocks, including 3MHz, 12MHz or 24MHz. The WM8903 can operate directly from a single 1.8V switched supply. For optimal power consumption, the digital core can be operated from a 1.0V supply. 4.5mW power consumption for DAC to headphone playback DAC SNR 96dB typical, THD -86dB typical ADC SNR 92dB typical, THD -80dB typical * * * * Control sequencer for pop minimised start-up and shutdown Single register write for default start-up sequence * * * * Stereo digital microphone input 3 single ended inputs per stereo channel 2 pseudo differential inputs per stereo channel 1 fully differential mic input per stereo channel * * Digital Dynamic Range Controller (compressor / limiter) Digital sidetone mixing * * * Ground-referenced headphone driver Ground-referenced line outputs Stereo differential line driver for direct interface to WM9001 speaker driver * 40-pin 5x5mm QFN package APPLICATIONS * * * Portable multimedia players Multimedia handsets Handheld gaming BLOCK DIAGRAM DACR DACL BYPASSR BYPASSL INTERRUPT GPIO3/ ADDR To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews MCLK DACDAT LRC ADCDAT BCLK SDIN SCLK VMID AVDD AGND WOLFSON MICROELECTRONICS plc Pre-Production, August 2009, Rev 3.1 Copyright (c)2009 Wolfson Microelectronics plc WM8903 Pre-Production TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ......................................................................... 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ELECTRICAL CHARACTERISTICS ...................................................................... 7 TERMINOLOGY ............................................................................................................ 7 COMMON TEST CONDITIONS .................................................................................... 7 INPUT SIGNAL PATH ................................................................................................... 8 OUTPUT SIGNAL PATH ............................................................................................. 10 BYPASS PATH............................................................................................................ 12 CHARGE PUMP .......................................................................................................... 13 OTHER PARAMETERS .............................................................................................. 13 POWER CONSUMPTION .................................................................................... 14 COMMON TEST CONDITIONS .................................................................................. 14 POWER CONSUMPTION MEASUREMENTS ............................................................ 14 SIGNAL TIMING REQUIREMENTS ..................................................................... 16 COMMON TEST CONDITIONS .................................................................................. 16 MASTER CLOCK ........................................................................................................ 16 AUDIO INTERFACE .................................................................................................... 17 CONTROL INTERFACE .............................................................................................. 19 DIGITAL FILTER CHARACTERISTICS ............................................................... 20 DAC FILTER RESPONSES......................................................................................... 21 ADC FILTER RESPONSES......................................................................................... 22 ADC HIGH PASS FILTER RESPONSES .................................................................... 23 DE-EMPHASIS FILTER RESPONSES ........................................................................ 24 DEVICE DESCRIPTION ....................................................................................... 25 ANALOGUE INPUT SIGNAL PATH ............................................................................ 25 ELECTRET CONDENSER MICROPHONE INTERFACE ............................................ 32 DIGITAL MICROPHONE INTERFACE ........................................................................ 35 ANALOGUE-TO-DIGITAL CONVERTER (ADC) ......................................................... 37 DYNAMIC RANGE CONTROL (DRC) ......................................................................... 40 DIGITAL MIXING ......................................................................................................... 46 DIGITAL-TO-ANALOGUE CONVERTER (DAC) ......................................................... 51 OUTPUT SIGNAL PATH ............................................................................................. 56 ANALOGUE OUTPUTS............................................................................................... 65 REFERENCE VOLTAGES AND MASTER BIAS ......................................................... 67 POP SUPPRESSION CONTROL ................................................................................ 69 CHARGE PUMP .......................................................................................................... 72 DC SERVO .................................................................................................................. 73 DIGITAL AUDIO INTERFACE ..................................................................................... 76 CLOCKING AND SAMPLE RATES ............................................................................. 87 w PP, Rev 3.1, August 2009 2 Pre-Production WM8903 GENERAL PURPOSE INPUT/OUTPUT (GPIO).......................................................... 91 INTERRUPTS.............................................................................................................. 96 CONTROL INTERFACE .............................................................................................. 98 CONTROL WRITE SEQUENCER ............................................................................. 100 POWER-ON RESET ................................................................................................. 109 QUICK START-UP AND SHUTDOWN ...................................................................... 111 CHIP RESET AND DEVICE ID .................................................................................. 112 REGISTER MAP................................................................................................. 113 REGISTER BITS BY ADDRESS ............................................................................... 117 APPLICATIONS INFORMATION ....................................................................... 153 RECOMMENDED EXTERNAL COMPONENTS ........................................................ 153 MIC DETECTION SEQUENCE USING MICBIAS CURRENT.................................... 154 IMPORTANT NOTICE ........................................................................................ 158 ADDRESS ................................................................................................................. 158 w PP, Rev 3.1, August 2009 3 WM8903 Pre-Production PIN CONFIGURATION ORDERING INFORMATION DEVICE WM8903LGEFK/V TEMPERATURE RANGE -40C to +85C PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 40-lead QFN MSL3 260C MSL3 260C (5x5x0.55mm, lead-free) WM8903LGEFK/RV -40C to +85C 40-lead QFN (5x5x0.55mm, lead-free, tape and reel) Note: Tube quantity = 95 Reel quantity = 3,500 w PP, Rev 3.1, August 2009 4 WM8903 Pre-Production PIN DESCRIPTION PIN NAME 1 DGND Supply TYPE DESCRIPTION 2 MCLK Digital Input Master clock for CODEC 3 GPIO2/ DMIC_DAT Digital Input/Output GPIO2 / Digital microphone data input 4 GPIO1/ DMIC_LR Digital Input/Output GPIO1 / Digital microphone clock output 5 INTERRUPT 6 BCLK 7 DACDAT 8 LRC 9 ADCDAT 10 CPVDD 11 CFB1 12 CPGND Digital ground (return path for DCVDD and DBVDD) Digital Output Interrupt output Digital Input/Output Audio interface bit clock Digital Input DAC digital audio data Digital Input/Output Audio interface left / right clock (common for ADC and DAC) Digital Output ADC digital audio data Supply Charge pump power supply Analogue Output Charge pump flyback capacitor pin Supply Charge pump ground 13 CFB2 Analogue Output Charge pump flyback capacitor pin 14 VPOS Analogue Output Charge pump positive supply decoupling (powers HPOUTL/R, LINEOUTL/R) 15 VNEG Analogue Output Charge pump negative supply decoupling (powers HPOUTL/R, LINEOUTL/R) 16 HPOUTR Analogue Output Right headphone output (line or headphone output) 17 HPGND Analogue Input Headphone ground 18 HPOUTL Analogue Output Left headphone output (line or headphone output) 19 LINEOUTR Analogue Output Right line output 1 (line output) 20 LINEGND Analogue Input Line-out ground 21 LINEOUTL Analogue Output Left line output 1 (line output) 22 LOP Analogue Output Left differential output positive side 23 LON Analogue Output Left differential output negative side 24 AVDD Supply Analogue power supply (powers analogue inputs, reference, ADC, DAC, LOP, LON, ROP, RON) 25 VMID Analogue Output Midrail voltage decoupling capacitor 26 AGND Supply Analogue power return Right differential output negative side 27 RON Analogue Output 28 ROP Analogue Output Right differential output positive side 29 MICBIAS Analogue Output Microphone bias 30 IN3R Analogue Input Right channel input 3 31 IN2R Analogue Input Right channel input 2 32 IN1R Analogue Input Right channel input 1 33 IN3L Analogue Input Left channel input 3 34 IN2L Analogue Input Left channel input 2 35 IN1L Analogue Input Left channel input 1 36 SDIN Digital Input/Output Control interface data Input / 2-wire acknowledge output 37 SCLK Digital Input Control interface clock Input 38 GPIO3 /ADDR Digital Input/Output GPIO3 / control interface address selection 39 DCVDD Supply Digital core supply 40 DBVDD Supply Digital buffer supply (powers audio interface and control interface) w PP, Rev 3.1, August 2009 5 WM8903 Pre-Production ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. MIN MAX AVDD, DCVDD CONDITION -0.3V +2.5V DBVDD, -0.3V +4.5V CPVDD -0.3V +2.2V (CPVDD + 0.3V) * -1 CPVDD + 0.3 Voltage range digital inputs DGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V HPOUTL, HPOUTR, LINEOUTL, LINEOUTR Temperature range, TA -40C +85C Storage temperature after soldering -65C +150C Notes 1. Analogue and digital grounds must always be within 0.3V of each other. 2. All digital and analogue supplies are completely independent from each other; there is no restriction on power supply sequencing. 3. HPOUTL, HPOUTR, LINEOUTL, LINEOUTR are outputs, and should not normally become connected to DC levels. However, if the limits above are exceeded, then damage to the WM8903 may occur. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN Digital supply range (Core) DCVDD 0.95 1.89 V Digital supply range (Buffer) DBVDD 1.42 3.6 V AVDD 1.71 2.0 V CPVDD 1.71 2.0 V +85 C Analogue supplies range Charge pump supply range Ground Operating Temperature (ambient) w DGND, AGND, CPGND TA TYP MAX 0 -40 +25 UNIT V PP, Rev 3.1, August 2009 6 WM8903 Pre-Production ELECTRICAL CHARACTERISTICS TERMINOLOGY 1. Signal-to-Noise Ratio (dB) - SNR is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20Hz to 20kHz. This ratio is also called idle channel noise. (No Auto-zero or Automute function is employed). 2. Total Harmonic Distortion (dB) - THD is the difference in level between a 1kHz full scale sinewave output signal and the first seven harmonics of the output signal. The amplitude of the fundamental frequency of the output signal is compared to the RMS value of the next seven harmonics and expressed as a ratio. 3. Total Harmonic Distortion + Noise (dB) - THD+N is the difference in level between a 1kHz full scale sine wave output signal and all noise and distortion products in the audio band. The amplitude of the fundamental reference frequency of the output signal is compared to the RMS value of all other noise and distortion products and expressed as a ratio. 4. Channel Separation (dB) - is a measure of the coupling between left and right channels. A full scale signal is applied to the left channel only, the right channel amplitude is measured. Then a full scale signal is applied to the right channel only and the left channel amplitude is measured. The worst case channel separation is quoted as a ratio. 5. Channel Level Matching (dB) - measures the difference in gain between the left and the right channels. 6. Power Supply Rejection Ratio (dB) - PSRR is a measure of ripple attenuation between the power supply pin and an output path. With the signal path idle, a small signal sine wave is summed onto the power supply rail, The amplitude of the sine wave is measured at the output port and expressed as a ratio. 7. All performance measurements carried out with 20kHz AES17 low pass filter for distortion measurements, and an A-weighted filter for noise measurement. Failure to use such a filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: * DCVDD = 1.2V * DBVDD = 1.8V * AVDD = CPVDD =1.8V * Ambient temperature = +25C * Audio signal: 1kHz sine wave, sampled at 48kHz with 24-bit data resolution Additional, specific test conditions are given within the relevant sections below. w PP, Rev 3.1, August 2009 7 WM8903 Pre-Production INPUT SIGNAL PATH Single-ended stereo line record - IN1L+IN1R pins to ADC output Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 00000b (-1.5dB) Total signal path gain = 4.45dB, incorporating 6dB single-ended to differential conversion gain PARAMETER SYMBOL TEST CONDITIONS MIN TYP Full Scale Input Signal Level (for ADC 0dBFS). 0.570 -4.88 1.61 Input Resistance Rin Input Capacitance Cin DC Offset 10 At ADC output with ADC_HPF_ENA=0 0.600 -4.45 1.70 MAX UNIT 0.630 -4.01 1.78 Vrms dBV Vpk-pk 12 k 10 pF 11864 LSBs (24-bit) 47 LSBs (16-bit) Signal to Noise Ratio SNR A-weighted Total Harmonic Distortion THD -5.45dBV input -78 -68 dBFS -66 dBFS Total Harmonic Distortion + Noise THD+N Channel Separation Channel Level Matching Power Supply Rejection Ratio PSRR 85 91 -5.45dBV input -76 1kHz signal, -5.45dBV 85 10kHz signal, -5.45dBV 80 1kHz signal, -5.45dBV +/-1 1kHz, 100mVpk-pk 60 20kHz, 100mV pk-pk 40 dBFS dB dB dB Pseudo-differential stereo line record - IN2L+IN3L / IN2R+IN3R pins to ADC output Test conditions: L_MODE = R_MODE = 01b (Differential Line) LIN_VOL = RIN_VOL = 01111b (+4.2dB) Total signal path gain = +4.20dB PARAMETER SYMBOL TEST CONDITIONS Line Input Full Scale Signal Level applied to IN2L or IN2R (for ADC 0dBFS output) MIN TYP MAX UNIT 0.586 -4.64 1.657 0.617 -4.20 1.745 0.648 -3.77 1.833 Vrms dBV Vpk-pk IN3L, IN3R input range Input Resistance Rin Input Capacitance Cin DC Offset 10 At ADC output with ADC_HPF_ENA=0 +/-100 mV 12 k 10 pF 11864 LSBs (24-bit) 47 LSBs (16-bit) Signal to Noise Ratio SNR A-weighted Total Harmonic Distortion THD -5.2dBV input -80 -66 dBFS -64 dBFS 85 92 Total Harmonic Distortion + Noise THD+N -5.2dBV input -78 Common Mode Rejection Ratio CMRR 1kHz, 100mV pk-pk 60 1kHz signal, -5.2dBV 85 10kHz signal, -5.2dBV 80 1kHz signal, -5.2dBV +/-1 1kHz, 100mVpk-pk 60 20kHz, 100mV pk-pk 40 Channel Separation Channel Level Matching Power Supply Rejection Ratio w PSRR dBFS dB dB dB dB PP, Rev 3.1, August 2009 8 WM8903 Pre-Production Single-ended stereo record from analogue microphones - IN2L / IN2R pins to ADC output Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 11111b (+28.3dB) Total signal path gain = +34.3dB, incorporating 6dB single-ended to differential conversion gain PARAMETER SYMBOL TEST CONDITIONS MIN TYP Single-ended mic input full-scale Signal Level (for ADC 0dBFS output) Input Resistance Rin Input Capacitance Cin DC offset 10 MAX UNIT 0.019 -34.3 0.055 Vrms dBV Vpk-pk 12 k 10 pF At ADC output with ADC_HPF_ENA=0 11864 LSBs (24-bit) 47 LSBs (16-bit) Signal to Noise Ratio SNR A-weighted 73 dBFS Total Harmonic Distortion THD -35dBV input -78 dBFS Total Harmonic Distortion + Noise THD+N Channel Level Matching Power Supply Rejection Ratio PSRR -35dBV input -77 dBFS 1kHz signal, -35dBV +/-3 dB 1kHz, 100mVpk-pk 60 20kHz, 100mV pk-pk 40 dB Differential stereo record from analogue microphones - IN1L+IN2L / IN1R+IN2R pins to ADC output Test conditions: L_MODE = R_MODE = 10b (Differential mic) LIN_VOL = RIN_VOL = 00111b (+30dB) Total signal path gain = +30dB PARAMETER SYMBOL TEST CONDITIONS MIN Differential Mic Input Full Scale Signal Level IN1L-IN2L / IN1R-IN2R (for ADC 0dBFS output) Input Resistance Rin Input Capacitance Cin DC Offset 100 At ADC output with ADC_HPF_ENA=0 TYP MAX UNIT 0.032 -30 0.089 Vrms dBV Vpk-pk 120 k 10 pF 189813 LSBs (24-bit) 742 LSBs (16-bit) Signal to Noise Ratio SNR A-weighted 75 dBFS Total Harmonic Distortion THD -31dBV input -78 dBFS Total Harmonic Distortion + Noise THD+N -31dBV input -72 dBFS Common Mode Rejection Ratio CMRR 1kHz, 100mVpk-pk 60 dB 1kHz signal, -31dBV 85 dB 10kHz signal, -31dBV 80 1kHz signal, -31dBV +/-1 1kHz, 100mVpk-pk 60 20kHz, 100mV pk-pk 40 Channel Separation Channel Level Matching PSRR (Referred to Input) w PSRR dB dB PP, Rev 3.1, August 2009 9 WM8903 Pre-Production PGA and microphone boost PARAMETER Minimum PGA gain setting TEST CONDITIONS MIN TYP MAX L_MODE/R_MODE= 00b or 01b -1.55 L_MODE/R_MODE= 10b +12 L_MODE/R_MODE= 00b or 01b +28.28 L_MODE/R_MODE= 10b +30 Single-ended to differential conversion gain L_MODE/R_MODE= 00b +6 PGA gain accuracy L_MODE/R_MODE= 00b Gain -1.5 to +6.7dB -1 +1 L_MODE/R_MODE= 00b Gain +7.5 to +28.3dB -1.5 +1.5 L_MODE/R_MODE= 1X Gain +12 to +24dB -1 +1 L_MODE/R_MODE= 1X Gain +27 to +30dB -1.5 +1.5 Maximum PGA gain setting Mute attenuation Equivalent input noise UNIT dB dB dB dB all modes of operation 88 dB L_MODE/R_MODE= 00b or 01b 114 828 Vrms nV/Hz OUTPUT SIGNAL PATH Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 15 load Test conditions: HPOUTL_VOL = HPOUTR_VOL = 111001b (0dB) PARAMETER Output Power (per Channel) SYMBOL TEST CONDITIONS Po 1% THD RLoad= 30 28 0.91 -0.76 mW Vrms dBV 1% THD RLoad= 15 30 0.67 -3.47 mW Vrms dBV DC Offset DC servo enabled, calibration complete. Signal to Noise Ratio SNR Total Harmonic Distortion THD Total Harmonic Distortion + Noise THD+N Channel Separation Channel Level Matching Power Supply Rejection Ratio w PSRR A-weighted RL=30; Po=2mW MIN TYP 0 90 MAX +/-1.5 96 UNIT mV dB -93 RL=30; Po=20mW -82 RL=15; Po=2mW -83 RL=15; Po=20mW -83 RL=30; Po=2mW -90 RL=30; Po=20mW -82 RL=15; Po=2mW -81 RL=15; Po=20mW -81 1kHz signal, 0dBFS 100 10kHz signal, 0dBFS 85 1kHz signal, 0dBFS +/-1 1kHz, 100mV pk-pk 60 20kHz, 100mV pk-pk 40 -72 -70 dB dB dB dB dB PP, Rev 3.1, August 2009 10 WM8903 Pre-Production Stereo Playback to Line-out - DAC input to LINEOUTL+LINEOUTR pins with 3.01k / 50pF load Test conditions: LINEOUTL_VOL = LINEOUTR_VOL = 111001b (0dB) PARAMETER SYMBOL TEST CONDITIONS Full Scale Output Signal Level MIN TYP MAX UNIT DAC 0dBFS output at 0dB volume 0.95 -0.446 2.69 1.0 0 2.83 1.05 0.424 2.97 Vrms dBV Vpk-pk DC servo enabled. Calibration complete. 0 +/-1.5 mV 90 DC offset Signal to Noise Ratio SNR A-weighted Total Harmonic Distortion THD 3.01k load -86 -77 dB THD+N 3.01k load -84 -75 dB Total Harmonic Distortion + Noise Channel Separation dB 1kHz signal, 0dBFS 100 10kHz signal, 0dBFS 85 1kHz signal, 0dBFS +/-1dB 1kHz, 100mVpk-pk 60 20kHz, 100mV pk-pk 40 Channel Level Matching Power Supply Rejection Ratio 95 PSRR dB dB dB Stereo Playback to Differential Line-out - DAC input to LOP+LON or ROP+RON pins with 10k / 50pF load Test conditions: SPKR_LVOL = SPKR_RVOL = 111001b (0dB) PARAMETER SYMBOL Full Scale Output Signal Level TEST CONDITIONS MIN TYP MAX 0dBFS Measured Differentially 0.95 -0.446 2.69 1.0 0 2.83 1.05 0.424 2.97 Common mode output level Vrms dBV Vpk-pk AVDD/2 Common mode output error +/-7 mV Signal to Noise Ratio SNR Total Harmonic Distortion THD -92 -82 dB THD+N -88 -80 dB Total Harmonic Distortion + Noise Channel Separation A-weighted PSRR 95 1kHz signal, 0dBFS 100 10kHz signal, 0dBFS 85 Channel Level Matching Power Supply Rejection Ratio 90 dB dB 1kHz signal +/-1dB 1kHz, 100mVpk-pk 60 20kHz, 100mV pk-pk 40 dB dB Output PGAs (HP, LINE and Differential LINE) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Minimum PGA gain setting -57 dB Maximum PGA gain setting 6 dB PGA Gain Step Size 1 PGA gain accuracy +6dB to 0dB -1.5 PGA gain accuracy 0dB to -57dB -1 Mute attenuation w HPOUTL/R dB +1.5 +1 77 LINEOUTL/R 79 Differential LINE (LOP-LOR/ROP-RON) 105 dB dB dB dB PP, Rev 3.1, August 2009 11 WM8903 Pre-Production BYPASS PATH Pseudo-differential stereo line input to stereo line output- IN2L-IN3L / IN2R-IN3R pins to LINEOUTL+LINEOUTR pins with 3.01k / 50pF load Test conditions: L_MODE = R_MODE = 01b (Differential Line) LIN_VOL = RIN_VOL = 01111b (+4.2dB) LINEOUTL_VOL = LINEOUTR_VOL = 111001b (0dB) Total signal path gain = +4.20dB PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Line Input Full Scale Signal Level applied to IN2L or IN2R (for ADC 0dBFS output) 0.617 -4.20 1.745 Vrms dBV Vpk-pk Full Scale Output Signal Level 1.0 0 2.83 Vrms dBV Vpk-pk dBV Signal to Noise Ratio SNR A-weighted 99 Total Harmonic Distortion THD -5.2dBV input -92 dBV THD+N -5.2dBV input -90 dBV Total Harmonic Distortion + Noise Channel Separation Channel Level Matching Power Supply Rejection Ratio PSRR 1kHz signal, -5.2dBV 85 10kHz signal, -5.2dBV 80 1kHz signal, -5.2dBV +/-1 1kHz, 100mVpk-pk 56 20kHz, 100mV pk-pk 40 dB dB dB Differential stereo line input to stereo line output- IN2L-IN3L / IN2R-IN3R pins to LINEOUTL+LINEOUTR pins with 3.01k / 50pF load Test conditions: L_MODE = R_MODE = 01b (Differential Line) LIN_VOL = RIN_VOL = 00101b (0dB) LINEOUTL_VOL = LINEOUTR_VOL = 111001b (0dB) Total signal path gain = 0dB PARAMETER MIN TYP MAX UNIT Line Input Full Scale Signal Level applied to IN2L or IN2R (for ADC 0dBFS output) SYMBOL TEST CONDITIONS 0.586 -4.64 1.657 0.617 -4.20 1.745 0.648 -3.77 1.833 Vrms dBV Vpk-pk Full Scale Output Signal Level 0.95 -0.446 2.69 1.0 0 2.83 1.05 0.424 2.97 Vrms dBV Vpk-pk Signal to Noise Ratio SNR A-weighted Total Harmonic Distortion THD -5.2dBV input -92 -82 dBV THD+N -5.2dBV input -89 -80 dBV Total Harmonic Distortion + Noise w 85 97 dBV PP, Rev 3.1, August 2009 12 WM8903 Pre-Production CHARGE PUMP PARAMETER SYMBOL TEST CONDITIONS MIN TYP Charge pump start-up time MAX 40 UNIT s External component requirements To achieve specified headphone output power and performance Flyback capacitor (between CFB1 and CFB2 pins) CFB at 2V 1 VPOS capacitor at 2V 2 F VNEG capacitor at 2V 2 F MIN TYP MAX UNIT -3% AVDD/2 +3% V F OTHER PARAMETERS VMID Reference PARAMETER TEST CONDITIONS Midrail Reference Voltage (VMID pin) Microphone bias (for analogue electret condenser microphones) Additional test conditions: MICBIAS_ENA=1, all parameters measured at the MICBIAS pin PARAMETER SYMBOL TEST CONDITIONS MIN Bias Voltage VMICBIAS Maximum source current IMICBIAS 3mA load current Noise spectral density Power Supply Rejection Ratio PSRR -5% TYP MAX 0.9xAVDD +5% UNIT V 4 mA nV/Hz At 1kHz 19 1kHz, 100mV pk-pk 50 20kHz, 100mV pk-pk 70 dB MICBIAS Current Detect Function (See Notes 1, 2) Current Detect Threshold (Microphone insertion) 100 MICDET_THR = 00 Current Detect Threshold (Microphone removal) A 15 Delay Time for Current Detect Interrupt tDET 1.25-15 ms MICBIAS Short Circuit (Hook Switch) Detect Function (See Notes 1, 2) Short Circuit Detect Threshold (Button press) MICSHORT_THR = 00 400 520 Short Circuit Detect Hysteresis (See Note 3) Minimum Delay Time for Short Circuit Detect Interrupt 647 A 50 tSHORT Short Circuit Detect measurement frequency 40 ms 250 Hz Notes: 1. If AVDD 1.8, current threshold values should be multiplied by (AVDD/1.8) 2. MICBIAS current detect and short circuit (Hook switch) detect functionality tested using GPIO pin rather than by 3. interrupt. Hysteresis = difference between Button Press and Button Release thresholds Digital Inputs / Outputs PARAMETER SYMBOL TEST CONDITIONS Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH IOH = +1mA Output LOW Level VOL IOL = -1mA w MIN TYP MAX UNIT 0.3xDBVDD V 0.1xDBVDD V 0.7xDBVDD V 0.9xDBVDD V PP, Rev 3.1, August 2009 13 WM8903 Pre-Production POWER CONSUMPTION The WM8903 power consumption is dependent on many parameters. Most significantly, it depends on supply voltages, sample rates, mode of operation, and output loading. The power consumption on each supply rail varies approximately with the square of the voltage. Power consumption is greater at fast sample rates than at slower ones. When the digital audio interface is operating in Master mode, the DBVDD current is significantly greater than in Slave mode. (Note also that power savings can be made by using MCLK as the BCLK source in Slave mode.) The output load conditions (impedance, capacitance and inductance) can also impact significantly on the device power consumption. COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: * * * * * Ambient temperature = +25C Audio signal = quiescent (zero amplitude) Sample rate = 44.1kHz MCLK = 12MHz Audio interface mode = Master (LRCLK_DIR=1, BCLK_DIR=1) Additional, variant test conditions are quoted within the relevant sections below. Where applicable, power dissipated in the headphone or line loads is included. POWER CONSUMPTION MEASUREMENTS Single-ended stereo line record - IN1L/R, IN2L/R or IN3L/R pins to ADC output. Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 00000b (-1.5dB) ADC_OSR128 = 0 Variant test conditions AVDD DCVDD DBVDD CPVDD TOTAL V mA V mA V mA V mA mW 44.1kHz sample rate 1.8 3.60 1.2 1.04 1.8 0.10 1.8 0.00 7.9 8kHz sample rate 1.8 3.40 1.2 0.50 1.8 0.03 1.8 0.00 6.8 Differential stereo record from analogue microphones - IN1L/R, IN2L/R or IN3L/R pins to ADC out. Test conditions: L_MODE = R_MODE = 10b (Differential mic) ADC_OSR128 = 0 Variant test conditions AVDD DCVDD DBVDD CPVDD TOTAL V mA V mA V mA V mA mW 44.1kHz sample rate 1.8 3.60 1.2 1.00 1.8 0.10 1.8 0.00 7.9 8kHz sample rate 1.8 3.40 1.2 0.50 1.8 0.03 1.8 0.00 6.8 w PP, Rev 3.1, August 2009 14 WM8903 Pre-Production Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 30 load. Test conditions DACBIAS_SEL = 01b (Normal bias x 0.5) DACVMID_BIAS_SEL = 11b (Normal bias x 0.75) PGA_BIAS = 011b (Normal bias x 0.5) CP_DYN_PWR = 1b (Charge pump controlled by real-time audio level) Variant test conditions AVDD DCVDD DBVDD CPVDD TOTAL V mA V mA V mA V mA mW Slave mode, 44.1kHz sample rate, quiescent 1.8 1.60 1.2 0.76 1.8 0.00 1.8 0.41 4.5 Master mode, 44.1kHz sample rate, quiescent 1.8 1.60 1.2 0.76 1.8 0.09 1.8 0.41 4.7 Master mode, 44.1kHz, Po = 0.1mW/channel 1.8 1.60 1.2 0.90 1.8 0.09 1.8 1.85 7.5 Master mode, 44.1kHz, Po = 1mW/channel 1.8 1.60 1.2 0.92 1.8 0.09 1.8 5.77 14.5 Master mode, 8kHz sample rate, quiescent 1.8 1.60 1.2 0.65 1.8 0.03 1.8 0.41 4.4 Master mode, 8kHz, Po = 0.1mW/channel 1.8 1.60 1.2 0.71 1.8 0.03 1.8 1.85 7.1 Stereo Playback to Line-out - DAC input to LINEOUTL+LINEOUTR or HPOUTL+HPOUTR pins with 3.01k / 50pF load Test conditions: CP_DYN_PWR = 1b (Charge pump controlled by real-time audio level) Variant test conditions AVDD DCVDD DBVDD CPVDD TOTAL V mA V mA V mA V mA mW 44.1kHz sample rate 1.8 1.95 1.2 0.76 1.8 0.09 1.8 0.32 5.2 8kHz sample rate 1.8 1.95 1.2 0.68 1.8 0.03 1.8 0.32 4.9 Stereo analogue bypass to headphones - IN1L/R, IN2L/R or IN3L/R pins to HPOUTL+HPOUTR pins with 30 load. Test conditions: Audio interface disabled Note that the Analogue bypass configuration does not benefit from the Class W dynamic control, and the power consumption is greater in this case than the DAC to Line-Out case. See "Charge Pump" section. Variant test conditions AVDD DCVDD DBVDD CPVDD TOTAL V mA V mA V mA V mA Quiescent 1.8 1.46 1.2 0.12 1.8 0.00 1.8 1.54 mW 5.5 Po = 0.1mW/channel 1.8 1.46 1.2 0.12 1.8 0.00 1.8 4.54 11.0 Off Test conditions: No Clocks applied Variant test conditions None w AVDD DCVDD DBVDD CPVDD TOTAL V mA V mA V mA V mA mW 1.8 0.01 1.2 0.012 1.8 0.003 1.8 0.005 0.047 PP, Rev 3.1, August 2009 15 WM8903 Pre-Production SIGNAL TIMING REQUIREMENTS COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: * * * * Ambient temperature = +25C DCVDD = 1.2V DBVDD = AVDD = CPVDD = 1.8V DGND = AGND = CPGND = 0V Additional, specific test conditions are given within the relevant sections below. MASTER CLOCK tMCLKY MCLK tMCLKL tMCLKH Figure 1 Master Clock Timing Master Clock Timing PARAMETER SYMBOL TMCLKY TEST CONDITIONS MCLKDIV2=1 MIN TYP MAX 40 UNIT ns MCLK cycle time TMCLKY MCLKDIV2=0 MCLK cycle time TMCLKY DCVDD 1.62V MCLK duty cycle TMCLKDS w 80 ns 54.25 ns MCLKDIV2=0 60:40 40:60 PP, Rev 3.1, August 2009 16 WM8903 Pre-Production AUDIO INTERFACE MASTER MODE Figure 2 Audio Interface Timing - Master Mode Audio Interface Timing - Master Mode PARAMETER SYMBOL MIN TYP MAX UNIT LRC propagation delay from BCLK falling edge tDL 10 ns ADCDAT propagation delay from BCLK falling edge tDDA 10 ns DACDAT setup time to BCLK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns w PP, Rev 3.1, August 2009 17 WM8903 Pre-Production SLAVE MODE Figure 3 Audio Interface Timing - Slave Mode Audio Interface Timing - Slave Mode PARAMETER SYMBOL MIN BCLK cycle time tBCY 50 TYP MAX UNIT BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRC set-up time to BCLK rising edge tLRSU 10 ns LRC hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 10 ns DACDAT set-up time to BCLK rising edge tDS 40 ns ns Note: BCLK period must always be greater than or equal to MCLK period. w PP, Rev 3.1, August 2009 18 WM8903 Pre-Production TDM MODE In TDM mode, it is important that two devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8903 ADCDAT pin tri-stating at the start and end of the data transmission is described below. Figure 4 Audio Interface Timing - TDM Mode Audio Interface Timing - TDM Mode PARAMETER SYMBOL MIN TYP MAX UNIT ADCDAT setup time from BCLK falling edge 4 ns ADCDAT release time from BCLK falling edge 25 ns CONTROL INTERFACE t3 t3 t5 SDIN t4 t6 t2 t8 SCLK t1 t9 t7 Figure 5 Control Interface Timing Control Interface Timing PARAMETER SYMBOL MIN SCLK Frequency TYP MAX UNIT 526 kHz SCLK Low Pulse-Width t1 1.3 s SCLK High Pulse-Width t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 SDIN, SCLK Rise Time t6 300 SDIN, SCLK Fall Time t7 300 Setup Time (Stop Condition) t8 Data Hold Time t9 Pulse width of spikes that will be suppressed tps w ns 600 0 ns ns ns 900 ns 5 ns PP, Rev 3.1, August 2009 19 WM8903 Pre-Production DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN +/- 0.05dB 0 TYP MAX UNIT ADC Filter Passband 0.454 fs -6dB 0.5fs Passband Ripple +/- 0.05 Stopband dB 0.546s Stopband Attenuation f > 0.546 fs -60 +/- 0.05dB 0 dB DAC Normal Filter Passband 0.454 fs -6dB Passband Ripple 0.5 fs 0.454 fs +/- 0.03 Stopband dB 0.546 fs Stopband Attenuation F > 0.546 fs -50 dB DAC Sloping Stopband Filter Passband +/- 0.03dB 0 0.25 fs +/- 1dB 0.25 fs 0.454 fs -6dB Passband Ripple 0.5 fs 0.25 fs +/- 0.03 Stopband 1 0.546 fs Stopband 1 Attenuation f > 0.546 fs -60 Stopband 2 dB 0.7 fs Stopband 2 Attenuation f > 0.7 fs 1.4 fs -85 Stopband 3 dB 0.7 fs dB 1.4 fs Stopband 3 Attenuation F > 1.4 fs -55 DAC FILTERS dB ADC FILTERS Mode Group Delay Mode Group Delay Normal 16.5 / fs Normal 16.5 / fs Sloping Stopband 18 / fs TERMINOLOGY 1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple - any variation of the frequency response in the pass-band region w PP, Rev 3.1, August 2009 20 WM8903 Pre-Production DAC FILTER RESPONSES Figure 6 DAC Filter Response for CLK_SYS_MODE = 10b (Clock is 250 x fs related) DAC_SB_FILT = 1b (Sloping StopBand Filter) Figure 7 DAC Filter Response for CLK_SYS_MODE = 00b or 01b DAC_SB_FILT = 1b (Sloping StopBand Filter) Sample Rate 24kHz Sample Rate 24kHz Figure 8 DAC Filter Response for CLK_SYS_MODE = 10b (Clock is 250 x fs related) Figure 9 DAC Filter Response for CLK_SYS_MODE = 00b or 01b DAC_SB_FILT = 0b (Normal Filter) Sample Rate > 24kHz (except 88.2kHz) DAC_SB_FILT = 0b (Normal Filter) Sample Rate > 24kHz w PP, Rev 3.1, August 2009 21 WM8903 Pre-Production Figure 10 DAC Filter Response for CLK_SYS_MODE = 01b (Clock is 272 x fs related) DAC_SB_FILT = 0b (Normal Filter) Sample Rate = 88.2kHz ADC FILTER RESPONSES Figure 11 ADC Filter Response for CLK_SYS_MODE = 10b (not applicable to 88.2/96kHz) w Figure 12 ADC Filter Response for CLK_SYS_MODE = 00b or 01b PP, Rev 3.1, August 2009 22 WM8903 Pre-Production Figure 13 ADC Filter Passband Ripple for CLK_SYS_MODE = 10b ADC HIGH PASS FILTER RESPONSES 2.1246m -2.3338m -1.1717 -8.3373 -2.3455 -16.672 -3.5193 -25.007 -4.6931 -33.342 -5.8669 -41.677 -7.0407 -50.012 -8.2145 -58.347 -9.3883 -66.682 -10.562 -75.017 -11.736 1 2.6923 7.2484 19.515 52.54 141.45 380.83 1.0253k 2.7605k 7.432k 20.009k -83.352 2 5.0248 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k 7.9761k 20.039k MAGNITUDE(dB) hpf_response.res MAGNITUDE(dB) hpf_response2.res MAGNITUDE(dB) hpf_response2.res#1 MAGNITUDE(dB) Figure 14 ADC Digital High Pass Filter Frequency Response (48kHz, Hi-Fi Mode, ADC_HPF_CUT[1:0]=00) Figure 15 ADC Digital High Pass Filter Ripple (48kHz, Voice Mode, ADC_HPF_CUT=01, 10 and 11) The plots shown are for 48kHz. For other sample rates, the plots should be scaled accordingly. w PP, Rev 3.1, August 2009 23 WM8903 Pre-Production DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB) MAGNITUDE(dB) 0.3 0 -1 0 5000 10000 15000 20000 0.25 0.2 -2 0.15 -3 0.1 -4 0.05 0 -5 -0.05 -6 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 -0.1 -7 -0.15 Frequency (Hz) -8 -9 -10 Frequency (Hz) Figure 16 De-Emphasis Digital Filter Response (32kHz) Figure 17 De-Emphasis Error (32kHz) MAGNITUDE(dB) MAGNITUDE(dB) 0.2 0 -1 0 5000 10000 15000 20000 25000 0.15 -2 -3 0.1 -4 0.05 -5 -6 0 -7 0 -8 5000 10000 15000 20000 25000 -0.05 -9 -0.1 -10 Frequency (Hz) Frequency (Hz) Figure 18 De-Emphasis Digital Filter Response (44.1kHz) Figure 19 De-Emphasis Error (44.1kHz) MAGNITUDE(dB) MAGNITUDE(dB) 0.15 0 0 5000 10000 15000 20000 25000 30000 -2 0.1 -4 0.05 -6 0 -8 -0.05 -10 -0.1 0 5000 10000 15000 20000 25000 30000 -0.15 -12 Frequency (Hz) Figure 20 De-Emphasis Digital Filter Response (48kHz) w Frequency (Hz) Figure 21 De-Emphasis Error (48kHz) PP, Rev 3.1, August 2009 24 WM8903 Pre-Production DEVICE DESCRIPTION ANALOGUE INPUT SIGNAL PATH The WM8903 has six analogue input pins, which may be used to support connections to multiple microphone or line input sources. The input multiplexer on the Left and Right channels can be used to select different configurations for each of the input sources. The analogue input paths can support line and microphone inputs, in single-ended, pseudo-differential and fully-differential modes. The input stage can also provide common mode noise rejection in some configurations. The Left and Right analogue input channels are routed to the Analogue to Digital converters (ADCs). There is also a bypass path for each channel, enabling the signal to be routed directly to the output mixers. The WM8903 input signal paths and control registers are illustrated in Figure 22. Figure 22 Block Diagram for Input Signal Path w PP, Rev 3.1, August 2009 25 WM8903 Pre-Production INPUT PGA ENABLE The input PGAs (Programmable Gain Amplifiers) and Multiplexers are enabled using register bits INL_ENA and INR_ENA, as shown in Table 1. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12 (0Ch) Power Management 0 1 INL_ENA 0 Left Input PGA Enable 0 = disabled 1 = enabled 0 INR_ENA 0 Right Input PGA Enable 0 = disabled 1 = enabled Table 1 Input PGA Enable To enable the input PGAs, the reference voltage VMID and the bias current must also be enabled. See "Reference Voltages and Master Bias" for details of the associated controls VMID_RES and BIAS_ENA. INPUT PGA CONFIGURATION The analogue input channels can each be configured in three different modes, which are as follows: Single-Ended Mode (Inverting) Differential Line Mode (Inverting) Differential Mic Mode (Non-Inverting) The mode is selected by the L_MODE and R_MODE fields for the Left and Right channels respectively. The input pins are selected using the L_IP_SEL_N and L_IP_SEL_P fields for the Left channel and the R_IP_SEL_N and R_IP_SEL_P for the Right channel. In Single-Ended mode, L_IP_SEL_N alone determines the Left Input pin, and the R_IP_SEL_N determines the Right Input pin. The three modes are illustrated in Figure 23, Figure 24 and Figure 25. It should be noted that the available gain and input impedance varies between configurations (see also "Electrical Characteristics"). The input impedance is constant with PGA gain setting. The Input PGA modes are selected and configured using the register fields described in Table 2. w PP, Rev 3.1, August 2009 26 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL R46 (2Eh) Analogue Left Input 1 5:4 R47 (2Fh) Analogue Right Input 1 DEFAULT DESCRIPTION L_IP_SEL_N [1:0] 00 Selects input for inverting side of left input path: 00 = IN1L 01 = IN2L 1X = IN3L 3:2 L_IP_SEL_P [1:0] 01 Selects input for non-inverting side of left input path: 00 = IN1L 01 = IN2L 1X = IN3L 1:0 L_MODE [1:0] 00 Sets the mode for the left analogue input: 00 = Single-Ended 01 = Differential Line 10 = Differential MIC 11 = Reserved 5:4 R_IP_SEL_N [1:0] 00 Selects input for inverting side of right input path: 00 = IN1R 01 = IN2R 1X = IN3R 3:2 R_IP_SEL_P [1:0] 01 Selects input for non-inverting side of right input path: 00 = IN1R 01 = IN2R 1X = IN3R 1:0 R_MODE [1:0] 00 Sets the mode for the right analogue input: 00 = Single-Ended 01 = Differential Line 10 = Differential MIC 11 = Reserved Table 2 Input PGA Mode Selection w PP, Rev 3.1, August 2009 27 WM8903 Pre-Production SINGLE-ENDED INPUT The Single-Ended PGA configuration is illustrated in Figure 23 for the Left channel. The available gain in this mode is from -1.57dB to +28.5dB in non-linear steps. The input impedance is 12k. The input to the ADC is phase inverted with respect to the selected input pin. Different input pins can be selected in the same mode by altering the L_IP_SEL_N field. The equivalent configuration is also available on the Right channel; this can be selected independently of the Left channel mode. Figure 23 Single Ended Mode (Inverting) DIFFERENTIAL LINE INPUT The Differential Line PGA configuration is illustrated in Figure 24 for the Left channel. The available gain in this mode is from -1.57dB to +28.5dB in non-linear steps. The input impedance is 12k. The input to the ADC is phase inverted with respect to the input pin selected by L_IP_SEL_N. The noninverting input pin is selected by L_IP_SEL_P. The equivalent configuration is also available on the Right channel; this can be selected independently of the Left channel mode. IN1L IN2L LIN_VOL (-1.57dB to +28.5dB, non-linear steps) MUX + IN3L BYPASSL L_MODE = 01 L_IP_SEL_N = 00 LIN_VOL (-1.57dB to +28.5dB, non-linear steps) - MUX + ADC L + L_MODE = 01 L_IP_SEL_P = 01 Figure 24 Differential Line Mode (Inverting) w PP, Rev 3.1, August 2009 28 WM8903 Pre-Production DIFFERENTIAL MICROPHONE INPUT The Differential Mic PGA configuration is illustrated in Figure 25 for the Left channel. The available gain in this mode is from +12dB to +30dB in 3dB linear steps. The input impedance is 120k. In this mode, there is no phase inversion between the input to the ADC and the input pin selected by L_IP_SEL_N. The second (inverting) input pin is selected by L_IP_SEL_P in this mode. The equivalent configuration is also available on the Right channel; this can be selected independently of the Left channel mode. IN1L LIN_VOL (+12dB to +30dB, in3dB steps) IN2L MUX + IN3L BYPASSL L_MODE = 1X L_IP_SEL_N = 00 LIN_VOL (+12dB to +30dB, in3dB steps) + MUX + ADC L - L_MODE = 1X L_IP_SEL_P = 01 Figure 25 Differential Mic Mode (Non-Inverting) INPUT PGA GAIN CONTROL The volume control gain for the Left and Right channels be independently controlled using the LIN_VOL and RIN_VOL register fields as described in Table 3. The available gain range varies according to the selected PGA Mode as detailed in Table 4. Note that the value `00000' must not be used in Differential Mic Mode, as the PGA will not function correctly under this setting. In singleended mode (L_MODE / R_MODE = 00b), the conversion from single-ended to differential within the WM8903 adds a further 6dB of gain to the signal path. Each input channel can be independently muted using LINMUTE and RINMUTE. There is no feature to ensure that volume changes are implemented glitch-free. Therefore, it is recommended to not adjust the gain dynamically whilst the signal path is enabled; the signal should be muted at the input or output stage prior to adjusting the volume control. REGISTER ADDRESS BIT R44 (2Ch) Analogue Left Input 0 7 4:0 R45 (2Dh) Analogue Right Input 0 7 4:0 LABEL LINMUTE LIN_VOL [4:0] RINMUTE RIN_VOL [4:0] DEFAULT 1 00101 1 00101 DESCRIPTION Left Input PGA Mute 0 = not muted 1 = muted Left Input PGA Volume (See Table 4 for volume range) Right Input PGA Mute 0 = not muted 1 = muted Right Input PGA Volume (See Table 4 for volume range) Table 3 Input PGA Volume Control w PP, Rev 3.1, August 2009 29 WM8903 Pre-Production LIN_VOL[4:0], RIN_VOL[4:0] GAIN - PGA MODE = 00 OR 01 GAIN - PGA MODE = 1X 00000 -1.5 dB Not valid 00001 -1.3 dB +12 dB 00010 -1.0 dB +15 dB 00011 -0.7 dB +18 dB 00100 -0.3 dB +21 dB 00101 0.0 dB +24 dB 00110 +0.3 dB +27 dB 00111 +0.7 dB +30 dB 01000 +1.0 dB +30 dB 01001 +1.4 dB +30 dB 01010 +1.8 dB +30 dB 01011 +2.3 dB +30 dB 01100 +2.7 dB +30 dB 01101 +3.2 dB +30 dB 01110 +3.7 dB +30 dB 01111 +4.2 dB +30 dB 10000 +4.8 dB +30 dB 10001 +5.4 dB +30 dB 10010 +6.0 dB +30 dB 10011 +6.7 dB +30 dB 10100 +7.5 dB +30 dB 10101 +8.3 dB +30 dB 10110 +9.2 dB +30 dB 10111 +10.2 dB +30 dB 11000 +11.4 dB +30 dB 11001 +12.7 dB +30 dB 11010 +14.3 dB +30 dB 11011 +16.2 dB +30 dB 11100 +19.2 dB +30 dB 11101 +22.3 dB +30 dB 11110 +25.2 dB +30 dB 11111 +28.3 dB +30 dB Table 4 Input PGA Volume Range w PP, Rev 3.1, August 2009 30 WM8903 Pre-Production INPUT PGA COMMON MODE AMPLIFIER In Differential Line Mode only, a Common Mode amplifier can be enabled as part of the input PGA circuit. This feature provides approximately 20dB reduction in common mode noise on the differential input, which can reduce problematic interference. Since the ADC has differential signal inputs, it has an inherent immunity to common mode noise (see "Electrical Characteristics") However, the presence of Common Mode noise can limit the usable signal range of the ADC path; enabling the Common Mode amplifier can solve this issue. It should be noted that the Common Mode amplifier consumes additional power and can also add its own noise to the input signal. For these reasons, it is recommended that the Common Mode Amplifier is only enabled if there is a known source of Common Mode interference. The Common Mode amplifier is controlled by the INL_CM_ENA and INR_CM_ENA fields as described in Table 5. Although the Common Mode amplifier may be enabled regardless of the input PGA mode, its function is only effective in the Differential Line Mode configuration. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R46 (2Eh) Analogue Left Input 1 6 INL_CM_ENA 1 Left Input PGA Common Mode Rejection enable 0 = Disabled 1 = Enabled (only available for L_MODE=01 - Differential Line) R47 (2Fh) Analogue Right Input 1 6 INR_CM_ENA 1 Right Input PGA Common Mode Rejection enable 0 = Disabled 1 = Enabled (only available for R_MODE=01 - Differential Line) Table 5 Common Mode Amplifier Enable w PP, Rev 3.1, August 2009 31 WM8903 Pre-Production ELECTRET CONDENSER MICROPHONE INTERFACE Electret Condenser microphones may be connected as single-ended or differential inputs to the Input PGAs described in the "Analogue Input Signal Path" section. The WM8903 provides a low-noise reference voltage suitable for biasing electret condenser microphones. This is provided on the MICBIAS pin, and can be enabled using the MICBIAS_ENA register bit. MICBIAS CURRENT DETECT FUNCTION Insertion/removal of a microphone or pressing/releasing a hook switch button will cause a significant change of MICBIAS current flow. Two current thresholds are provided, set by MICDET_THR and MICSHORT_THR. When a change of current which crosses either threshold is detected, an interrupt event can be generated. In a typical application, accessory insertion would be detected when the MICBIAS current exceeds MICDET_THR, and microphone hookswitch operation would be detected when the MICBIAS current exceeds MICSHORT_THR. The Threshold Detection functions are both inputs to the Interrupt control circuit and can be used to trigger an Interrupt event when MIC_DET_ENA=1 - see "Interrupts". The interrupt flag can be read back via the control interface, or the microphone status can be read back via a GPIO pin - see "General Purpose Input/Output (GPIO)". Hysteresis and digital filtering are implemented in the hook switch detect circuit to improve reliability in conditions where AC current spikes are present due to ambient noise conditions. Hysteresis and digital filtering applies to both methods of detection, i.e. interrupt events, or GPIO pin state. The register fields used to configure MICBIAS functionality are described in Table 6. Performance parameters for this circuit block can be found in the "Electrical Characteristics" section. Further guidance on the usage of the MICBIAS current monitoring features is described on the following pages. REGISTER ADDRESS R6 (06h) Mic Bias Control 0 BIT LABEL DEFAULT DESCRIPTION Reserved. Writing `1' to these register bits will have no effect. MICBIAS Current Detect Insertion Threshold 00 = 0.063mA 01 = 0.26mA 10 = 0.45mA 11 = 0.635mA If AVDD 1.8, values are scaled MICBIAS Short Circuit Button Push Threshold 00 = 0.52mA 01 = 0.77mA 10 = 1.2mA 11 = 1.43mA If AVDD 1.8, values are scaled MICBIAS Current and Short Circuit Detect Enable 0 = disabled 1 = enabled MICBIAS Enable 0 = disabled 1 = enabled 7:6 Reserved 00 5:4 MICDET_THR [1:0] 00 3:2 MICSHORT_TH R [1:0] 00 1 MICDET_ENA 0 0 MICBIAS_ENA 0 Table 6 MICBIAS Control w PP, Rev 3.1, August 2009 32 WM8903 Pre-Production MICROPHONE INSERTION / REMOVAL DETECTION In a typical application, microphone insertion would be detected when the MICBIAS current exceeds the Current Detect threshold set by MICDET_THR. In order to generate a MICBIAS Current Detect interrupt from this event, MICDET_INV must be cleared to 0 (see "Interrupts"). For detection of microphone removal, the MICDET_INV bit must be set to 1. In this case, a MICBIAS Current Detect interrupt is generated when the MICBIAS current falls below the threshold set by MICDET_THR. MICROPHONE INSERTION / REMOVAL DE-BOUNCE AND FILTERING The detection of these events is bandwidth limited for best noise rejection, and is subject to detection delay time tDET, as specified in the Electrical Characteristics. Provided that the MICDET_THR field has been set appropriately, each insertion or removal event is guaranteed to be detected within the delay time tDET. It is likely that the microphone socket contacts will have mechanical "bounce" when a microphone is inserted or removed, and hence the resultant control signal will not be a clean logic level transition. Since tDET has a range of values, it is possible that the interrupt will be generated before the mechanical "bounce" has ceased. Hence after a mic insertion or removal has been detected, a time delay should be applied before re-configuring the MICDET_INV bit. The maximum possible mechanical bounce times for mic insertion and removal must be understood by the software programmer. Utilising a GPIO pin to monitor the steady state of the microphone detection function does not change the timing of the detection mechanism, so there will also be a delay tDET before the signal changes state. It may be desirable to implement de-bounce in the host processor when monitoring the state of the GPIO signal. To illustrate this, an example sequence including mic insertion detection is detailed in the "Applications Information" section on page 154. MICROPHONE INSERTION / REMOVAL CLOCKING REQUIREMENTS A clock is required for the Current Detect circuit. This requires: 1. MCLK to be present 2. CLK_SYS_ENA = 1 3. WSMD_CLK_ENA = 1 Any microphone insertion (or removal) event which happens while one or more of the above criteria are not satisfied (for example during a low power mode where the CPU has disabled MCLK) will still be detected, but only after the clocking conditions are met. An example is illustrated in Figure 27, where the mic is inserted while MCLK is stopped. (1) insertion event happens at any time during this period (2) insertion indicated tDET after MCLK re-started tDET MCLK Mic insertion event IRQ GPIO Figure 26 MIC Detection events without MCLK w PP, Rev 3.1, August 2009 33 WM8903 Pre-Production MICROPHONE HOOK SWITCH DETECTION In a typical application, microphone hook switch operation would be detected when the MICBIAS current exceeds the Short Circuit Detect threshold set by MICSHORT_THR. In order to generate a MICBIAS Short Circuit Detect interrupt from this event, MICSHRT_INV must be cleared to 0 (see "Interrupts"). For detection of the hook switch release, the MICSHRT_INV bit must be set to 1. In this case, a MICBIAS Short Circuit Detect interrupt is generated when the MICBIAS current falls below the threshold set by MICSHORT_THR. MICROPHONE HOOK SWITCH DE-BOUNCE AND FILTERING The possibility of spurious hook switch interrupts due to ambient noise conditions can be removed by 1. Careful analysis of microphone behaviour under extremely high sound pressure levels or during mechanical shock, such that the AC current swing during such conditions is understood. 2. By correct selection of the MICBIAS resistor value, such that current flow while the hook switch is pressed is significantly higher than that caused by AC current swing during such conditions. Careful analysis and understanding of (1) and (2) can completely remove the possibility of spurious hook switch interrupts due to ambient noise conditions. Where the MICBIAS resistor is large enough such that the minimum specified the DC level when MICSHORT_THR = 00 is close to the level of possible MICBIAS AC current spikes, the probability of false detections is greatly reduced by 2 design features: 1. Hysteresis of the hook switch detect function means that a different current threshold is used for detecting button push and button release. 2. Digital filtering means that the hook switch detection event is only signalled when the MICBIAS current has satisfied the threshold condition for 10 successive measurements, as shown in Error! Reference source not found.. The hook switch detect measurement frequency and the detection delay time tSHORT are detailed in the "Electrical Characteristics". Figure 27 MIC Hook Switch Detect Filtering The filtering algorithm helps to reject spurious interrupts caused by very high current spikes due to ambient conditions such as wind noise or mechanical shock. Note that the filtering algorithm provides only limited rejection of very high current spikes with frequencies less than or equal to the hook switch detect measurement frequency, or frequencies equal to harmonics of the hook switch detect measurement frequency. An example sequence including hook switch detection is detailed in the "Applications Information" section on page 154. w PP, Rev 3.1, August 2009 34 WM8903 Pre-Production MICROPHONE HOOK SWITCH CLOCKING REQUIREMENTS A clock is required for the Hook Switch Detect circuit. This requires: 1. MCLK to be present 2. CLK_SYS_ENA = 1 3. WSMD_CLK_ENA = 1 Any hook switch press (or release) which happens while one or more of the above criteria are not satisfied (for example during a low power mode where the CPU has disabled MCLK) can still be detected after the clocking conditions are met. The example sequence in Figure 26, where the event happened while MCLK was stopped, is also applicable to microphone hook switch press (or release). DIGITAL MICROPHONE INTERFACE The WM8903 supports a two-channel digital microphone interface. The two-channel audio data is multiplexed on the DMIC_DAT input and clocked by the DMIC_LR output. The Digital Microphone Input, DMIC_DAT, is provided on the GPIO2/DMIC_DAT pin. The associated clock, DMIC_LR, is provided on the GPIO1/DMIC_LR pin. The Digital Microphone Input is selected as input by setting the ADC_DIG_MIC bit. When the Digital Microphone Input is selected, the ADC input is deselected. The Digital Microphone Interface configuration is illustrated in Figure 28. Figure 28 Digital Microphone Interface Control Because the WM8903 digital microphone interface pins are powered in the DBVDD domain, it is recommended to power the digital microphone from the same DBVDD supply as WM8903. When GPIO1 is configured as DMIC_LR Clock output, the WM8903 outputs a clock which supports Digital Mic operation at a multiple of the ADC sampling rate, in the range 1-3MHz. Note that, although the ADC is not used when the digital microphone interface is selected, it is still necessary to set the ADC sample rate in order to ensure correct operation of the DSP functions associated with the digital microphone. See "Clocking and Sample Rates" for the details of the supported clocking configurations. When GPIO2/DMIC_DAT is configured as DMIC_DAT input, this pin is the digital microphone input. Up to two microphones can share this pin; the two microphones are interleaved as illustrated in Figure 29. The digital microphone interface requires that MIC1 transmits a data bit each time that DMIC_LR is high, and MIC2 transmits when DMIC_LR is low. The WM8903 samples the digital microphone data in the middle of each DMIC_LR clock phase. Each microphone must tri-state its data output when the other microphone is transmitting. w PP, Rev 3.1, August 2009 35 WM8903 Pre-Production Figure 29 Digital Microphone Interface Timing The digital microphone interface control fields are described in Table 7. REGISTER ADDRESS R164 (A4h) Clock Rate Test 4 BIT 9 LABEL ADC_DIG_MIC DEFAULT 0 DESCRIPTION Enables Digital Microphone mode. 0 = Audio DSP input is from ADC 1 = Audio DSP input is from digital microphone interface Table 7 Digital Microphone Interface Control In addition to setting the ADC_DIG_MIC bit as described in Table 7, the pins GPIO1/DMIC_LR and GPIO2/DMIC_DAT must also be configured to provide the digital microphone interface function. See "General Purpose Input/Output (GPIO)" for details. w PP, Rev 3.1, August 2009 36 WM8903 Pre-Production ANALOGUE-TO-DIGITAL CONVERTER (ADC) The WM8903 uses two 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full-scale input level is proportional to AVDD. See "Electrical Characteristics" section for further details. Any input signal greater than full scale may overload the ADC and cause distortion. The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits. REGISTER ADDRESS R18 (12h) Power Management 6 BIT LABEL DEFAULT DESCRIPTION 1 ADCL_ENA 0 Left ADC Enable 0 = disabled 1 = enabled 0 ADCR_ENA 0 Right ADC Enable 0 = disabled 1 = enabled Table 8 ADC Enable Control Configuring the ADC for 96kHz sample rate requires a specific sequence as detailed in the "Clocking and Sample Rates" section. ADC DIGITAL VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to +17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: MUTE for X = 0 ADC gain = 0.375 x (X-192) dB for 1 X 239; ADC gain = +17.625dB for 239 X 255 The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the ADCL_VOL or ADCR_VOL control data is loaded into the respective control register, but does not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to ADC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R36 (24h) ADC Digital Volume Left BIT 8 7:0 R37 (25h) ADC Digital Volume Right 8 7:0 LABEL ADCVU ADCL_VOL [7:0] ADCVU ADCR_VOL [7:0] DEFAULT DESCRIPTION N/A ADC Volume Update Writing a 1 to this bit causes left and right ADC volume to be updated simultaneously 1100_0000 (0dB) Left ADC Digital Volume (See Table 10 for volume range) N/A ADC Volume Update Writing a 1 to this bit causes left and right ADC volume to be updated simultaneously 1100_0000 (0dB) Right ADC Digital Volume (See Table 10 for volume range) Table 9 ADC Digital Volume Control w PP, Rev 3.1, August 2009 37 WM8903 Pre-Production ADCL_VOL or ADCL_VOL or ADCL_VOL or ADCL_VOL or ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 Table 10 ADC Digital Volume Range w PP, Rev 3.1, August 2009 38 WM8903 Pre-Production HIGH-PASS FILTER (HPF) A digital high-pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in handheld applications (e.g. wind noise, handling noise or mechanical vibration). This filter is controlled using the ADC_HPF_ENA and ADC_HPF_CUT register bits (see Table 11). In hi-fi mode the high pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.7Hz at fs=44.1kHz. In voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300Hz (e.g. ADC_HPF_CUT=11 at fs=8kHz or ADC_HPF_CUT=10 at fs=16kHz). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R38 (26h) ADC Digital 0 6:5 ADC_HPF_CUT [1:0] 00 ADC Digital High Pass Filter CutOff Frequency (fc) 00 = Hi-fi mode (fc=4Hz at fs=48kHz) 01 = Voice mode 1 (fc=127Hz at fs=16kHz) 10 = Voice mode 2 (fc=130Hz at fs=8kHz) 11 = Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate fs. See Table 12 for cut-off frequencies at all supported sample rates) 4 ADC_HPF_ENA 1 ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled Table 11 ADC High-pass Filter Control Registers Value of ADC_HPF_CUT bits Sample Rate (kHz) 00 01 10 11 Cut-off frequency (Hz) 8.000 0.7 64 130 11.025 0.9 88 178 267 367 16.000 1.3 127 258 532 22.050 1.9 175 354 733 24.000 2.0 190 386 798 32.000 2.7 253 514 1063 44.100 3.7 348 707 1464 48.000 4.0 379 770 1594 88.200 7.4 696 1414 2928 96.000 8.0 758 1540 3188 Table 12 ADC High-pass Filter Cut-off Frequencies Filter response plots for the ADC high-pass filter are shown in "Digital Filter Characteristics". w PP, Rev 3.1, August 2009 39 WM8903 Pre-Production ADC OVERSAMPLING RATIO (OSR) The ADC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is high for best performance; using the lower OSR setting reduces ADC power consumption. REGISTER ADDRESS BIT LABEL DEFAULT R10 (0Ah) Analogue ADC 0 0 ADC_OSR128 1 DESCRIPTION ADC Oversampling Ratio 0 = Low Power (64 x fs) 1 = High Performance (128 x fs) Note that the Low Power options is not supported when CLK_SYS_MODE=10 Table 13 ADC Oversampling Ratio Note that the Low Power (64 x fs) oversampling option is not supported when CLK_SYS_MODE=10 (see "Clocking and Sample Rates", Table 61). DYNAMIC RANGE CONTROL (DRC) The dynamic range controller (DRC) is a circuit which can be enabled in the digital data path of the ADC. Its function is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates `anti-clip' and `quick release' features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. The DRC is enabled as shown in Table 14. REGISTER ADDRESS R40 (28h) DRC 0 BIT 15 LABEL DRC_ENA DEFAULT 0 DESCRIPTION DRC enable 1 = enabled 0 = disabled Table 14 DRC Enable COMPRESSION/LIMITING CAPABILITIES The DRC supports two different compression regions, specified by R0 and R1, separated by a "knee" at input amplitude T. For signals above the knee, the compression slope R0 applies; for signals below the knee, the compression slope R1 applies. The overall DRC compression characteristic in "steady state" (i.e. where the input amplitude is nearconstant) is illustrated in Figure 30. w PP, Rev 3.1, August 2009 40 WM8903 DRC Output Amplitude (dB) Pre-Production Figure 30 DRC Compression Characteristic The slope of R0 and R1 are determined by register fields DRC_R0_SLOPE_COMP and DRC_R1_SLOPE_COMP respectively. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. The "knee" in Figure 30 is represented by T and Y, which are determined by register fields DRC_THRESH_COMP and DRC_AMP_COMP respectively. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation The DRC Compression parameters are defined in Table 15. w PP, Rev 3.1, August 2009 41 WM8903 Pre-Production REGISTER ADDRESS R42 (2Ah) DRC 2 R43 (2Bh) DRC 3 BIT LABEL DEFAULT DESCRIPTION 5:3 DRC_R0_SLOP E_COMP [2:0] 100 Compressor slope R0 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved 2:0 DRC_R1_SLOP E_COMP [2:0] 000 Compressor slope R1 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved 10:5 DRC_THRESH_ COMP [5:0] 000000 Compressor threshold T (dB) 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB ... (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 4:0 DRC_AMP_CO MP [4:0] 00000 Compressor amplitude at threshold YT (dB) 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB ... (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved Table 15 DRC Compression Control GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN and DRC_MAXGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 30. If the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. The maximum gain prevents quiet signals (or silence) from being excessively amplified. w PP, Rev 3.1, August 2009 42 WM8903 Pre-Production REGISTER ADDRESS R41(29h) DRC 1 BIT LABEL DEFAULT DESCRIPTION 3:2 DRC_MINGAIN [1:0] 00 Minimum gain the DRC can use to attenuate audio signals 00 = 0dB (default) 01 = -6dB 10 = -12dB 11 = -18dB 1:0 DRC_MAXGAIN [1:0] 01 Maximum gain the DRC can use to boost audio signals 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 36dB Table 16 DRC Gain Limits DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period of time. The DRC_ATTACK_RATE determines how quickly the DRC gain decreases when the signal amplitude is high. The DRC_DECAY_RATE determines how quickly the DRC gain increases when the signal amplitude is low. These register fields are described in Table 17. Note that the register defaults are suitable for general purpose microphone use. REGISTER ADDRESS R41 (29h) DRC 1 BIT LABEL DEFAULT DESCRIPTION 15:12 DRC_ATTACK_ RATE [3:0] 0011 Gain attack rate (seconds/6dB) 0000 = instantaneous 0001 = 363us 0010 = 726us 0011 = 1.45ms (default) 0100 = 2.9ms 0101 = 5.8ms 0110 = 11.6ms 0111 = 23.2ms 1000 = 46.4ms 1001 = 92.8ms 1010 = 185.6ms 1011-1111 = Reserved 11:8 DRC_DECAY_R ATE [3:0] 0010 Gain decay rate (seconds/6dB) 0000 = 186ms 0001 = 372ms 0010 = 743ms (default) 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = Reserved Table 17 DRC Time Constants w PP, Rev 3.1, August 2009 43 WM8903 Pre-Production ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the DRC_ANTICLIP_ENA bit. Note that the feed-forward processing increases the latency in the input signal path. For low-latency applications (e.g. telephony), it may be desirable to reduce the delay, although this will also reduce the effectiveness of the anti-clip feature. The latency is determined by the DRC_FF_DELAY bit. If necessary, the latency can be minimised by disabling the anti-clip feature altogether. The DRC Anti-Clip control bits are described in Table 18. REGISTER ADDRESS R40 (28h) DRC 0 BIT LABEL DEFAULT DESCRIPTION 5 DRC_FF_DELAY 1 Feed-forward delay for anti-clip feature 0 = 5 samples 1 = 9 samples Time delay can be calculated as 5/fs or 9/ fs, where fs is the sample rate. 1 DRC_ANTICLIP_ ENA 1 Anti-clip enable 0 = disabled 1 = enabled Table 18 DRC Anti-Clip Control Note that the Anti-Clip feature operates entirely in the digital domain, i.e. after the ADC. It cannot be used to prevent signal clipping in the analogue domain (e.g. in the input PGAs or ADCs), nor in the source signal. Analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. QUICK RELEASE CONTROL The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. The Quick Release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of DRC_DECAY_RATE. The Quick-Release feature is enabled by setting the DRC_QR_ENA bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by DRC_THRESH_QR, then the normal decay rate (DRC_DECAY_RATE) is ignored and a faster decay rate (DRC_RATE_QR) is used instead. The DRC Quick-Release control bits are described in Table 19. w PP, Rev 3.1, August 2009 44 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R40 (28h) DRC 0 2 DRC_QR_ENA 1 Quick release enable 0 = disabled 1 = enabled R41 (29h) DRC 1 7:6 DRC_THRESH_ QR [1:0] 01 Quick release crest factor threshold 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 30dB 5:4 DRC_RATE_QR [1:0] 00 Quick release decay rate (seconds/6dB) 00 = 0.725ms (default) 01 = 1.45ms 10 = 5.8ms 11 = Reserved Table 19 DRC Quick-Release Control GAIN SMOOTHING The DRC includes a gain smoothing filter in order to prevent gain ripples. A programmable level of hysteresis is also used to control the DRC gain. This improves the handling of very low frequency input signals whose period is close to the DRC attack/decay time. DRC Gain Smoothing is enabled by default and it is recommended to use the default register settings. The extent of the gain smoothing filter may be adjusted or disabled using the control fields described in Table 20. REGISTER ADDRESS R40 (28h) DRC 0 BIT LABEL DEFAULT DESCRIPTION 12:11 DRC_THRESH_ HYST [1:0] 01 Gain smoothing hysteresis threshold 00 = Low 01 = Medium (recommended) 10 = High 11 = Reserved 3 DRC_SMOOTH _ENA 1 Gain smoothing enable 0 = disabled 1 = enabled 0 DRC_HYST_EN A 1 Gain smoothing hysteresis enable 0 = disabled 1 = enabled Table 20 DRC Gain Smoothing w PP, Rev 3.1, August 2009 45 WM8903 Pre-Production INITIALISATION When the DRC is initialised, the gain is set to the level determined by the DRC_STARTUP_GAIN register field. The default setting is 0dB, but values from -18dB to +36dB are available, as described in Table 21. REGISTER ADDRESS R40 (28h) DRC 0 BIT LABEL DEFAULT 10:6 DRC_STARTUP_ GAIN [4:0] 00110 DESCRIPTION Initial gain at DRC startup 00000 = -18dB 00001 = -15dB 00010 = -12dB 00011 = -9dB 00100 = -6dB 00101 = -3dB 00110 = 0dB (default) 00111 = 3dB 01000 = 6dB 01001 = 9dB 01010 = 12dB 01011 = 15dB 01100 = 18dB 01101 = 21dB 01110 = 24dB 01111 = 27dB 10000 = 30dB 10001 = 33dB 10010 = 36dB 10011 to 11111 = Reserved Table 21 DRC Initialisation DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right channel of the digital audio interface. In addition, data from either of the digital audio interface channels can be routed to either the left or the right DAC. See "Digital Audio Interface" for more information on the audio interface. DIGITAL MIXING PATHS Figure 31 shows the digital mixing paths available in the WM8903 digital core. w PP, Rev 3.1, August 2009 46 WM8903 Pre-Production Figure 31 Digital Mixing Paths The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left and right digital audio interface data. These register bits are described in Table 22. The input data source for each DAC can be changed under software control using register bits DACL_SRC and DACR_SRC. The polarity of each DAC input may also be modified using register bits DACL_DATINV and DACR_DATINV. These register bits are described in Table 22. w PP, Rev 3.1, August 2009 47 WM8903 Pre-Production REGISTER ADDRESS R24 (18h) Audio Interface 0 R38 (26h) ADC Digital 0 BIT LABEL DEFAULT DESCRIPTION 12 DACL_DATINV 0 Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted 11 DACR_DATINV 0 Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted 7 AIFADCL_SRC 0 Left Digital Audio channel source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 6 AIFADCR_SRC 1 Right Digital Audio channel source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 5 AIFDACL_SRC 0 Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data 4 AIFDACR_SRC 1 Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data 1 ADCL_DATINV 0 Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted 0 ADCR_DATINV 0 Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted Table 22 Digital Mixing Control w PP, Rev 3.1, August 2009 48 WM8903 Pre-Production DAC INTERFACE VOLUME BOOST A digital gain function is available at the audio interface to boost the DAC volume when a small signal is received on DACDAT. This is controlled using register bits DAC_BOOST[1:0]. To prevent clipping at the DAC input, this function should not be used when the boosted DAC data is expected to be greater than 0dBFS. REGISTER ADDRESS R24 (18h) Audio Interface 0 BIT 10:9 LABEL DAC_BOOST [1:0] DEFAULT 00 DESCRIPTION DAC Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS) 10 = +12dB (Input data must not exceed -12dBFS) 11 = +18dB (Input data must not exceed -18dBFS) Table 23 Digital Mixing Control DIGITAL SIDETONE Digital sidetone mixing (from ADC output into DAC input) is available when ADCs and DACs are operating at the same sample rate. Digital data from either left or right ADC can be mixed with the audio interface data on the left and right DAC channels. Sidetone data is taken from the ADC high-pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). The digital sidetone will not function when ADCs and DACs are operating at different sample rates. When using the digital sidetone, it is recommended that the ADCs are enabled before un-muting the DACs to prevent pop noise. The DAC volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the DAC input. When using the digital sidetone, it is recommended that dynamic control of the charge pump is not enabled, i.e. CP_DYN_PWR should be cleared to 00. See the "Charge Pump" section for details. The digital sidetone is controlled as shown in Table 24. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R32 (20h) DAC Digital 0 11:8 ADCL_DAC_SV OL [3:0] 0000 Left Digital Sidetone Volume (See Table 25 for volume range) 7:4 ADCR_DAC_SV OL [3:0] 0000 Right Digital Sidetone Volume (See Table 25 for volume range) 3:2 ADC_TO_DACL [1:0] 00 Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved 1:0 ADC_TO_DACR [1:0] 00 Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Table 24 Digital Sidetone Control w PP, Rev 3.1, August 2009 49 WM8903 Pre-Production ADCL_DAC_SVOL or ADCR_DAC_SVOL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SIDETONE VOLUME -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 0 0 0 Table 25 Digital Sidetone Volume in dB w PP, Rev 3.1, August 2009 50 WM8903 Pre-Production DIGITAL-TO-ANALOGUE CONVERTER (DAC) The WM8903 DACs receive digital input data from the DACDAT pin and via the digital sidetone path (see "Digital Mixing" section). The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The Wolfson SmartDACTM architecture offers reduced power consumption, whilst also delivering a reduction in high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The analogue outputs from the DACs can then be mixed with other analogue inputs before being sent to the analogue output pins (see "Output Signal Path"). The DACs are enabled by the DACL_ENA and DACR_ENA register bits. REGISTER ADDRESS R18 (12h) Power Management 6 BIT LABEL DEFAULT DESCRIPTION 3 DACL_ENA 0 Left DAC Enable 0 = DAC disabled 1 = DAC enabled 2 DACR_ENA 0 Right DAC Enable 0 = DAC disabled 1 = DAC enabled Table 26 DAC Enable Control DAC DIGITAL VOLUME CONTROL The output level of each DAC can be controlled digitally over a range from -71.625dB to 0dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by: MUTE for X = 0 DAC gain = 0.375 x (X-192) dB for 1 X 192 DAC gain = 0dB for 192 X 255 The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the DACL_VOL or DACR_VOL control data is loaded into the respective control register, but does not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to DAC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R30 (1Eh) DAC Digital Volume Left BIT 8 7:0 R31 (1Fh) DAC Digital Volume Right 8 7:0 LABEL DACVU DACL_VOL [7:0] DACVU DACR_VOL [7:0] DEFAULT DESCRIPTION N/A DAC Volume Update Writing a 1 to this bit causes left and right DAC volume to be updated simultaneously 1100_0000 (0dB) Left DAC Digital Volume (See Table 28 for volume range) N/A DAC Volume Update Writing a 1 to this bit causes left and right DAC volume to be updated simultaneously 1100_0000 (0dB) Right DAC Digital Volume (See Table 28 for volume range) Table 27 DAC Digital Volume Control w PP, Rev 3.1, August 2009 51 WM8903 Pre-Production DACL_VOL or DACL_VOL or DACL_VOL or DACL_VOL or DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 Table 28 DAC Digital Volume Range w PP, Rev 3.1, August 2009 52 WM8903 Pre-Production DAC SOFT MUTE AND SOFT UN-MUTE The WM8903 has a soft mute function. When enabled, this gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the DAC_MUTEMODE register bit. The DAC is not muted by default (DAC_MUTE = 0). To mute the DAC, this function must be enabled by setting DAC_MUTE to 1. Soft Mute Mode would typically be enabled (DAC_MUTEMODE = 1) when using DAC_MUTE during playback of audio data so that when DAC_MUTE is subsequently disabled, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). Soft Mute Mode would typically be disabled (DAC_MUTEMODE = 0) when un-muting at the start of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). DAC muting and un-muting using volume control bits DACL_VOL and DACR_VOL. DAC muting DAC_MUTE. and un-muting using soft mute bit Soft Mute Mode not enabled (DAC_MUTEMODE = 0). DAC muting DAC_MUTE. and un-muting using soft mute bit Soft Mute Mode enabled (DAC_MUTEMODE = 1). Figure 32 DAC Mute Control The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 can be selected, as shown in Table 29. The ramp rate determines the rate at which the volume is increased or decreased. The actual ramp time depends on the extent of the difference between the muted and un-muted volume settings. REGISTER ADDRESS R33 (21h) DAC Digital 1 BIT LABEL DEFAULT DESCRIPTION 10 DAC_MUTERA TE 0 DAC Soft Mute Ramp Rate 0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) 9 DAC_MUTEM ODE 0 DAC Soft Mute Mode 0 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to change immediately to DACL_VOL and DACR_VOL settings 1 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the DACL_VOL and DACR_VOL settings 3 DAC_MUTE 0 DAC Soft Mute Control 0 = DAC Un-mute 1 = DAC Mute Table 29 DAC Soft-Mute Control w PP, Rev 3.1, August 2009 53 WM8903 Pre-Production DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on whichever DAC is enabled. To prevent clipping, a -6dB attenuation is automatically applied to the mono mix. Only one DAC must be enabled in order to use this function. REGISTER ADDRESS R33 (21h) DAC Digital 1 BIT 12 LABEL DAC_MONO DEFAULT 0 DESCRIPTION DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DAC) Table 30 DAC Mono Mix DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. See "Digital Filter Characteristics" for details of de-emphasis filter characteristics. REGISTER ADDRESS BIT R33 (21h) DAC Digital 1 2:1 LABEL DEEMPH [1:0] DEFAULT 00 DESCRIPTION DAC De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate Table 31 DAC De-Emphasis Control DAC SLOPING STOPBAND FILTER Two DAC filter types are available, selected by the register bit DAC_SB_FILT. When operating at sample rates 24kHz (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (DAC_SB_FILT=1) to reduce out-of-band noise which can be audible at low DAC sample rates. See "Digital Filter Characteristics" for details of DAC filter characteristics. REGISTER ADDRESS R33 (21h) DAC Digital 1 BIT 11 LABEL DAC_SB_FILT DEFAULT 0 DESCRIPTION Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode (recommended when fs 24kHz) Table 32 DAC Sloping Stopband Filter w PP, Rev 3.1, August 2009 54 WM8903 Pre-Production DAC BIAS CONTROL The analogue circuits within the DAC use the Master bias current (see "Reference Voltages and Master Bias"). The DAC bias currents can also be reduced using the DACBIAS_SEL and DACVMID_SEL fields as described in Table 33. These can be used to reduce power consumption, but may have a marginal impact on audio performance in some usage modes. The DAC bias currents can be increased using the DAC_BIAS_BOOST field. Setting this bit doubles the bias level of DACBIAS_SEL and DACVMID_BIAS_SEL. This offers a performance improvement, but also an increase in power consumption. Note that the increased DAC VMID buffer bias is unlikely to give better performance; when DAC_BIAS_BOOST is set, it is recommended to set DACVMID_BIAS_SEL = 01 in order to restore the Normal DAC VMID buffer bias level. REGISTER ADDRESS R8 (08h) Analogue DAC 0 BIT LABEL DEFAULT DESCRIPTION 5 DAC_BIAS_BOO ST 0 DAC Bias boost 0 = Disable 1 = Enable When DAC Bias boost is enabled, the bias selected by DACBIAS_SEL and DACVMID_BIAS_SEL are both doubled. 4:3 DACBIAS_SEL 00 DAC bias current select 00 = Normal bias 01 = Normal bias x 0.5 10 = Normal bias x 0.66 11 = Normal bias x 0.75 2:1 DACVMID_BIAS_ SEL 00 DAC VMID buffer bias select 00 = Normal bias 01 = Normal bias x 0.5 10 = Normal bias x 0.66 11 = Normal bias x 0.75 Table 33 DAC Bias Control DAC OVERSAMPLING RATIO (OSR) The DAC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is low for reduced power consumption; using the higher OSR setting improves the DAC signal-to-noise performance. REGISTER ADDRESS R33 (21h) DAC Digital 1 BIT LABEL DEFAULT DESCRIPTION 0 DAC_OSR 0 DAC Oversampling Control 0 = Low power (normal oversample) 1 = High performance (double rate) Table 34 DAC Oversampling Control w PP, Rev 3.1, August 2009 55 WM8903 Pre-Production OUTPUT SIGNAL PATH The WM8903 has one pair of analogue mixers (the "left" and right" mixers) feeding the headphone outputs HPOUTL and HPOUTR as well as the line outputs LINEOUTL and LINEOUTR, and a separate pair of mixers (the "speaker mixers") feeding the differential line outputs LON/LOP and RON/ROP (these pins are in the "Analogue Outputs" section). The output signal paths and associated control registers are illustrated in Figure 33. CFB1 CFB2 CPVDD CPGND VPOS VNEG Figure 33 Output Signal Path and Control Registers w PP, Rev 3.1, August 2009 56 WM8903 Pre-Production OUTPUT SIGNAL PATHS ENABLE Each output pin and each mixer can be independently enabled and disabled as shown in Table 35. Note that the Headphone Outputs and Line Outputs are also controlled by fields located within Register R90 and R94, which provide suppression of pops & clicks when enabling and disabling these signal paths. These outputs cannot be fully enabled without the appropriate write operations to Registers R90 and R94. See Pop Suppression Control" for details of these registers. Under recommended usage conditions, all the control bits associated with enabling the Headphone Outputs and the Line Outputs will be configured by running the default Start-Up and Shut-Down sequences as described in the "Control Write Sequencer" section. In these cases, the user does not need to set the register fields in R13, R14, R15, R90 and R94 directly. REGISTER ADDRESS BIT R13 (0Dh) Power Management 1 1 MIXOUTL_ENA 0 Left Output Mixer Enable 0 = disabled 1 = enabled 0 MIXOUTR_ENA 0 Right Output Mixer Enable 0 = disabled 1 = enabled 1 HPL_PGA_ENA 0 Left Headphone Output Enable 0 = disabled 1 = enabled 0 HPR_PGA_ENA 0 Right Headphone Output Enable 0 = disabled 1 = enabled 1 LINEOUTL_PGA_ ENA 0 Left Line Output Enable 0 = disabled 1 = enabled 0 LINEOUTR_PGA _ENA 0 Right Line Output Enable 0 = disabled 1 = enabled 1 MIXSPKL_ENA 0 Left Speaker Mixer Enable 0 = disabled 1 = enabled 0 MIXSPKR_ENA 0 Right Speaker Mixer Enable 0 = disabled 1 = enabled 1 SPKL_ENA 0 Left Speaker Output Enable 0 = disabled 1 = enabled 0 SPKR_ENA 0 Right Speaker Output Enable 0 = disabled 1 = enabled R14 (0Eh) Power Management 2 R15 (0Fh) Power Management 3 R16 (10h) Power Management 4 R17 (11h) Power Management 5 LABEL DEFAULT DESCRIPTION Table 35 Output Signal Paths Enable To enable the output PGAs and mixers, the reference voltage VMID and the bias current must also be enabled. See "Reference Voltages and Master Bias" for details of the associated controls VMID_RES and BIAS_ENA. w PP, Rev 3.1, August 2009 57 WM8903 Pre-Production OUTPUT PGA BIAS CONTROL The output PGA circuits use the Master bias current (see "Reference Voltages and Master Bias"). The output PGA bias currents can also be controlled using the PGA_BIAS field as described in Table 36. Selecting a lower bias can be used to reduce power consumption, but may have a marginal impact on audio performance in some usage modes. Selecting a higher bias offers a performance improvement, but also an increase in power consumption. REGISTER ADDRESS BIT R172 (ACh) Analogue Output Bias 0 6:4 LABEL PGA_BIAS [2:0] DEFAULT DESCRIPTION 000 Headphone and Lineout PGA bias control 000 = Normal bias 001 = Normal bias x 1.5 010 = Normal bias x 0.75 011 = Normal bias x 0.5 100 = Normal bias x 0.33 101 = Normal bias 110 = Normal bias 111 = Normal bias x 2 Table 36 Output PGA Bias Control OUTPUT DRIVERS BIAS CONTROL The bias of the Headphone and Lineout drivers can be controlled independently of the PGA bias. These may be increased or decreased using the OUTPUTS_BIAS field as described in Table 37. This can be used to reduce power consumption or improve performance. If it is desired to improve the performance of the outputs with the minimum increase in power consumption, then it is recommended to increase the OUTPUTS_BIAS level and to use the default setting of PGA_BIAS. REGISTER ADDRESS BIT LABEL DEFAULT R187 (BBh) Analogue Output Bias 2 2:0 OUTPUTS_BIAS [2:0] 000 DESCRIPTION Headphone and Lineout Output Drivers bias control 000 = Normal bias 001 = Normal bias x 1.5 010 = Normal bias x 0.75 011 = Normal bias x 0.5 100 = Normal bias x 0.33 101 = Normal bias 110 = Normal bias 111 = Normal bias x 2 Table 37 Output Drivers Bias Control w PP, Rev 3.1, August 2009 58 WM8903 Pre-Production OUTPUT MIXER CONTROL Each of the four output mixers has the same four inputs: * * DAC Left DAC Right * * Bypass Left Bypass Right The input signals to the left and right mixers (feeding HPOUTL/R and LINEOUTL/R) are enabled using the register fields described in Table 38. These mixers do not provide volume controls on the inputs or outputs. However, input signals can be attenuated at source using the control fields LIN_VOL, RIN_VOL, DACL_VOL and DACR_VOL. REGISTER ADDRESS BIT LABEL DEFAULT R50 (32h) Analogue Left Mix 0 3 DACL_TO_MIXO UTL 1 Left DAC to Left Output Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXO UTL 0 Right DAC to Left Output Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MI XOUTL 0 Left Analogue Input to Left Output Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_M IXOUTL 0 Right Analogue Input to Left Output Mixer Enable 0 = disabled 1 = enabled 3 DACL_TO_MIXO UTR 0 Left DAC to Right Output Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXO UTR 1 Right DAC to Right Output Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MI XOUTR 0 Left Analogue Input to Right Output Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_M IXOUTR 0 Right Analogue Input to Right Output Mixer Enable 0 = disabled 1 = enabled R51 (33h) Analogue Right Mix 0 DESCRIPTION Table 38 Headphone and Line Output Mixer Control w PP, Rev 3.1, August 2009 59 WM8903 Pre-Production The input signals to the speaker mixers are enabled and controlled using the register fields described in Table 39. These mixers provide a selectable 0dB or -6dB volume control on each input. The input signals may also be controlled at source using the control fields LIN_VOL, RIN_VOL, DACL_VOL and DACR_VOL, but it should be noted that adjusting these fields would also affect the other output mixers. REGISTER ADDRESS BIT LABEL DEFAULT R52 (34h) Analogue Spk Mix Left 0 3 DACL_TO_MIXSP KL 0 Left DAC to Left Spkr Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXS PKL 0 Right DAC to Left Spkr Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MI XSPKL 0 Left Analogue Input to Left Spkr Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_MI XSPKL 0 Right Analogue Input to Left Spkr Mixer Enable 0 = disabled 1 = enabled 3 DACL_MIXSPKL_ VOL 0 Left DAC to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB 2 DACR_MIXSPKL_ VOL 0 Right DAC to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB 1 BYPASSL_MIXSP KL_VOL 0 Left Analogue Input to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB 0 BYPASSR_MIXS PKL_VOL 0 Right Analogue Input to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB 3 DACL_TO_MIXSP KR 0 Left DAC to Right Spkr Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXS PKR 0 Right DAC to Right Spkr Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MI XSPKR 0 Left Analogue Input to Right Spkr Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_MI XSPKR 0 Right Analogue Input to Right Spkr Mixer Enable 0 = disabled 1 = enabled R53 (35h) Analogue Spk Mix Left 1 R54 (36h) Analogue Spk Mix Right 0 w DESCRIPTION PP, Rev 3.1, August 2009 60 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R55 (37h) Analogue Spk Mix Right 1 3 DACL_MIXSPKR_ VOL 0 Left DAC to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB 2 DACR_MIXSPKR _VOL 0 Right DAC to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB 1 BYPASSL_MIXSP KR_VOL 0 Left Analogue Input to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB 0 BYPASSR_MIXS PKR_VOL 0 Right Analogue Input to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB Table 39 Speaker Mixer Control OUTPUT VOLUME CONTROL Each analogue output can be independently controlled. The headphone output control fields are described in Table 40. The line output control fields are described in Table 41. The differential line output control fields are described in Table 42. The output pins are described in more detail in "Analogue Outputs". The volume and mute status of each output can be controlled individually. To prevent "zipper noise" when a volume adjustment is made, a zero-cross function is provided on all output paths. When this function is enabled, volume updates will not take place until a zero-crossing is detected. In the event of a long period without zero-crossings, a timeout will apply. The timeout must be enabled by setting the TO_ENA bit, as defined in Table 61. The volume update bits control the loading of the output driver volume data. For example, when HPOUTVU is set to 0, the headphone volume data can be loaded into the respective control register, but will not actually change the gain setting. The Left and Right headphone volume settings are updated when a 1 is written to HPOUTVU. This makes it possible to update the gain of a Left/Right pair of output paths simultaneously. w PP, Rev 3.1, August 2009 61 WM8903 Pre-Production REGISTER ADDRESS R57 (39h) Analogue OUT1 Left BIT DEFAULT DESCRIPTION 8 HPL_MUTE 0 Left Headphone Output Mute 0 = Un-mute 1 = Mute 7 HPOUTVU 0 Headphone Output Volume Update Writing a 1 to this bit will update HPOUTL and HPOUTR volumes simultaneously. 6 HPOUTLZC 0 Left Headphone Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 R58 (3Ah) Analogue OUT1 Right LABEL HPOUTL_VOL [5:0] 10_1101 Left Headphone Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB 8 HPR_MUTE 0 Right Headphone Output Mute 0 = Un-mute 1 = Mute 7 HPOUTVU 0 Headphone Output Volume Update Writing a 1 to this bit will update HPOUTL and HPOUTR volumes simultaneously. 6 HPOUTRZC 0 Right Headphone Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 HPOUTR_VOL [5:0] 10_1101 Right Headphone Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Table 40 Volume Control for HPOUTL and HPOUTR w PP, Rev 3.1, August 2009 62 WM8903 Pre-Production REGISTER ADDRESS R59 (3Bh) Analogue OUT2 Left R60 (3Ch) Analogue OUT2 Right BIT LABEL DEFAULT DESCRIPTION 8 LINEOUTL_MUTE 0 Left Line Output Mute 0 = Un-mute 1 = Mute 7 LINEOUTVU 0 Line Output Volume Update Writing a 1 to this bit will update LINEOUTL and LINEOUTR volumes simultaneously. 6 LINEOUTLZC 0 Left Line Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 LINEOUTL_VOL [5:0] 11_1001 8 LINEOUTR_MUT E 0 7 LINEOUTVU 0 Line Output Volume Update Writing a 1 to this bit will update LINEOUTL and LINEOUTR volumes simultaneously. 6 LINEOUTRZC 0 Right Line Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 LINEOUTR_VOL [5:0] 11_1001 Left Line Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Right Line Output Mute 0 = Un-mute 1 = Mute Right Line Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Table 41 Volume Control for LINEOUTL and LINEOUTR w PP, Rev 3.1, August 2009 63 WM8903 Pre-Production REGISTER ADDRESS R62 (3Eh) Analogue OUT3 Left BIT DEFAULT DESCRIPTION 8 SPKL_MUTE 1 Left Speaker Output Mute 0 = Un-mute 1 = Mute 7 SPKVU 0 Speaker Output Volume Update Writing a 1 to this bit will update LON/LOP and RON/ROP volumes simultaneously. 6 SPKLZC 0 Left Speaker Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 R63 (3Fh) Analogue OUT3 Right LABEL SPKL_VOL [5:0] 11_1001 Left Speaker Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Right Speaker Output Mute 0 = Un-mute 1 = Mute 8 SPKR_MUTE 1 7 SPKVU 0 Speaker Output Volume Update Writing a 1 to this bit will update LON/LOP and RON/ROP volumes simultaneously. 6 SPKRZC 0 Right Speaker Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 SPKR_VOL [5:0] 11_1001 Right Speaker Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Table 42 Volume Control for LON/LOP and RON/ROP w PP, Rev 3.1, August 2009 64 WM8903 Pre-Production ANALOGUE OUTPUTS The WM8903 has eight analogue output pins: * * * Headphone outputs, HPOUTL and HPOUTR Line outputs, LINEOUTL and LINEOUTR Differential line outputs, LON/LOP and RON/ROP The output signal paths and associated control registers are illustrated in Figure 33. HEADPHONE OUTPUTS - HPOUTL AND HPOUTR The headphone outputs are designed to drive 16 or 32 headphones. These outputs are groundreferenced, i.e. no series capacitor is required between the pins and the headphone load. They are powered by an on-chip charge pump (see "Charge Pump" section). Signal volume at the headphone outputs is controlled as shown in Table 40. LINE OUTPUTS - LINEOUTL AND LINEOUTR The line outputs are similar to the headphone outputs in design. They are ground-referenced and power by the on-chip charge pump. However, these outputs are intended for driving line loads, as the charge pump powering both the Headphone and Line outputs can only provide sufficient power to drive one set of headphones at any given time. Signal volume at the line outputs is controlled as shown in Table 41. DIFFERENTIAL LINE OUTPUTS - LON/LOP AND RON/ROP The differential line outputs are designed to differential line loads, including external loudspeaker drivers. The WM9001 is an ideal component for driving loudspeakers from these outputs. These pins are referenced to VMID (AVDD/2) and are powered directly from the AVDD supply. Signal volume at the differential line outputs is controlled as shown in Table 42. w PP, Rev 3.1, August 2009 65 WM8903 Pre-Production EXTERNAL COMPONENTS FOR GROUND-REFERENCED OUTPUTS In the case of the ground referenced outputs HPOUTL, HPOUTR, LINEOUTL and LINEOUTR, it is recommended to connect a zobel network to the audio output pins for best audio performance in all applications. The components of the zobel network have the effect of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions. Possible sources of these instabilities include the inductive load of a headphone coil or an active load in the form of an external line amplifier. The capacitance of lengthy cables or PCB tracks can also lead to amplifier instability. The zobel network should comprise a 20 resistor and 0.1F capacitor in series with each other, as illustrated in Figure 34. Output 0.1uF Load 20 Figure 34 Zobel Network Components for HPOUTL, HPOUTR, LINEOUTL and LINEOUTR It is recommended to include these components for best audio quality and amplifier stability in all cases. The differential line outputs LOP/LON and ROP/RON would, typically, be connected to differential line drivers such as the WM9001 speaker driver. In such applications, a zobel network is not required on these differential line outputs. w PP, Rev 3.1, August 2009 66 WM8903 Pre-Production REFERENCE VOLTAGES AND MASTER BIAS This section describes the analogue reference voltage and bias current controls. It also describes the VMID soft-start circuit for pop-free start-up and shut-down. Note that, under the recommended usage conditions of the WM8903, these features will be configured by running the default Start-Up and Shut-Down sequences as described in the "Control Write Sequencer" section. In these cases, the user does not need to set these register fields directly. The analogue circuits in the WM8903 require a mid-rail analogue reference voltage, VMID. This reference is generated from AVDD via a programmable resistor chain. Together with the external VMID decoupling capacitor, the programmable resistor chain results in a slow, normal or fast charging characteristic on VMID. This is controlled by VMID_RES[1:0], and can be used to optimise the reference for normal operation, low power standby or for fast start-up as described in Table 43. The analogue circuits in the WM8903 require a bias current. The normal bias current is enabled by setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also. The normal bias current can also be controlled using the ISEL field as described in Table 43. This can be used to reduce power consumption, but may have a detrimental impact on audio performance in some usage modes. The default setting is recommended. Note that the ADC, DAC and Output PGA bias circuits may also be adjusted in order to reduce power consumption. For details, see "Analogue-to-Digital Converter (ADC)", "Digital-to-Analogue Converter (DAC)" or "Output Signal Path". An alternate bias current source (Start-Up Bias) is provided for pop-free start-up; this is selected using POBCTRL (see Table 44). Note that the default setting of POBCTRL selects the Start-Up Bias. The normal bias is only selected when POBCTRL is set to logic 0. REGISTER ADDRESS BIT R4 (04h) Bias Control 0 3:2 ISEL [1:0] 10 Master Bias control 00 = Normal bias x 0.5 01 = Normal bias x 0.75 10 = Normal bias 11 = Normal bias x 1.5 0 BIAS_ENA 0 Enables the Normal bias current generator (for all analogue functions) 0 = Disabled 1 = Enabled VMID_RES [1:0] 00 VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) R5 (05h) VMID Control 0 2:1 LABEL DEFAULT DESCRIPTION Table 43 Reference Voltages w PP, Rev 3.1, August 2009 67 WM8903 Pre-Production A pop-suppressed start-up requires VMID to be enabled smoothly, without the step change normally associated with the initial stage of the VMID capacitor charging. A pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal path prior to the VMID reference voltage being applied. The WM8903 incorporates pop-suppression circuits which address these requirements. The alternate current source (Start-Up Bias) is enabled by STARTUP_BIAS_ENA. The start-up bias is selected (in place of the normal bias) by POBCTRL. It is recommended that the start-up bias is used during start-up, before switching back to the higher quality, normal bias. VMID_IO_ENA has the same functionality as STARTUP_BIAS_ENA. The start-up bias is enabled by setting either of these bits. A soft-start circuit is provided in order to control the switch-on of the VMID reference. The soft-start control circuit is enabled by setting VMID_SOFT. Three slew rates are provided, under control of the VMID_SOFT field. When the soft-start circuit is enabled prior to enabling VMID_RES, the reference voltage rises smoothly, without the step change that would otherwise occur. It is recommended that the soft-start circuit and the output signal path be enabled before VMID is enabled by VMID_RES. A soft shut-down is provided, using the soft-start control circuit and the start-up bias current generator. The soft shut-down of VMID is achieved by setting VMID_SOFT, STARTUP_BIAS_ENA and POBCTRL to select the start-up bias current and soft-start circuit prior to setting VMID_RES=00. REGISTER ADDRESS BIT R4 (04h) Bias Control 0 4 POBCTRL 1 Selects the bias current source 0 = Normal bias 1 = Start-Up bias 1 STARTUP_BIAS_ ENA 0 Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled 5 VMID_IO_ENA 0 Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled (same functionality as STARTUP_BIAS_ENA) VMID_SOFT [1:0] 10 VMID soft start enable / slew rate control 00 = Disabled 01 = Fast soft start 10 = Nominal soft start 11 = Slow soft start R5 (05h) VMID Control 0 4:3 LABEL DEFAULT DESCRIPTION Table 44 Soft Start Control w PP, Rev 3.1, August 2009 68 WM8903 Pre-Production POP SUPPRESSION CONTROL The WM8903 incorporates Wolfson's SilentSwitchTM technology which enables pops normally associated with Start-Up, Shut-Down or signal path control to be suppressed. To achieve maximum benefit from these features, careful attention is required to the sequence and timing of these controls. Note that, under the recommended usage conditions of the WM8903, these features will be configured by running the default Start-Up and Shut-Down sequences as described in the "Control Write Sequencer" section. In these cases, the user does not need to set these register fields directly. The analogue inputs to the WM8903 and the Differential Line (Speaker) outputs are biased to VMID in normal operation. In order to avoid audible pops caused by a disabled signal path dropping to AGND, the WM8903 can maintain these connections at VMID when the relevant input or output stage is disabled. This is achieved by connecting a buffered VMID reference to the input or output. The buffered VMID reference is enabled by setting VMID_BUF_ENA. When the buffered VMID reference is enabled, it is connected to any unused input pins by setting the BUFIO_ENA register bit. When buffered VMID is enabled, it is connected to any disabled Differential Line outputs (speaker driver outputs) by setting VMID_TIE_ENA. The resistance associated with VMID_TIE_ENA can be either 500 or 20k, depending on the VROI register bit. The output paths can be actively discharged to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known output stage condition prior to enabling the soft-start VMID reference voltage. This is also desirable in shut-down to prevent the external connections from being affected by the internal circuits. The Differential Line outputs (speaker driver outputs) can be discharged to AGND by setting SPK_DISCHARGE. The ground-referenced Headphone outputs and Line outputs are shorted to AGND by default; the short circuit is removed on each of these paths by setting the applicable fields HPL_RMV_SHORT, HPR_RMV_SHORT, LINEOUTL_RMV_SHORT or LINEOUTR_RMV_SHORT. The ground-referenced Headphone output and Line output drivers are designed to suppress pops and clicks when enabled or disabled. However, it is necessary to control the drivers in accordance with a defined sequence in start-up and shut-down to achieve the pop suppression. It is also necessary to schedule the DC Servo offset correction at the appropriate point in the sequence (see "DC Servo"). Table 45 and Table 46 describe the recommended sequences for enabling and disabling these output drivers. SEQUENCE HEADPHONE ENABLE LINEOUT ENABLE Step 1 HPL_ENA = 1 HPR_ENA = 1 LINEOUTL_ENA = 1 LINEOUTR_ENA = 1 Step 2 HPL_ENA_DLY = 1 HPR_ENA_DLY = 1 LINEOUTL_ENA_DLY = 1 LINEOUTR_ENA_DLY = 1 DC offset correction DC offset correction Step 4 HPL_ENA_OUTP = 1 HPR_ENA_OUTP = 1 LINEOUTL_ENA_OUTP = 1 LINEOUTR_ENA_OUTP = 1 Step 5 HPL_RMV_SHORT = 1 HPR_RMV_SHORT = 1 LINEOUTL_RMV_SHORT = 1 LINEOUTR_RMV_SHORT = 1 Step 3 Table 45 Headphone / Line Output Enable Sequence SEQUENCE HEADPHONE DISABLE LINEOUT DISABLE Step 1 HPL_RMV_SHORT = 0 HPR_RMV_SHORT = 0 LINEOUTL_RMV_SHORT LINEOUTR_RMV_SHORT Step 2 HPL_ENA = 0 HPL_ENA_DLY = 0 HPL_ENA_OUTP = 0 HPR_ENA = 0 HPR_ENA_DLY = 0 HPR_ENA_OUTP = 0 LINEOUTL_ENA LINEOUTL_ENA_DLY LINEOUTL_ENA_OUTP LINEOUTR_ENA LINEOUTR_ENA_DLY LINEOUTR_ENA_OUTP Table 46 Headphone / Line Output Disable Sequence w PP, Rev 3.1, August 2009 69 WM8903 Pre-Production The register bits relating to pop suppression control are defined in Table 47. REGISTER ADDRESS R5 (05h) VMID Control 0 R65 (41h) R90 (5Ah) Analogue HP 0 w BIT LABEL DEFAULT DESCRIPTION 7 VMID_TIE_ENA 0 VMID buffer to Differential Lineouts 0 = Disabled 1 = Enabled (only applies when relevant outputs are disabled, ie. SPLK=0 or SPKR=0. Resistance is controlled by VROI.) 6 BUFIO_ENA 0 VMID buffer to unused Inputs/Outputs 0 = Disabled 1 = Enabled 0 VMID_BUF_ENA 0 VMID Buffer Enable 0 = Disabled 1 = Enabled 1 SPK_DISCHARG E 0 Speaker Discharge Enable 0 = Disabled 1 = Enable 0 VROI 0 Select VMID_TIE_ENA resistance for disabled Differential Lineouts 0 = 20k ohm 1 = 500 ohm 7 HPL_RMV_SHOR T 0 Removes HPL short 0 = HPL short enabled 1 = HPL short removed In normal operation, this bit is set to 1 6 HPL_ENA_OUTP 0 Enables HPL output stage 0 = Disabled 1 = Enabled 5 HPL_ENA_DLY 0 Enables HPL intermediate stage 0 = Disabled 1 = Enabled 4 HPL_ENA 0 Enables HPL input stage 0 = Disabled 1 = Enabled 3 HPR_RMV_SHO RT 0 Removes HPR short 0 = HPR short enabled 1 = HPR short removed In normal operation, this bit is set to 1 2 HPR_ENA_OUTP 0 Enables HPR output stage 0 = Disabled 1 = Enabled 1 HPR_ENA_DLY 0 Enables HPR intermediate stage 0 = Disabled 1 = Enabled 0 HPR_ENA 0 Enables HPR input stage 0 = Disabled 1 = Enabled PP, Rev 3.1, August 2009 70 WM8903 Pre-Production REGISTER ADDRESS R94 (5Eh) Analogue Lineout 0 BIT LABEL DEFAULT DESCRIPTION 7 LINEOUTL_RMV _SHORT 0 Removes LINEOUTL short 0 = LINEOUTL short enabled 1 = LINEOUTL short removed In normal operation, this bit is set to 1 6 LINEOUTL_ENA_ OUTP 0 Enables LINEOUTL output stage 0 = Disabled 1 = Enabled 5 LINEOUTL_ENA_ DLY 0 Enables LINEOUTL intermediate stage 0 = Disabled 1 = Enabled 4 LINEOUTL_ENA 0 Enables LINEOUTL input stage 0 = Disabled 1 = Enabled 3 LINEOUTR_RMV _SHORT 0 Removes LINEOUTR short 0 = LINEOUTR short enabled 1 = LINEOUTR short removed In normal operation, this bit is set to 1 2 LINEOUTR_ENA _OUTP 0 Enables LINEOUTR output stage 0 = Disabled 1 = Enabled 1 LINEOUTR_ENA _DLY 0 Enables LINEOUTR intermediate stage 0 = Disabled 1 = Enabled 0 LINEOUTR_ENA 0 Enables LINEOUTR input stage 0 = Disabled 1 = Enabled Table 47 Pop Suppression Control w PP, Rev 3.1, August 2009 71 WM8903 Pre-Production CHARGE PUMP The WM8903 incorporates a dual-mode Charge Pump which generates the supply rails for the headphone and line output drivers (LINEOUTL/R). The Charge Pump has a single supply input, CPVDD, and generates split rails VPOS and VNEG according to the selected mode of operation. The Charge Pump connections are illustrated in Figure 35 (see "Electrical Characteristics" for external component values). An input decoupling capacitor may also be required at CPVDD, depending upon the system configuration. Figure 35 Charge Pump External Connections The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the output voltages (VPOS and VNEG) as well as the switching frequency in order to optimise the power consumption according to the operating conditions. This can take two forms, which are selected using the CP_DYN_PWR register bit. * * Register control (CP_DYN_PWR = 0) Dynamic control (CP_DYN_PWR = 1) Under Register control, the HPOUTL_VOL, HPOUTR_VOL, LINEOUTL_VOL and LINEOUTR_VOL register settings are used to control the charge pump mode of operation. Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of operation. This is the Wolfson `Class W' mode, which allows the power consumption to be optimised in real time, but can only be used if the DAC is the only signal source. This mode should not be used if the Bypass Paths are used to mix additional analogue inputs into the output signal path. Under the recommended usage conditions of the WM8903, the Charge Pump will be enabled by running the default Start-Up sequence as described in the "Control Write Sequencer" section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate. When using the digital sidetone, it is recommended that dynamic control of the charge pump is not enabled, i.e. CP_DYN_PWR should be cleared to 00. Dynamic control of the charge pump does not include the sidetone volume in its calculations, hence with a low DAC signal but high sidetone volume, the headphone amplifier could clip. CHARGE PUMP CLOCK The charge pump clock is derived from MCLK, i.e. an MCLK signal must be present for the charge pump to function. The clock division from MCLK is handled transparently by the WM8903 without user intervention, as long as MCLK and sample rates are set correctly (see "Clocking and Sample Rates" section). The Charge pump is driven from CLK_SYS plus a 4 kHz clock also generated from the CLK_SYS, and requires a minimum CLK_SYS of 2.8224 MHz. The charge pump internal clock is derived from CLK_SYS, using a clock divider to generate a nominal 1MHz clock. The clock divider ratio depends on the SAMPLE_RATE[3:0], CLK_SYS_MODE[1:0], and CLK_SYS_RATE[3:0] register settings. w PP, Rev 3.1, August 2009 72 WM8903 Pre-Production For example, with MCLKDIV2=0 256fs gives a charge pump clock division ratio of 12, hence * MCLK=12.288MHz gives a charge pump frequency of 1.024MHz at full output power. * MCLK=11.2896MHz gives a charge pump frequency of 940.8kHz at full output power. 128fs gives a charge pump clock division ratio of 6, hence * MCLK=6.144MHz gives a charge pump frequency of 1.024MHz at full output power. * MCLK=5.6448MHz gives a charge pump frequency of 940.8kHz at full output power CHARGE PUMP REGISTERS The Charge Pump control fields are described in Table 48. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R98 (62h) Charge Pump 0 0 CP_ENA 0 Enable charge-pump digits 0 = disable 1 = enable R104 (68h) Class W 0 0 CP_DYN_PWR 0 Enable dynamic charge pump power control 0 = charge pump controlled by volume register settings 1 = charge pump controlled by realtime audio level Table 48 Charge Pump Control DC SERVO The WM8903 provides a DC servo circuit on the headphone and line outputs in order to remove DC offset from these ground-referenced outputs. When enabled, the DC servo ensures that the DC level of these outputs remains within 1.5mV of ground. Removal of the DC offset is important because any deviation from GND at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption. Additionally, the presence of DC offsets can result in audible pops and clicks at power up and power down. The recommended usage of the DC Servo is initialised by running the default Start-Up sequence as described in the "Control Write Sequencer" section. The default Start-Up sequence selects START_STOP servo mode, which causes a one-off correction to be performed, after which the measured DC offset is then maintained on the headphone and line outputs. If a different usage is required, e.g. if one or more of the outputs is not in use, or if periodic DC offset correction is required, then the default Start-Up sequence may be modified according to specific requirements. The relevant control fields are defined in Table 49 . If DC offset correction is not required on any output, then DCS_MASTER_ENA should be set to 0. Setting this field to 0 before running the Start-Up sequence will disable the DC Servo on all outputs. If DC offset correction is only required on selected channels, then DCS_ENA should be set accordingly. Setting this field to 1111b enables the DC Servo on all outputs. Setting any bit to 0 disables the DC Servo on the corresponding output. Disabling the DC Servo on unused outputs reduces power consumption in the device. To modify this within the Start-Up sequence, the data in WSEQ Address 23 and WSEQ Address 24 should be updated (see "Control Write Sequencer") before running the sequence. w PP, Rev 3.1, August 2009 73 WM8903 Pre-Production If periodic updates to the DC offset correction is required, then DCS_MODE should be modified. Setting this field to 11b selects START_UPDATE servo mode, which causes the DC offset to be measured and corrected on a periodic basis. The default time between updates is approximately 10 minutes. Scheduling periodic updates enables the WM8903 to compensate for any change in DC offsets which might have occurred due to power supply drift or other factors. To modify this within the Start-Up sequence, the data in WSEQ Address 22 should be updated (see "Control Write Sequencer") before running the sequence. REGISTER ADDRESS R67 (43h) DC Servo 0 R69 (45h) DC Servo 2 BIT 4 LABEL DCS_MASTER_EN A 3:0 DCS_ENA[3:0] 1:0 DCS_MODE [1:0] DEFAULT 1 0000 00 DESCRIPTION DC Servo Master Control 0 = DC Servo Reset 1 = DC Servo Enabled DC Servo Enable [3] - HPOUTL enable [2] - HPOUTR enable [1] - LOUTL enable [0] - LOUTR enable DC Servo Mode 00 = WRITE_STOP 01 = WRITE_UPDATE 10 = START_STOP 11 = START_UPDATE Table 49 DC Servo Control To reduce power consumption when unused audio outputs are disabled, the DC Servo correction should also be disabled. The WM8903 provides the capability to quickly resume the necessary DC Servo correction when the outputs are re-enabled, without the time delay associated with the START_STOP mode of DC Servo operation. If the DC Servo correction is disabled using the DCS_ENA bits, but the DCS_MASTER_ENA bit is maintained at 1, then the DC Servo will retain the latest correction values in its memory. These values will be re-applied when the DC Servo is later enabled via the DCS_ENA bits. An alternative method to apply known correction settings is to read the correction values from the WM8903 register map and to store these for later use. After DC offset correction has been performed, the applicable correction values can be read from the fields in the Servo Readback registers R81 to R84 described in Table 50. Setting DCS_MODE to 00b or 01b selects WRITE_STOP mode and WRITE_UPDATE mode respectively. WRITE_STOP mode is similar to START_STOP mode, except that the DC Servo correction factors are read from internal registers, instead of being calculated from the measured output conditions. In the same way, WRITE_UPDATE mode is similar to START_UPDATE mode. When the DC Servo is commanded to one of these modes, the initial DC offset correction values are read from the _WRITE_VAL field in registers R71 to R74 described in Table 50. Selecting WRITE_STOP or WRITE_UPDATE mode applies initial settings which should be written to registers R71 to R74 before the DC Servo is enabled. In WRITE_STOP mode, no further DC correction is applied. In WRITE_UPDATE mode, the DC Servo will periodically measure and adjust the DC offset correction. Similar to START_UPDATE mode, the default time between updates is approximately 10 minutes. w PP, Rev 3.1, August 2009 74 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R71 (47h) DC Servo 4 7:0 DCS_HPOUTL_WRITE_VAL [7:0] 0000_0000 Value to send to Left Headphone Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV R72 (48h) DC Servo 5 7:0 DCS_HPOUTR_WRITE_VA L [7:0] 0000_0000 Value to send to Right Headphone Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV R73 (49h) DC Servo 6 7:0 DCS_LOUTL_WRITE_VAL [7:0] 0000_0000 Value to send to Left Line Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV R74 (4Ah) DC Servo 7 7:0 DCS_LOUTR_WRITE_VAL [7:0] 0000_0000 Value to send to Right Line Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV R81 (51h) DC Servo Readback 1 7:0 DCS_HPOUTL_INTEG [7:0] 0000_0000 Readback value on Left Headphone Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV R82 (52h) DC Servo Readback 2 7:0 DCS_HPOUTR_INTEG [7:0] 0000_0000 Readback value on Headphone Right Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV R83 (53h) DC Servo Readback 3 7:0 DCS_LOUTL_INTEG [7:0] 0000_0000 Readback value on Left Line Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV R84 (54h) DC Servo Readback 4 7:0 DCS_LOUTR_INTEG [7:0] 0000_0000 Readback value on Right Line Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV Table 50 DC Servo Initial Settings and Readback w PP, Rev 3.1, August 2009 75 WM8903 Pre-Production DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data into the WM8903 and outputting ADC data from it. It uses four pins: * * * ADCDAT: ADC data output DACDAT: DAC data input LRC: DAC and ADC data alignment clock * BCLK: Bit clock, for synchronisation Note that the BCLK pin can also support other functions, as described under "General Purpose Input/Output (GPIO)". BCLK is the default function on this pin (GP5_FN = 1h). Under default conditions, the other GPIO control fields for this pin have no effect. MASTER AND SLAVE MODE OPERATION The LRC and BCLK pins can be independently configured as either inputs or outputs, as shown in Table 51. REGISTER ADDRESS R25 (19h) Audio Interface 1 BIT LABEL DEFAULT DESCRIPTION 9 LRCLK_DIR 0 Audio Interface LRC Direction 0 = LRC is input 1 = LRC is output 6 BCLK_DIR 0 Audio Interface BCLK Direction 0 = BCLK is input 1 = BCLK is output Table 51 Audio Interface Pin Direction Control When both LRC and BCLK are configured as outputs, the WM8903 operates as a master device and controls the timing of data transfer on the ADCDAT and DACDAT pins (see Figure 36). When both LRC and BCLK are configured as inputs, the WM8903 operates as a slave device, and data timing is controlled by an external master (see Figure 37). Additionally, two "mixed" modes (BCLK as input, LRC as output and vice versa) can be selected. When BCLK is not selected (GP5_FN 1), the WM8903 uses the MCLK input as the Bit Clock, provided that BCLK_DIR is set to 0 to configure BCLK as an input, ie. BCLK slave mode. This configuration can offer power consumption benefits in addition to flexibility of GPIO functionality, Figure 36 Master Mode Figure 37 Slave Mode When the BCLK pin is an output (BCLK_DIR=1), BCLK is derived from the internal CLK_SYS signal (see "Clocking and Sample Rates"). In this case, the BCLK frequency is controlled in relation to CLK_SYS by the BCLK_DIV register field. When BCLK is an input, BCLK_DIV has no effect. When the LRC pin is an output (LRCLK_DIR=1), LRC is derived from BCLK (irrespective of whether BCLK is an input or output). In this case, the LRC frequency is controlled in relation to BCLK by the LRCLK_RATE register field. When LRC is an input, LRCLK_RATE has no effect. w PP, Rev 3.1, August 2009 76 WM8903 Pre-Production BCLK_DIV and LRCLK_RATE are defined in Table 52. The clocking scheme is illustrated in the "Clocking and Sample Rates" section - see Figure 54. REGISTER ADDRESS BIT LABEL DEFAULT R26 (1Ah) Audio Interface 2 4:0 BCLK_DIV [4:0] 0_1000 R27 (1Bh) Audio Interface 3 10:0 LRCLK_RATE [10:0] 000_0010 _0010 DESCRIPTION BCLK Frequency (Master Mode) 00000 = CLK_SYS 00001 = Reserved 00010 = CLK_SYS / 2 00011 = CLK_SYS / 3 00100 = CLK_SYS / 4 00101 = CLK_SYS / 5 00110 = Reserved 00111 = CLK_SYS / 6 01000 = CLK_SYS / 8 (default) 01001 = CLK_SYS / 10 01010 = Reserved 01011 = CLK_SYS / 12 01100 = CLK_SYS / 16 01101 = CLK_SYS / 20 01110 = CLK_SYS / 22 01111 = CLK_SYS / 24 10000 = Reserved 10001 = CLK_SYS / 30 10010 = CLK_SYS / 32 10011 = CLK_SYS / 44 10100 = CLK_SYS / 48 LRC Rate (Master Mode) LRC clock output = BCLK / LRCLK_RATE Integer (LSB = 1) Valid range: 8 to 2047 50:50 LRCLK duty cycle is only guaranteed with even values (8, 10, ... ... , 2047). Table 52 Digital Audio Interface Clock Output Control AUDIO DATA FORMATS Four basic audio data formats are supported: * Left justified * * * Right justified I 2S DSP mode All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. Time Division Multiplexing (TDM) is available in all four data format modes. The WM8903 can be programmed to send and receive data in one of two time slots. PCM operation is supported using the DSP mode. w PP, Rev 3.1, August 2009 77 WM8903 Pre-Production The register bits controlling audio data format and word length are summarised in Table 53. REGISTER ADDRESS R25 (19h) Audio Interface 1 BIT LABEL DEFAULT DESCRIPTION 7 AIF_BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 4 AIF_LRCLK_INV 0 LRC Polarity / DSP Mode A-B select. Right, left and I2S modes - LRC polarity 0 = Not Inverted 1 = Inverted DSP Mode - Mode A-B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 3:2 AIF_WL [1:0] 00 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 AIF_FMT [1:0] 10 Digital Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP Table 53 Audio Data Format Control In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. Figure 38 Left Justified Audio Interface (assuming n-bit word length) w PP, Rev 3.1, August 2009 78 WM8903 Pre-Production In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. Figure 39 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 40 I2S Justified Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selected by AIF_LRCLK_INV) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output resembles the frame pulse shown in Figure 41 and Figure 42. In device slave mode, Figure 43 and Figure 44, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. w PP, Rev 3.1, August 2009 79 WM8903 Pre-Production Figure 41 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master) Figure 42 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master) Figure 43 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) w PP, Rev 3.1, August 2009 80 WM8903 Pre-Production Figure 44 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=0, Slave) TIME DIVISION MULTIPLEXING (TDM) TDM allows more than two devices to share a single digital audio bus, as shown below. BCLK WM8903 LRC Processor ADCDAT DACDAT BCLK Third audio device LRC ADCDAT DACDAT Figure 45 TDM with WM8903 as Master w PP, Rev 3.1, August 2009 81 WM8903 Pre-Production BCLK WM8903 LRC Processor ADCDAT DACDAT BCLK Third audio device LRC ADCDAT DACDAT Figure 46 TDM with Third Audio Device as Master The WM8903 supports TDM in master and slave modes, for both incoming and outgoing audio data, in all data formats and word lengths. When TDM is enabled, two time slots (Slot 0 and Slot 1) are available on the ADCDAT and/or DACDAT pins. The control bits for TDM are shown in Table 54. REGISTER ADDRESS R25 (19h) Audio Interface 1 BIT LABEL DEFAULT DESCRIPTION 13 AIFDAC_TDM 0 DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT 12 AIFDAC_TDM_ CHAN 0 DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 11 AIFADC_TDM 0 ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT 10 AIFADC_TDM_ CHAN 0 ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 Table 54 TDM Control When TDM is enabled, the ADCDAT pin is tri-stated immediately before and immediately after data transmission, to allow another audio device to drive this signal line for the remainder of the sample period. It is important that two devices do not attempt to drive the data pin simultaneously, as this could result in a short circuit (see "Signal Timing Requirements" for details of the ADCDAT output relative to BCLK signal). The transmission times of two devices can be prevented from overlapping by providing additional, unused BCLK cycles. For example, the audio interface could run at 32 BCLK cycles per data sample even though the WM8903 word length is only 24-bit. This creates an 8-bit gap between transmissions. When using such a scheme, it is recommended to add pull-down resistors to the DACDAT and ADCDAT lines, as shown in Figure 45, and Figure 46. Note: The WM8903 is a 24-bit device. In 32-bit mode (AIF_WL=11), the 8 LSBs are ignored on the receiving side and not driven on the transmitting side. w PP, Rev 3.1, August 2009 82 WM8903 Pre-Production When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as shown in Figure 47 to Figure 51. Figure 47 TDM in Right-Justified Mode Figure 48 TDM in Left-Justified Mode Figure 49 TDM in I2S Mode w PP, Rev 3.1, August 2009 83 WM8903 Pre-Production Figure 50 TDM in DSP Mode A 1/fs 1 BCLK LRC BCLK ADCDAT / DACDAT SLOT0 L SLOT0 R SLOT1 L SLOT1 R Figure 51 TDM in DSP Mode B COMPANDING The WM8903 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 55. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low-amplitude signals than for high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. REGISTER ADDRESS R24 (18h) Audio Interface 0 BIT LABEL DEFAULT DESCRIPTION 3 ADC_COMP 0 ADC Companding Enable 0 = disabled 1 = enabled 2 ADC_COMPMO DE 0 ADC Companding Type 0 = -law 1 = A-law 1 DAC_COMP 0 DAC Companding Enable 0 = disabled 1 = enabled 0 DAC_COMPMO DE 0 DAC Companding Type 0 = -law 1 = A-law Table 55 Companding Control w PP, Rev 3.1, August 2009 84 WM8903 Pre-Production Companding uses a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) } for -1 x 1 A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) } for x 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) } for 1/A x 1 u-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input Figure 52 -Law Companding A-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.2 0.4 0.6 0.8 1 Normalised Input Figure 53 A-Law Companding w PP, Rev 3.1, August 2009 85 WM8903 Pre-Production The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). Companded data is transmitted in the first 8 MSBs of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4 bits), as shown in Table 56. BIT7 BIT[6:4] BIT[3:0] SIGN EXPONENT MANTISSA Table 56 8-bit Companded Word Composition 8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles per LRC frame. When using DSP mode B, 8bit data words may be transferred consecutively every 8 BCLK cycles. 8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 or ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0. LOOPBACK A loopback function is provided for test and evaluation purposes. When the LOOPBACK register bit is set, the output data from the ADC is fed directly into the DAC input. REGISTER ADDRESS R24 (18h) Audio Interface 0 BIT 8 LABEL LOOPBACK DEFAULT DESCRIPTION 0 Digital Loopback Function 0 = No loopback 1 = Loopback enabled (ADC data output is directly input to DAC data input) Table 57 Loopback Control Note: When the digital sidetone is enabled, ADC data will continue to be added to DAC data when loopback is enabled. w PP, Rev 3.1, August 2009 86 WM8903 Pre-Production CLOCKING AND SAMPLE RATES The WM8903 supports a wide range of standard audio sample rates from 8kHz to 96kHz. When the DAC and ADC are both enabled, they operate at the same sample rate, fs. Note that the 88.2kHz and 96kHz sample rate settings are not valid for Digital Microphone operation, or ADC in USB mode. CLOCKING ARCHITECTURE All internal clocks are derived from MCLK, as shown in Figure 54. Note that BCLK and LRC are described in the "Digital Audio Interface" section. Figure 54 WM8903 Clocking Overview The system clock is enabled using the CLK_SYS_ENA register bit, which should be enabled for normal operation with MCLK applied. The DSP clocking is enabled by CLK_DSP_ENA. For normal operation, CLK_DSP_ENA must be set. Note that the default Start-Up sequence (see "Control Write Sequencer") causes the CLK_DSP_ENA bit to be set. The Zero-Cross feature associated with the Output PGA volume updates includes a timeout option to ensure the volume update occurs even if a zero cross is not detected. To enable this timeout, the TO_ENA bit must be set. The internal clock CLK_SYS is derived from MCLK as controlled by MCLKDIV2 (see Table 61). The SAMPLE_RATE field should be set according to the desired Sample Rate (fs). Given the ratio of CLK_SYS to fs, the control fields CLK_SYS_RATE and CLK_SYS_MODE should be set in accordance with Table 62. When these fields are set correctly, the Sample Rate Decoder circuit automatically determines the clocking configuration for all other circuits within the WM8903. w PP, Rev 3.1, August 2009 87 WM8903 Pre-Production CONTROL INTERFACE CLOCKING In certain configurations, such as analog bypass to differential line outputs, WM8903 can be used without MCLK (compared to LINEOUTL/R, which requires the charge pump hence requires MCLK). Without MCLK applied, CLK_SYS_ENA should be left in its default state otherwise there is limited access to the register map as detailed in Table 58. MCLK PRESENT CLK_SYS_ENA REGISTER ACCESS R22 (TO ADJUST CLK_SYS_ENA) ALL OTHER REGISTERS Yes Don't care Yes Yes No 0 (default) Yes Yes No 1 Yes No Table 58 Serial Interface Access with CLK_SYS_ENA and MCLK DAC SETUP For correct DAC functionality with sample rates up to 48kHz, one of the following CLK_SYS limits must be observed, depending on the setting of the DAC_MONO and DAC_OSR register bits. See "Digital to Analogue Converter (DAC)" for definitions of DAC_MONO and DAC_OSR. CONDITIONS CLK_SYS DAC_MONO = 0 DAC_OSR = 0 CLK_SYS 128 x fs DAC_MONO = 0 DAC_OSR = 1 CLK_SYS 256 x fs DAC_MONO = 1 DAC_OSR = 0 CLK_SYS 64 x fs DAC_MONO = 1 DAC_OSR = 1 CLK_SYS 128 x fs Table 59 Minimum CLK_SYS for DAC Operation For correct DAC functionality with 88.2kHz or 96kHz sample rates, and if the ADC is not configured, 125 x fs or 128 x fs must be selected, or in the case of 88.2kHz, 136 x fs can also be selected. The correct setting of SAMPLE_RATE should be selected (i.e. 1001 or 1010). The CLK_SYS frequency should not exceed the limitations stated in the "Signal Timing Requirements" section. For best DAC noise performance, CLK_SYS 3MHz. (Note that there is no equivalent condition for ADC noise performance.) ADC SETUP For correct ADC functionality with sample rates up to 48kHz, it must be ensured that CLK_SYS 256 x fs. At 48kHz, if ADC_OSR = 0, it must be ensured that CLK_SYS 128 x fs. For correct ADC functionality with 88.2kHz or 96kHz sample rates, CLK_SYS must equal 128 x fs, and the SAMPLE_RATE register should be set for half the required sample rate. For example, shows the settings required for 96kHz ADC sample rate. CONDITION REGISTER BITS SETTING CLK_SYS = 128 x fs CLK_SYS_RATE 0001 CLK_SYS_MODE 00 Sample rate setting for 48kHz SAMPLE_RATE 1000 BCLK = CLK_SYS / 2 BCLK_DIV 0_0010 LRCLK = BCLK / 64 LRCLK_RATE 000_0100_0000 Table 60 Clock Settings for ADC at 96kHz Sample Rate Configuring the ADC for 88.2kHz requires the same settings as detailed in Table 60, except that SAMPLE_RATE should be set to 44.1kHz (0111). The CLK_SYS frequency should not exceed the limitations stated in the "Signal Timing Requirements" section. Simultaneous ADC and DAC operation at 88.2kHz or 96kHz sample rates is not possible, but ADC and DAC can both be set up to the required sample rates, then selected alternately using the DACL_ENA, DACR_ENA, ADCL_ENA, ADCR_ENA. w PP, Rev 3.1, August 2009 88 WM8903 Pre-Production CLOCKING REGISTERS The WM8903 clocking is configured using the register bits defined in Table 61. REGISTER ADDRESS BIT LABEL R20 (14h) Clock Rates 0 0 R21 (15h) Clock Rates 1 13:10 CLK_SYS_RAT E [3:0] 0011 9:8 CLK_SYS_MOD E [1:0] 00 3:0 SAMPLE_RATE [3:0] 1000 MCLKDIV2 DEFAULT 0 DESCRIPTION Enables divide by 2 on MCLK 0 = CLK_SYS = MCLK 1 = CLK_SYS = MCLK / 2 CLK_SYS_RATE and CLK_SYS_MODE together determine the clock division ratio (CLK_SYS / fs); see Table 62 Selects the Sample Rate (fs) 0000 = 8kHz 0001 = 11.025kHz 0010 = 12kHz 0011 = 16kHz 0100 = 22.05kHz 0101 = 24kHz 0110 = 32kHz 0111 = 44.1kHz 1000 = 48kHz 1001 = 88.2kHz (Not available for Digital Microphone. Not used for 88.2kHz ADC.) 1010 = 96kHz (Not available for Digital Microphone. Not used for 96kHz ADC) 1011 to 1111 = Reserved If the desired sample rate is not listed in this table, then the closest alternative should be chosen. R22 (16h) Clock Rates 2 2 CLK_SYS_ENA 0 System Clock enable 0 = Disabled 1 = Enabled 1 CLK_DSP_ENA 0 DSP Clock enable 0 = Disabled 1 = Enabled 0 TO_ENA 0 Zero Cross timeout enable 0 = Disabled 1 = Enabled Table 61 Clocking Control w PP, Rev 3.1, August 2009 89 WM8903 CLK_SYS_RATE Pre-Production Available CLK_SYS / fs ratios CLK_SYS_MODE 00 01 10 or 11 0000 64 68 125 0001 128 136 125 0010 192 204 250 0011 256 272 250 0100 384 408 375 0101 512 544 500 0110 768 816 750 0111 1024 1088 1000 1000 1408 1496 1000 1001 1536 1632 1500 1010 to 1111 Reserved Table 62 Sample Rate Decoder Control The clock division ratios available with CLK_SYS_MODE = 00 are suitable for use with standard audio master clocks. For example, with a 12.288MHz CLK_SYS and 48kHz sample rate, the CLK_SYS to fs ratio is 256. In this case, the required setting for CLK_SYS_RATE is 0011, as shown above. USB MODE Other settings of CLK_SYS_MODE allow compatibility with a USB clock, at sample rates of up to 48kHz. For example, with a 12MHz (USB) clock and an 8kHz sample rate, the CLK_SYS to fs ratio is 1500. In this case, the required setting for CLK_SYS_RATE is 1001. Note that 44.1kHz and related sample rates are approximate when derived from a USB clock. For example, with a 12MHz MCLK and a division ratio of 272, the exact sample rate obtained is 44.118Hz rather than 44.1kHz. This 0.04% offset is inaudible and can be ignored. 48kHz and related sample rates are exact in all modes of operation, provided that MCLK itself is exact. DIGITAL MICROPHONE When GPIO1/DMIC_LR is configured as DMIC_LR Clock output, the WM8903 outputs a clock which supports Digital Microphone operation at a multiple of the ADC sampling rate. The precise clock frequency varies according to the MCLK frequency, the SAMPLE_RATE field and other settings. The clock frequency is always within the range 1MHz - 3MHz, and some examples are shown in Table 63. SAMPLE RATE CLK_SYS CLK_SYS RATIO DMIC_LR FREQUENCY DMIC_LR RATIO 8kHz 12.288MHz 1536fs 1.024MHz 128fs 8kHz 12MHz 1500fs 1.200MHz 150fs 16kHz 12.288MHz 768fs 2.048MHz 128fs 16kHz 12MHz 750fs 2.400MHz 150fs 48kHz 12.288MHz 256fs 1.536MHz 32fs 48kHz 12MHz 250fs 2.400MHz 50fs 44.1kHz 11.2896MHz 256fs 2.822MHz 64fs 44.1kHz 12MHz 272fs 3.000MHz 68fs 32kHz 12MHz 375fs 2.400MHz 75fs 24kHz 12MHz 500fs 2.400MHz 100fs 12kHz 12MHz 1000fs 1.500MHz 125fs Table 63 Digital Microphone Clock Note that the 88.2kHz and 96kHz sample rate settings are not valid for Digital Microphone operation. w PP, Rev 3.1, August 2009 90 WM8903 Pre-Production GENERAL PURPOSE INPUT/OUTPUT (GPIO) The WM8903 provides five multi-function pins which can be configured to provide a number of different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins are: * GPIO1/DMIC_LR * * * GPIO2/DMIC_DAT GPIO3/ADDR INTERRUPT (GPIO4) * BCLK (GPIO5) Table 64 lists the functions are available on each of these pins. The default function is highlighted for each pin. GPIO PINS GPIO Pin Function GPIO1/D GPIO2/D MIC_LR MIC_DAT GPIO3/ ADDR INTERRUPT (GPIO4) BCLK (GPIO5) GPIO output Yes Yes Yes Yes Yes BCLK input/output No No No No Yes Interrupt output Yes Yes Yes Yes Yes Digital Microphone Clock (DMIC_LR) Yes No No No No Digital Microphone Data (DMIC_DAT) No Yes No No No GPIO input Yes Yes Yes Yes Yes MICBIAS Current detect output Yes Yes Yes Yes Yes MICBIAS Short Circuit detect output Yes Yes Yes Yes Yes Table 64 GPIO Functions Available The register fields that control the functionality of these pins are described in Table 65. For each pin, the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1 to 5). Note that the INTERRUPT pin is also referred to as GPIO4; the BCLK pin is also referred to as GPIO5. The pin direction, set by GPn_DIR, must be set according to function selected by GPn_FN. The characteristics of any pin selected as an output may be controlled by setting GPn_OP_CFG - an output pin may be either CMOS or Open-Drain. When a pin is configured as a GPIO output, its level can be set to logic 0 or logic 1 using the GPn_LVL field. A pin configured as a GPIO input can be used to trigger an Interrupt event. This input may be configured as active high or active low using the GPn_IP_CFG field. De-bouncing of this input may be enabled using the GPn_DB field. Internal pull-up and pull-down resistors may be enabled using the GPn_PU and GPn_PD fields. (Note that if GPn_PU and GPn_PD are both set for any GPIO pin, then the pull-up and pull-down will be disabled.) Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt event. The register field GPn_INTMODE selects edge detect or level detect Interrupt functionality. Edge detect raises an interrupt on rising and falling transitions. Level detect asserts the interrupt for as long as the GPIO status is asserted. See "Interrupts". The Digital Microphone Interface and MICBIAS Current Detect functions are described in the "Analogue Input Signal Path" section. Interrupt Output is the default function of GPIO4. See "Interrupts" for further details. w PP, Rev 3.1, August 2009 91 WM8903 Pre-Production BCLK is the default function of GPIO5. This may be input or output. Note that, when BCLK is enabled on this pin (GP5_FN = 1h), the other GPIO control fields for this pin have no effect. When BCLK is not enabled on this pin (GP5_FN 1h), the WM8903 uses the MCLK input as the Bit Clock. See "Digital Audio Interface" for further details. REGISTER ADDRESS BIT R116 (74h) GPIO Control 1 13:8 R117 (75h) GPIO Control 2 GP1_FN[5:0] DEFAULT 00_0000 DESCRIPTION GPIO 1 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h = DMIC_LR Clock output 07h to 3Fh = Reserved 7 GP1_DIR 1 GPIO Pin Direction 0 = Output 1 = Input 6 GP1_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP1_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP1_LVL 0 GPIO Output Level (when GP1_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP1_PD 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP1_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP1_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP1_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced 13:8 7 w LABEL GP2_FN[5:0] GP2_DIR 00_0000 1 GPIO 2 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h = DMIC_DAT Data input 07h to 3Fh = Reserved GPIO Pin Direction 0 = Output 1 = Input PP, Rev 3.1, August 2009 92 WM8903 Pre-Production REGISTER ADDRESS R118 (76h) GPIO Control 3 w BIT LABEL DEFAULT DESCRIPTION 6 GP2_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP2_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP2_LVL 0 GPIO Output Level (when GP2_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP2_PD 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP2_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP2_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP2_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced 13:8 GP3_FN[5:0] 00_0000 GPIO 3 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 07h = DMIC_LR Clock output 06h to 3Fh = Reserved 7 GP3_DIR 1 GPIO Pin Direction 0 = Output 1 = Input 6 GP3_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP3_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP3_LVL 0 GPIO Output Level (when GP3_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP3_PD 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP3_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP3_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered PP, Rev 3.1, August 2009 93 WM8903 Pre-Production REGISTER ADDRESS BIT 0 R119 (77h) GPIO Control 4 R120 (78h) GPIO Control 5 w 13:8 LABEL GP3_DB GP4_FN[5:0] DEFAULT 0 00_0010 DESCRIPTION GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced GPIO 4 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h to 3Fh = Reserved 7 GP4_DIR 0 GPIO Pin Direction 0 = Output 1 = Input 6 GP4_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP4_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP4_LVL 0 GPIO Output Level (when GP4_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP4_PD 0 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP4_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP4_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP4_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced GPIO 5 Pin Function select 00h = GPIO output 01h = BCLK 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h to 3Fh = Reserved 13:8 GP5_FN[5:0] 00_0001 7 GP5_DIR 1 GPIO Pin Direction 0 = Output 1 = Input 6 GP5_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP5_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high PP, Rev 3.1, August 2009 94 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 4 GP5_LVL 0 GPIO Output Level (when GP5_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP5_PD 0 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP5_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP5_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP5_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced Table 65 GPIO Control w PP, Rev 3.1, August 2009 95 WM8903 Pre-Production INTERRUPTS The Interrupt Controller has multiple inputs. These include the GPIO input pins and the MICBIAS current detection circuits. Any combination of these inputs can be used to trigger an Interrupt (IRQ) event. There is an Interrupt Status field associated with each of the IRQ inputs. These are listed within the Interrupt Status Register (R121), as described in Table 66. The status of the IRW inputs can be read at any time from this register or else in response to the Interrupt Output being signalled via a GPIO pin. The Interrupt Output represents the logical `OR' of all the unmasked IRQ inputs. The bits within the Interrupt Status register (R121) are latching fields and, once they are set, they are not reset until the Status Register is read. Accordingly, the Interrupt Output is not reset until each of the unmasked IRQ inputs has been read. Note that, if the condition that caused the IRQ input to be asserted is still valid, then the Interrupt Output will remain set even after the Status register has been read. When GPIO input is used as Interrupt event, polarity can be set using GP_IP_CFG as described in Table 65. The polarity of the MICBIAS detection functions can be set using MICDET_INV and MICSHRT_INV as described in Table 66. This allows the IRQ event to be used to indicate the removal of a microphone accessory in addition to insertion detection. By default, the Interrupt Output is Active High. The polarity can be inverted using IRQ_POL. The Interrupt Output may be configured on the INTERRUPT/GPIO4 pin or on the GPIO1/DMIC_LR, GPIO2/DMIC_DAT, GPIO3/ADDR or BCLK/GPIO5 pins. Interrupt Output is the default function on the INTERRUPT pin (GP4_FN = 2h), but the INTERRUPT pin can also be used to support other functions. See "General Purpose Input/Output (GPIO)" for details of how to configure GPIO pins for Interrupt (IRQ) output. The WM8903 Interrupt Controller circuit is illustrated in Figure 54. The associated control fields are described in Table 66. GPIO_IRQ[1] IM_GP1_EINT GPIO_IRQ[2] GPIO_IRQ[3] GPIO_IRQ[4] Latches GPIO_IRQ[5] Reset on status register read IRQ_POL INTERRUPT WSEQ_BUSY MIC_DETECT MICDET_INV MIC_SHORT MICSHRT_INV IM_MICSHRT_EINT Status Registers Read-only; cleared on read Figure 55 Interrupt Controller w PP, Rev 3.1, August 2009 96 WM8903 Pre-Production REGISTER ADDRESS R121 (79h) Interrupt Status 1 R122 (7Ah) Interrupt Status 1 Mask w BIT LABEL DEFAULT DESCRIPTION 15 MICSHRT_EINT 0 14 MICDET_EINT 0 13 WSEQ_BUSY_E INT 0 4 GP5_EINT 0 3 GP4_EINT 0 2 GP3_EINT 0 1 GP2_EINT 0 0 GP1_EINT 0 15 IM_MICSHRT_E INT 1 14 IM_MICDET_EI NT 1 13 IM_WSEQ_BUS Y_EINT 1 4 IM_GP5_EINT 1 3 IM_GP4_EINT 1 2 IM_GP3_EINT 1 1 IM_GP2_EINT 1 MICBIAS Short Circuit detect IRQ status 0 = Short Circuit current IRQ not set 1 = Short Circuit current IRQ set MICBIAS Current detect IRQ status 0 = Current detect IRQ not set 1 = Current detect IRQ set Write Sequencer Busy IRQ status 0 = WSEQ IRQ not set 1 = WSEQ IRQ set The Write Sequencer asserts this flag when it has completed a programmed sequence - ie it indicates that the Write Sequencer is NOT Busy. GPIO5 IRQ status 0 = GPIO5 IRQ not set 1 = GPIO5 IRQ set GPIO4 IRQ status 0 = GPIO4 IRQ not set 1 = GPIO4 IRQ set GPIO3/ADDR IRQ status 0 = GPIO3 IRQ not set 1 = GPIO3 IRQ set GPIO2/DMIC_DAT IRQ status 0 = GPIO2 IRQ not set 1 = GPIO2 IRQ set GPIO1/DMIC_LR IRQ status 0 = GPIO1 IRQ not set 1 = GPIO1 IRQ set Interrupt mask for MICBIAS Short Circuit detect 0 = Not masked 1 = Masked Interrupt mask for MICBIAS Current detect 0 = Not masked 1 = Masked Interrupt mask for WSEQ Busy indication 0 = Not masked 1 = Masked Interrupt mask for GPIO5 0 = Not masked 1 = Masked Interrupt mask for GPIO4 0 = Not masked 1 = Masked Interrupt mask for GPIO3/ADDR 0 = Not masked 1 = Masked Interrupt mask for GPIO2/DMIC_DAT 0 = Not masked 1 = Masked PP, Rev 3.1, August 2009 97 WM8903 Pre-Production REGISTER ADDRESS R123 (7Bh) Interrupt Polarity 1 R126 (7Eh) Interrupt Control BIT LABEL DEFAULT DESCRIPTION Interrupt mask for GPIO1/DMIC_LR 0 = Not masked 1 = Masked MICBIAS Short Circuit detect polarity 0 = Detect current increase above threshold 1 = Detect current decrease below threshold MICBIAS Current Detect polarity 0 = Detect current increase above threshold 1 = Detect current decrease below threshold Interrupt Output polarity 0 = Active high 1 = Active low 0 IM_GP1_EINT 1 15 MICSHRT_INV 0 14 MICDET_INV 0 0 IRQ_POL 0 Table 66 Interrupt Control CONTROL INTERFACE The WM8903 is controlled by writing to registers through a 2-wire serial control interface. A control word consists of 24 bits, transmitted as 3 bytes. The first byte (bits B23 to B16) is a register address that select which control register is accessed. The remaining two bytes (bits B15 to B0) are data, corresponding to the 16 bits in each control register. In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 7-bit device ID (this is not the same as the 8-bit address of each register in the WM8903). The default device ID for the WM8903 is 0011010 (0x34h). Alternatively, the device ID can be set to 0011011 (0x36) by pulling the GPIO3/ADDR pin high during device start-up, when the internal poweron reset signal PORB (see "Power-on Reset") is released. The setup and hold times for device ID selection are shown in Table 67. After the device ID has been selected, the GPIO3/ADDR pin can be used as a GPIO. SYMBOL MIN Tpusetup 100 TYP MAX UNIT s Tpuhold 100 s Table 67 GPIO3/ADDR Latch on Power-up Timing The WM8903 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device ID, register address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit device ID + Read/Write bit, MSB first). If the device ID received matches the device ID of the WM8903, then the WM8903 responds by pulling SDIN low on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is `1' when operating in write only mode, the WM8903 returns to the idle condition and waits for a new start condition and valid address. Register map access is possible with or without a Master Clock (MCLK). However, if CLK_SYS_ENA has been set to 1, then a Master Clock must be present for control register Read/Write operations. If CLK_SYS_ENA = 1 and MCLK is not present, then register access will be unsuccessful. If it cannot be assured that MCLK is present when accessing the register map, then CLK_SYS_ENA should be cleared to 0 to ensure correct operation. The register containing CLK_SYS_ENA (R22) can be accessed even if CLK_SYS_ENA = 1 and MCLK is not present. See also the Control Interface Clocking "section. w PP, Rev 3.1, August 2009 98 WM8903 Pre-Production The WM8903 supports the following read and write operations: * * Single write Single read * * Multiple write using auto-increment Multiple read using auto-increment The data format for these operations is shown below Terminology used in the following figures: TERMINOLOGY DESCRIPTION S Start Condition Sr Repeated start A Acknowledge P Stop Condition RW ReadNotWrite 0 = Write 1 = Read [White field] Data flow from bus master to WM8903 [Grey field] Data flow from WM8903 to bus master Table 68 Control Interface Terminology Figure 56 Single Write Figure 57 Single Read Figure 58 Multiple Write using Auto-increment Figure 59 Multiple Read Using Auto-increment w PP, Rev 3.1, August 2009 99 WM8903 Pre-Production CONTROL WRITE SEQUENCER The Control Write Sequencer is a programmable unit that forms part of the WM8903 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently. Default sequences for Start-Up and Shut-Down are provided (see "Default Sequences" section). It is recommended that these default sequences are used unless changes become necessary. When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The host processor informs the sequencer of the start index of the required sequence within the sequencer's memory. At each step of the sequence, the contents of the selected register fields are read from the sequencer's memory and copied into the WM8903 control registers. This continues sequentially through the sequencer's memory until an "End of Sequence" bit is encountered; at this point, the sequencer stops and an Interrupt status flag is asserted. For cases where the timing of the write sequence is important, a programmable delay can be set for specific steps within the sequence. Note that the Control Write Sequencer's internal clock is derived from the internal clock CLK_SYS. An external MCLK signal must be present for it to function, and the CLK_SYS must be enabled by setting CLK_SYS_ENA (see "Clocking and Sample Rates"). The clock division from MCLK is handled transparently by the WM8903 without user intervention, as long as MCLK and sample rates are set correctly. INITIATING A SEQUENCE The Register fields associated with running the Control Write Sequencer are described in Table 69. The Write Sequencer Clock is enabled by setting the WSMD_CLK_ENA bit. Note that the operation of the Control Write Sequencer also requires the internal clock CLK_SYS to be enabled via the CLK_SYS_ENA (see "Clocking and Sample Rates"). The start index of the required sequence must be written to the WSEQ_START_INDEX field. Setting the WSEQ_START bit initiates the sequencer at the given start index. The Write Sequencer can be interrupted by writing a logic 1 to the WSEQ_ABORT bit. The current status of the Write Sequencer can be read using two further register fields - when the WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. Note that, whilst the Control Write Sequencer is running a sequence (indicated by the WSEQ_BUSY bit), normal read/write operations to the Control Registers cannot be supported. (The Write Sequencer registers and the Software Reset register can still be accessed when the Sequencer is busy.) The index of the current step in the Write Sequencer can be read from the WSEQ_CURRENT_INDEX field; this is an indicator of the sequencer's progress. On completion of a sequence, this field holds the index of the last step within the last commanded sequence. When the Write Sequencer reaches the end of a sequence, it asserts the WSEQ_BUSY_EINT flag in Register R121 (see Table 66 within the "Interrupts" section). This flag can be used to generate an Interrupt Event on completion of the sequence. Note that the WSEQ_BUSY_EINT flag is asserted to indicate that the WSEQ is NOT Busy. w PP, Rev 3.1, August 2009 100 WM8903 Pre-Production REGISTER ADDRESS BIT R108 (6Ch) Write Sequencer 0 8 R111 (6Fh) Write Sequencer 3 9 R112 (70h) Write Sequencer 4 LABEL DEFAULT DESCRIPTION 0 Write Sequencer / Mic Detect Clock Enable. 0 = Disabled 1 = Enabled Previously called WSEQ_ENA. WSEQ_ABORT 0 Writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface. 8 WSEQ_START 0 Writing a 1 to this bit starts the write sequencer at the memory location indicated by the WSEQ_START_INDEX field. The sequence continues until it reaches an "End of sequence" flag. At the end of the sequence, this bit will be reset by the Write Sequencer. 5:0 WSEQ_START_ INDEX [5:0] 00_0000 Sequence Start Index. This is the memory location of the first command in the selected sequence. 0 to 31 = RAM addresses 32 to 48 = ROM addresses 49 to 63 = Reserved 9:4 WSEQ_CURRE NT_INDEX [5:0] 00_0000 Sequence Current Index. This is the location of the most recently accessed command in the write sequencer memory. WSMD_CLK_E NA 0 WSEQ_BUSY 0 Sequencer Busy flag (Read Only). 0 = Sequencer idle 1 = Sequencer busy Note: it is not possible to write to control registers via the control interface while the Sequencer is Busy. Table 69 Write Sequencer Control - Initiating a Sequence PROGRAMMING A SEQUENCE A sequence consists of write operations to data bits (or groups of bits) within the control registers. The Register fields associated with programming the Control Write Sequencer are described in Table 70. For each step of the sequence being programmed, the Sequencer Index must be written to the WSEQ_WRITE_INDEX field. The values 0 to 31 correspond to all the available RAM addresses within the Write Sequencer memory. (Note that memory addresses 32 to 48 also exist, but these are ROM addresses, which are not programmable.) Having set the Index as described above, Register R109 must be written to (containing the Control Register Address, the Start Bit Position and the Field Width applicable to this step of the sequence). Also, Register R110 must be written to (containing the Register Data, the End of Sequence flag and the Delay time required after this step is executed). After writing to these two registers, the next step in the sequence may be programmed by updating WSEQ_WRITE_INDEX and repeating the procedure. WSEQ_ADDR is an 8-bit field containing the Control Register Address in which the data should be written. w PP, Rev 3.1, August 2009 101 WM8903 Pre-Production WSEQ_DATA_START is a 4-bit field which identifies the LSB position within the selected Control Register to which the data should be written. Setting WSEQ_DATA_START = 0100 will cause 1-bit data to be written to bit 4. With this setting, 4-bit data would be written to bits 7:4 and so on. WSEQ_DATA_WIDTH is a 3-bit field which identifies the width of the data block to be written. This enables selected portions of a Control Register to be updated without any concern for other bits within the same register, eliminating the need for read-modify-write procedures. Values of 0 to 7 correspond to data widths of 1 to 8 respectively. For example, setting WSEQ_DATA_WIDTH = 010 will cause a 3-bit data block to be written. Note that the maximum value of this field corresponds to an 8-bit data block; writing to register fields greater than 8 bits wide must be performed using two separate operations of the Control Write Sequencer. WSEQ_DATA is an 8-bit field which contains the data to be written to the selected Control Register. The WSEQ_DATA_WIDTH field determines how many of these bits are written to the selected register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTH) are ignored. WSEQ_DELAY is a 4-bit field which controls the waiting time between the current step and the next step in the sequence. The total delay time per step (including execution) is given by: T = k x (2 WSEQ_DELAY + 8) where k = 62.5s (under recommended operating conditions) This gives a useful range of execution/delay times from 562s up to 2.048s per step. WSEQ_EOS is a 1-bit field which indicates the End of Sequence. If this bit is set, then the Control Write Sequencer will automatically stop after this step has been executed. w PP, Rev 3.1, August 2009 102 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT R108 (6Ch) Write Sequencer 0 4:0 WSEQ_WRIT E_INDEX [4:0] 0_0000 R109 (6Dh) Write Sequencer 1 14:12 WSEQ_DATA _WIDTH [2:0] 000 Width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 11:8 WSEQ_DATA _START [3:0] 0000 Bit position of the LSB of the data block written in this sequence step. 0000 = Bit 0 ... 1111 = Bit 15 7:0 WSEQ_ADDR [7:0] 0000_0000 Control Register Address to be written to in this sequence step. 14 WSEQ_EOS 0 End of Sequence flag. This bit indicates whether the Control Write Sequencer should stop after executing this step. 0 = Not end of sequence 1 = End of sequence (Stop the sequencer after this step). 11:8 WSEQ_DELA Y [3:0] 0000 Time delay after executing this step. Total time per step (including execution) = 62.5s x (2WSEQ_DELAY + 8) 7:0 WSEQ_DATA [7:0] 0000_0000 Data to be written in this sequence step. When the data width is less than 8 bits, then one or more of the MSBs of WSEQ_DATA are ignored. It is recommended that unused bits be set to 0. R110 (6Eh) Write Sequencer 2 DESCRIPTION Sequence Write Index. This is the memory location to which any updates to R109 and R110 will be copied. 0 to 31 = RAM addresses Table 70 Write Sequencer Control - Programming a Sequence In summary, the Control Register to be written is set by the WSEQ_ADDR field. The data bits that are written are determined by a combination of WSEQ_DATA_START, WSEQ_DATA_WIDTH and WSEQ_DATA. This is illustrated below for an example case of writing to the ADCL_DAC_SVOL field within Register 32. In this example, the Start Position is bit 08 (WSEQ_DATA_START = 1000b) and the Data width is 4 bits (WSEQ_DATA_WIDTH = 0011b). With these settings, the Control Write Sequencer would updated the Control Register R32 [11:08] with the contents of WSEQ_DATA [3:0]. w PP, Rev 3.1, August 2009 103 WM8903 Pre-Production Figure 60 Control Write Sequencer Example DEFAULT SEQUENCES When the WM8903 is powered up, two Control Write Sequences are available through ROM/default settings. The purpose of these sequences, and the register write required to initiate them is summarised in Table 71. In both cases a single register write will initiate the sequence. WSEQ START ADDRESS WSEQ FINISH ADDRESS PURPOSE TO INITIATE 0 29 Start-Up sequence Write 0100h to Register R111 (6Fh) 32 48 Shut-Down sequence Write 0120h to Register R111 (6Fh) Table 71 Write Sequencer Default Sequences Note on Shut-Down sequence: The instruction at Index Address 32 (20h) shorts the outputs LINEOUTL and LINEOUTR. If the Line outputs are not in use at the time the sequence is run, then the sequence could, instead, be started at Index Address 33. Index addresses 0 to 31 may be programmed to users' own settings at any time, as described in "Programming a Sequence" Users' own settings remain in memory and are not affected by software resets (i.e. writing to Register R0). However, any non-default sequences are lost when the device is powered down. The full definition of the ROM/default sequencer configuration is detailed in Table 72. w PP, Rev 3.1, August 2009 104 WM8903 Pre-Production WSEQ INDEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 0 R4 (4h) 5 bits Bit 0 1Ah 0h 0b POBCTRL = 1 ISEL = 10 STARTUP_BIAS_ENA = 1 BIAS_ENA = 0 1 R65 (41h) 1 bit Bit 1 01h 9h 0b SPK_DISCHARGE = 1 Wait 32ms 2 R17 (11h) 2 bits Bit 0 03h 0h 0b SPKL_ENA = 1 SPKR_ENA = 1 3 R65 (41h) 1 bit Bit 1 00h 0h 0b SPK_DISCHARGE = 0 4 R5 (5h) 8 bits Bit 0 F7h Bh 0b VMID_TIE_ENA = 1 BUFIO_ENA = 1 VMID_IO_ENA = 1 VMID_SOFT = 10 VMID_RES = 11 VMID_BUF_ENA = 1 Wait 128ms 5 R17 (11h) 2 bits Bit 0 00h 0h 0b SPKL_ENA = 0 SPKR_ENA = 0 6 R5 (5h) 2 bits Bit 3 00h 0h 0b VMID_SOFT = 00 7 R5 (5h) 2 bits Bit 1 01h 0h 0b VMID_RES = 01 8 R4 (4h) 1 bit Bit 0 01h 0h 0b BIAS_ENA = 1 9 R14 (Eh) 2 bits Bit 0 03h 0h 0b HPL_PGA_ENA = 1 HPR_PGA_ENA = 1 10 R13 (Dh) 2 bits Bit 0 03h 0h 0b MIXOUTL = 1 MIXOUTR = 1 11 R15 (Fh) 2 bits Bit 0 03h 0h 0b LINEOUTL_PGA_ENA = 1 LINEOUTR_PGA_ENA = 1 12 R22 (16h) 1 bit Bit 1 01h 0h 0b CLK_DSP_ENA = 1 13 R18 (12h) 2 bits Bit 2 03h 5h 0b DACL_ENA = 1 DACR_ENA = 1 Wait 2 ms 14 R255 (FFh) 1 bit Bit 0 00h 0h 0b Spare step 15 R4 (4h) 1 bit Bit 4 00h 0h 0b POBCTRL = 0 16 R98 (62h) 1 bit Bit 0 01h 6h 0b CP_ENA = 1 Wait 4ms 17 R255 (FFh) 1 bit Bit 0 00h 0h 0b Spare step 18 R90 (5Ah) 8 bits Bit 0 11h 0h 0b HPL_RMV_SHORT = 0 HPL_ENA_OUTP = 0 HPL_ENA_DLY = 0 HPL_ENA = 1 HPR_RMV_SHORT = 0 HPR_ENA_OUTP = 0 HPR_ENA_DLY = 0 HPR_ENA = 1 w PP, Rev 3.1, August 2009 105 WM8903 WSEQ INDEX Pre-Production REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 19 R94 (5Eh) 8 bits Bit 0 11h 0h 0b LINEOUTL_RMV_SHORT = 0 LINEOUTL_ENA_OUTP = 0 LINEOUTL_ENA_DLY = 0 LINEOUTL_ENA = 1 LINEOUTR_RMV_SHORT = 0 LINEOUTR_ENA_OUTP = 0 LINEOUTR_ENA_DLY = 0 LINEOUTR_ENA = 1 20 R90 (5Ah) 8 bits Bit 0 33h 0h 0b HPL_RMV_SHORT = 0 HPL_ENA_OUTP = 0 HPL_ENA_DLY = 1 HPL_ENA = 1 HPR_RMV_SHORT = 0 HPR_ENA_OUTP = 0 HPR_ENA_DLY = 1 HPR_ENA = 1 21 R94 (5Eh) 8 bits Bit 0 33h 0h 0b LINEOUTL_RMV_SHORT = 0 LINEOUTL_ENA_OUTP = 0 LINEOUTL_ENA_DLY = 1 LINEOUTL_ENA = 1 LINEOUTR_RMV_SHORT = 0 LINEOUTR_ENA_OUTP = 0 LINEOUTR_ENA_DLY = 1 LINEOUTR_ENA = 1 22 R69 (45h) 2 bits Bit 0 02h 0h 0b DCS_MODE = 10 23 R67 (43h) 4 bits Bit 0 0Fh Ch 0b DCS_ENA = 1111 Wait 256ms 24 R67 (43h) 4 bits Bit 0 0Fh 7h 0b DCS_ENA = 1111 Wait 8ms 25 R255 (FFh) 1 bit Bit 0 00h 0h 0b Spare step 26 R90 (5Ah) 8 bits Bit 0 77h 0h 0b HPL_RMV_SHORT = 0 HPL_ENA_OUTP = 1 HPL_ENA_DLY = 1 HPL_ENA = 1 HPR_RMV_SHORT = 0 HPR_ENA_OUTP = 1 HPR_ENA_DLY = 1 HPR_ENA = 1 27 R94 (5Eh) 8 bits Bit 0 77h 0h 0b LINEOUTL_RMV_SHORT = 0 LINEOUTL_ENA_OUTP = 1 LINEOUTL_ENA_DLY = 1 LINEOUTL_ENA = 1 LINEOUTR_RMV_SHORT = 0 LINEOUTR_ENA_OUTP = 1 LINEOUTR_ENA_DLY = 1 LINEOUTR_ENA = 1 w PP, Rev 3.1, August 2009 106 WM8903 Pre-Production WSEQ INDEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 28 R90 (5Ah) 8 bits Bit 0 FFh 0h 0b HPL_RMV_SHORT = 1 HPL_ENA_OUTP = 1 HPL_ENA_DLY = 1 HPL_ENA = 1 HPR_RMV_SHORT = 1 HPR_ENA_OUTP = 1 HPR_ENA_DLY = 1 HPR_ENA = 1 29 R94 (5Eh) 8 bits Bit 0 FFh 0h 1b LINEOUTL_RMV_SHORT = 1 LINEOUTL_ENA_OUTP = 1 LINEOUTL_ENA_DLY = 1 LINEOUTL_ENA = 1 LINEOUTR_RMV_SHORT = 1 LINEOUTR_ENA_OUTP = 1 LINEOUTR_ENA_DLY = 1 LINEOUTR_ENA = 1 End of Default Startup Sequence 30 R255 (FFh) 1 bit Bit 0 00h 0h 0b Spare step 31 R255 (FFh) 1 bit Bit 0 00h 0h 0b Spare step 32 R94 (5Eh) 8 bits Bit 0 77h 0h 0b Start of default shut-down sequence LINEOUTL_RMV_SHORT = 0 LINEOUTL_ENA_OUTP = 1 LINEOUTL_ENA_DLY = 1 LINEOUTL_ENA = 1 LINEOUTR_RMV_SHORT = 0 LINEOUTR_ENA_OUTP = 1 LINEOUTR_ENA_DLY = 1 LINEOUTR_ENA = 1 33 R90 (5Ah) 8 bits Bit 0 77h 0h 0b HPL_RMV_SHORT = 0 HPL_ENA_OUTP = 1 HPL_ENA_DLY = 1 HPL_ENA = 1 HPR_RMV_SHORT = 0 HPR_ENA_OUTP = 1 HPR_ENA_DLY = 1 HPR_ENA = 1 34 R90 (5Ah) 8 bits Bit 0 00h 0h 0b HPL_RMV_SHORT = 0 HPL_ENA_OUTP = 0 HPL_ENA_DLY = 0 HPL_ENA = 0 HPR_RMV_SHORT = 0 HPR_ENA_OUTP = 0 HPR_ENA_DLY = 0 HPR_ENA = 0 35 R94 (5Eh) 8 bits Bit 0 00h 0h 0b LINEOUTL_RMV_SHORT = 0 LINEOUTL_ENA_OUTP = 0 LINEOUTL_ENA_DLY = 0 LINEOUTL_ENA = 0 LINEOUTR_RMV_SHORT = 0 LINEOUTR_ENA_OUTP = 0 LINEOUTR_ENA_DLY = 0 LINEOUTR_ENA = 0 36 R67 (43h) 4 bits Bit 0 00h 0h 0b DCS_ENA = 0000 w PP, Rev 3.1, August 2009 107 WM8903 WSEQ INDEX Pre-Production REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 37 R98 (62h) 1 bit Bit 0 00h 0h 0b CP_ENA = 0 38 R18 (12h) 2 bits Bit 2 00h 0h 0b DACL_ENA = 0 DACR_ENA = 0 39 R22 (16h) 1 bit Bit 1 00h 0h 0b CLK_DSP_ENA = 0 40 R14 (0Eh) 2 bits Bit 0 00h 0h 0b HPL_PGA_ENA = 0 HPR_PGA_ENA = 0 41 R15 (0Fh) 2 bits Bit 0 00h 0h 0b LINEOUTL_PGA_ENA = 0 LINEOUTR_PGA_ENA = 0 42 R13 (0Dh) 2 bits Bit 0 00h 0h 0b MIXOUTL_ENA = 0 MIXOUTR_ENA = 0 43 R4 (04h) 1 bit Bit 0 00h 0h 0b BIAS_ENA = 0 44 R5 (05h) 2 bits Bit 3 02h 0h 0b VMID_SOFT = 10 45 R5 (05h) 1 bit Bit 0 00h Ch 0b VMID_BUF_ENA = 0 Wait 256ms 46 R5 (05h) 1 bit Bit 0 00h 9h 0b VMID_BUF_ENA = 0 Wait 32ms 47 R5 (05h) 8 bits Bit 0 00h 0h 0b VMID_TIE_ENA = 0 BUFIO_ENA = 0 VMID_IO_ENA = 0 VMID_SOFT = 00 VMID_RES = 00 VMID_BUF_ENA = 0 48 R4 (04h) 2 bits Bit 0 00h 0h 1b STARTUP_BIAS_ENA = 0 BIAS_ENA = 0 End of Default Shutdown Sequence Table 72 Write Sequencer Default Values w PP, Rev 3.1, August 2009 108 WM8903 Pre-Production POWER-ON RESET Figure 61 Internal Power on Reset Circuit Schematic The WM8903 includes an internal Power-On-Reset Circuit, as shown in Figure 61, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. It asserts PORB low if AVDD or DCVDD is below a minimum threshold. POWER-UP TIMING - AVDD POWERED BEFORE DCVDD Figure 62 Typical Power up Sequence where AVDD is Powered before DCVDD Figure 62 shows the power-up sequence where AVDD is powered up before DCVDD. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Once AVDD is at full supply level, and DCVDD rises to Vpord_on the internal PORB is set high, all registers are in their default state and writes to the control interface may now take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off. w PP, Rev 3.1, August 2009 109 WM8903 Pre-Production POWER-UP TIMING - DCVDD POWERED BEFORE AVDD Figure 63 Typical Power up Sequence where DCVDD is Powered before AVDD Figure 63 shows the power-up sequence where DCVDD is powered up before AVDD. It is assumed that DCVDD is at the specified operating voltage before AVDD rises to the minimum threshold, Vpora. At this point, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises to Vpora_on, PORB is released high, all registers are in their default state and writes to the control interface may take place. On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpord_off. POWER-UP / POWER-DOWN CHARACTERISTICS The threshold voltages and timing characteristics for power-up and power-down are listed in Table 73. SYMBOL MIN TYP MAX UNIT Vpora 0.5 V Vpora_on 1.15 V Vpora_off 1.12 V Vpord_on 0.57 V Vpord_off 0.56 V Tpor 10.6 s Table 73 Typical POR Operation (typical values, not tested) Notes: w 1. If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpora_off or Vpord_off) then the chip does not reset and resumes normal operation when the voltage is back to the recommended level again. 2. The chip enters reset at power down when AVDD or DCVDD falls below Vpora_off or Vpord_off. This may be important if the supply is turned on and off frequently by a power management system. 3. The minimum tpor period is maintained even if DCVDD and AVDD have zero rise time. This specification is guaranteed by design rather than test. PP, Rev 3.1, August 2009 110 WM8903 Pre-Production QUICK START-UP AND SHUTDOWN The WM8903 has the capability to perform a quick start-up and shut-down with a minimum number of register operations. The Control Write Sequencer is configured with default start-up settings that configure the device for DAC playback via Headphone and Line Output. Assuming a 12.288MHz external clock, the start-up sequence configures the device for 48kHz playback mode. The start-up sequence requires three register write operations. The shut-down sequence requires just a single register write. The minimum procedure for executing the quick start-up and shut-down sequences is described below. See "Control Write Sequencer" for more details. START-UP An external clock must be applied to MCLK. The default start-up sequence assumes this is 12MHz. The following register operations will initiate the default start-up sequence. REGISTER ADDRESS VALUE DESCRIPTION R108 (6Ch) 0100h WSMD_CLK_ENA = 1 This enables the Write Sequencer Clock R22 (16h) 0004h CLK_SYS_ENA = 1 This enables the System Clock R111 (6Fh) 0100h WSEQ_START_INDEX = 00 WSEQ_START = 1 WSEQ_ABORT = 0 This starts the Write Sequencer at Index address 0 (00h) Table 74 Quick Start Enable Assuming 12MHz input clock, the start-up sequence will take approximately 425ms to complete. The WSEQ_BUSY bit (in Register R112, see Table 69) will be set to 1 while the sequence runs. When this bit returns to 0, the device has been set up and is ready for DAC playback operation. SHUTDOWN The default shut-down sequences assumes the initial device conditions are as configured by the default start-up sequence. The following register operation will initiate the default shut-down sequence. REGISTER ADDRESS R111 (6Fh) VALUE DESCRIPTION 0120h WSEQ_START_INDEX = 20h WSEQ_START = 1 WSEQ_ABORT = 0 This starts the Write Sequencer at Index address 32 (20h) Table 75 Quick Shut-Down Enable Assuming 12.288MHz input clock, the shut-down sequence will take approximately 325ms to complete. The WSEQ_BUSY bit (in Register R112, see Table 69) will be set to 1 while the sequence runs. When this bit returns to 0, the system clock can be disabled (CLK_SYS_ENA=0) and MCLK can be stopped. w PP, Rev 3.1, August 2009 111 WM8903 Pre-Production CHIP RESET AND DEVICE ID The WM8903 can be reset by writing to Register 0. This is a read-only register field, and the contents will not be affected by writing to this Register. The Device ID can be read back from Register 0. The Chip Revision ID can be read back from Register 1, as described in Table 76. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 (00h) SW Reset and ID 15:0 SW_RST_DE C_ID1 [15:0] 8903h Writing to this register resets all registers to their default state. Reading from this register will indicate Device ID 8903h. R1 (01h) Revision Number 3:0 CHIP_REV [3:0] 0010b Reading from this register will indicate the Revision ID. Table 76 Chip Reset and ID w PP, Rev 3.1, August 2009 112 WM8903 Pre-Production REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8903 can be configured using the Control Interface. REG NAME R0 (0h) SW Reset and ID R1 (1h) Revision Number 0 0 0 0 0 0 0 0 0 0 0 0 R4 (4h) Bias Control 0 0 0 0 0 0 0 0 0 0 0 0 POBCT RL R5 (5h) VMID Control 0 0 0 0 0 0 0 0 0 R6 (6h) Mic Bias Control 0 0 0 0 0 0 0 0 0 0 0 MICDET_THR[1: MICSHORT_TH MICDE MICBIA 0] R[1:0] T_ENA S_ENA 0000h R8 (8h) Analogue DAC 0 0 0 0 0 0 0 0 0 0 0 DAC_B DACBIAS_SEL[ DACVMID_BIAS IAS_B 1:0] _SEL[1:0] OOST 0 0001h R10 (0Ah) Analogue ADC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_O SR128 0001h R12 (Ch) Power Management 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INL_EN INR_E A NA 0000h R13 (Dh) Power Management 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIXOU MIXOU TL_EN TR_EN A A 0000h R14 (Eh) Power Management 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPL_P HPR_P GA_EN GA_EN A A 0000h R15 (Fh) Power Management 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINEO LINEO UTL_P UTR_P GA_EN GA_EN A A 0000h R16 (10h) Power Management 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIXSP MIXSP KL_EN KR_EN A A 0000h R17 (11h) Power Management 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPKL_ SPKR_ ENA ENA 0000h R18 (12h) Power Management 6 0 0 0 0 0 0 0 0 0 0 0 0 DACL_ DACR_ ADCL_ ADCR_ ENA ENA ENA ENA 0000h R20 (14h) Clock Rates 0 0 0 0 0 0 0 0 0 0 0 0 0 R21 (15h) Clock Rates 1 0 0 0 0 0 0 R22 (16h) Clock Rates 2 0 0 0 0 0 0 0 R24 (18h) Audio Interface 0 0 0 0 R25 (19h) Audio Interface 1 0 0 R26 0 0 Audio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SW_RST_DEV_ID1[15:0] w CLK_SYS_RATE[3:0] 0 0 CLK_SYS_MOD E[1:0] 0 0 0 8903h CHIP_REV[3:0] 0002h START BIAS_E NA UP_BI AS_EN A 0018h VMID_ BUFIO VMID_I VMID_SOFT[1:0 VMID_RES[1:0] VMID_ TIE_EN _ENA O_ENA ] BUF_E A NA 0000h ISEL[1:0] 0 0 0 0 MCLKD IV2 SAMPLE_RATE[3:0] 0C08h 0000h DACL_ DACR_ DAC_BOOST[1: LOOPB AIFAD AIFAD AIFDA AIFDA ADC_C ADC_C DAC_C DAC_C DATIN DATIN 0] ACK CL_SR CR_SR CL_SR CR_SR OMP OMPM OMP OMPM V V C C C C ODE ODE 0050h 0 0 0 0 0 0 AIF_BC BCLK_ LK_INV DIR 0 0 0 0 AIF_LR CLK_IN V 0 0400h CLK_S CLK_D TO_EN YS_EN SP_EN A A A AIFDA AIFDA AIFAD AIFAD LRCLK C_TDM C_TDM C_TDM C_TDM _DIR _CHAN _CHAN 0 DEFAULT AIF_WL[1:0] AIF_FMT[1:0] BCLK_DIV[4:0] 0002h 0008h PP, Rev 3.1, August 2009 113 WM8903 REG NAME Pre-Production 15 14 13 12 11 Audio Interface 3 0 0 0 0 0 DAC Digital Volume Left 0 0 0 0 0 0 0 DACVU DACL_VOL[7:0] 00C0h R31 (1Fh) DAC Digital Volume Right 0 0 0 0 0 0 0 DACVU DACR_VOL[7:0] 00C0h R32 (20h) DAC Digital 0 0 0 0 0 R33 (21h) DAC Digital 1 0 0 0 R36 (24h) ADC Digital Volume Left 0 0 0 0 0 0 0 ADCVU ADCL_VOL[7:0] 00C0h R37 (25h) ADC Digital Volume Right 0 0 0 0 0 0 0 ADCVU ADCR_VOL[7:0] 00C0h R38 (26h) ADC Digital 0 0 0 0 0 0 0 0 0 DRC_E NA 0 0 (1Ah) Interface 2 R27 (1Bh) R30 (1Eh) R40 (28h) DRC 0 R41 (29h) DRC 1 10 9 8 7 5 4 3 2 1 0 LRCLK_RATE[10:0] ADCL_DAC_SVOL[3:0] DAC_M DAC_S DAC_M DAC_M ONO B_FILT UTERA UTEM TE ODE DRC_THRESH_ HYST[1:0] DRC_ATTACK_RATE[3:0] 6 ADCR_DAC_SVOL[3:0] 0 0 0 0 0 ADC_HPF_CUT[ ADC_H 1:0] PF_EN A 0022h ADC_TO_DACL[ ADC_TO_DACR 1:0] [1:0] 0000h DAC_M DEEMPH[1:0] DAC_O UTE SR 0000h ADCL_ ADCR_ DATIN DATIN V V 0000h DRC_S DRC_Q DRC_A DRC_H MOOT R_ENA NTICLI YST_E P_ENA NA H_ENA 09Afh DRC_THRESH_ DRC_RATE_QR DRC_MINGAIN[ DRC_MAXGAIN QR[1:0] [1:0] 1:0] [1:0] 3241h DRC_STARTUP_GAIN[4:0] DRC_DECAY_RATE[3:0] 0 DEFAULT DRC_F F_DEL AY 0 0 0 R42 (2Ah) DRC 2 0 0 0 0 0 R43 (2Bh) DRC 3 0 0 0 0 0 R44 (2Ch) Analogue Left Input 0 0 0 0 0 0 0 0 0 LINMU TE 0 R45 (2Dh) Analogue Right Input 0 0 0 0 0 0 0 0 0 RINMU TE 0 R46 (2Eh) Analogue Left Input 1 0 0 0 0 0 0 0 0 0 INL_C L_IP_SEL_N[1:0 L_IP_SEL_P[1:0 M_ENA ] ] L_MODE[1:0] 0044h R47 (2Fh) Analogue Right Input 1 0 0 0 0 0 0 0 0 0 INR_C R_IP_SEL_N[1:0 R_IP_SEL_P[1:0 R_MODE[1:0] M_ENA ] ] 0044h R50 (32h) Analogue Left Mix 0 0 0 0 0 0 0 0 0 0 0 0 0 DACL_ DACR_ BYPAS BYPAS TO_MI TO_MI SL_TO SR_TO XOUTL XOUTL _MIXO _MIXO UTL UTL 0008h R51 (33h) Analogue Right Mix 0 0 0 0 0 0 0 0 0 0 0 0 0 DACL_ DACR_ BYPAS BYPAS TO_MI TO_MI SL_TO SR_TO XOUTR XOUTR _MIXO _MIXO UTR UTR 0004h R52 (34h) Analogue Spk Mix Left 0 0 0 0 0 0 0 0 0 0 0 0 0 DACL_ DACR_ BYPAS BYPAS TO_MI TO_MI SL_TO SR_TO XSPKL XSPKL _MIXS _MIXS PKL PKL 0000h R53 (35h) Analogue Spk Mix Left 1 0 0 0 0 0 0 0 0 0 0 0 0 DACL_ DACR_ BYPAS BYPAS MIXSP MIXSP SL_MI SR_MI KL_VO KL_VO XSPKL XSPKL _VOL _VOL L L 0000h R54 (36h) Analogue Spk Mix Right 0 0 0 0 0 0 0 0 0 0 0 0 0 DACL_ DACR_ BYPAS BYPAS TO_MI TO_MI SL_TO SR_TO XSPKR XSPKR _MIXS _MIXS PKR PKR 0000h R55 (37h) Analogue Spk Mix 0 0 0 0 0 0 0 0 0 0 0 0 DACL_ DACR_ BYPAS BYPAS MIXSP MIXSP SL_MI SR_MI 0000h w 0 0 0 0 0 DRC_R0_SLOPE_COMP DRC_R1_SLOPE_COMP [2:0] [2:0] DRC_THRESH_COMP[5:0] 0020h DRC_AMP_COMP[4:0] 0000h 0 LIN_VOL[4:0] 0085h 0 RIN_VOL[4:0] 0085h PP, Rev 3.1, August 2009 114 WM8903 Pre-Production REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 Right 1 2 1 0 DEFAULT KR_VO KR_VO XSPKR XSPKR L L _VOL _VOL R57 (39h) Analogue OUT1 Left 0 0 0 0 0 0 0 HPL_M HPOUT HPOUT UTE VU LZC HPOUTL_VOL[5:0] 002Dh R58 (3Ah) Analogue OUT1 Right 0 0 0 0 0 0 0 HPR_M HPOUT HPOUT UTE VU RZC HPOUTR_VOL[5:0] 002Dh R59 (3Bh) Analogue OUT2 Left 0 0 0 0 0 0 0 LINEO LINEO LINEO UTL_M UTVU UTLZC UTE LINEOUTL_VOL[5:0] 0039h R60 (3Ch) Analogue OUT2 Right 0 0 0 0 0 0 0 LINEO LINEO LINEO UTR_M UTVU UTRZC UTE LINEOUTR_VOL[5:0] 0039h R62 (3Eh) Analogue OUT3 Left 0 0 0 0 0 0 0 SPKL_ SPKVU SPKLZ MUTE C SPKL_VOL[5:0] 0139h R63 (3Fh) Analogue OUT3 Right 0 0 0 0 0 0 0 SPKR_ SPKVU SPKRZ MUTE C SPKR_VOL[5:0] 0139h R65 (41h) Analogue SPK Output Control 0 0 0 0 0 0 0 0 0 0 0 0 0 R67 (43h) DC Servo 0 0 0 0 0 0 0 0 0 0 0 0 DCS_M ASTER _ENA R69 (45h) DC Servo 2 0 0 0 0 0 0 0 0 0 0 0 0 R71 (47h) DC Servo 4 0 0 0 0 0 0 0 0 DCS_HPOUTL_WRITE_VAL[7:0] 0000h R72 (48h) DC Servo 5 0 0 0 0 0 0 0 0 DCS_HPOUTR_WRITE_VAL[7:0] 0000h R73 (49h) DC Servo 6 0 0 0 0 0 0 0 0 DCS_LOUTL_WRITE_VAL[7:0] 0000h R74 (4Ah) DC Servo 7 0 0 0 0 0 0 0 0 DCS_LOUTR_WRITE_VAL[7:0] 0000h R81 (51h) DC Servo Readback 1 0 0 0 0 0 0 0 0 DCS_HPOUTL_INTEG[7:0] 0000h R82 (52h) DC Servo Readback 2 0 0 0 0 0 0 0 0 DCS_HPOUTR_INTEG[7:0] 0000h R83 (53h) DC Servo Readback 3 0 0 0 0 0 0 0 0 DCS_LOUTL_INTEG[7:0] 0000h R84 (54h) DC Servo Readback 4 0 0 0 0 0 0 0 0 DCS_LOUTR_INTEG[7:0] 0000h R90 (5Ah) Analogue HP 0 0 0 0 0 0 0 0 0 HPL_R HPL_E HPL_E HPL_E HPR_R HPR_E HPR_E HPR_E MV_SH NA_OU NA_DL NA MV_SH NA_OU NA_DL NA ORT TP Y ORT TP Y 0000h R94 (5Eh) Analogue Lineout 0 0 0 0 0 0 0 0 0 LINEO LINEO LINEO LINEO LINEO LINEO LINEO LINEO UTL_R UTL_E UTL_E UTL_E UTR_R UTR_E UTR_E UTR_E MV_SH NA_OU NA_DL NA MV_SH NA_OU NA_DL NA Y TP ORT Y TP ORT 0000h R98 (62h) Charge Pump 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP_EN A 0000h R104 (68h) Class W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP_DY N_PW R 0010h R108 (6Ch) Write Sequencer 0 0 0 0 0 0 0 0 WSMD _CLK_ ENA 0 0 0 R109 (6Dh) Write Sequencer 1 0 WSEQ_DATA_WIDTH[2: 0] R110 (6Eh) Write Sequencer 2 0 WSEQ _EOS 0 0 R111 (6Fh) Write Sequencer 3 0 0 0 0 w 0 0 SPK_D VROI ISCHA RGE DCS_ENA[3:0] 0 0 0010h DCS_MODE[1:0] WSEQ_WRITE_INDEX[4:0] 0000h 00A4h 0000h WSEQ_DATA_START[3:0] WSEQ_ADDR[7:0] 0000h WSEQ_DELAY[3:0] WSEQ_DATA[7:0] 0000h 0 0 WSEQ WSEQ _ABOR _STAR T T 0 0 WSEQ_START_INDEX[5:0] 0000h PP, Rev 3.1, August 2009 115 WM8903 REG Pre-Production NAME 15 14 13 12 11 10 R112 (70h) Write Sequencer 4 0 0 0 0 0 0 R116 (74h) GPIO Control 1 0 0 R117 (75h) GPIO Control 2 0 R118 (76h) GPIO Control 3 R119 (77h) 3 2 1 0 DEFAULT 0 0 0 WSEQ _BUSY 0000h GP1_FN[5:0] GP1_DI GP1_O GP1_IP GP1_L GP1_P GP1_P GP1_IN GP1_D R P_CFG _CFG VL D U TMOD B E 00A8h 0 GP2_FN[5:0] GP2_DI GP2_O GP2_IP GP2_L GP2_P GP2_P GP2_IN GP2_D R P_CFG _CFG VL D U TMOD B E 00A8h 0 0 GP3_FN[5:0] GP3_DI GP3_O GP3_IP GP3_L GP3_P GP3_P GP3_IN GP3_D R P_CFG _CFG VL D U TMOD B E 00A8h GPIO Control 4 0 0 GP4_FN[5:0] GP4_DI GP4_O GP4_IP GP4_L GP4_P GP4_P GP4_IN GP4_D R P_CFG _CFG VL D U TMOD B E 0220h R120 (78h) GPIO Control 5 0 0 GP5_FN[5:0] GP5_DI GP5_O GP5_IP GP5_L GP5_P GP5_P GP5_IN GP5_D R P_CFG _CFG VL D U TMOD B E 01A0h R121 (79h) Interrupt Status 1 MICSH MICDE WSEQ RT_EIN T_EINT _BUSY T _EINT 0 0 0 0 0 0 0 0 GP5_EI GP4_EI GP3_EI GP2_EI GP1_EI NT NT NT NT NT 0000h R122 (7Ah) Interrupt Status 1 Mask IM_MIC IM_MIC IM_WS SHRT_ DET_EI EQ_BU EINT NT SY_EI NT 0 0 0 0 0 0 0 0 IM_GP IM_GP IM_GP IM_GP IM_GP 5_EINT 4_EINT 3_EINT 2_EINT 1_EINT FFFFh R123 (7Bh) Interrupt Polarity 1 MICSH MICDE RT_INV T_INV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h R126 (7Eh) Interrupt Control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ_P OL 0000h R164 (A4h) Clock Rate Test 4 0 0 0 0 0 0 ADC_D IG_MIC 0 0 0 0 0 0 0 0 0 0028h R172 (ACh) Analogue Output Bias 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h R187 (BBh) Analogue Output Bias 2 0 0 0 0 0 0 0 0 0 w 9 8 7 6 5 4 WSEQ_CURRENT_INDEX[5:0] PGA_BIAS[2:0] 0 0 0 0 OUTPUTS_BIAS[2:0] 0000h PP, Rev 3.1, August 2009 116 WM8903 Pre-Production REGISTER BITS BY ADDRESS REGISTER ADDRESS BIT R0 (00h) SW Reset and ID 15:0 LABEL DEFAULT DESCRIPTION SW_RST_DEV_ID1[15:0] 1000_1001_0000_0011 Writing to this register resets all registers to their default state. Reading from this register will indicate Device ID 8903h. Register 00h SW Reset and ID REGISTER ADDRESS R1 (01h) Revision Number BIT LABEL DEFAULT 3:0 CHIP_REV[3:0] 0010 DESCRIPTION Reading from this register will indicate the Revision ID. Register 01h Revision Number REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 (04h) Bias Control 0 4 POBCTRL 1 Selects the bias current source for output amplifiers and VMID buffer 0 = Default bias 1 = Start-Up bias 3:2 ISEL[1:0] 10 Master Bias control 00 = Normal bias x 0.5 01 = Normal bias x 0.75 10 = Normal bias 11 = Normal bias x 1.5 1 STARTUP_BIAS_ENA 0 Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled 0 BIAS_ENA 0 Enables the Normal bias current generator (for all analogue functions) 0 = Disabled 1 = Enabled Register 04h Bias Control 0 w PP, Rev 3.1, August 2009 117 WM8903 REGISTER ADDRESS R5 (05h) VMID Control 0 Pre-Production BIT LABEL DEFAULT DESCRIPTION 7 VMID_TIE_ENA 0 VMID buffer to Differential Lineouts 0 = Disabled 1 = Enabled (only applies when relevant outputs are disabled, ie. SPLK=0 or SPKR=0. Resistance is controlled by VROI.) 6 BUFIO_ENA 0 VMID buffer to unused input and output pins. 0 = Disabled 1 = Enabled 5 VMID_IO_ENA 0 Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled (same functionality as STARTUP_BIAS_ENA) 4:3 VMID_SOFT[1:0] 00 VMID soft start enable / slew rate control 00 = Disabled 01 = Fast soft start 10 = Nominal soft start 11 = Slow soft start 2:1 VMID_RES[1:0] 00 VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) 0 VMID_BUF_ENA 0 VMID Buffer Enable 0 = Disabled 1 = Enabled Register 05h VMID Control 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) Mic Bias Control 0 7:6 Reserved 00 Reserved. Writing `1' to these register bits will have no effect. 5:4 MICDET_THR [1:0] 00 MICBIAS Current Detect Insertion Threshold 00 = 0.063mA 01 = 0.26mA 10 = 0.45mA 11 = 0.635mA If AVDD 1.8, values are scaled 3:2 MICSHORT_THR[1:0] 00 MICBIAS Short Circuit Button Push Threshold 00 = 0.52mA 01 = 0.77mA 10 = 1.2mA 11 = 1.43mA If AVDD 1.8, values are scaled 1 MICDET_ENA 0 MICBIAS Current and Short Circuit Detect Enable 0 = disabled 1 = enabled 0 MICBIAS_ENA 0 MICBIAS Enable 0 = disabled 1 = enabled Register 06h Mic Bias Control 0 w PP, Rev 3.1, August 2009 118 WM8903 Pre-Production REGISTER ADDRESS R8 (08h) Analogue DAC 0 BIT LABEL DEFAULT DESCRIPTION 5 DAC_BIAS_BOOST 0 DAC Bias boost 0 = Disable 1 = Enable When DAC Bias boost is enabled, the bias selected by DACBIAS_SEL and DACVMID_BIAS_SEL are both doubled. 4:3 DACBIAS_SEL[1:0] 00 DAC bias current select 00 = Normal bias 01 = Normal bias x 0.5 10 = Normal bias x 0.66 11 = Normal bias x 0.75 2:1 DACVMID_BIAS_SEL[1:0] 00 DAC VMID buffer bias select 00 = Normal bias 01 = Normal bias x 0.5 10 = Normal bias x 0.66 11 = Normal bias x 0.75 Register 08h Analogue DAC 0 REGISTER ADDRESS R10 (0Ah) Analogue ADC 0 BIT LABEL DEFAULT 0 ADC_OSR128 1 DESCRIPTION ADC Oversampling Ratio 0 = Low Power (64 x fs) 1 = High Performance (128 x fs) Note that the Low Power options is not supported when CLK_SYS_MODE=10 Register 10h Analogue ADC 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12 (0Ch) Power Management 0 1 INL_ENA 0 Left Input PGA Enable 0 = disabled 1 = enabled 0 INR_ENA 0 Right Input PGA Enable 0 = disabled 1 = enabled Register 0Ch Power Management 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R13 (0Dh) Power Management 1 1 MIXOUTL_ENA 0 Left Output Mixer Enable 0 = disabled 1 = enabled 0 MIXOUTR_ENA 0 Right Output Mixer Enable 0 = disabled 1 = enabled Register 0Dh Power Management 1 w PP, Rev 3.1, August 2009 119 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R14 (0Eh) Power Management 2 1 HPL_PGA_ENA 0 Left Headphone Output Enable 0 = disabled 1 = enabled 0 HPR_PGA_ENA 0 Right Headphone Output Enable 0 = disabled 1 = enabled Register 0Eh Power Management 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R15 (0Fh) Power Management 3 1 LINEOUTL_PGA_ENA 0 Left Line Output Enable 0 = disabled 1 = enabled 0 LINEOUTR_PGA_ENA 0 Right Line Output Enable 0 = disabled 1 = enabled Register 0Fh Power Management 3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R16 (10h) Power Management 4 1 MIXSPKL_ENA 0 Left Speaker Mixer Enable 0 = disabled 1 = enabled 0 MIXSPKR_ENA 0 Right Speaker Mixer Enable 0 = disabled 1 = enabled Register 10h Power Management 4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R17 (11h) Power Management 5 1 SPKL_ENA 0 Left Speaker Output Enable 0 = disabled 1 = enabled 0 SPKR_ENA 0 Right Speaker Output Enable 0 = disabled 1 = enabled Register 11h Power Management 5 w PP, Rev 3.1, August 2009 120 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R18 (12h) Power Management 6 3 DACL_ENA 0 Left DAC Enable 0 = DAC disabled 1 = DAC enabled 2 DACR_ENA 0 Right DAC Enable 0 = DAC disabled 1 = DAC enabled 1 ADCL_ENA 0 Left ADC Enable 0 = disabled 1 = enabled 0 ADCR_ENA 0 Right ADC Enable 0 = disabled 1 = enabled Register 12h Power Management 6 REGISTER ADDRESS BIT LABEL DEFAULT R20 (14h) Clock Rates 0 0 MCLKDIV2 0 DESCRIPTION Enables divide by 2 on MCLK 0 = CLK_SYS = MCLK 1 = CLK_SYS = MCLK / 2 Register 14h Clock Rates 0 REGISTER ADDRESS BIT LABEL DEFAULT R21 (15h) Clock Rates 1 13:10 CLK_SYS_RATE[3:0] 0011 DESCRIPTION CLK_SYS / Sample rate (fs) ratio if CLK_SYS_MODE = 00 (256*fs related clocks) 0000 = 64*fs 0001 = 128*fs 0010 = 192*fs 0011 = 256*fs 0100 = 384*fs 0101 = 512*fs 0110 = 768*fs 0111 = 1024 *fs 1000 = 1408*fs 1001 = 1536*fs 1010 to 1111 = Reserved if CLK_SYS_MODE = 01 (272*fs related clocks) 0000 = 68*fs 0001 = 136*fs 0010 = 204*fs 0011 = 272*fs 0100 = 408*fs 0101 = 544*fs 0110 = 816*fs 0111 = 1088 *fs 1000 = 1496*fs 1001 = 1632*fs w PP, Rev 3.1, August 2009 121 WM8903 REGISTER ADDRESS Pre-Production BIT LABEL DEFAULT DESCRIPTION 1010 to 1111 = Reserved if CLK_SYS_MODE = 10 (250*fs related clocks) 0000 = 125*fs 0001 = 125*fs 0010 = 250*fs 0011 = 250*fs 0100 = 375*fs 0101 = 500*fs 0110 = 750*fs 0111 = 1000 *fs 1000 = 1000*fs 1001 = 1500*fs 1010 to 1111 = Reserved 9:8 CLK_SYS_MODE[1:0] 00 CLK_SYS mode 00 = 256*fs related 01 = 272*fs related 10 = 250*fs related 11 = Reserved 3:0 SAMPLE_RATE[3:0] 1000 Selects the Sample Rate (fs) 0000 = 8kHz 0001 = 11.025kHz 0010 = 12kHz 0011 = 16kHz 0100 = 22.05kHz 0101 = 24kHz 0110 = 32kHz 0111 = 44.1kHz 1000 = 48kHz 1001 = 88.2kHz (Not available for Digital Microphone. Not used for 88.2kHz ADC.) 1010 = 96kHz (Not available for Digital Microphone. Not used for 96kHz ADC). 1011 to 1111 = Reserved If the desired sample rate is not listed in this table, then the closest alternative should be chosen. Register 15h Clock Rates 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R22 (16h) Clock Rates 2 2 CLK_SYS_ENA 0 System Clock enable 0 = Disabled 1 = Enabled 1 CLK_DSP_ENA 0 DSP Clock enable 0 = Disabled 1 = Enabled 0 TO_ENA 0 Zero Cross timeout enable 0 = Disabled 1 = Enabled Register 16h Clock Rates 2 w PP, Rev 3.1, August 2009 122 WM8903 Pre-Production REGISTER ADDRESS R24 (18h) Audio Interface 0 BIT LABEL DEFAULT DESCRIPTION 12 DACL_DATINV 0 Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted 11 DACR_DATINV 0 Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted 10:9 DAC_BOOST[1:0] 00 DAC Digital Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS) 10 = +12dB (Input data must not exceed -12dBFS) 11 = +18dB (Input data must not exceed -18dBFS) 8 LOOPBACK 0 Digital Loopback Function 0 = No loopback 1 = Loopback enabled (ADC data output is directly input to DAC data input) 7 AIFADCL_SRC 0 Left Digital Audio channel source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 6 AIFADCR_SRC 1 Right Digital Audio channel source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 5 AIFDACL_SRC 0 Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data 4 AIFDACR_SRC 1 Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data 3 ADC_COMP 0 ADC Companding Enable 0 = disabled 1 = enabled 2 ADC_COMPMODE 0 ADC Companding Type 0 = -law 1 = A-law 1 DAC_COMP 0 DAC Companding Enable 0 = disabled 1 = enabled 0 DAC_COMPMODE 0 DAC Companding Type 0 = -law 1 = A-law Register 18h Audio Interface 0 w PP, Rev 3.1, August 2009 123 WM8903 REGISTER ADDRESS R25 (19h) Audio Interface 1 Pre-Production BIT LABEL DEFAULT DESCRIPTION 13 AIFDAC_TDM 0 DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT 12 AIFDAC_TDM_CHAN 0 DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 11 AIFADC_TDM 0 ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT 10 AIFADC_TDM_CHAN 0 ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 9 LRCLK_DIR 0 Audio Interface LRC Direction 0 = LRC is input 1 = LRC is output 7 AIF_BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 6 BCLK_DIR 0 Audio Interface BCLK Direction 0 = BCLK is input 1 = BCLK is output 4 AIF_LRCLK_INV 0 LRC Polarity / DSP Mode A-B select. Right, left and I2S modes - LRC polarity 0 = Not Inverted 1 = Inverted DSP Mode - Mode A-B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 3:2 AIF_WL[1:0] 00 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 AIF_FMT[1:0] 10 Digital Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP Register 19h Audio Interface 1 w PP, Rev 3.1, August 2009 124 WM8903 Pre-Production REGISTER ADDRESS R26 (1Ah) Audio Interface 2 BIT LABEL DEFAULT 4:0 BCLK_DIV[4:0] 0_1000 DESCRIPTION BCLK Frequency (Master Mode) 00000 = CLK_SYS 00001 = Reserved 00010 = CLK_SYS / 2 00011 = CLK_SYS / 3 00100 = CLK_SYS / 4 00101 = CLK_SYS / 5 00110 = Reserved 00111 = CLK_SYS / 6 01000 = CLK_SYS / 8 (default) 01001 = CLK_SYS / 10 01010 = Reserved 01011 = CLK_SYS / 12 01100 = CLK_SYS / 16 01101 = CLK_SYS / 20 01110 = CLK_SYS / 22 01111 = CLK_SYS / 24 10000 = Reserved 10001 = CLK_SYS / 30 10010 = CLK_SYS / 32 10011 = CLK_SYS / 44 10100 = CLK_SYS / 48 Register 1Ah Audio Interface 2 REGISTER ADDRESS R27 (1Bh) Audio Interface 3 BIT 10:0 LABEL DEFAULT DESCRIPTION LRCLK_RATE[10:0] 000_0010_0010 LRC Rate (Master Mode) LRC clock output = BCLK / LRCLK_RATE Integer (LSB = 1) Valid range: 8 to 2047 LRCLK duty cycle is only guaranteed with even values (8, 10, ... ... , 2047). Register 1Bh Audio Interface 3 REGISTER ADDRESS R30 (1Eh) DAC Digital Volume Left BIT LABEL DEFAULT 8 DACVU 0 7:0 DACL_VOL[7:0] 1100_0000 DESCRIPTION DAC Volume Update Writing a 1 to this bit causes left and right DAC volume to be updated simultaneously Left DAC Digital Volume 00h = Mute 01h = -71.625dB 02h = -71.250dB ... (0.375dB steps) C0h to FFh = 0dB Register 1Eh DAC Digital Volume Left w PP, Rev 3.1, August 2009 125 WM8903 REGISTER ADDRESS R31 (1Fh) DAC Digital Volume Right Pre-Production BIT LABEL DEFAULT 8 DACVU 0 7:0 DESCRIPTION DAC Volume Update Writing a 1 to this bit causes left and right DAC volume to be updated simultaneously DACR_VOL[7:0] 1100_0000 Right DAC Digital Volume 00h = Mute 01h = -71.625dB 02h = -71.250dB ... (0.375dB steps) C0h to FFh = 0dB Register 1Fh DAC Digital Volume Right REGISTER ADDRESS R32 (20h) DAC Digital 0 BIT LABEL DEFAULT DESCRIPTION 11:8 ADCL_DAC_SVOL[3:0] 0000 Left Digital Sidetone Volume 0000 = -36dB 0001 = -33dB (... 3dB steps) 1011 = -3dB 11XX = 0dB 7:4 ADCR_DAC_SVOL[3:0] 0000 Right Digital Sidetone Volume 0000 = -36dB 0001 = -33dB (... 3dB steps) 1011 = -3dB 11XX = 0dB 3:2 ADC_TO_DACL[1:0] 00 Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved 1:0 ADC_TO_DACR[1:0] 00 Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Register 20h DAC Digital 0 w PP, Rev 3.1, August 2009 126 WM8903 Pre-Production REGISTER ADDRESS R33 (21h) DAC Digital 1 BIT LABEL DEFAULT DESCRIPTION 12 DAC_MONO 0 DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DAC) 11 DAC_SB_FILT 0 Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode (recommended when fs 24kHz) 10 DAC_MUTERATE 0 DAC Soft Mute Ramp Rate 0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) 9 DAC_MUTEMODE 0 DAC Soft Mute Mode 0 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to change immediately to DACL_VOL and DACR_VOL settings 1 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the DACL_VOL and DACR_VOL settings 3 DAC_MUTE 0 DAC Soft Mute Control 0 = DAC Un-mute 1 = DAC Mute 2:1 DEEMPH[1:0] 00 DAC De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate 0 DAC_OSR 0 DAC Oversampling Control 0 = Low power (normal oversample) 1 = High performance (double rate) Register 21h DAC Digital 1 REGISTER ADDRESS R36 (24h) ADC Digital Volume Left BIT LABEL DEFAULT 8 ADCVU 0 7:0 ADCL_VOL[7:0] 1100_0000 DESCRIPTION ADC Volume Update Writing a 1 to this bit causes left and right ADC volume to be updated simultaneously Left ADC Digital Volume 00h = Mute 01h = -71.625dB 02h = -71.250dB ... (0.375dB steps) C0h = 0dB ... (0.375dB steps) EFh = +17.625dB F0h to FFh = +17.625dB Register 24h ADC Digital Volume Left w PP, Rev 3.1, August 2009 127 WM8903 REGISTER ADDRESS R37 (25h) ADC Digital Volume Right Pre-Production BIT LABEL DEFAULT 8 ADCVU 0 7:0 DESCRIPTION ADC Volume Update Writing a 1 to this bit causes left and right ADC volume to be updated simultaneously ADCR_VOL[7:0] 1100_0000 Right ADC Digital Volume 00h = Mute 01h = -71.625dB 02h = -71.250dB ... (0.375dB steps) C0h = 0dB ... (0.375dB steps) EFh = +17.625dB F0h to FFh = +17.625dB Register 25h ADC Digital Volume Right REGISTER ADDRESS R38 (26h) ADC Digital 0 BIT LABEL DEFAULT DESCRIPTION 6:5 ADC_HPF_CUT[1:0] 00 ADC Digital High Pass Filter Cut-Off Frequency (fc) 00 = Hi-fi mode (fc=4Hz at fs=48kHz) 01 = Voice mode 1 (fc=127Hz at fs=16kHz) 10 = Voice mode 2 (fc=130Hz at fs=8kHz) 11 = Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate fs.) 4 ADC_HPF_ENA 0 ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled 1 ADCL_DATINV 0 Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted 0 ADCR_DATINV 0 Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted Register 26h ADC Digital 0 w PP, Rev 3.1, August 2009 128 WM8903 Pre-Production REGISTER ADDRESS R40 (28h) DRC 0 BIT LABEL DEFAULT DESCRIPTION 15 DRC_ENA 0 DRC enable 1 = enabled 0 = disabled 12:11 DRC_THRESH_HYST[1:0] 01 Gain smoothing hysteresis threshold 00 = Low 01 = Medium (recommended) 10 = High 11 = Reserved 10:6 DRC_STARTUP_GAIN[4:0] 0_0110 5 DRC_FF_DELAY 1 Feed-forward delay for anti-clip feature 0 = 5 samples 1 = 9 samples Time delay can be calculated as 5/fs or 9/ fs, where fs is the sample rate. 3 DRC_SMOOTH_ENA 1 Gain smoothing enable 0 = disabled 1 = enabled 2 DRC_QR_ENA 1 Quick release enable 0 = disabled 1 = enabled 1 DRC_ANTICLIP_ENA 1 Anti-clip enable 0 = disabled 1 = enabled 0 DRC_HYST_ENA 1 Gain smoothing hysteresis enable 0 = disabled 1 = enabled Initial gain at DRC startup 00000 = -18dB 00001 = -15dB 00010 = -12dB 00011 = -9dB 00100 = -6dB 00101 = -3dB 00110 = 0dB (default) 00111 = 3dB 01000 = 6dB 01001 = 9dB 01010 = 12dB 01011 = 15dB 01100 = 18dB 01101 = 21dB 01110 = 24dB 01111 = 27dB 10000 = 30dB 10001 = 33dB 10010 = 36dB 10011 to 11111 = Reserved Register 28h DRC 0 w PP, Rev 3.1, August 2009 129 WM8903 REGISTER ADDRESS R41 (29h) DRC 1 Pre-Production BIT LABEL DEFAULT DESCRIPTION 15:12 DRC_ATTACK_RATE[3:0] 0011 Gain attack rate (seconds/6dB) 0000 = instantaneous 0001 = 363us 0010 = 726us 0011 = 1.45ms (default) 0100 = 2.9ms 0101 = 5.8ms 0110 = 11.6ms 0111 = 23.2ms 1000 = 46.4ms 1001 = 92.8ms 1010 = 185.6ms 1011-1111 = Reserved 11:8 DRC_DECAY_RATE[3:0] 0010 Gain decay rate (seconds/6dB) 0000 = 186ms 0001 = 372ms 0010 = 743ms (default) 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = Reserved 7:6 DRC_THRESH_QR[1:0] 01 Quick release crest factor threshold 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 30dB 5:4 DRC_RATE_QR[1:0] 00 Quick release decay rate (seconds/6dB) 00 = 0.725ms (default) 01 = 1.45ms 10 = 5.8ms 11 = Reserved 3:2 DRC_MINGAIN[1:0] 00 Minimum gain the DRC can use to attenuate audio signals 00 = 0dB (default) 01 = -6dB 10 = -12dB 11 = -18dB 1:0 DRC_MAXGAIN[1:0] 01 Maximum gain the DRC can use to boost audio signals 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 36dB Register 29h DRC 1 w PP, Rev 3.1, August 2009 130 WM8903 Pre-Production REGISTER ADDRESS R42 (2Ah) DRC 2 BIT LABEL DEFAULT DESCRIPTION 5:3 DRC_R0_SLOPE_COMP[2:0] 100 Compressor slope R0 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved 2:0 DRC_R1_SLOPE_COMP[2:0] 000 Compressor slope R1 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved Register 2Ah DRC 2 REGISTER ADDRESS R43 (2Bh) DRC 3 BIT LABEL DEFAULT DESCRIPTION 10:5 DRC_THRESH_COMP[5:0] 00_0000 Compressor threshold T (dB) 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB ... (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 4:0 DRC_AMP_COMP[4:0] 0_0000 Compressor amplitude at threshold YT (dB) 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB ... (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved Register 2Bh DRC 3 w PP, Rev 3.1, August 2009 131 WM8903 REGISTER ADDRESS R44 (2Ch) Analogue Left Input 0 Pre-Production BIT LABEL DEFAULT 7 LINMUTE 1 4:0 LIN_VOL[4:0] 0_0101 DESCRIPTION Left Input PGA Mute 0 = not muted 1 = muted Left Input PGA Volume If L_MODE = 00 (Single ended) OR L_MODE = 01 (Differential Line) 00000 -1.5 00001 -1.3 00010 -1.0 00011 -0.7 00100 -0.3 00101 +0.0 (default) 00110 +0.3 00111 +0.7 01000 +1.0 01001 +1.4 01010 +1.8 01011 +2.3 01100 +2.7 01101 +3.2 01110 +3.7 01111 +4.2 10000 +4.8 10001 +5.4 10010 +6.0 10011 +6.7 10100 +7.5 10101 +8.3 10110 +9.2 10111 +10.2 11000 +11.4 11001 +12.7 11010 +14.3 11011 +16.2 11100 +19.2 11101 +22.3 11110 +25.2 11111 +28.3 If L_MODE = 1X (Differential MIC) 00000 Not valid 00001 +12 00010 +15 00011 +18 00100 +21 00101 (default) +24 00110 +27 00111 +30 01XXX +30 1XXXX +30 Register 2Ch Analogue Left Input 0 w PP, Rev 3.1, August 2009 132 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT R45 (2Dh) Analogue Right Input 0 7 RINMUTE 1 4:0 RIN_VOL[4:0] 0_0101 DESCRIPTION Right Input PGA Mute 0 = not muted 1 = muted Right Input PGA Volume If R_MODE = 00 (Single ended) OR R_MODE = 01 (Differential Line) 00000 -1.5 00001 -1.3 00010 -1.0 00011 -0.7 00100 -0.3 00101 +0.0 (default) 00110 +0.3 00111 +0.7 01000 +1.0 01001 +1.4 01010 +1.8 01011 +2.3 01100 +2.7 01101 +3.2 01110 +3.7 01111 +4.2 10000 +4.8 10001 +5.4 10010 +6.0 10011 +6.7 10100 +7.5 10101 +8.3 10110 +9.2 10111 +10.2 11000 +11.4 11001 +12.7 11010 +14.3 11011 +16.2 11100 +19.2 11101 +22.3 11110 +25.2 11111 +28.3 If R_MODE = 1X (Differential MIC) 00000 Not valid 00001 +12 00010 +15 00011 +18 00100 +21 00101 (default) +24 00110 +27 00111 +30 01XXX +30 1XXXX +30 Register 2Dh Analogue Right Input 0 w PP, Rev 3.1, August 2009 133 WM8903 REGISTER ADDRESS R46 (2Eh) Analogue Left Input 1 Pre-Production BIT LABEL DEFAULT DESCRIPTION 6 INL_CM_ENA 1 Left Input PGA Common Mode Rejection enable 0 = Disabled 1 = Enabled (only available for L_MODE=01 - Differential Line) 5:4 L_IP_SEL_N[1:0] 00 Selects input for inverting side of left input path: 00 = IN1L 01 = IN2L 1X = IN3L 3:2 L_IP_SEL_P[1:0] 01 Selects input for non-inverting side of left input path: 00 = IN1L 01 = IN2L 1X = IN3L 1:0 L_MODE[1:0] 00 Sets the mode for the left analogue input: 00 = Single-Ended 01 = Differential Line 10 = Differential MIC 11 = Reserved Register 2Eh Analogue Left Input 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R47 (2Fh) Analogue Right Input 1 6 INR_CM_ENA 1 Right Input PGA Common Mode Rejection enable 0 = Disabled 1 = Enabled (only available for R_MODE=01 - Differential Line) 5:4 R_IP_SEL_N[1:0] 00 Selects input for inverting side of right input path: 00 = IN1R 01 = IN2R 1X = IN3R 3:2 R_IP_SEL_P[1:0] 01 Selects input for non-inverting side of right input path: 00 = IN1R 01 = IN2R 1X = IN3R 1:0 R_MODE[1:0] 00 Sets the mode for the right analogue input: 00 = Single-Ended 01 = Differential Line 10 = Differential MIC 11 = Reserved Register 2Fh Analogue Right Input 1 w PP, Rev 3.1, August 2009 134 WM8903 Pre-Production REGISTER ADDRESS R50 (32h) Analogue Left Mix 0 BIT LABEL DEFAULT DESCRIPTION 3 DACL_TO_MIXOUTL 1 Left DAC to Left Output Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXOUTL 0 Right DAC to Left Output Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MIXOUTL 0 Left Analogue Input to Left Output Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_MIXOUTL 0 Right Analogue Input to Left Output Mixer Enable 0 = disabled 1 = enabled Register 32h Analogue Left Mix 0 REGISTER ADDRESS R51 (33h) Analogue Right Mix 0 BIT LABEL DEFAULT DESCRIPTION 3 DACL_TO_MIXOUTR 0 Left DAC to Right Output Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXOUTR 1 Right DAC to Right Output Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MIXOUTR 0 Left Analogue Input to Right Output Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_MIXOUTR 0 Right Analogue Input to Right Output Mixer Enable 0 = disabled 1 = enabled Register 33h Analogue Right Mix 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R52 (34h) Analogue Spk Mix Left 0 3 DACL_TO_MIXSPKL 0 Left DAC to Left Spkr Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXSPKL 0 Right DAC to Left Spkr Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MIXSPKL 0 Left Analogue Input to Left Spkr Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_MIXSPKL 0 Right Analogue Input to Left Spkr Mixer Enable 0 = disabled 1 = enabled Register 34h Analogue Spk Mix Left 0 w PP, Rev 3.1, August 2009 135 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R53 (35h) Analogue Spk Mix Left 1 3 DACL_MIXSPKL_VOL 0 Left DAC to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB 2 DACR_MIXSPKL_VOL 0 Right DAC to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB 1 BYPASSL_MIXSPKL_VOL 0 Left Analogue Input to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB 0 BYPASSR_MIXSPKL_VOL 0 Right Analogue Input to Left Spkr Mixer volume control 0 = 0dB 1 = -6dB Register 35h Analogue Spk Mix Left 1 REGISTER ADDRESS R54 (36h) Analogue Spk Mix Right 0 BIT LABEL DEFAULT DESCRIPTION 3 DACL_TO_MIXSPKR 0 Left DAC to Right Spkr Mixer Enable 0 = disabled 1 = enabled 2 DACR_TO_MIXSPKR 0 Right DAC to Right Spkr Mixer Enable 0 = disabled 1 = enabled 1 BYPASSL_TO_MIXSPKR 0 Left Analogue Input to Right Spkr Mixer Enable 0 = disabled 1 = enabled 0 BYPASSR_TO_MIXSPKR 0 Right Analogue Input to Right Spkr Mixer Enable 0 = disabled 1 = enabled Register 36h Analogue Spk Mix Right 0 REGISTER ADDRESS R55 (37h) Analogue Spk Mix Right 1 BIT LABEL DEFAULT DESCRIPTION 3 DACL_MIXSPKR_VOL 0 Left DAC to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB 2 DACR_MIXSPKR_VOL 0 Right DAC to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB 1 BYPASSL_MIXSPKR_VOL 0 Left Analogue Input to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB 0 BYPASSR_MIXSPKR_VOL 0 Right Analogue Input to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB Register 37h Analogue Spk Mix Right 1 w PP, Rev 3.1, August 2009 136 WM8903 Pre-Production REGISTER ADDRESS R57 (39h) Analogue OUT1 Left BIT LABEL DEFAULT DESCRIPTION 8 HPL_MUTE 0 Left Headphone Output Mute 0 = Un-mute 1 = Mute 7 HPOUTVU 0 Headphone Output Volume Update Writing a 1 to this bit will update HPOUTL and HPOUTR volumes simultaneously. 6 HPOUTLZC 0 Left Headphone Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 HPOUTL_VOL[5:0] 10_1101 Left Headphone Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Register 39h Analogue OUT1 Left REGISTER ADDRESS R58 (3Ah) Analogue OUT1 Right BIT LABEL DEFAULT DESCRIPTION 8 HPR_MUTE 0 Right Headphone Output Mute 0 = Un-mute 1 = Mute 7 HPOUTVU 0 Headphone Output Volume Update Writing a 1 to this bit will update HPOUTL and HPOUTR volumes simultaneously. 6 HPOUTRZC 0 Right Headphone Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 HPOUTR_VOL[5:0] 10_1101 Right Headphone Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Register 3Ah Analogue OUT1 Right w PP, Rev 3.1, August 2009 137 WM8903 REGISTER ADDRESS R59 (3Bh) Analogue OUT2 Left Pre-Production BIT LABEL DEFAULT DESCRIPTION 8 LINEOUTL_MUTE 0 Left Line Output Mute 0 = Un-mute 1 = Mute 7 LINEOUTVU 0 Line Output Volume Update Writing a 1 to this bit will update LINEOUTL and LINEOUTR volumes simultaneously. 6 LINEOUTLZC 0 Left Line Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 LINEOUTL_VOL[5:0] 11_1001 Left Line Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Register 3Bh Analogue OUT2 Left REGISTER ADDRESS R60 (3Ch) Analogue OUT2 Right BIT LABEL DEFAULT DESCRIPTION 8 LINEOUTR_MUTE 0 Right Line Output Mute 0 = Un-mute 1 = Mute 7 LINEOUTVU 0 Line Output Volume Update Writing a 1 to this bit will update LINEOUTL and LINEOUTR volumes simultaneously. 6 LINEOUTRZC 0 Right Line Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 LINEOUTR_VOL[5:0] 11_1001 Right Line Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Register 3Ch Analogue OUT2 Right w PP, Rev 3.1, August 2009 138 WM8903 Pre-Production REGISTER ADDRESS R62 (3Eh) Analogue OUT3 Left BIT LABEL DEFAULT DESCRIPTION 8 SPKL_MUTE 1 Left Speaker Output Mute 0 = Un-mute 1 = Mute 7 SPKVU 0 Speaker Output Volume Update Writing a 1 to this bit will update LON/LOP and RON/ROP volumes simultaneously. 6 SPKLZC 0 Left Speaker Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 SPKL_VOL[5:0] 11_1001 Left Speaker Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Register 3Eh Analogue OUT3 Left REGISTER ADDRESS R63 (3Fh) Analogue OUT3 Right BIT LABEL DEFAULT DESCRIPTION 8 SPKR_MUTE 1 Right Speaker Output Mute 0 = Un-mute 1 = Mute 7 SPKVU 0 Speaker Output Volume Update Writing a 1 to this bit will update LON/LOP and RON/ROP volumes simultaneously. 6 SPKRZC 0 Right Speaker Output Zero Cross Enable 0 = disabled 1 = enabled 5:0 SPKR_VOL[5:0] 11_1001 Right Speaker Output Volume 000000 = -57dB 000001 = -56dB (... 1dB steps) 111001 = 0dB (... 1dB steps) 111110 = +5dB 111111 = +6dB Register 3Fh Analogue OUT3 Right w PP, Rev 3.1, August 2009 139 WM8903 REGISTER ADDRESS R65 (41h) Analogue SPK Output Control 0 Pre-Production BIT LABEL DEFAULT DESCRIPTION 1 SPK_DISCHARGE 0 Speaker Discharge Enable 0 = Disabled 1 = Enable 0 VROI 0 Select VMID_TIE_ENA resistance for disabled Differential Lineouts 0 = 20k ohm 1 = 500 ohm Register 41h Analogue SPK Output Control 0 REGISTER ADDRESS R67 (43h) DC Servo 0 BIT LABEL DEFAULT 4 DCS_MASTER_ENA 1 3:0 DCS_ENA[3:0] 0000 DESCRIPTION DC Servo Master Control 0 = DC Servo Reset 1 = DC Servo Enabled DC Servo Enable [3] - HPOUTL enable [2] - HPOUTR enable [1] - LINEOUTL enable [0] - LINEOUTR enable Register 43h DC Servo 0 REGISTER ADDRESS R69 (45h) DC Servo 2 BIT LABEL DEFAULT 1:0 DCS_MODE[1:0] 00 DESCRIPTION DC Servo Mode 00 = WRITE_STOP 01 = WRITE_UPDATE 10 = START_STOP 11 = START_UPDATE Register 45h DC Servo 2 REGISTER ADDRESS BIT LABEL R71 (47h) DC Servo 4 7:0 DCS_HPOUTL_WRITE_VA L [7:0] DEFAULT DESCRIPTION 0000_0000 Value to send to Left Headphone Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 47h DC Servo 4 REGISTER ADDRESS BIT LABEL R72 (48h) DC Servo 5 7:0 DCS_HPOUTR_WRITE_VA L [7:0] DEFAULT DESCRIPTION 0000_0000 Value to send to Right Headphone Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 48h DC Servo 5 w PP, Rev 3.1, August 2009 140 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL R73 (49h) DC Servo 6 7:0 DCS_LOUTL_WRITE_VA L [7:0] DEFAULT DESCRIPTION 0000_0000 Value to send to Left Line Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 49h DC Servo 6 REGISTER ADDRESS BIT LABEL R74 (4Ah) DC Servo 7 7:0 DCS_LOUTR_WRITE_VA L [7:0] DEFAULT DESCRIPTION 0000_0000 Value to send to Right Line Output Servo in a WRITE mode Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 4Ah DC Servo 7 REGISTER ADDRESS BIT R81 (51h) DC Servo Readback 1 7:0 LABEL DEFAULT DESCRIPTION DCS_HPOUTL_INTEG [7:0] 0000_0000 Readback value on Left Headphone Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 51h DC Servo Readback 1 REGISTER ADDRESS BIT R82 (52h) DC Servo Readback 2 7:0 LABEL DEFAULT DESCRIPTION DCS_HPOUTR_INTEG [7:0] 0000_0000 Readback value on Right Headphone Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 52h DC Servo Readback 2 REGISTER ADDRESS BIT R83 (53h) DC Servo Readback 3 7:0 LABEL DCS_LOUTL_INTEG [7:0] DEFAULT DESCRIPTION 0000_0000 Readback value on Left Line Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 53h DC Servo Readback 3 w PP, Rev 3.1, August 2009 141 WM8903 Pre-Production REGISTER ADDRESS BIT R84 (54h) DC Servo Readback 4 7:0 LABEL DEFAULT DCS_LOUTR_INTEG [7:0] DESCRIPTION 0000_0000 Readback value on Right Line Output Servo. Two's complement format. LSB is 0.25mV. Range is +/-32mV Register 54h DC Servo Readback 4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R90 (5Ah) Analogue HP 0 7 HPL_RMV_SHORT 0 Left channel output short removal: set after output stage has been enabled 6 HPL_ENA_OUTP 0 Enables left channel output stage; set after offset cancellation is done 5 HPL_ENA_DLY 0 delayed left channel enable, set with at least 20us delay to HPL_ENA; reset together with HPL_ENA 4 HPL_ENA 0 enables left headphone ampl. channel 3 HPR_RMV_SHORT 0 right channel output short removal: set after output stage has been enabled 2 HPR_ENA_OUTP 0 enables right channel output stage; set after offset cancellation is done 1 HPR_ENA_DLY 0 delayed right channel enable, set with at least 20us delay to HPR_ENA; reset together with HPR_ENA 0 HPR_ENA 0 enables right headphone ampl. channel Register 5Ah Analogue HP 0 REGISTER ADDRESS R94 (5Eh) Analogue Lineout 0 BIT LABEL DEFAULT DESCRIPTION 7 LINEOUTL_RMV_SHORT 0 left channel output short removal: set after output stage has been enabled 6 LINEOUTL_ENA_OUTP 0 enables left channel output stage; set after offset cancellation is done 5 LINEOUTL_ENA_DLY 0 delayed left channel enable, set with at least 20us delay to LINEOUTL_ENA; reset together with LINEOUTL_ENA 4 LINEOUTL_ENA 0 enables left lineout ampl. channel 3 LINEOUTR_RMV_SHORT 0 right channel output short removal: set after output stage has been enabled 2 LINEOUTR_ENA_OUTP 0 enables right channel output stage; set after offset cancellation is done 1 LINEOUTR_ENA_DLY 0 delayed right channel enable, set with at least 20us delay to LINEOUTR_ENA; reset together with LINEOUTR_ENA 0 LINEOUTR_ENA 0 enables right lineout ampl. channel Register 5Eh Analogue Lineout 0 w PP, Rev 3.1, August 2009 142 WM8903 Pre-Production REGISTER ADDRESS R98 (62h) Charge Pump 0 BIT LABEL DEFAULT 0 CP_ENA 0 DESCRIPTION Enable charge-pump digits 0 = disable 1 = enable Register 62h Charge Pump 0 REGISTER ADDRESS R104 (68h) Class W 0 BIT LABEL DEFAULT 0 CP_DYN_PWR 0 DESCRIPTION Enable dynamic charge pump power control 0 = charge pump controlled by volume register settings 1 = charge pump controlled by real-time audio level Register 68h Class W 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R108 (6Ch) Write Sequencer 0 8 WSMD_CLK_ENA 0 Write Sequencer / Mic Detect Clock Enable. 0 = Disabled 1 = Enabled Previously called WSEQ_ENA. 4:0 WSEQ_WRITE_INDEX[4:0] 0_0000 Sequence Write Index. This is the memory location to which any updates to R109 and R110 will be copied. 0 to 31 = RAM addresses Register 6Ch Write Sequencer 0 REGISTER ADDRESS R109 (6Dh) Write Sequencer 1 BIT LABEL DEFAULT DESCRIPTION 14:12 WSEQ_DATA_WIDTH[2:0] 000 Width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 11:8 WSEQ_DATA_START[3:0] 0000 Bit position of the LSB of the data block written in this sequence step. 0000 = Bit 0 ... 1111 = Bit 15 7:0 WSEQ_ADDR[7:0] 0000_0000 Control Register Address to be written to in this sequence step. Register 6Dh Write Sequencer 1 w PP, Rev 3.1, August 2009 143 WM8903 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R110 (6Eh) Write Sequencer 2 14 WSEQ_EOS 0 End of Sequence flag. This bit indicates whether the Control Write Sequencer should stop after executing this step. 0 = Not end of sequence 1 = End of sequence (Stop the sequencer after this step). 11:8 WSEQ_DELAY[3:0] 0000 7:0 WSEQ_DATA[7:0] Time delay after executing this step. Total delay time per step (including execution)= 62.5s x (2^WSEQ_DELAY + 8) 0000_0000 Data to be written in this sequence step. When the data width is less than 8 bits, then one or more of the MSBs of WSEQ_DATA are ignored. It is recommended that unused bits be set to 0. Register 6Eh Write Sequencer 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R111 (6Fh) Write Sequencer 3 9 WSEQ_ABORT 0 Writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface. 8 WSEQ_START 0 Writing a 1 to this bit starts the write sequencer at the memory location indicated by the WSEQ_START_INDEX field. The sequence continues until it reaches an "End of sequence" flag. At the end of the sequence, this bit will be reset by the Write Sequencer. 5:0 WSEQ_START_INDEX[5:0] 00_0000 Sequence Start Index. This is the memory location of the first command in the selected sequence. 0 to 31 = RAM addresses 32 to 48 = ROM addresses 49 to 63 = Reserved Register 6Fh Write Sequencer 3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R112 (70h) Write Sequencer 4 9:4 WSEQ_CURRENT_INDEX[5:0] 00_0000 Sequence Current Index. This is the location of the most recently accessed command in the write sequencer memory. 0 WSEQ_BUSY 0 Sequencer Busy flag (Read Only). 0 = Sequencer idle 1 = Sequencer busy Note: it is not possible to write to control registers via the control interface while the Sequencer is Busy. Register 70h Write Sequencer 4 w PP, Rev 3.1, August 2009 144 WM8903 Pre-Production REGISTER ADDRESS R116 (74h) GPIO Control 1 BIT LABEL DEFAULT DESCRIPTION 13:8 GP1_FN[5:0] 00_0000 7 GP1_DIR 1 GPIO Pin Direction 0 = Output 1 = Input 6 GP1_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP1_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP1_LVL 0 GPIO Output Level (when GP1_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP1_PD 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP1_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP1_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP1_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced GPIO 1 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h = DMIC_LR Clock output 07h to 3Fh = Reserved Register 74h GPIO Control 1 w PP, Rev 3.1, August 2009 145 WM8903 REGISTER ADDRESS R117 (75h) GPIO Control 2 Pre-Production BIT LABEL DEFAULT DESCRIPTION 13:8 GP2_FN[5:0] 00_0000 7 GP2_DIR 1 GPIO Pin Direction 0 = Output 1 = Input 6 GP2_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP2_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP2_LVL 0 GPIO Output Level (when GP2_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP2_PD 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP2_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP2_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP2_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced GPIO 2 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h = DMIC_DAT Data input 07h to 3Fh = Reserved Register 75h GPIO Control 2 w PP, Rev 3.1, August 2009 146 WM8903 Pre-Production REGISTER ADDRESS R118 (76h) GPIO Control 3 BIT LABEL DEFAULT DESCRIPTION 13:8 GP3_FN[5:0] 00_0000 7 GP3_DIR 1 GPIO Pin Direction 0 = Output 1 = Input 6 GP3_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP3_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP3_LVL 0 GPIO Output Level (when GP3_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP3_PD 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP3_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP3_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP3_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced GPIO 3 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h - 3Fh = Reserved Register 76h GPIO Control 3 w PP, Rev 3.1, August 2009 147 WM8903 REGISTER ADDRESS R119 (77h) GPIO Control 4 Pre-Production BIT LABEL DEFAULT DESCRIPTION 13:8 GP4_FN[5:0] 00_0010 7 GP4_DIR 0 GPIO Pin Direction 0 = Output 1 = Input 6 GP4_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP4_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP4_LVL 0 GPIO Output Level (when GP4_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP4_PD 0 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP4_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP4_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP4_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced GPIO 4 Pin Function select 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h - 3Fh = Reserved Register 77h GPIO Control 4 w PP, Rev 3.1, August 2009 148 WM8903 Pre-Production REGISTER ADDRESS R120 (78h) GPIO Control 5 BIT LABEL DEFAULT DESCRIPTION 13:8 GP5_FN[5:0] 00_0001 7 GP5_DIR 1 GPIO Pin Direction 0 = Output 1 = Input 6 GP5_OP_CFG 0 Output pin configuration 0 = CMOS 1 = Open-drain 5 GP5_IP_CFG 1 Input pin configuration 0 = Active low 1 = Active high 4 GP5_LVL 0 GPIO Output Level (when GP5_FN = 00000) 0 = Logic 0 1 = Logic 1 3 GP5_PD 0 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100k) 2 GP5_PU 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100k) 1 GP5_INTMODE 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GP5_DB 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced GPIO 5 Pin Function select 00h = GPIO output 01h = BCLK 02h = IRQ output 03h = GPIO input 04h = MICBIAS Current detect 05h = MICBIAS Short Circuit detect 06h - 3Fh = Reserved Register 78h GPIO Control 5 w PP, Rev 3.1, August 2009 149 WM8903 REGISTER ADDRESS R121 (79h) Interrupt Status 1 Pre-Production BIT LABEL DEFAULT DESCRIPTION 15 MICSHRT_EINT 0 MICBIAS Short Circuit detect IRQ status 0 = Short Circuit current IRQ not set 1 = Short Circuit current IRQ set 14 MICDET_EINT 0 MICBIAS Current detect IRQ status 0 = Current detect IRQ not set 1 = Current detect IRQ set 13 WSEQ_BUSY_EINT 0 Write Sequencer Busy IRQ status 0 = WSEQ IRQ not set 1 = WSEQ IRQ set The Write Sequencer asserts this flag when it has completed a programmed sequence - ie it indicates that the Write Sequencer is NOT Busy. 4 GP5_EINT 0 GPIO5 IRQ status 0 = GPIO5 IRQ not set 1 = GPIO5 IRQ set 3 GP4_EINT 0 GPIO4 IRQ status 0 = GPIO4 IRQ not set 1 = GPIO4 IRQ set 2 GP3_EINT 0 GPIO3/ADDR IRQ status 0 = GPIO3 IRQ not set 1 = GPIO3 IRQ set 1 GP2_EINT 0 GPIO2/DMIC_DAT IRQ status 0 = GPIO2 IRQ not set 1 = GPIO2 IRQ set 0 GP1_EINT 0 GPIO1/DMIC_LR IRQ status 0 = GPIO1 IRQ not set 1 = GPIO1 IRQ set Register 79h Interrupt Status 1 w PP, Rev 3.1, August 2009 150 WM8903 Pre-Production REGISTER ADDRESS R122 (7Ah) Interrupt Status 1 Mask BIT LABEL DEFAULT DESCRIPTION 15 IM_MICSHRT_EINT 1 Interrupt mask for MIC Short Circuit Detect 0 = Not masked 1 = Masked 14 IM_MICDET_EINT 1 Interrupt mask for MIC Current Detect 0 = Not masked 1 = Masked 13 IM_WSEQ_BUSY_EINT 1 Interrupt mask for WSEQ Busy indication 0 = Not masked 1 = Masked 4 IM_GP5_EINT 1 Interrupt mask for GPIO5 0 = Not masked 1 = Masked 3 IM_GP4_EINT 1 Interrupt mask for GPIO4 0 = Not masked 1 = Masked 2 IM_GP3_EINT 1 Interrupt mask for GPIO3/ADDR 0 = Not masked 1 = Masked 1 IM_GP2_EINT 1 Interrupt mask for GPIO2/DMIC_DAT 0 = Not masked 1 = Masked 0 IM_GP1_EINT 1 Interrupt mask for GPIO1/DMIC_LR 0 = Not masked 1 = Masked Register 7Ah Interrupt Status 1 Mask REGISTER ADDRESS R123 (7Bh) Interrupt Polarity 1 BIT LABEL DEFAULT DESCRIPTION 15 MICSHRT_INV 0 MICBIAS Short Circuit detect polarity 0 = Detect current increase above threshold 1 = Detect current decrease below threshold 14 MICDET_INV 0 MICBIAS Current Detect polarity 0 = Detect current increase above threshold 1 = Detect current decrease below threshold Register 7Bh Interrupt Polarity 1 REGISTER ADDRESS R126 (7Eh) Interrupt Control BIT LABEL DEFAULT 0 IRQ_POL 0 DESCRIPTION Interrupt Output polarity 0 = Active high 1 = Active low Register 7Eh Interrupt Control w PP, Rev 3.1, August 2009 151 WM8903 REGISTER ADDRESS R164 (A4h) Clock Rate Test 4 Pre-Production BIT LABEL DEFAULT 9 ADC_DIG_MIC 0 DESCRIPTION Enables Digital Microphone mode. 0 = Audio DSP input is from ADC 1 = Audio DSP input is from digital microphone interface Register A4h Clock Rate Test 4 REGISTER ADDRESS BIT LABEL R172 (ACh) Analogue Output Bias 0 6:4 PGA_BIAS [2:0] DEFAULT 000 DESCRIPTION Headphone and Lineout PGA bias control 000 = Normal bias 001 = Normal bias x 1.5 010 = Normal bias x 0.75 011 = Normal bias x 0.5 100 = Normal bias x 0.33 101 = Normal bias 110 = Normal bias 111 = Normal bias x 2 Register ACh Analogue Output Bias 0 REGISTER ADDRESS R187 (BBh) Analogue Output Bias 2 BIT 2:0 LABEL OUTPUTS_BIA S [2:0] DEFAULT 000 DESCRIPTION Headphone and Lineout Output Drivers bias control 000 = Normal bias 001 = Normal bias x 1.5 010 = Normal bias x 0.75 011 = Normal bias x 0.5 100 = Normal bias x 0.33 101 = Normal bias 110 = Normal bias 111 = Normal bias x 2 Register BBh Analogue Output Bias 2 w PP, Rev 3.1, August 2009 152 WM8903 Pre-Production APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Design notes (1) Capacitor Type Decouplers: For C3, C4, C8, C9, a single 4.7uF X5R ceramic can be used. Charge pump capacitor types are critical. Capacitors must meet DC co-efficient requirement. See datasheet text. AC coupling capacitors: C6, C7, C10, C11, C12 and C13 are recommended to be Tantalum with low ESR. (2) Capacitor positioning Decouplers and charge pump capacitors should be positioned as close to WM8903 as possible. C8, C9, C16 are the most important. C1, C2, C3, C4, C17, C18 should also be very close to WM8903. (3) Zobel Network All Zobel networks are a requirement if either HPOUT or LINEOUT is used. See datasheet text. Zobel Network should be positioned reasonably close to WM8903 (4) R3 and R4 R3 and R4 can be populated with other values to remove common mode noise on the microphone Figure 64 Recommended External Components As well as selection of correct capacitor values, together with careful PCB layout, it is important to select the correct capacitor type for the charge pump. Capacitors generally reduce in value as the DC bias voltage across the capacitor is increased, this is known as the voltage coefficient of the capacitor. Verifying that the required capacitance can be met at the specified DC voltage depends on the capacitor design, so the individual capacitor datasheet must be consulted. The requirements of each capacitor, and some example capacitor parts are detailed in Table 77, and also discussed in the application note "WAN0214: External Component Requirements for Ground Referenced Outputs". Audio performance may be impacted if the capacitor does not meet the capacitance requirements at a given DC voltage. w PP, Rev 3.1, August 2009 153 WM8903 CAPACITOR Pre-Production REQUIRED CAPACITANCE VALUE RATED VOLTAGE EXAMPLE OF CURRENT CAPACITOR TECHNOLOGY DIELECTRIC CASE SIZE (EIA) MANUFACTURER P/N CFB1-CFB2 1F at 2vDC 2.2F 6.3v X5R 0402 Kemet C0402C225M9PAC MuRata GRM155R60J225ME15_EIA VPOS, VNEG CPVDD 2F at 2vDC (1) 2.2F 10v X5R 0603 MuRata GRM188R61A225KE34D (2) 4.7F 6.3v X5R 0402 MuRata GRM155R60J475M_EIA Table 77 Capacitor Examples The zobel network (C19,20,21,22, R9,10,11,12 in Figure 64) is required on HPOUTL/R and LINEOUTL/R if the output is being used. Stability of either set of outputs across all process corners cannot be guaranteed without the zobel network. If any Ground-referenced output pin is not required, the zobel network components can be omitted from that output pin, and the pin can be left floating. The zobel network requirement is detailed further in the applications note WAN_0212 "Class W Headphone Impedance Compensation". MIC DETECTION SEQUENCE USING MICBIAS CURRENT This section details an example sequence which summarises how the host processor can configure and detect the events supported by the MICBIAS current detect function (see "Electret Condenser Microphone Interface"): * Mic insertion/removal * Hook switch press/release Figure 65 shows an example of how the MICBIAS current flow varies versus time, during mic insertion and hook switch events. The Y axis is annotated with the Mic detection thresholds, and the X axis is annotated with the stages of an example sequence as detailed in Table 78, to illustrate how the host processor can implement mic insertion and hook switch detection. The sequence assumes that the polling of the control interface, by checking the interrupt flags, has been used to monitor changes in the microphone insertion or hook switch detection functions, rather than connection of a WM8903 GPIO. This means that the maximum possible mechanical bounce times for mic insertion and removal must be understood by the software programmer. At every step in the following process, the host processor should poll the interrupt status register. w PP, Rev 3.1, August 2009 154 Pre-Production WM8903 Figure 65 Mic Insert and Hook Switch Detect: Example MICBIAS Current Plot w PP, Rev 3.1, August 2009 155 WM8903 STEP Pre-Production DETAILS 1 Mic not inserted. To detect mic insertion, Host processor must initialise interrupts and clear MICDET_INV = 0. At every step, the host processor should poll the interrupt status register. 2 Mechanical bounce of jack socket during Mic insertion. Host processor may already detect a mic insertion interrupt during this step. Once detected, the host processor can set MICDET_INV = 1, unless mechanical bounce can last longer than the shortest possible TDET, in which case the host processor should not set MICDET_INV = 1 until step 3. 3 Mic fully inserted. If not already cleared, Host processor must now set MICDET_INV = 1. To detect Hook switch press, Host processor must clear MICSHRT_INV = 0. At this step, the diagram shows no AC current swing, due to a very low ambient noise level. 4 Mic fully inserted. Diagram shows AC current swing due to high levels of background noise (such as wind). 5 Mechanical bounce during hook switch press. The hook switch interrupt is unlikely to be set during this step, because 10 successive samples of the MICBIAS current exceeding the hook switch threshold have not yet been sampled. 6 Hook switch is fully pressed down. After TSHORT, 10 successive samples of the MICBIAS current exceeding the hook switch threshold have been detected, hence a hook switch interrupt will be generated, and the host processor can immediately set MICSHRT_INV = 1. 7 Mechanical bounce during hook switch release. The hook switch interrupt is unlikely to be set during this step, because 10 successive samples of the MICBIAS current lower than the hook switch threshold have not yet been sampled. 8 Hook switch fully released. After TSHORT, 10 successive samples of the MICBIAS current lower than the hook switch threshold have been detected, hence a hook switch interrupt will be generated, and the host processor can immediately clear MICSHRT_INV = 0. 9 Mechanical bounce of jack socket during Mic removal. Host processor may already detect a mic removal interrupt during this step. Once detected, the host processor can clear MICDET_INV = 0, unless mechanical bounce can last longer than the shortest possible TDET, in which case the host processor should not clear MICDET_INV = 0 until step 10. 10 Mic fully removed. If not already set, Host processor must now clear MICDET_INV = 0. Table 78 Mic Insert and Hook Switch Detect: Example Sequence Alternatively, utilising a GPIO pin to monitor the MICBIAS current detect functionality permits the host processor to monitor the steady state of microphone detection or hook switch press functions. Because the GPIO shows the steady state condition, software de-bounce may be easier to implement in the host processor, dependant on the processor performance characteristics, hence use of the GPIO is likely to simplify the rejection of mechanical bounce. Changes of state in the GPIO pin are also subject to the time delays tDET and tSHORT. Further details can be found in the applications note WAN_0213 "WM8903 ECM mic detection using MICBIAS current". w PP, Rev 3.1, August 2009 156 WM8903 Pre-Production PACKAGE DIMENSIONS FL: 40 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.55 mm BODY, 0.40 mm LEAD PITCH TOP VIEW SEE DETAIL A D2 B D2/2 31 DM051.A D 39 40 INDEX AREA (D/2 X E/2) L 1 30 2 EXPOSED 6 GND PADDLE E2/2 A A 10 21 E SEE DETAIL B 2X 11 18 17 B e E2 b aaa C ccc M C A B aaa C 2X DETAIL A ccc C A1 SEATING PLANE PIN #1 IDENTIFICATION CHAMFER R0.300 X 45o 40x b bbb M C A B 0.08 C e EXPOSED GND PADDLE R DATUM DETAIL B 1 e/2 TERMINAL TIP C 1 A L (A3) 1 R 1 Symbols A A1 A3 b D D2 E E2 e L aaa bbb ccc REF: Dimensions (mm) NOM MAX 0.55 0.60 0.02 0.05 0.203 REF 0.15 0.20 0.25 5.00 BSC 3.55 3.6 3.65 5.00 BSC 3.55 3.6 3.65 0.4 BSC 0.35 0.4 0.45 Tolerances of Form and Position MIN 0.50 0 NOTE 1 2 2 0.15 0.10 0.10 JEDEC, MO-220 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220. 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION. w PP, Rev 3.1, August 2009 157 WM8903 Pre-Production IMPORTANT NOTICE Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. 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Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PP, Rev 3.1, August 2009 158