CY14B101Q1-LHXI - Cypress Semiconductor Corp.

1 Mbit (128K x 8) Serial SPI nvSRAM

CY14B101Q1

CY14B101Q2

CY14B101Q3

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 001-50091 Rev. *D Revised January 04, 2010

Features

■

1 Mbit Nonvolatile SRAM

❐

Internally organized as 128K x 8

❐

STORE to QuantumTrap Nonvolatile Elements initiated au-

tomatically on Power Down (AutoStore) or by user using HSB

Pin (Hardware Store) or SPI instruction (Software Store )

❐

RECALL to SRAM initiate d on Power Up (Powe r Up Recall)

or by SPI Instruction (Software RECALL)

❐

Automatic STORE on Power Down with a small Capacitor

■

High Reliability

❐

Infinite Read, Write, and RECALL Cycles

❐

1 Million STORE cycles to QuantumTrap

❐

Data Retention: 20 Years

■

High Speed Serial Peripheral Interface (SPI)

❐

40 MHz Clock Rate

❐

Supports SPI Modes 0 (0,0) and 3 (1,1)

■

Write Protection

❐

Hardware Protection using Write Protect (WP) Pin

❐

Software Protection using Write Disable Instruction

❐

Software Block Protection for 1/4,1/2, or entire Array

■

Low Power Consumption

❐

Single 3V +20%, –10% Operation

❐

Average V

current of 10 mA at 40 MHz Operation

■

Industry Standard Configurations

❐

Industrial Temperature

❐

CY14B101Q1 has identical pin configuration to industry stan-

dard 8-pin NV Memory

❐

8-pin DFN and 16-pin SOIC Packages

❐

RoHS Compliant

Functional Overview

The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3

combines a 1 Mbit nonvolatile static RAM with a nonvolatile

element in each memory cell. The memory is organized as 128K

words of 8 bits each. The embedded nonvolatile elements incor-

porate the QuantumTrap technology, creating the world’s most

reliable nonvolatile memory. The SRAM provides infinite read

and write cycles, while the QuantumTrap cell provides highly

reliable nonvolatile storage of data. Data transfers from SRAM to

the nonvolatile elements (STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM from the nonvolatile memory (RECALL operation).

Both STORE and RECALL operati ons can also be triggered by

the user.

Configuration

Feature CY14B101Q1 CY14B101Q2 CY14B101Q3

AutoStore No Yes Yes

Software

STORE Yes Yes Yes

Hardware

STORE No No Yes

Instruction

Address

Decoder

Data I/O register

Status register

Power Control

STORE/RECALL

Control

Instruction decode

Write protect

Control logic

Quantum Trap

STORE

RECALL

SCK

VCC VCAP

HSB

128K X 8

SRAM ARRAY

128K X 8

A0-A16

D0-D7

HOLD

Logic Block Diagram

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 2 of 24

Contents

Features ............................................................................... 1

Functional Overview ................... ................. ......................1

Configuration ......................................................................1

Logic Block Diagram ................ ............................ ..............1

Contents ..............................................................................2

Pinouts ................................................................................3

Device Operation ................................................................4

SRAM Write ...................................................................4

SRAM Read ..................................................................4

STORE Operation .........................................................4

AutoStore Operation ......................................................5

Software Store Operation ..............................................5

Hardware STORE and HSB pin Operation ...................5

RECALL Operation ........................................................5

Hardware Recall (Power Up) .........................................5

Software RECALL .........................................................5

Disabling and Enabling AutoStore .................................6

Serial Peripheral Interface .................................................6

SPI Overview ............ ... ............................ ......................6

SPI Modes ............. ... ............................ .........................7

SPI Operating Features ......................................................8

Power Up ............ ... ............................ ............................8

Power On Reset ..................... ... ............................ ........8

Power Down ...................... .. ............................ ..............8

Active Power and Standby Power Modes .....................8

SPI Functional Description ................................................8

Status Register ...................................................................9

Read Status Register (RDSR) Instruction .....................9

Write Status Register (WRSR) Instruction ....................9

Write Protection and Block Protection ...........................10

Write Enable (WREN) Instruction ................................10

Write Disable (WRDI) Instruction ................................10

Block Protection ........... ............................ ...................10

Write Protect (WP) Pin ................................................11

Memory Access ................................................................11

Read Sequence (READ) .............................................11

Write Sequence (WRITE) ............................................11

Software STORE ..................... ....................................12

Software RECALL ..... ............................. .....................13

AutoStore Disable (ASDISB) .......................................13

AutoStore Enable (ASENB) .........................................13

HOLD Pin Operation ....... ............................ ................13

Maximum Ratings .............................................................14

DC Electrical Characteristics ............ ... ...........................14

Data Retention and Endurance .......................................15

Capacitance ......................................................................15

Thermal Resistance ..........................................................15

AC Test Conditions ..........................................................15

AC Switching Characteristics .........................................16

AutoStore or Power Up RECALL ....................................17

Software Controlled STORE an d RECALL Cycles ........18

Hardware STORE Cycle ...................................................19

Part Numbering Nomenclature ....... ............................ .....20

Ordering Information ........................................................20

Package Diagrams ............................................................21

Document History Page ..................................................23

Sales, Solutions, and Legal Information ........................24

Worldwide Sales and Design Support .........................24

Products ......................................................................24

PSoC Solutions ..........................................................24

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 3 of 24

Pinouts

Figure 1. Pin Diagram - 8-Pin DFN

[1, 3, 2]

Figure 2. Pin Diagram - 16-Pin SOIC

Table 1. Pin Definitions

Pin Name I/O Type Description

CS Input Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low

power standby mode.

SCK Input Serial Clock. Runs at speeds up to maximum 40 MHz. All inputs are latched at the rising edge of

this clock. Outputs are driven at the falling edge of the clock.

SI Input Serial Input. Pin for input of all SPI instructions and data.

SO Output Serial Output. Pin for output of data through SPI.

WP Input Write Protect. Implements hardware write protection in SPI.

HOLD Input HOLD Pin. Suspends Serial Operation.

HSB Input/Output Hardware STORE Busy: A weak internal pull up keeps this pin pulled high. If not used, this pin is

left as No Connect.

Output: Indicates busy status of nvSRAM when LOW.

Input: Hardware STORE implemented by pulling this pin LOW ex ternally.

CAP

Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the

SRAM to nonvolatile elements. If AutoS tore is not needed, this pin must be left as No Connect. It

must never be connected to GND.

NC No Connect No Connect: This pin is not connected to the die.

GND Power Supply Ground

Power Supply Power Supply (2.7V to 3.6V)

CY14B101Q1

Top Vi ew

not to scale

GND

VCC

HOLD

SCK

CY14B101Q2

Top Vi ew

not to scale

VCAP

GND

VCC

HOLD

SCK

GND

CAP

NC 16

SCK

HSB

HOLD

CY14B101Q3

Top Vi e w

not to scale

Notes

1. HSB pin is not avai l a b le in 8 DF N packages.

2. CY14B101Q1 part does not have V

CAP

pin and does not support AutoStore.

3. CY14B101Q2 part does not have WP pin

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 4 of 24

Device Operation

CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM

memory with a nonvolatile element in each memory cell. All the

reads and writes to nvSRAM happen to th e SRAM which gives

nvSRAM the unique capability to handle infinite writes to the

memory. The data in SRAM is secured by a STORE sequence

which transfers the data in parallel to the nonvolatile Quantum

Trap cells. A small capacitor (V

CAP

) is used to AutoStore the

SRAM data in nonvolatile cells when power goes down providing

power down data security. The Quantum Trap nonvolatile

elements built in the reliable SONOS technology make nvSRAM

the ideal choice for secure data storage.

The 1 Mbit memory array is organized as 128K words x 8 bits.

The memory can be accessed through a standard SPI interface

that enables very high clock speeds upto 40 MHz with zero cycle

delay read and write cycles. This device supp orts SPI modes 0

and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.

The device is enabled using the Chip Select pin (CS) and

accessed through Serial Input (SI), Serial Output (SO), and

Serial Clock (SCK) pins.

This device provides the feature for hardware and software write

protection through WP pin and WRDI instruction respectively

along with mechanisms for block write protection (1/4, 1/2, or full

array) using BP0 and BP1 pins in the status register . Further , the

HOLD pin can be used to suspend any serial communication

without resetting the serial sequence.

CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard

SPI opcodes for memory access. In addi tion to the general SPI

instructions for read and write, it provides four special

instructions which enable access to four nvSRAM specific

functions: STORE, RECALL, AutoStore Disable (ASDISB), and

AutoStore Enable (ASENB).

The major benefit of nvSRAM SPI over serial EEPROMs is that

all reads and writes to n vSRAM are performed at the spe ed of

SPI bus with zero delay . Therefore, no wait time is required after

any of the memory accesses. The STORE and RECALL

operations need finite time to complete and all memory accesses

are inhibited during this time. While a STORE or RECALL

operation is in progress, the busy status of the device is indicated

by the Hardware STORE Busy (HSB) pin and also reflected on

the RDY bit of the Status Register .

The Device is availabl e in three different pin configurations th at

enable the user to choose a part which fits in best in their appli-

cation

The feature summary is given in Table 2.

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not

use up any endurance cycles of the nonvolatile memory. This

enables user to perform infinite write operations. A Write cycle is

performed through the SPI WRITE instruction. The WRITE

instruction is issued through the SI pin of the nvSRAM and

consists of the WRITE opcode, three bytes of address, and one

byte of data. Write to nvSRAM is done at SPI bus speed with zero

cycle delay.

The device allows burst mode writes to be performed through

SPI. This enables write operations on consecutive addresses

without issuing a new WRITE instruction. When the last address

in memory is reached, the address rolls over to 0x0000 and the

device continues to write.

The SPI write cycle sequence is defined expli citly in the M emory

Access section of SPI Protocol Description.

SRAM Read

A read cycle is performed at the SPI bu s speed and the data is

read out with zero cycle delay after the READ instruction is

performed. The READ instruction is issued through the SI pin of

the nvSRAM and consists of the READ o pcode and 3 bytes of

address. The data is read out on the SO pin.

This device allows burst mode reads to be performed through

SPI. This enables reads on consecutive addresses without

issuing a new READ instruction. When the last address in

memory is reached in burst mode read, the address rolls over to

0x0000 and the device continues to read.

The SPI read cycle sequence is defined explicitly in the Memory

Access section of SPI Protocol Description.

STORE Operation

STORE operation transfers the data from the SRAM to the

nonvolatile Quantum Trap cells. The device stores data to the

nonvolatile cells using one of three STORE operations:

AutoStore, activated o n device power down; Software STORE,

activated by a STORE instruction in the SPI; Hardware STORE,

activated by the HSB. During the STORE cycle, an erase of the

previous nonvolatile data is first performed, followed by a

program of the nonvolatile elements. After a STORE cycle is

initiated, further input and output are disabled until the cycle is

completed.

The HSB signal or the RDY bit in the Status register can be

monitored by the system to detect if a STORE cycle is in

progress. The busy status of nvSRAM is indicated by HSB being

pulled LOW or RDY bit being set to ‘1’. To avoid unnecessary

nonvolatile STOREs, AutoStore and Hardware STORE opera-

tions are ignored unless at least one write operation has taken

place since the most recent STORE or RECALL cycle. Software

initiated STORE cycles are performed regardless of whether a

write operation has taken place.

Table 2. Feature Summary

Feature CY14B101Q1 CY14B101Q2 CY14B101Q3

WP Yes No Yes

CAP

No Yes Yes

HSB No No Yes

AutoStore No Yes Yes

Power Up

RECALL Yes Yes Yes

Hardware

STORE No No Yes

Software

STORE Yes Yes Yes

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 5 of 24

AutoStore Operation

The AutoSt ore operation is a unique featu re of nvSRAM which

automatically stores the SRAM data to QuantumTrap during

power down. This Store mechanism is implemented using a

capacitor (V

CAP

) and enables the device to safely STORE the

data in the nonvolatile memory when power goes down.

During normal ope ration, the device draws current from V

charge the capacitor connected to the V

CAP

pin. When the

voltage on the V

pin drops below V

SWITCH

during power down,

the device inhibits all memory accesses to nvSRAM and

automatically performs a conditional STORE operation using the

charge from the V

CAP

capacitor. The AutoStore operation is not

initiated if no write cycle has been performed since last RECALL.

Note If a capacitor is not connected to V

CAP

pin, Autostore must

be disabled by issuing the AutoStore Disable instruction

specified in AutoStore Disable (ASDISB) on page 13. If

AutoS tore is enabled without a capacitor on V

CAP

pin, the device

attempts an AutoStore operation without sufficient charge to

complete the S tore. This may corrupt the data stored in nvSRAM

and S tatus register . In such case, WRSR instruction needs to be

issued to update the nonvolatile bits BP0, BP1, WPEN to resume

normal functi onality.

During power down, the memory accesses are inhibited after the

voltage on V

pin drops below V

SWITCH

. To avoid inadvertent

writes, it must be ensured that CS is not left floating prior to this

event. Therefore, during power down the device must be

deselected and CS must be allowed to follow V

Figure 3 shows the proper connection of the storage capacitor

CAP

) for AutoStore operation. Refer to DC Electrical Charac-

teristics on page 14 for the size of the V

CAP

Note CY14B101Q1 does not sup port AutoStore operation . The

user must perform Software STORE operation by using the SPI

STORE instruction to secure the data.

Software Store Operation

Software STORE enables the user to trigger a ST ORE operation

through a special SPI instruction. This operation is initiated

irrespective of whether a write has been performed since last nv

operation.

A STORE cycle takes t

STORE

to complete, during which all the

memory accesses to nvSRAM are inhibited. The RDY bit of the

Status register or the H SB pin may be polled to find the R eady

or Busy status of the nvSRAM. After the t

STORE

cycle time is

completed, the SRAM is activated again for read and write

operations.

Hardware STORE and HSB pin Operation

The HSB pin in CY14B101Q3 is used to control and

acknowledge STORE operations. If no STORE or RECALL is in

progress, this pin can be used to request a Hardware STORE

cycle. When the HSB

pin is driven LOW, nvSRAM condition ally

initiates a STORE operation after t

DELAY

duration. An actual

STORE cycle starts only if a write to the SRAM has been

performed since the last STORE or RECALL cycle. Reads a nd

Writes to the memory are inhibited for t

STORE

duration or as long

as HSB pin is LOW.

The HSB

pin also acts as an open drain driver that is internally

driven LOW to indicate a b usy condition, when a STORE cycle

(initiated by any means) or Power up RECALL is in progress.

Upon completion of the STORE operation, the nvSRAM remains

disabled until the HSB

pin returns HIGH. Leave the HSB pin

unconnected if not used.

Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY bit

of the SPI status register may be probed to determine the Ready

or Busy status of nvSRAM

Figure 3. AutoStore Mode

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile

Quantum Trap elements to the SRAM. A RECALL may be

initiated in two ways: Hardware RECALL, initiated on power up;

and Software RECALL, initiated by a SPI RECALL instruction.

Internally, RECALL is a two-step procedure. First, the SRAM

data is cleared. Next, the nonvolatile information is transferred

into the SRAM ce lls. All memory accesses are inhibited while a

RECALL cycle is in progress. The RECALL opera tion does not

alter the data in the nonvolatile elements.

Hardware Recall (Power Up)

During power up, when V

crosses V

SWITCH

, an automatic

RECALL sequence is initiated which transfers the content of

nonvolatile memory on to the SRAM. The data would previously

have been stored o n the non volatile memory through a STORE

sequence.

A Power Up Recall cycle takes t

time to complete and the

memory access is disabled during this time. HSB pin can be

used to detect the Ready status of the device. user

Software RECALL

Software RECALL enables the user to initiate a RECALL

operation to restore the content of nonvolatile memory on to the

SRAM. A Software RECALL is issued by using the SPI

instruction for RECALL.

A Software RECALL takes t

RECALL

to complete during which all

memory accesses to nvSRAM are inhibited. The controller must

provide sufficient delay for the RECALL operation to complete

before issuing any memory access instructions.

0.1uF

VCC

10kOhm

VCAP

CS VCAP

VSS

VCC

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 6 of 24

Disabling and Enabling AutoStore

If the application does n ot require the AutoStore feature, it can

be disabled by using the ASDISB in struction. If this is done, the

nvSRAM does not perform a STORE operation at power down.

AutoStore can be re-enabled by using the ASENB instruction.

However, these operations are not nonvolatile and if the user

needs this setting to survive power cycle, a STORE operation

must be performed following Autostore Disable or Enable

operation.

Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from

the factory. In CY14B101Q1, V

CAP

pin is not present and

AutoStore option is not available. The Autostore Enable and

Disable instructions to CY14 B101Q1 are ignored.

Note If AutoSt ore is disabled and V

CAP

is not required, leave it

open. V

CAP

pin must never be connected to GND. Power Up

Recall operation cannot be disabled in any case.

Serial Peripheral Interface

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input

(SI), Serial Output (SO) and Serial Clock (SCK) pins.

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides serial

access to nvSRAM through SPI interface. The SPI bus on this

device can run at speeds up to 40 MHz

The SPI is a synchronous serial interface which uses clock and

data pins for memory access and su pports multiple devices on

the data bus. A device on SPI bus is activated using a chip select

pin.

The relationship between chip select, clock, and data is dictated

by the SPI mode. This device supports SPI modes 0 and 3. In

both these modes, da ta is clocked into nvSRAM on rising edge

of SCK starting from the first rising edge after CS goes active.

The SPI protocol is controlled by opcodes. These opcodes

specify the commands from the bus master to the slave device.

After CS is activated the first byte transferred from the bus

master is the opcode. Following the opcode, any addresses and

data are then transferred. The CS must go inactive after an

operation is complete and before a new opcode can be issued.

The commonly used terms used in SPI protocol are given below:

SPI Master

The SPI Master device controls the operations on a SPI bus. An

SPI bus may have only one master with one or more slave

devices. All the slaves share the same SPI bus lines and master

may select any of the slave devices using the Chip Select pin.

All the operations must be initiated by the master activating a

slave device by pulling the CS pin of the slave LOW . The master

also generates the Serial Clock (SCK) and all the data trans-

mission on SI and SO lines are synchronized with this clock.

SPI Slave

SPI slave device is activated by the master through the Chip

Select line. A slave device gets the Serial Clock (SCK) as an

input from the SPI master and all the communication is synchro-

nized with this clo ck. SPI slave never initiates a communication

on the SPI bus and acts on the instruction from the master.

CY14B101Q1/CY14B101Q2/CY14B101Q3 operates as a SPI

slave and may share the SPI bus with other SPI slave devices.

Chip Select (CS)

For selecting any slave device, the master needs to pull down

the corresponding CS pin. Any instruction can be issued to a

slave device only wh ile the CS pin is LOW. Whe n the device is

not selected, data through the SI pin is ignored and the serial

output pin (SO) remains in a high impedance state.

Note A new instruction must begin wi th the fal ling edge o f Chip

Select (CS). Therefore, only one opcode can be issued for each

active Chip Sele ct cycle.

Serial Clock (SCK)

Serial clock is generated by the SPI master and the communi-

cation is synchronized with this clock after CS goes LOW.

CY14B101Q1/CY1 4B101Q2 /CY14B101 Q3 e nables SPI mode s

0 and 3 for data communication. In both these modes, the inputs

are latched by the slave device on the rising edge of SCK and

outputs are issued on the falling edge. Therefo r e, the first rising

edge of SCK signifies the arrival of first bit (MSB) of SPI

instruction on the SI pin. Further, all dat a inputs and outputs are

synchronized with SCK.

Data Transmission - SI and SO

SPI data bus consists of two lines, SI and SO, for serial data

communication. The SI is also refe rred to as M OSI (Ma ster O ut

Slave In) and SO is referred to as MISO (Master In Slave Out).

The master issues instructions to the slave through the SI pin,

while the slave responds through the SO pin. Multiple slave

devices may share the SI and SO lines as described earlier.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

The 1 Mbit serial nvSRAM requires a 3-byte address for any read

or write operation. However, since the actual address is o nly 17

bits, it implies that the first seven bits which are fed in are ignored

by the device. Although these seven bits are ‘don’t care’,

Cypress recommends that these bits are treated as 0s to enable

seamless transition to higher memory densities.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard

opcodes for memory accesses. In addition to the memory

accesses, it provides additional opcodes for the nvSRAM

specific functions: STORE, RECALL, AutoStore Enable, and

AutoStore Disa ble. Refer to Table 3 on page 8 for details.

Invalid Opcode

If an invalid opcode i s received, the opcode is ignored and the

device ignores any additional serial data on the SI pin till the next

falling ed ge of CS and the SO pin remains tristated.

Status Register

CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status

SPI bus. These bits are described in Table 5 on pag e 9.

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 7 of 24

SPI Modes

CY14B101Q1/CY14B101 Q2/CY14B101Q3 may be driven by a

microcontroller with its SPI peripheral running in either of the

following two modes:

■

SPI Mode 0 (CPOL=0, CPHA=0)

■

SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched-in on the rising edge

of Serial Clock (SCK) starting from the first risin g edge after CS

goes active. If the clock starts from a HIGH state (in mode 3), the

first rising edge, after the clock toggles, is considered. The output

data is available on the falling edge of Serial Clock (SCK).

The two SPI modes are shown in Figure 5 and Figure 6. The

status of clock when the bus master is in St andby mode and not

transferring data is:

■

SCK remains at 0 for Mode 0

■

SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for either

Mode 0 or Mode 3. T he device detects the SPI mode from the

status of SCK pin when the device is selected by bringing the CS

pin LOW . If SCK pin is LOW when device is selected, SPI Mode

0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3.

Figure 4. System Configuration Usin g SPI nvSRAM

xQ101B41YCxQ101B41YC

uController

SCK

MOSI

MISO

SI SO OSISKCSSCK

CS HOLD HOLDCS

CS1

CS2

HOLD1

HOLD2

Figure 5. SPI Mode 0

LSB

MSB

76543210

SCK

0 1 2 3 4 5 6 7

Figure 6. SPI Mode 3

SCK

SI 76543210

LSB

MSB

0 12 34 56 7

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 8 of 24

SPI Operating Features

Power Up

Power up is defined as the co ndition when the power supply is

turned on and V

crosses Vswitch voltage. During this time, the

Chip Select (CS) must be allowed to follow the V

voltage.

Therefore, CS must be connected to V

through a suitable pull

up resistor. As a built-in safety feature, Chip Select (CS) is both

edge sensitive and level sensitive. After power up, the device is

not selected until a falling edge is detected on Chip Select (CS).

This ensures that Chip Select (CS) must have been HIGH,

before going Low to start the first operation.

As described earlier, nvSRAM performs a Power Up Recall

operation after power up and therefore, all memory accesses are

disabled for t

RECALL

duration after power up. The HSB pin can

be probed to check the ready or busy status of nvSRAM after

power up.

Power On Reset

A Power On Reset (POR) circuit is included to prevent

inadvertent writes. At power up, the device does not respond to

any instruction until the V

reaches the Power On Reset

threshold voltage (V

SWITCH

). After V

transitions the POR

threshold, the device is internally reset and performs an Powe r

Up Recall operation. The device is in the following state after

POR:

■

Deselected (after Power up, a falling edge is required on Chip

Select (CS) before any instructions are started).

■

Standby power mode

■

Not in the ho l d co nd ition

■

Status register state:

❐

Write Enable (WEN) bit is reset to 0.

❐

WPEN, BP1, BP0 unchanged from previous power down

The WPEN, BP1, and BP0 bits of the S tatus Register are nonvol-

atile bits and remain unchanged from the previous power down.

Before selecting and i ssuing instructions to the memory, a valid

and stable V

voltage must be applied. This voltage must

remain valid until the end of the transmissi on of the instructio n.

Power Down

At power down (continuous decay of V

), when V

drops from

the normal operating voltage and below the V

SWITCH

threshold

voltage, the device stops responding to any instruction sent to it.

If a write cycle is in progress during power down, it is allowed

DELAY

time to complete after Vcc transitions below V

SWITCH

after which all memory accesses are inhibited and a conditional

AutoStore operation is performed (AutoStore is not performed if

no writes have happened since last RECALL cycle). This feature

prevents inadvertent writes to nvSRAM from happening during

power down.

However , to completely avoid the possibility of inadvertent writes

during power down, ensure th at the device is deselected and is

in Standby Power Mode, and the Chip Select (CS) follows the

voltage applied on V

Active Power and Standby Power Modes

When Chip Sele ct (CS) is LOW, the device is selected, and is in

the Active Power mode. The device consumes I

current, as

specified in DC Electrical Characteristics on page 14. When Chip

Select (CS) is HIGH, the device is deselected and the device

goes into the Standby Power mode if a STORE or RECALL cycle

is not in progress. If a STORE or RECALL cycle is in progress,

device goes into the Standby Power Mode after the STORE or

RECALL cycle is completed. In the Standby Power mode, the

current drawn by the device drops to I

SPI Functional Description

The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit

instruction register. Instructions and their opcodes are listed in

Table 3. All instructions, addresses, and data are transferred with

the MSB first and start with a HIGH to LOW CS transition. There

are, in all, 12 SPI instructions which provide access to most of

the functions in nvSRAM. Further, the WP and HOLD pins

provide additional functionality driven through hardware.

The SPI instructions are divided based on their functionality in

the following types:

❐

Status Register Access: WRSR and RDSR instructions

❐

Write Protection Functions: WREN and WRDI instructions

along with WP pin and WEN, BP0, and BP1 bits

❐

SRAM memory Access: READ and WRITE instructions

❐

nvSRAM special instructions: STORE, RECALL, ASENB,

and ASDISB

Table 3. Instruction Set

Instruction

Category Instruction

Name Opcode Operation

Status Register

Control Instruc-

tions

WREN 0000 0110 Set Write Enable

Latch

WRDI 0000 0100 Reset Write

Enable Latch

RDSR 0000 0101 Read Status

WRSR 0000 00 01 Write Status

SRAM

Read/Write

Instructions

READ 0000 0011 Read Data From

Memory Array

WRITE 0000 0010 Write Data To

Memory Array

Special NV

Instructions

STORE 0011 1100 Software STORE

RECALL 0110 0000 Software

RECALL

ASENB 0101 1001 AutoStore Enable

ASDISB 0 001 1001 AutoStore

Disable

Reserved - Reserved - 0001 1110 Reserved for

Internal use

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 9 of 24

Status Register

The status register bits are listed in Table 3. The status register consists of Ready bit (RDY) and data protection bits BP1, BP0, WEN,

and WPEN. The RDY bit can be polled to che ck the Ready or Busy status while a nvSRAM STORE cycle is in progress. The status

register can be modified by WRSR instruction and read by RDSR instruction. However , only WPEN, BP1, and BP0 bits of the Status

Register can be modified by using WRSR instruction. WRSR instruction has no effect on WEN and RDY bits. The default value shipped

from the factory for BP1, BP2 and WPEN bits is ‘0’.

Read Sta tu s Regi st er (RD S R) In stru ct io n

The Read Status Register instruction provides access to the

status register . This instruction is used to probe the Write Enable

Status of the de vice or the Ready status of the device. RDY bit

is set by the device to 1 whenever a STORE cycle is in progress.

The Block Protection and WPEN bits indicate the extent of

protection employed.

This instruction is issued after the falling edge of CS using the

opcode for RDSR.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status

and bit 1 (WEN and RDY). The BP0 and BP1 bi ts can be used

to select one of four levels of block protect ion. Further , WPEN bit

can be set to ‘1’ to enable the use of Write Protect (WP) pin.

WRSR instruction is a write instruction and needs writes to be

enabled (WEN bit set to ‘1’) using the WREN instruction before

it is issued. The instruction is issued after the falling edge of CS

using the opcode for WRSR followed by 8 bits of data to be

stored in the S tatus Register. Since, only bits 2, 3, and 7 can be

modified by WRSR instruction, it is recommended to leave the

other bits as ‘0’ while writing to the Status Register

Note In CY14B101Q1/CY14B101Q2/CY14B101Q3, the values

written to Status Register are saved to non volatile memory onl y

after a STORE operation. If AutoS tore is disabled (or while using

CY14B101Q1), any modifications to the S tatus Register must be

secured by using a Software STORE operation

Note CY14B101Q2 does not have WP pin . Any modification to

bit 7 of the Status register has no effect on the functionality of

CY14B101Q2.

Table 4. Status Register Forma t

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN (0) X X X BP1 (0) BP0 (0) WEN RDY

Table 5. Status Register Bit Definition

Bit Definition Description

Bit 0 (RDY) Ready Read Only bit indicates the ready status of device to perform a memory access. This bit is

set to “1” by the device while a STORE or Software RECALL cycle is in progress.

Bit 1 (WEN) Write Enable WEN indicates if the device is write-enabled. Setting WEN = '1' enables writes and setting

WEN = '0' disables all write operations

Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details see Table 6 on page 10.

Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details see Table 6 on page 10.

Bit 7 (WPEN) Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see T able 7 on page 1 1.

Figure 7. Read Status Register (RDSR) Instruction Timing

SCK

01234567

0000 01 0 0

MSB LSB

HI-Z

012345 67

Data LSB

D0D1

D5D6

MSB

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 10 of 24

Write Protection and Block Protection

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features

for both software and hardware write protection using WRDI

instruction and WP. Additionally, this device also provides block

protection mechanism through BP0 and BP1 pins of the Sta tus

The write enable and disable status of the device is indicated by

WEN bit of the status register . The write instructions (WRSR and

WRITE) and nvSRAM special instruction (STORE, RECALL,

ASENB, and ASDISB) need the write to b e enable d (WEN bit =

1) before they can be issued.

Write Enable (WREN) Instruction

On power up, the device is always in the write disable state. The

following WRITE, WRSR, or nvSRAM special instruction must

therefore be preceded by a Write Enable instruction. If the device

is not write enabled (WEN = ‘0’ ), it ignores the write instructions

and returns to the standby state when CS is brought HIGH. A

new CS falling edge is required to re-initiate serial communi-

cation. The instruction is issued following the falling edge of CS.

When this instruction is used, the WEN bit of status register is

set to ‘1’. WEN bit defaults to ‘0’ on power up.

Note After completion of a write instruction (W RSR or WRITE)

or nvSRAM special instruction (STORE, RECALL, ASENB, and

ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to

provide protection from any inadvertent writes. Therefore,

WREN instruction needs to be used before a new write

instruction is issued.

Write Disable (WRDI) Instruction

Write Disable instruction disables the write by clearing the WEN

bit to ‘0’ in order to protect the device against inadvertent writes.

This instruction is issued following falling edge of CS followed by

opcode for WRDI instruction. The WEN bit is cleared on the

rising edge of CS following a WRDI instruction.

Block Protection

Block protection is provided usi ng the BP0 and BP1 pins of the

Status register. These bits can be set using WRSR instruction

and probed using the RDSR instruction. The nvSRAM is divided

into four array segments. One-quarter, one-half, or all of the

memory segments can be protected. Any data within the

protected segment is read only. Table 6 shows the function of

Block Protect bits.

Figure 8. Write Status Register (WRSR) Instruction Timing

SCK

01 23 4567

00000001

MSB LSB

00D7

HI-Z

012345 67

Opcode Data in

Figure 9. WREN Instruction

0 0 0 0 0 1 1 0

SCK

Hi-Z

0 1 2 3 4 5 6 7

Figure 10. WRDI Instruction

Table 6. Block Write Protect Bits

Level Status Register

Bits Array Addresses Protected

BP1 BP0

000 None

1 (1/4) 0 1 0x18000-0x1FFFF

2 (1/2) 1 0 0x10000-0x1FFFF

3 (All) 1 1 0x00000-0x1FFFF

0 00 00 1 00

SCK

Hi-Z

0 1 2 3 4 5 6 7

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 11 of 24

Write Protect (WP) Pin

The write protect pin (WP) is used to provide hardware write

protecti on. W P pin enables all normal read and write operations

when held HIGH. When the WP pin is brought LOW and WPEN

bit is “1”, all write opera tions to the status register are inhibited.

The hardware write protection function is blocked when the

WPEN bit is “0”. This enables the user to install the device in a

system with the WP pin tied to ground, and still write to the status

WP pin can be used along with WPEN and Block Protect bits

(BP1 and BP0) of the status register to inhibit writes to memory.

When WP pin is LOW and WPEN is set to “1”, any modifications

to status register are disabled. Therefore, the memory is

protected by setting the BP0 and BP1 bits and the WP pin inhibits

any modification of the status register bits, providing hardware

write protection.

Note WP going LOW when CS is still LOW has no effect on any

of the ongoing write operations to the status register.

Note CY14B101Q2 does not have WP pin and therefore does

not provide hardware write protection.

Table 7 summarizes all the protection features of this device

Memory Access

All memory accesses are done using the READ and WRITE

instructions. These instructions cann ot be use d w hile a STORE

or RECALL cycle is in progress. A STORE cycle in progress is

indicated by the RDY bit of the status register and the HSB pin.

Read Sequence (READ)

The read operations on this device are performed by giving the

instruction on Serial Input pin (SI) and reading the output on

Serial Output (SO) pin. The following sequence needs to be

followed for a read operation: After the CS line is pulled LOW to

select a device, the read opcode is transmitted through the SI

line followed by three bytes of address. The Most Significant

address byte contains A16 in bit 0 and other bits as ‘don’t cares’.

Address bits A15 to A0 are sent in the following two address

bytes. After the last address bit is transmitted on the SI pin, the

data (D7-D0) at the specific address is shifted out on the SO line

on the falling edge of SCK. Any other data on SI line after the last

address bit is ignored.

CY14B101Q1/CY14B101Q2/CY14B101Q3 allows reads to be

performed in bursts through SPI which can be used to read

consecutive addresses without issuing a new READ instruction.

If only one byte is to be read, the C S line must be driven HIGH

after one byte of data comes out. However, the read sequence

may be continued by holding the CS l ine LO W and the address

is automatically incremented and data continues to shift out on

SO pin. When the last data memory address (0x1FFFF) is

reached, the address rolls over to 0x0000 and the device

continues to read.

Write Sequence (WRITE)

The write operations on this device are performed through the

Serial Input (SI) pin. To perform a write operation, if the device is

write disabled, then the device must first be write enabled

through the WREN instruction. When the writes are enabled

(WEN = ‘1’), WRITE instruction is issued after the falling edge of

CS. A WRITE instruction constitutes transmitting the WRITE

opcode on SI line followed by 3 bytes address sequence and the

data (D7-D0) which is to be written. The Most Significant address

byte contains A16 in bit 0 with other bits being ‘don’t cares’.

Address bits A15 to A0 are sent in the following two address

bytes.

CY14B101Q1/CY14B101Q2/CY14B101Q3 enables writes to be

performed in bursts through SPI which can be used to write

consecutive addresses without issuing a new WRITE instruction.

If only one byte is to be written, the CS line must be driven HIGH

after the D0 (LSB of data) is transmitted. However, if more bytes

are to be written, CS line must be held LOW and address is

incremented automatically . The following bytes on the SI line are

treated as data bytes and written in th e successive addresses.

When the last data memory address (0x1FF FF) is reached , the

address rolls over to 0x0000 and the device continues to write.

The WEN bit is reset to “0” on completion of a WRITE sequence.

Note When a burst write reaches a protected block address, it

continues the address increment into the protected space but

does not write any data to the protected memory. If the address

roll over takes the burst write to unpro tected space, it resumes

writes. The same operation is true if a burst write is initiated

within a write protected block.

Table 7. Write Protection Operation

WPEN WP WEN Protected

Blocks Unprotected

Blocks Status

X X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 LOW 1 Protected Writable Protected

1 HIGH 1 Protected Writable Writable

Figure 11. Read Instruction Timing

SCK

012345 67 0765432

120212223012345 67

MSB LSB

Data

Op-Code

0000001 00000 0

A16 A3 A1A2 A0

17-bit Address

MSB LSB

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 12 of 24

nvSRAM Special Instructions

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four

special instructions which enables access to four nvSRAM

specific functions: STORE, RECALL, ASDISB, and ASENB.

Table 8 lists th ese instructions.

Software STORE

When a STORE instruction is executed, nvSRAM performs a

Software STORE operation. The STORE operation is issued

irrespective of whether a write has taken place since last STORE

or RECALL operation.

To issue this instruction, the device must be write enabled (WEN

bit = ‘1’). The instruction is performed by transmitting the STORE

opcode on the SI pin following the falling edge of CS. The WEN

bit is cleared on the positive edge of CS following the STORE

instruction.

Figure 12. Burst Mode Read Instruction Timing

Figure 13. Write Instruction Timing

Figure 14. Burst Mode Write Instruction Timing

SCK

LSB

Op-Code

17-bit Address

MSB LSB

01 2 3 456 70765432

120 21 22 23 01234567 01234567

0000 00 11 00 00 00 0

A16 A3 A2 A1 A0

D2D3

Data Byte 1 Data Byte N

MSB LSB

MSB

D2D3

D7 D0D7

SCK

01234 5

6 7 0765432

12021222301234567

MSB LSB

Data

D0D1

D5D6D7

Op-Code

00 00001 000 0

A16 A3 A1A2 A0

17-bit Address

MSB LSB

HI-Z

SCK

MSB LSB

Op-Code

17-bit Address

MSB LSB

01 234567

076 5 432

120 21 22 23 01 234567 01 234567

0 00000

100000000

A16 A3 A2 A1 A0

HI-Z

Data Byte 1 Data Byte N

D2D3

D7 D0D7

Table 8. nvSRAM Special Instructions

Function Name Opcode Operation

STORE 0011 1100 Software STORE

RECALL 0110 0000 Software RECALL

ASENB 0101 1001 AutoStore Enable

ASDISB 0001 1001 AutoStore Disable

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 13 of 24

Software RECALL

When a RECALL instruction is executed, nvSRAM performs a

Software RECALL operation. To issue this instruction, the device

must be write enabled (WEN = ‘1’).

The instruction is performed by transmitting the RECALL opcode

on the SI pin following the falling edge of CS. The WEN bit is

cleared on the positive edge of CS following the RECALL

instruction.

AutoStore Disable (ASDISB)

AutoStore is enabled by default in CY14B101Q2/CY14B101Q3.

The ASDISB instruction disables the AutoStore. This setting is

not nonvolatile and needs to be followed by a STORE sequence

to survive the power cycle.

To issue this instruction, the device must be write enabled (WEN

= ‘1’). The instruction is performed by tran smitting the ASDISB

opcode on the SI pin following the falling edge of CS. The WEN

bit is cleared on the positive edge of CS following the ASDISB

instruction.

AutoStore Enable (ASENB)

The AutoStore Enable instruction enables the AutoStore on

CY14B101Q1. This setting is not nonvolatile and needs to be

followed by a STORE sequence to survive the power cycle.

To issue this instruction, the device must be write enabled (WEN

= ‘1’). The instruction is performed by transmitting the ASENB

opcode on the SI pin following the falling edge of CS. The WEN

bit is cleared on the positive edge of CS following the ASENB

instruction.

Note If ASDISB and ASENB instructions are executed in

CY14B101Q1, the device is busy for the duration of software

sequence processing time (t

). However, ASDISB and ASENB

instructions have no effect on CY14B101Q1 as AutoStore is

internally disabled.

HOLD Pin Operation

The HOLD pin is used to p ause the serial communication. When

the device is selected and a serial sequence is underway , HOLD

is used to pause the serial communication with the master device

without resetting the ongoing serial sequence. To pause, the

HOLD pin must be brought LOW when the SC K pin is LOW. To

resume serial communication, the HOLD pin must be brought

HIGH when the SCK pin is LOW (SCK may toggle during HOLD).

While the device serial communicatio n is paused, in puts to the

SI pin are ignored and the SO pin is in the high impedance state.

This pin can b e used by the master with the CS pin to p a use th e

serial communication by bringing the pin HOLD LOW and

deselecting an SPI slave to establish communication with

another slave device, without the serial communication being

reset. The communication may be resumed at a later point by

selecting the device and setting the HOLD pin HIGH.

Figure 15. Software STORE Operation

Figure 16. Sof tware RECALL Operation

Figure 17. AutoStore Disable Operation

0 0 1 1 1 1 0 0

SCK

Hi-Z

0 1 2 3 4 5 6 7

0 1 1 0 0 0 0 0

SCK

0 1 2 3 4 5 6 7

Hi-Z

0 0 0 1 1 0 0 1

SCK

Hi-Z

0 1 2 3 4 5 6 7

Figure 18. AutoStore Enable Operation

Figure 19. HOLD Operation

0 1 0 1 1 0 0 1

SCK

Hi-Z

0 1 2 3 4 5 6 7

SCK

HOLD

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 14 of 24

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Storage Temperature ............... .. ................–65°C to +150°C

Maximum Accumulated Storage Time

At 150°C Ambient Temperature................... .....1000h

At 85°C Ambient Temperature.................. ... 20 Ye ars

Ambient Temperature with

Power Applied.............................................–55°C to +150°C

Supply Voltage on V

Relative to GND........–0.5V to +4.1V

DC Voltage Applied to Outputs

in High-Z State.......................................–0.5V to V

+ 0.5V

Input Voltage............................... ... ........–0.5V to V

+ 0.5V

Transient Voltage (<20 ns) on

Any Pin to Ground Potential............... ....–2.0V to V

+ 2.0V

Package Power Dissipation

Capability (T

= 25°C)....................................................1.0W

Surface Mount Lead Soldering

Temperature (3 Seconds) ..........................................+260°C

DC Output Current (1 output at a time, 1s duration).....15 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch up Current.................................................... > 200 mA

Table 9. Operating Range

Range Ambient Temperature V

Industrial –40°C to +85°C 2.7V to 3.6V

DC Electrical Characteristics

Over the Operating Range (V

= 2.7V to 3.6V)

Parameter Description Test Conditions Min Typ

[4]

Max Unit

Power Supply Voltage 2.7 3.0 3.6 V

CC1

Average V

Current At f

SCK

= 40 MHz.

Values obtained without output loads (I

OUT

= 0 mA) 10 mA

CC2

Average V

Current

during ST OR E All Inputs Don’t Care, V

= Max.

Average current for duration t

STORE

10 mA

CC4

Average V

CAP

Current

during AutoStore

Cycle

All Inputs Don’t Care. Average current for duration

STORE

5mA

Standby Current CS > (V

– 0.2V). V

< 0.2V or > (V

– 0.2V).

Standby current level after nonvolatile cycle is complete.

Inputs are static. f = 0 MHz.

5mA

IX[5]

Input Leakage Current

(except HSB)V

= Max, V

< V

–1 +1 µA

Input Leakage Current

(for HSB)V

= Max, V

< V

–100 +1 µA

Off State Output

Leakage Current V

= Max, V

< V

OUT

< V

–1 +1 µA

Input HIGH Voltage 2.0 V

+ 0.5 V

Input LOW Voltage V

– 0.5 0.8 V

Output HIGH Voltage I

OUT

= –2 mA 2.4 V

Output LOW Voltage I

OUT

= 4 mA 0.4 V

CAP

Storage Capacitor Between V

CAP

pin and V

, 5V Rated 61 68 180 µF

Notes

4. Typical values are at 25°C, V

= V

(Typ). Not 100% tested.

5. The HSB pin has I

OUT

= -2 uA for V

of 2.4V when both active high and LOW drivers are disabled. When they are enabled standard V

and V

are valid. This

parameter is characterized but not tested.

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 15 of 24

AC Test Conditions

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <3 ns

Input and Output Timing Reference Levels....................1.5V

Data Retention and Endurance

Parameter Description Min Unit

DATA

Data Retention 20 Years

Nonvolatile STORE Operations 1,000 K

Capacitance

Parameter

[6]

Description Test Conditions Max Unit

Input Capacitance T

= 25°C, f = 1MHz,

= V

(T yp) 6pF

OUT

Output Pin Capacitance 8 pF

Thermal Resistance

Parameter

[6]

Description Test Conditions 16-SOIC 8-DFN Unit

Thermal Resistance

(Junction to Ambient) Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA / JESD51.

55.17 17.7 °C/W

Thermal Resistance

(Junction to Case) 2.64 18.8 °C/W

Figure 20. AC Test Loads and Waveforms

3.0V

OUTPUT

5 pF

789Ω

3.0V

OUTPUT

30 pF

789Ω

577Ω577Ω

Note

6. These parameters are guaranteed by design and are not tested.

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 16 of 24

AC Switching Characteristics

Cypress

Parameter Alt.

Parameter Description 40MHz Unit

Min Max

SCK

Clock Frequency, SCK 40 MHz

Clock Pulse Width Low 11 ns

Clock Pulse Width High 11 ns

CS High Time 20 ns

CSS

CES

CS Setup Time 10 ns

CSH

CEH

CS Hold Time 10 ns

Data In Setup Time 5 ns

Data In Hold Time 5 ns

HOLD Hold Time 5 ns

HOLD Setup Time 5 ns

Output Valid 9 ns

HHZ

HOLD to Output High Z 15 ns

HLZ

HOLD to Output Low Z 15 ns

Output Hold Time 0 ns

HZCS

DIS

Output Disable Time 25 ns

Figure 21. Synchronous Data Timing (Mode 0)

Figure 22. HOLD Ti ming

HI-Z

VALID IN

HI-Z

SCK

tCL

tCH

tCSS

tSD tHD

tCO tOH

tCS

tCSH

tHZCS

SCK

HOLD

tSH

tHHZ tHLZ

tHH

tSH

tHH

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 17 of 24

AutoStore or Power Up RECALL

Parameters Description CY14B101Q1/CY14B101Q2/

CY14B101Q3 Unit

Min Max

FA [7]

Power Up RECALL Duration 20 ms

STORE [8]

STORE Cycle Duration 8ms

DELAY [9]

Time Allowed to Complete SRAM Cycle 25 ns

SWITCH

Low Voltage Tr igger Level 2.65 V

VCCRISE[6]

VCC Rise Time 150 μs

HDIS[6]

HSB Output Disa ble Voltage 1.9 V

LZHSB[6]

HSB To Output Active Time 5 μs

HHHD[6]

HSB High Active Time 500 ns

Switching Waveforms

Figure 23. AutoStore or Power Up RECALL

[10]

VSWITCH

VHDIS

VVCCRISE tSTORE tSTORE

tHHHD tHHHD

tDELAY

tLZHSB tLZHSB

tFA

HSB OUT

AutoStore

POWER-

RECALL

Read & Write

Inhibited

(RWI)

POWER-UP

RECALL

Read & Write BROWN

OUT

AutoStore

POWER-UP

RECALL

Read & Write POWER

DOWN

AutoStore

Note Note

Note

VCC

Notes

7. t

starts from the time V

rises above V

SWITCH.

8. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware Store is not init iated

9. On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM oper ation continues to be enabled for time t

DELAY

10.Read and Write cycles are ignored during STORE, RECALL, and while V

is below V

SWITCH.

11. HSB pin is driven high to V

only by internal 100kOhm resistor, HSB driver is disabled.

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 18 of 24

Software Controlled STORE and RECALL Cycles

Parameter Description CY14B101Q1/CY14B101Q2/

CY14B101Q3 Unit

Min Max

RECALL

RECALL Duration 200 μs

SS [12, 13]

Soft Sequence Processing Time 100 μs

Switching Waveforms

Figure 24. Software STORE Cycle

[13]

Figure 25. Software RECALL Cycle

[13]

0 0 1 1 1 1 0 0

SCK

RWI

Hi-Z

0 1 2 3 4 5 6 7

RDY

tSTORE

0 1 1 0 0 0 0 0

SCK

0 1 2 3 4 5 6 7

RWI

Hi-Z

RDY

tRECALL

Notes

12.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to ef fectively register command.

13.Commands such as STORE and RECALL lock out I/O until operation is complete whic h further increases this time. See the specific command.

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 19 of 24

Hardware STORE Cycle

Parameter Description CY14B101Q3 Unit

Min Max

DHSB

HSB To Ou tput Active Time when write latch not set 25 ns

PHSB

Hardware STORE Pulse Width 15 ns

Switching Waveforms

Figure 26. Hardware STORE Cycle

[8]

HSB (IN)

HSB (OUT)

RWI

HSB (IN)

HSB (OUT)

RWI

tHHHD

tSTORE

tPHSB

tDELAY

tLZHSB

tDELAY tDHSB tDHSB

tPHSB

HSB pin is driven high to VCC only by Internal

100K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

Write Latch not set

Write Latch set

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 20 of 24

Part Numbering Nomenclature

Option:

T - Tape and Reel

Blank - Std.

Q - Serial SPI nvSRAM

Density:

101 - 1 Mb

Voltage:

B - 3.0V

Cypress

CY 14 B 101 Q 1-SF X I T

14 - nvSRAM

Pb-free

Package:

SF - 16 SOIC

LH - 8 DFN

1 - With WP

2 - With V

CAP

3 -

With V

CAP,

WP and HSB

Temperature:

I - Industrial (-40 to 85

Ordering Information

Ordering Code Package

Diagram Package Type Operating

Range

CY14B101Q1-LHXIT 001-50671 8 DFN (With WP) Industrial

CY14B101Q1-LHXI 001-50671 8 DFN (With WP)

CY14B101Q2-LHXIT 001-50671 8 DFN (With V

CAP

)

CY14B101Q2-LHXI 001-50671 8 DFN (With V

CAP

)

CY14B101Q3-SFXIT 51-85022 16 SOIC (

With V

CAP,

WP and HSB)

CY14B101Q3-SFXI 51-85022 16 SOIC (

With V

CAP,

WP and HSB)

All the above parts are Pb-free.

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 21 of 24

Package Diagrams

Figure 27. 8-Pin (196 mil) DFN Package (001-50671)

1. ALL DIMENSIONS ARE IN MILLIMETERS

3. BASED ON REF JEDEC # MO-240 EXCEPT DIMENSIONS (L) and (b)

NOTES:

2. PACKAGE WEIGHT: TBD

001-50671 *A

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 22 of 24

Figure 28. 16-Pin (300 mil) SOIC (51-85 022)

Package Diagrams

(continued)

51-85022 *B

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *D Page 23 of 24

Document History Page

Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3 1 MBit (128K x 8) Serial SPI nvSRAM

Document Number: 001-50091

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

** 2607408 GSIN/

GVCH/AESA 12/19/08 New Datasheet

*A 2654487 GVCH/PYRS 02/04/2009 Moved from Advance information to Preliminary

Changed part number from CY14B101QxA to CY14B101 Qx

Updated pin description of V

CAP

Updated Device operation and SPI peripheral interface description

Added Factory setting values for BP1, BP2 and WPEN bits

Updated Real Time Clock operation description

Changed I

CC2

from 5mA to 10mA

*B 2733293 GVCH/AESA 07/08/2009 Corrected typo error in the Document History Page (Description of change)

Corrected Typo error of footnote 2 and 3

Updated AutoStore operation description

Updated test condition of I

CC1

and I

parameter

Updated V

HDIS

parameter description

*C 2757348 08/28/2009 08/28/2009 Moved data sheet status from Preliminary to Final

Removed commercial temperature related specs

Added thermal resistance values for 16-SOIC and DFN package

Added note to Write Sequence (WRITE) description

*D 2839453 GVCH/PYRS 01/06/1 0 Changed STORE cycles to QuantumTrap from 200K to 1 Million

Updated Figure 3

Added Contents

Document #: 001-50091 Rev. *D Revised January 04, 20 10 Page 24 of 24

All products and company names mentioned in this document are the trademarks of their respective holders.

CY14B101Q1

CY14B101Q2

CY14B101Q3

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress pro d ucts are n ot war ran ted no r inte nd ed to be used fo r

medical, life supp or t, l if e savi n g, cr it ical control or saf ety ap pli c at ions, unless pursuant to an express writte n ag reement with Cypress. Furthermore, Cyp ress doe s not auth or iz e its products for use as

critical components in life-support systems where a malfunction or failur e may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and in ternati onal tr eaty provi sion s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-exclu sive , non-tr ansfer able l icense to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wit h a Cypress

integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this S ource Code exce pt as specified above is prohib ited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOS E. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liabil ity ar ising ou t of t he app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical componen ts in life-suppo rt systems where

a malfunction or failure may reasonably be expected to result in sign ificant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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