CYBLE-224110-00 EZ-BLETM Creator XT/XR Module General Description The Cypress CYBLE-224110-00 is a fully certified and qualified module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-224110-00 is a turnkey solution that includes onboard power amplifier (PA), low-noise amplifier (LNA), crystal oscillators, chip antenna, passive components, and the Cypress PSoC(R) 4 BLE. Refer to the PSoC 4 BLE datasheet for additional details on the capabilities of the PSoC 4 BLE device used on this module. RX current consumption BLE silicon: 16.4 mA (radio only) SE2438T: 5.5 mA (PA/LNA only) Low power mode support (BLE silicon only) Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on Hibernate: 150 nA with SRAM retention Stop: 60 nA with XRES wakeup The EZ-BLETM Creator XT/XR module provides extended industrial temperature operation (XT) as well as extended communication range (XR). The EZ-BLE XT/XR module is a scalable and reconfigurable platform architecture, combining programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-224110-00 also includes digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The CYBLE-224110-00 includes a royalty-free BLE stack compatible with Bluetooth 4.1. Integrated PA/LNA Module Description Module size: 9.5 mm x 15.4 mm x 1.80 mm (with shield) Extended range: Up to 400 meters bidirectional communication[1,2] Up to 450 meters in beacon-only mode[1] Supports output power of +9.5 dBm and RXS of -95 dBm Programmable Analog Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode 12-bit, 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin One low-power comparator that operates in Deep-Sleep mode Programmable Digital Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and datapath Cypress-provided peripheral Component library, user-defined state machines, and Verilog input Extended industrial temperature range: -40 C to +105 C Up to 25 GPIOs 256-KB flash memory, 32-KB SRAM memory Capacitive Sensing Bluetooth 4.1 qualified single-mode module QDID: 82951 Declaration ID: D030799 Certified to FCC, CE, MIC, KC, and ISED regulations Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance Segment LCD Drive LCD drive supported on all GPIOs (common or segment) 32-bit processor (0.9 DMIPS/MHz), operating at up to 48 MHz Operates in Deep-Sleep mode with four bits per pin memory Watchdog timer with dedicated internal low-speed oscillator Serial Communication Two-pin SWD for programming Power Consumption TX output power: -18 dbm to +9.5 dbm RX Receive Sensitivity: -95 dbm Two independent runtime reconfigurable serial communication blocks (SCBs) with I2C, SPI, or UART functionality Timing and Pulse-Width Modulation Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks Received signal strength indicator (RSSI) with 1-dB resolution Center-aligned, Edge, and Pseudo-random modes One-second connection interval with PA/LNA active: 26.3 A Up to 25 Programmable GPIOs TX current consumption: BLE silicon: 15.6 mA (radio only, 0 dbm) SE2438T: 20 mA (PA/LNA only, +9.5 dBm) Any GPIO pin can be CapSense, LCD, analog, or digital Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable Notes 1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +9.5 dBm. 2. Specified as EZ-BLE XT/XR module to module range. Mobile phone connection will decrease based on the PA/LNA performance of the mobile phone used. Cypress Semiconductor Corporation Document Number: 002-11264 Rev. *G * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised March 15, 2018 CYBLE-224110-00 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. Overview: EZ-BLE Module Portfolio, Module Roadmap PSoC 4 BLE Silicon Datasheet Application notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are: AN96841 - Getting Started with EZ-BLE Module (R) AN91267 - Getting Started with PSoC 4 BLE (R) AN97060 - PSoC 4 BLE and PRoCTM BLE - Over-The-Air (OTA) Device Firmware Upgrade (DFU) Guide AN91162 - Creating a BLE Custom Profile AN91184 - PSoC 4 BLE - Designing BLE Applications AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications (R) (R) AN85951 - PSoC 4 CapSense Design Guide (R) AN95089 - PSoC 4/PRoCTM BLE Crystal Oscillator Selection and Tuning Techniques AN91445 - Antenna Design and RF Layout Guidelines Technical Reference Manual (TRM): (R) PSoC 4 BLE Technical Reference Manual (R) PSoC 4 BLE Registers Technical Reference Manual (R) PRoC and PSoC Programming Specifications Knowledge Base Article KBA212334 - Pin Mapping Differences Between the EZ-BLETM Creator Evaluation Board (CYBLE-224110-EVAL) and the BLE Pioneer Kit (CY8CKIT-042-BLE) KBA97095 - EZ-BLETM Module Placement KBA213260 - RF Regulatory Certifications for CYBLE-224110-00 and CYBLE-224116-01 EZ-BLETM Creator XT/XR Modules KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules KBA210802 - Queries on BLE Qualification and Declaration Processes KBA2108122 - 3D Model Files for EZ-BLE/EZ-BT Modules Development Kits: CYBLE-224110-EVAL, CYBLE-224110-00 Evaluation Board (R) CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer Kit (R) CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit Test and Debug Tools: (R) CYSmart, Bluetooth LE Test and Debug Tool (Windows) (R) CYSmart Mobile, Bluetooth LE Test and Debug Tool (Android/iOS Mobile App) Two Design Environments to Get You Started Quickly PSoC(R) CreatorTM Integrated Design Environment (IDE) PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling, and debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC ComponentsTM. PSoC Components are analog and digital "virtual chips," represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. Bluetooth Low Energy Component The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack. EZ-SerialTM BLE Firmware Platform The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed in BLE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control signals through the module's GPIOs, making it easy to add BLE functionality quickly to existing designs. Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for User Manuals and instructions for getting started as well as detailed reference materials. EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If EZ-Serial is not pre-loaded on your module, you can download each EZ-BLE module's firmware images on the EZ-Serial webpage. Technical Support Frequently Asked Questions (FAQs): Learn more about our BLE ECO System. Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE. Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-11264 Rev. *G Page 2 of 47 CYBLE-224110-00 Contents Overview ............................................................................ 4 Module Description...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 8 Power Supply Connections and Recommended External Components.................................................................... 12 Power Connections ................................................... 12 Connection Options................................................... 12 External Component Recommendation .................... 12 Critical Components List ........................................... 15 Antenna Design ......................................................... 15 Power Amplifier (PA) and Low Noise Amplifier (LNA) 15 Enabling Extended Range Feature ........................... 16 Power Saving Measures with PA/LNA Operation ..... 17 Electrical Specification .................................................. 18 GPIO ......................................................................... 20 XRES......................................................................... 22 Analog Peripherals .................................................... 22 Digital Peripherals ..................................................... 26 Serial Communication ............................................... 28 Memory ..................................................................... 29 System Resources .................................................... 29 Environmental Specifications ....................................... 35 Environmental Compliance ....................................... 35 RF Certification .......................................................... 35 Safety Certification ..................................................... 35 Environmental Conditions ......................................... 35 Document Number: 002-11264 Rev. *G ESD and EMI Protection ........................................... 35 Regulatory Information .................................................. 36 FCC ........................................................................... 36 ISED .......................................................................... 37 European Declaration of Conformity ......................... 38 MIC Japan ................................................................. 38 KC Korea................................................................... 38 Packaging........................................................................ 39 Ordering Information ...................................................... 41 Part Numbering Convention ...................................... 41 Acronyms ........................................................................ 42 Document Conventions ................................................. 44 Units of Measure ....................................................... 44 Document History Page ................................................. 45 Sales, Solutions, and Legal Information ...................... 47 Worldwide Sales and Design Support....................... 47 Products .................................................................... 47 PSoC(R) Solutions ...................................................... 47 Cypress Developer Community................................. 47 Technical Support ..................................................... 47 Page 3 of 47 CYBLE-224110-00 Overview Module Description The CYBLE-224110-00 is an integrated wireless module designed to be soldered to the main host board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Length (X) 9.50 0.15 mm Width (Y) 15.40 0.15 mm Length (X) 7.00 mm Width (Y) 5.00 mm PCB thickness Height (H) 0.50 0.10 mm Shield height Height (H) 1.10 0.10 mm Module dimensions Antenna location dimensions Maximum component height Height (H) 1.30-mm typical (chip antenna) Total module thickness (bottom of module to highest component) Height (H) 1.80-mm typical See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-224110-00. Document Number: 002-11264 Rev. *G Page 4 of 47 CYBLE-224110-00 Figure 1. Module Mechanical Drawing Top View Side View Bottom View Note 3. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Table 3. Document Number: 002-11264 Rev. *G Page 5 of 47 CYBLE-224110-00 Pad Connection Interface As shown in the bottom view of Figure 1 on page 5, the CYBLE-224110-00 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-224110-00 module. Table 2. Solder Pad Connection Description Name SP Connections Connection Type 32 Solder Pads Pad Length Dimension Pad Width Dimension Pad Pitch 0.71 mm 0.41 mm 0.76 mm Figure 2. Solder Pad Dimensions (Seen from Bottom) Document Number: 002-11264 Rev. *G Page 6 of 47 CYBLE-224110-00 To maximize RF performance, the host layout should follow these recommendations: 1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area shown in item 2. Refer to AN96841 for module placement best practices. 2. To maximize RF performance, the area immediately around the Cypress BLE module chip antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 3 (dimensions are in mm). Figure 3. Recommended Host PCB Keep-Out Area Around the CYBLE-224110-00 Chip Antenna Host PCB Keep-Out Area Around Chip Antenna Document Number: 002-11264 Rev. *G Page 7 of 47 CYBLE-224110-00 Recommended Host PCB Layout Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-224110-00. Dimensions are in millimeters unless otherwise noted. The minimum recommended host PCB pad length is 0.91 mm (0.455 mm from center of the pad to either side) is recommended as shown in Figure 6. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 4. Host Layout Pattern for CYBLE-224110-00 Document Number: 002-11264 Rev. *G Figure 5. Module Pad Location from Origin Page 8 of 47 CYBLE-224110-00 Table 3 provides the center location for each solder pad on the CYBLE-224110-00. All dimensions are referenced to the center of the solder pad. Refer to Figure 6 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location Solder Pad (Center of Pad) Location (X,Y) from Orign (mm) Dimension from Orign (mils) 1 (0.26, 3.37) (10.24, 132.68) 2 (0.26, 4.13) (10.24, 162.68) 3 (0.26, 4.89) (10.24, 192.68) 4 (0.26, 5.66) (10.24, 222.68) 5 (0.26, 6.42) (10.24, 252.68) 6 (0.26, 7.18) (10.24, 282.68) 7 (0.26, 7.94) (10.24, 312.68) 8 (0.26, 8.70) (10.24, 342.68) 9 (0.56, 15.14) (22.05, 596.06) 10 (1.32,15.14) (51.97, 596.06) 11 (2.08, 15.14) (81.89, 596.06) 12 (2.84,15.14) (111.81, 596.06) 13 (3.61, 15.14) (142.13, 596.06) 14 (4.37, 15.14) (172.13, 596.06) 15 (5.13, 15.14) (202.13, 596.06) 16 (5.89, 15.14) (231.89, 596.06) 17 (6.65,15.14) (261.81, 596.06) 18 (7.42, 15.14) (292.13, 596.06) 19 (8.18, 15.14) (322.05, 596.06) 20 (8.94, 15.14) (351.97, 596.06) 21 (9.24, 14.04) (363.78, 552.76) 22 (9.24, 13.28) (363.78, 522.83) 23 (9.24, 12.51) (363.78,492.52) 24 (9.24, 11.75) (363.78, 462.60) 25 (9.24,10.99) (363.78, 432.68) 26 (9.24,10.23) (363.78, 402.76) 27 (9.24, 9.47) (363.78, 372.83) 28 (9.24, 8.70) (363.78, 342.52) 29 (9.24, 7.94) (363.78, 312.60) 30 (9.24, 7.18) (363.78, 282.68) 31 (9.24, 6.42) (363.78, 252.76) 32 (9.24,5.66) (363.78, 222.83) Document Number: 002-11264 Rev. *G Page 9 of 47 CYBLE-224110-00 Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-224110-00, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a . . Table 4. Digital Peripheral Capabilities Pad Number Device Port Pin UART SPI I2 C TCPWM[4,5] [5] 1 GND 2 XRES 3 P1.5 4 P1.1 5 P1.0 6 P0.1 7 P0.4 8 P0.5 9 P0.7 10 P1.3 11 VDDR 12 P0.6 13 P1.2 14 VDD 15 P1.4 16 P2.1 CapSense (SCB0_TX) (SCB0_MISO) (SCB0_SCL) (SCB1_SS1) (SCB1_TX) (SCB0_RX) (SCB0_TX) (SCB0_CTS) (SCB1_MISO) (SCB1_SCL) (SCB0_MOSI) (SCB0_SDA) (SCB0_MISO) (SCB0_SCL) (SCB0_SCLK) (SCB1_SS3) (SCB0_RTS) (SCB0_SS0) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (SCB1_SS2) (TCPWM) (SCB0_RX) (SCB0_MOSI) (SCB0_SDA) (SCB0_SS2) (TCPWM) (TCPWM) P2.6 20 P3.0 21 P2.3 22 VREF Reference Voltage Input P3.7 P3.1 27 P3.6 28 P2.5 29 P5.0 30 P5.1 31 P2.4 32 GND[5] Digital Power Supply Input (2.0 V to 3.6 V) 19 26 (TCPWM) (TCPWM) (TCPWM) (TCPWM) 25 (SCB0_SS3) (SCB0_RX) (SCB1_RX) (SCB1_TX) (SCB1_CTS) (SCB0_TX) (SCB1_RTS) P2.2 P3.4 (TCPWM) VDDA P3.5 SWD GPIO (SWDCLK) Radio Power Supply (2.0 V to 3.6 V) 17 23 LCD Ground Connection External Reset Hardware Connection Input 18 24 WCO ECO Out OUT Analog Power Supply Input (2.0 V to 3.6 V) (SCB0_SDA) (SCB1_SDA) (SCB1_SCL) (SCB0_SCL) (SCB1_RX) (SCB1_SS0) (SCB1_SDA) (SCB1_TX) (SCB1_SCLK) (SCB1_SCL) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (TCPWM) (TCPWM3_P) (TCPWM3_N) (TCPWM) (SWDIO) Ground Connection Notes 4. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions. 5. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system. Document Number: 002-11264 Rev. *G Page 10 of 47 CYBLE-224110-00 . Table 5. Analog Peripheral Capabilities Pad Number Device Port Pin 1 GND[5] Ground Connection 2 XRES External Reset Hardware Connection Input 3 P1.5 4 P1.1 5 P1.0 6 P0.1 7 P0.4 8 P0.5 SARMUX OPAMP (CTBm1_OA1_INP) (CTBm1_OA0_INN) (CTBm1_OA0_INP) (COMP1_INP) (COMP1_INN) 9 P0.7 10 P1.3 (CTBm1_OA1_OUT) 11 VDDR Radio Power Supply (2.0 V to 3.6 V) 12 P0.6 13 P1.2 14 VDD 15 P1.4 16 P2.1 17 VDDA 18 P2.2 19 P2.6 20 P3.0 21 P2.3 22 VREF 23 P3.4 24 P3.5 25 P3.7 26 P3.1 27 P3.6 28 P2.5 29 P5.0 30 P5.1 31 P2.4 32 GND Document Number: 002-11264 Rev. *G LPCOMP (CTBm1_OA0_OUT) Digital Power Supply Input (2.0 V to 3.6 V) (CTBm1_OA1_INN) (CTBm0_OA0_INN) Analog Power Supply Input (2.0 V to 3.6 V) (CTBm0_OA0_OUT) (CTBm0_OA0_INP) (CTBm0_OA1_OUT) Reference Voltage Input (Optional) (CTBm0_OA1_INP) (CTBm0_OA1_INN) Ground Connection Page 11 of 47 CYBLE-224110-00 Power Supply Connections and Recommended External Components Power Connections External Component Recommendation The CYBLE-224110-00 contains three power supply connections: VDD, VDDA, and VDDR. The VDD and VDDA connections supply power for the digital and analog device operation respectively. VDDR supplies power for the device radio and PA/LNA. In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. VDD, VDDA, and VDDR accept a supply range of 2.0 V to 3.6 V. These specifications can be found in Table 13. The maximum power supply ripple for all power connections on the module is 100 mV, as shown in Table 11. Figure 7 details the recommended host schematic options for a single supply scenario. The use of one or three ferrite beads will depend on the specific application and configuration of the CYBLE-224110-00. The power supply ramp rate of VDD and VDDA must be equal to or greater than that of VDDR when the radio is used. Figure 8 details the recommended host schematic for an independent supply scenario. Connection Options The recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). Two connection options are available for any application: 1. Single supply: Connect VDD, VDDA, and VDDR to the same supply. 2. Independent supply: Power VDD, VDDA, and VDDR separately. Figure 7. Recommended Host Schematic Options for a Single Supply Option Single Ferrite Bead Option Document Number: 002-11264 Rev. *G Three Ferrite Bead Option Page 12 of 47 CYBLE-224110-00 Figure 8. Recommended Host Schematic for an Independent Supply Option Document Number: 002-11264 Rev. *G Page 13 of 47 CYBLE-224110-00 The CYBLE-224110-00 schematic is shown in Figure 9. Figure 9. CYBLE-224110-00 Schematic Diagram Document Number: 002-11264 Rev. *G Page 14 of 47 CYBLE-224110-00 Critical Components List Table 6 details the critical components used in the CYBLE-224110-00 module. Table 6. Critical Component List Component Reference Designator Silicon U1 Description 76-pin WLCSP PSoC 4 with BLE Crystal Y1 24.000 MHz, 10PF Crystal Y2 32.768 kHz, 12.5PF Antenna Design Table 7 details the antenna used on the CYBLE-224110-00 module. The Cypress module performance improves many of these characteristics. For more information, see Table 12. Table 7. Chip Antenna Specifications Item Description Chip Antenna Manufacturer Johanson Technology Inc. Chip Antenna Part Number 2450AT18B100 Frequency Range 2400-2500 MHz Peak Gain 0.5-dBi typical Average Gain -0.5-dBi typical Return Loss 9.5-dB minimum Power Amplifier (PA) and Low Noise Amplifier (LNA) Table 8 details the PA/LNA that is used on the CYBLE-224110-00 module. For more information, see Table 12. Table 8. Power Amplifier/Low Noise Amplifier Details Item Description PA/LNA Manufacturer Skyworks Inc. PA/LNA Part Number SE2438T Power Supply Range 2.0 V ~ 3.6 V Table 9 details the power consumption of the integrated PA/LNA used on the CYBLE-224110-00 module. Table 9 only details the current consumption of the SE2438T PA/LNA. VDDR = 3 V, TA = +25 C, measured on the SE2438T evaluation board, unless otherwise noted. Table 9. Power Amplifier/Low Noise Amplifier Current Consumption Specifications Min Typ Max Units Total supply current ICC_Tx14 Total supply current ICC_Tx12 Parameter Symbol Tx mode POUT = +14 dBm Test Condition - 33 - mA Tx mode POUT = +12 dBm - 25 - mA Total supply current ICC_Tx10 Quiescent current ICQ_Tx Tx mode POUT = +10 dBm - 20 - mA No RF - 6 - mA Total supply current ICC_RXHG Total supply current ICC_RXLG Rx Low Noise Amplifier (LNA) High Gain mode - 5.5 - mA Rx LNA Low Gain mode - 2.7 - mA Total supply current ICC_RXBypass Sleep supply current ICC_OFF Rx Bypass mode - - 10 A No RF - 0.05 1.0 A Document Number: 002-11264 Rev. *G Page 15 of 47 CYBLE-224110-00 Enabling Extended Range Feature The CYBLE-224110-00 module comes with an integrated power amplifier/low-noise amplifier to allow for extended communication range of up to 400 meters full line-of-sight. This section describes the firmware steps required to enable extended range operation of the CYBLE-224110-00 module. For detailed step-by-step instructions, refer to Appendix B.2.3.2 in the application note, Getting Started with EZ-BLE Module. The PA/LNA integrated on the CYBLE-224110-00 module must be configured properly in order for the module to function as intended. In cases which require radio transmission without extended range functionality, the PA/LNA must be set to Bypass mode in order to ensure that the RF signal reaches the antenna. If the PA/LNA is disabled instead, the antenna will be unable to radiate any signal. Please refer to Table 10 for the correct CSD and CPS configurations for PA/LNA Bypass mode. The Skyworks SE2438T PA/LNA is controlled by PSoC4 BLE and uses four pins: 1.Two pins for the radio enable (CPS - P0[2], CSD - P0[3]). The CPS and CSD pins are controlled in the firmware application code of the CYBLE-224110-00. 2.One pin to control the PA enable (P3[2]). The PA enable pin is controlled directly by the BLE Link Layer. 3.One pin to control the LNA enable (P3[3]). The LNA enable pin is controlled directly by the BLE Link Layer. 4.Ensure that the PSoC(R) 4 BLE silicon device "Adv/Scan TX Power Level (dBm)" and "Connection TX Power Level (dBm)" in the BLE component are both set to -6 dBm[6]. To enable the extended range functionality, follow these steps: 1."Drag and drop two "Digital Output Pin" components from the Component Catalog to the schematic page in PSoC Creator 2."Double-click the pins and rename them as CPS and CSD. The HW connection option in the component configuration should be unchecked as these are Firmware GPIOs. 3."To configure the CPS and CSD pins, open your project's Design-Wide Resources file (for example, "Project_Name.cydwr") from your Workspace Explorer and click the "Pins" tab. The "Pins" tab is used to select the physical device connections for the outputs (CPS, CSD). These pins are connected to the enable pins of the Skyworks SE2438T Power Amplifier. For the extended range operation to function, it is required to configure the CPS and CSD pins to P0[2] and P0[3] respectively. 4."Open your project's main.c file and write the following code to define the register at the top of the code. /* define the test register to switch the PA/LNA hardware control pins */ #define CYREG_SRSS_TST_DDFT_CTRL 0x40030008 5.Locate/add the event "CYBLE_EVT_STACK_ON" in the application code and insert the following four lines of code to enable the Skyworks SE2438T. /* Mandatory events to be handled by BLE application code */ case CYBLE_EVT_STACK_ON: /* Enable the Skyworks SE2438T PA/LNA */ CSD_Write(1); CPS_Write(1); /* Configure the Link Layer to automatically switch PA control pin P3[2] and LNA control pin P3[3] */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_RF_CONFIG), 0x0331); CY_SET_XTND_REG32((void CYFAR *)(CYREG_SRSS_TST_DDFT_CTRL), 0x80000302); Note 6. The CYBLE-224110-00 module is certified for FCC, ISED, CE, MIC, and KC regulations at an output power of +9.5 dBm. To achieve this output power, RFO2 (PSoC 4 BLE silicon PA level) must be set to the -6 dBm setting in firmware. Settings higher than this will result in higher output power than specified in the CYBLE-224110-00 certifications. Document Number: 002-11264 Rev. *G Page 16 of 47 CYBLE-224110-00 Power Saving Measures with PA/LNA Operation The section will describe power saving measures available for controlling the integrated PA/LNA on the CYBLE-224110-00 module. Table 10 lists the states available through via the CSD and CPS logic control signals. Table 10. PA/LNA Logic Controls and Power Modes PA/LNA Mode CSD (P0[3]) Logic State CPS (P0[2]) Logic State Description 0 0 0 All Off. Lowest Power Mode PA and LNA are off 1 0 1 Standby Mode Recommended mode for low power operation 2 1 0 TX and RX Bypass Mode 3 1 1 High Power TX and High Gain RX Power Optimization Tips with Extended Range Functionality If left in High Power TX and High Gain RX mode continuously, the integrated PA/LNA on the CYBLE-224110-00 module will draw more current than desired. Optimizing the average power consumption of the CYBLE-224110-00 module can be accomplished via the CSD and CPS logic control signals explained in Enabling Extended Range Feature and shown in Table 10. To minimize power consumption of a BLE solution that is using the extended range feature of the CYBLE-224110-00, the PA/LNA should be set to either Mode 0 (All Off) or Mode 1 (Standby). Transitioning the PA/LNA from Mode 3 (High Power and High Gain) to either Mode 0 or 1 needs to be taken care of in the application firmware. The recommendations below should be followed when changing modes of the PA/LNA on the CYBLE-224110-00 module. 1.To set the PA/LNA to a low power mode, either Power Mode 0 or Power Mode 1 should be entered just before the BLE application firmware transitions the PSoC(R) 4 BLE silicon device to a Sleep or Deep Sleep mode. To execute the transition of the PA/LNA to a lower power mode, the following code should be used in the low power routine in the application firmware. Power Mode 0 and Power Mode 1 PA/LNA commands are both shown. /* Set the Skyworks SE2438T PA/LNA to Power Mode 0 (All Off)*/ CSD_Write(0); CPS_Write(0); /* Set the Skyworks SE2438T PA/LNA to Power Mode 1 (Standby)*/ CSD_Write(0); CPS_Write(1); 2.When the BLE system is transitioning to Active mode (that is, waking from low power mode) and extended range functionality is required, it is necessary to enable the PA/LNA to Power Mode 3. Enabling the PA/LNA should be the first action completed when the PSoC(R) 4 BLE silicon device transitions from a low power mode to active mode. Enabling the PA/LNA to Power Mode 3 can be completed using the following commands in the wakeup routine of the application firmware. /* Set the Skyworks SE2438T PA/LNA to Power Mode 3 (High Power and High Gain)*/ CSD_Write(1); CPS_Write(1); 3.Power Mode 2 (TX/RX Bypass) is not recommended for typical low power mode use. The Bypass mode should be considered if a transition from Extended Range functionality to short-range communication is desired on-the-fly. Transitions from Active mode to Bypass mode are only recommended after a BLE event has completed and no RF activity is in process. Document Number: 002-11264 Rev. *G Page 17 of 47 CYBLE-224110-00 Electrical Specification Table 11 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 11. CYBLE-224110-00 Absolute Maximum Ratings Parameter Description Min Typ Max Units Details/Conditions VDD_ABS VDD, VDDA and VDDR supply relative to VSS (VSSD = VSSA) -0.3 - 3.6 V Restricted by SE2438T VCCD_ABS Direct digital core voltage input relative to VSSD -0.5 - 1.95 V Absolute maximum VDD_RIPPLE Maximum power supply ripple for VDD, VDDA and VDDR input voltage - - 100 mV VGPIO_ABS GPIO voltage -0.5 - VDD +0.5 V Absolute maximum IGPIO_ABS Maximum current per GPIO -25 - 25 mA Absolute maximum IGPIO_injection GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS -0.5 - 0.5 mA Absolute maximum current injected per pin LU Pin current for latch up -200 200 mA - Max Units Details/Conditions Configurable via register settings. PA active. dBm RFO2 = -6 dBm PA/LNA active. 3.0-V supply Ripple frequency of 100 kHz to 750 kHz Table 12 details the RF characteristics for the Cypress BLE module. Table 12. CYBLE-224110-00 RF Performance Characteristics Parameter Description Min Typ RF output power on ANT PA active -3.5 0 9.5 RFO2 RF output power on ANT PA bypassed -18 0 3 PSoC 4 BLE Silicon. ConfigdBm urable via register settings. PA in bypass mode. RXS1 RF receive sensitivity on ANT LNA active - -95 - dBm Measured value RXS2 RF receive sensitivity on ANT LNA bypassed - -87 - dBm Measured value RFO1 [7] FR Module frequency range 2402 - 2480 MHz - GP Peak gain - 0.5 - dBi - RL Return loss - -10 - dB - Table 13 through Table 55 list the module-level electrical characteristics for the CYBLE-224110-00. All specifications are valid for - 40 C TA 105 C, except where noted. Specifications are valid for 2.0 V to 3.6 V, except where noted. Table 13. CYBLE-224110-00 DC Specifications Parameter VDD Description Power supply input voltage (VDD, VDDA, VDDR) Min Typ Max Units 2.0 - 3.6 V Details/Conditions Restricted by SE2438T VDDR VDD Active Mode, VDD = 2.0 V to 3.6 V T = 25 C, VDD = 3.3 V IDD3 Execute from flash; CPU at 3 MHz - 1.7 - mA IDD4 Execute from flash; CPU at 3 MHz - - - mA T = -40 C to 105 C Note 7. The CYBLE-224110-00 module is certified for FCC, ISED, CE, MIC, and KC regulations at an output power of +9.5 dBm. To achieve this output power, RFO2 must be set to the -6 dBm setting in firmware. Settings higher than this will result in higher output power than specified in the CYBLE-224110-00 certifications. Document Number: 002-11264 Rev. *G Page 18 of 47 CYBLE-224110-00 Table 13. CYBLE-224110-00 DC Specifications (continued) Parameter Description Min Typ Max Units Details/Conditions T = 25 C, VDD = 3.3 V IDD5 Execute from flash; CPU at 6 MHz - 2.5 - mA IDD6 Execute from flash; CPU at 6 MHz - - - mA T = -40 C to 105 C IDD7 Execute from flash; CPU at 12 MHz - 4 - mA IDD8 Execute from flash; CPU at 12 MHz - - - mA T = -40 C to 105 C IDD9 Execute from flash; CPU at 24 MHz - 7.1 - mA IDD10 Execute from flash; CPU at 24 MHz - - - mA T = -40 C to 105 C IDD11 Execute from flash; CPU at 48 MHz - 13.4 - mA IDD12 Execute from flash; CPU at 48 MHz - - - mA T = -40 C to 105 C - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz T = 25 C, VDD = 3.3 V T = 25 C, VDD = 3.3 V T = 25 C, VDD = 3.3 V Sleep Mode, VDD and VDDR = 2.0 V to 3.6 V, PA/LNA in All Off mode IDD13 IMO on - Sleep Mode, VDD and VDDR = 2.0 V to 3.6 V, PA/LNA in All Off mode IDD14 ECO on - Deep-Sleep Mode, VDD and VDDR = 2.0 V to 3.6 V, PA/LNA in All Off mode IDD15 WDT with WCO on - 2.3 - A T = 25 C, VDD = 3.3 V IDD16 WDT with WCO on - - - A T = -40 C to 105 C IDD18 WDT with WCO on - - - A T = -40 C to 105 C Hibernate Mode, VDD and VDDR = 2.0 V to 3.6 V, PA/LNA in All Off mode IDD27 GPIO and reset active - 150 - nA T = 25 C, VDD = 3.3 V IDD28 GPIO and reset active - - - nA T = -40 C to 105 C Stop Mode, VDD = VDDR = 2.0 V to 3.6 V, PA/LNA in All Off IDD33 Stop-mode current (VDD) - 20 - nA T = 25 C, VDD = 3.3 V IDD34 Stop-mode current (VDDR) - 540 -- nA T = 25 C, VDDR = 3.3 V IDD35 Stop-mode current (VDD) - - - nA T = -40 C to 105 C nA T = -40 C to 105 C, VDDR = 2.0 V to 3.6 V IDD36 Stop-mode current (VDDR) - - - Min DC Typ - Max 48 Table 14. AC Specifications Parameter FCPU CPU frequency Description TSLEEP Wakeup from Sleep mode - 0 - TDEEPSLEEP Wakeup from Deep-Sleep mode - - 25 THIBERNATE Wakeup from Hibernate mode - - 2 TSTOP Wakeup from Stop mode - - 2 Document Number: 002-11264 Rev. *G Units Details/Conditions MHz 2.0 V VDD 3.6 V Guaranteed by characteris zation 24-MHz IMO. Guaranteed s by characterization Guaranteed by characterims zation Guaranteed by characterims zation Page 19 of 47 CYBLE-224110-00 GPIO Table 15. GPIO DC Specifications Parameter VIH[8] Description Typ Max Units Input voltage HIGH threshold 0.7 x VDD - - V LVTTL input, 2.0 V VDD 2.7 V 0.7 x VDD - - V LVTTL input, 2.7 V VDD 3.6 V 2.0 - - V - - 0.3 x VDD V Input voltage LOW threshold VIL Min Details/Conditions CMOS input - - CMOS input LVTTL input, 2.0 V VDD 2.7 V - - 0.3 x VDD V - LVTTL input, 2.7 V VDD 3.6 V - - 0.8 V - VOH Output voltage HIGH level VDD -0.6 - - V IOH = 4 mA at 3.3-V VDD VOL Output voltage LOW level - - 0.6 V IOL = 8 mA at 3.3-V VDD RPULLUP Pull-up resistor 3.5 5.6 8.5 k - RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k - IIL Input leakage current (absolute value) - - 2 nA IIL_CTBM Input leakage on CTBm input pins - - 4 nA CIN Input capacitance - - 7 pF VHYSTTL Input hysteresis LVTTL 25 40 - mV VHYSCMOS Input hysteresis CMOS 0.05 x VDD - - 1 - IDIODE Current through protection diode to VDD/VSS - - 100 A - ITOT_GPIO Maximum total source or sink chip current - - 200 mA - 25 C, VDD = 3.3 V - - 2.7 V VDD 3.6 V Note 8. VIH must not exceed VDD + 0.2 V. Document Number: 002-11264 Rev. *G Page 20 of 47 CYBLE-224110-00 Table 16. GPIO AC Specifications Parameter Description Min Typ Max Units Details/Conditions TRISEF Rise time in Fast-Strong mode 2 - 12 ns 3.3-V VDD, CLOAD = 25 pF TFALLF Fall time in Fast-Strong mode 2 - 12 ns 3.3-V VDD, CLOAD = 25 pF TRISES Rise time in Slow-Strong mode 10 - 60 ns 3.3-V VDD, CLOAD = 25 pF TFALLS Fall time in Slow-Strong mode 10 - 60 ns 3.3-V VDD, CLOAD = 25 pF FGPIOUT1 GPIO FOUT; 3.3 V VDD 3.6 V Fast-Strong mode - - 33 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT2 GPIO FOUT; 2.0 VVDD 3.3 V Fast-Strong mode - - 16.7 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT3 GPIO FOUT; 3.3 V VDD 3.6 V Slow-Strong mode - - 7 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT4 GPIO FOUT; 2.0 V VDD 3.3 V Slow-Strong mode - - 3.5 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOIN GPIO input operating frequency 2.0 V VDD 3.6 V - - 48 MHz 90/10% VIO Min Typ Max Units Table 17. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Parameter Description Details/Conditions IIL Input leakage (absolute value). VIH > VDD - - 10 A 25C, VDD = 0 V, VIH = 3.0 V VOL Output voltage LOW level - - 0.4 V IOL = 20 mA, VDD > 2.9 V Table 18. OVT GPIO AC Specifications (P5_0 and P5_1 Only) Parameter Description Min Typ Max Units Details/Conditions TRISE_OVFS Output rise time in Fast-Strong mode 1.5 - 12 ns 25-pF load, 10%-90%, VDD=3.3 V TFALL_OVFS Output fall time in Fast-Strong mode 1.5 - 12 ns 25-pF load, 10%-90%, VDD=3.3 V TRISESS Output rise time in Slow-Strong mode 10 - 60 ns 25-pF load, 10%-90%, VDD = 3.3 V TFALLSS Output fall time in Slow-Strong mode 10 - 60 ns 25-pF load, 10%-90%, VDD = 3.3 V FGPIOUT1 GPIO FOUT; 3.3 V VDD 3.6 V Fast-Strong mode - - 24 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT2 GPIO FOUT; 2.0 V VDD 3.3 V Fast-Strong mode - - 16 MHz 90/10%, 25-pF load, 60/40 duty cycle Document Number: 002-11264 Rev. *G Page 21 of 47 CYBLE-224110-00 XRES Table 19. XRES DC Specifications Parameter Description Min Typ Max Units Details/Conditions VIH Input voltage HIGH threshold 0.7 x VDDD - - V CMOS input VIL Input voltage LOW threshold - - 0.3 x VDD V CMOS input RPULLUP Pull-up resistor 3.5 5.6 8.5 k - CIN Input capacitance - 3 - pF - VHYSXRES Input voltage hysteresis - 100 - mV - IDIODE Current through protection diode to VDD/VSS - - 100 A - Min Typ Max Units Details/Conditions 1 - - s - Min Typ Max Units Details/Conditions 1300 A Table 20. XRES AC Specifications Parameter TRESETWIDTH Description Reset pulse width Analog Peripherals Opamp Table 21. Opamp Specifications Parameter Description IDD (Opamp Block Current. VDD = 2.0 V. No Load) IDD_HI Power = high - 1000 IDD_MED Power = medium - 500 - A IDD_LOW Power = low - 250 350 A GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V) GBW_HI Power = high 6 - - MHz GBW_MED Power = medium 4 - - MHz GBW_LO Power = low - 1 - MHz 10 - - mA IOUT_MAX_MID Power = medium 10 - - mA IOUT_MAX_LO - 5 - mA IOUT_MAX (VDDA 2.7 V, 500 mV from Rail) IOUT_MAX_HI Power = high Power = low VOUT (VDDA 2.7 V) VOUT_1 Power = high, ILOAD=10 mA 0.5 - VDDA - 0.5 V VOUT_2 Power = high, ILOAD=1 mA 0.2 - VDDA - 0.2 V VOUT_3 Power = medium, ILOAD=1 mA 0.2 - VDDA - 0.2 V VOUT_4 Power = low, ILOAD=0.1 mA 0.2 - VDDA - 0.2 V VOS_TR Offset voltage, trimmed 1 0.5 1 mV High mode VOS_TR Offset voltage, trimmed - 1 - mV Medium mode VOS_TR Offset voltage, trimmed - 2 - mV Low mode VOS_DR_TR Offset voltage drift, trimmed -10 3 10 V/C High mode VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Medium mode VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Low mode CMRR DC 65 70 - dB VDD = 3.6 V, High-power mode PSRR At 1 kHz, 100-mV ripple 70 85 - dB VDD = 3.6 V Document Number: 002-11264 Rev. *G Page 22 of 47 CYBLE-224110-00 Table 21. Opamp Specifications (continued) Parameter Description Min Typ Max Units Details/Conditions Noise VN1 Input referred, 1 Hz-1 GHz, power = high - 94 - Vrms VN2 Input referred, 1 kHz, power = high - 72 - nV/rtHz VN3 Input referred, 10 kHz, power = high - 28 - nV/rtHz VN4 Input referred, 100 kHz, power = high - 15 - nV/rtHz CLOAD Stable up to maximum load. Performance specs at 50 pF - - 125 pF Slew_rate Cload = 50 pF, Power = High, VDDA 2.7 V 6 - - V/s T_op_wake From disable to enable, no external RC dominating - 300 - s 150 - ns Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.) TPD1 Response time; power = high TPD2 Response time; power = medium - 400 - ns TPD3 Response time; power = low - 2000 - ns Vhyst_op Hysteresis - 10 - mV - Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5 V) GBW_DS Gain bandwidth product - 50 - kHz IDD_DS Current - 15 - A Vos_DS Offset voltage - 5 - mV Vos_dr_DS Offset voltage drift - 20 - V/C Vout_DS Output voltage 0.2 - VDD - 0.2 V Vcm_DS Common mode voltage 0.2 - VDD - 1.8 V Min Typ Max Units - - 10 mV Table 22. Comparator DC Specifications Parameter Description VOFFSET1 Input offset voltage, Factory trim Details/Conditions VOFFSET2 Input offset voltage, Custom trim - - 6 mV VOFFSET3 Input offset voltage, ultra-low-power mode - 12 - mV VHYST Hysteresis when enabled - 10 35 mV VICM1 Input common mode voltage in normal mode 0 - VDD - 0.1 V VICM2 Input common mode voltage in low-power mode 0 - VDD V VICM3 Input common mode voltage in ultra low-power mode 0 - VDD -1.15 V CMRR Common mode rejection ratio 50 - - dB VDD 2.7 V CMRR Common mode rejection ratio 42 - - dB VDD 2.7 V ICMP1 Block current, normal mode - - 400 A ICMP2 Block current, low-power mode - - 100 A ICMP3 Block current in ultra-low-power mode - 6 - A ZCMP DC input impedance of comparator 35 - - M Document Number: 002-11264 Rev. *G Modes 1 and 2 Page 23 of 47 CYBLE-224110-00 Table 23. Comparator AC Specifications Parameter Description Min Typ Max Units Details/Conditions TRESP1 Response time, normal mode, 50-mV overdrive - 38 - ns 50-mV overdrive TRESP2 Response time, low-power mode, 50-mV overdrive - 70 - ns 50-mV overdrive TRESP3 Response time, ultra-low-power mode, 50-mV overdrive - 2.3 - s 200-mV overdrive VDD 2.6 V for Temp < 0 C VDD 2.0 V for Temp < 0 C Min -5 Typ 1 Max 5 Units Details/Conditions C -40 to +85 C Temperature Sensor Table 24. Temperature Sensor Specifications Parameter TSENSACC Description Temperature-sensor accuracy SAR ADC Table 25. SAR ADC DC Specifications Min Typ Max Units A_RES Parameter Resolution Description - - 12 bits A_CHNIS_S Number of channels - single-ended - - 8 8 full-speed[9] A-CHNKS_D Number of channels - differential - - 4 Diff inputs use neighboring I/Os[9] A-MONO Monotonicity - - - Yes A_GAINERR Gain error - - 0.1 % With external reference A_OFFSET Input offset voltage - - 2 mV Measured with 1-V VREF A_ISAR Current consumption - - 1 mA A_VINS Input voltage range - single-ended VSS - VDDA V A_VIND Input voltage range - differential VSS - VDDA V A_INRES Input resistance - - 2.2 k A_INCAP Input capacitance - - 10 pF VREFSAR Trimmed internal reference to SAR -1 - 1 % Details/Conditions Percentage of Vbg (1.024 V) Table 26. SAR ADC AC Specifications Parameter Description Min Typ Max Units dB A_PSRR Power-supply rejection ratio 70 - - A_CMRR Common-mode rejection ratio 66 - - dB A_SAMP Sample rate - - 1 Msps Fsarintref SAR operating speed without external ref. bypass - - 100 ksps Details/ Conditions Measured at 1-V reference 12-bit resolution Note 9. A maximum of eight single-ended ADC Channels can be accomplished only if the AMUX Buses are not being used for other funcitonality (e.g. CapSense). If the AMUX Buses are being used for other functionality, then the maximum number of single-ended ADC channels is six. Similarly, if the AMUX Buses are being used for other functionalty, then the maximum number of differential ADC channels is three. Document Number: 002-11264 Rev. *G Page 24 of 47 CYBLE-224110-00 Table 26. SAR ADC AC Specifications (continued) Parameter Description Min Typ Max Units 65 - - dB Details/ Conditions FIN = 10 kHz A_SNR Signal-to-noise ratio (SNR) A_BW Input bandwidth without aliasing - - A_SAMP/2 kHz A_INL Integral nonlinearity. VDD = 2.0 V to 3.6 V, 1 Msps -1.7 - 2 LSB VREF = 1 V to VDD A_INL Integral nonlinearity. VDD = 2.0 V to 3.6 V, 1 Msps -1.5 - 1.7 LSB VREF = 1.71 V to VDD A_INL Integral nonlinearity. VDD = 2.0 V to 3.6 V, 500 ksps -1.5 - 1.7 LSB VREF = 1 V to VDD A_dnl Differential nonlinearity. VDD = 2.0 V to 3.6 V, 1 Msps -1 - 2.2 LSB VREF = 1 V to VDD A_DNL Differential nonlinearity. VDD = 2.0 V to 3.6 V, 1 Msps -1 - 2 LSB VREF = 1.71 V to VDD A_DNL Differential nonlinearity. VDD = 2.0 V to 3.6 V, 500 ksps -1 - 2.2 LSB VREF = 1 V to VDD A_THD Total harmonic distortion - - -65 dB Description Min Typ Max Units VCSD Voltage range of operation 2.0 - 3.6 V IDAC1 DNL for 8-bit resolution -1 - 1 LSB IDAC1 INL for 8-bit resolution -3 - 3 LSB IDAC2 DNL for 7-bit resolution -1 - 1 LSB IDAC2 INL for 7-bit resolution -3 - 3 LSB SNR Ratio of counts of finger to noise 5 - - Ratio IDAC1_CRT1 Output current of IDAC1 (8 bits) in High range - 612 - A IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low range - 306 - A IDAC2_CRT1 Output current of IDAC2 (7 bits) in High range - 305 - A IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low range - 153 - A FIN = 10 kHz CSD CSD Block Specifications Parameter Document Number: 002-11264 Rev. *G Details/ Conditions Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scan Page 25 of 47 CYBLE-224110-00 Digital Peripherals Timer Table 27. Timer DC Specifications Parameter ITIM1 Description Block current consumption at 3 MHz Min - Typ - Max 46 Units A Details/Conditions 16-bit timer, 105 C ITIM2 Block current consumption at 12 MHz - - 137 A 16-bit timer, 105 C ITIM3 Block current consumption at 48 MHz - - 560 A 16-bit timer, 105 C Table 28. Timer AC Specifications Parameter TTIMFREQ Description Operating frequency Min FCLK Typ - Max 48 Units MHz Details/Conditions TCAPWINT Capture pulse width (internal) 2 x TCLK - - ns TCAPWEXT Capture pulse width (external) 2 x TCLK - - ns TTIMRES Timer resolution TCLK - - ns TTENWIDINT Enable pulse width (internal) 2 x TCLK - - ns TTENWIDEXT Enable pulse width (external) 2 x TCLK - - ns TTIMRESWINT Reset pulse width (internal) 2 x TCLK - - ns TTIMRESEXT Reset pulse width (external) 2 x TCLK - - ns 16-bit counter 16-bit counter Counter Table 29. Counter DC Specifications Parameter ICTR1 Description Block current consumption at 3 MHz Min - Typ - Max 42 ICTR2 Block current consumption at 12 MHz - - 130 Units A A ICTR3 Block current consumption at 48 MHz - - 535 A Details/Conditions 16-bit counter Table 30. Counter AC Specifications Parameter TCTRFREQ Description Operating frequency Min FCLK Typ - Max 48 Units MHz TCTRPWINT Capture pulse width (internal) 2 x TCLK - - ns TCTRPWEXT Capture pulse width (external) 2 x TCLK - - ns TCTRES Counter Resolution TCLK - - ns TCENWIDINT Enable pulse width (internal) 2 x TCLK - - ns TCENWIDEXT Enable pulse width (external) 2 x TCLK - - ns TCTRRESWINT Reset pulse width (internal) 2 x TCLK - - ns TCTRRESWEXT Reset pulse width (external) 2 x TCLK - - ns Document Number: 002-11264 Rev. *G Details/Conditions Page 26 of 47 CYBLE-224110-00 Pulse Width Modulation (PWM) Table 31. PWM DC Specifications Parameter Description Min Typ Max Units Details/Conditions IPWM1 Block current consumption at 3 MHz - - 42 A 16-bit PWM IPWM2 Block current consumption at 12 MHz - - 130 A 16-bit PWM IPWM3 Block current consumption at 48 MHz - - 535 A 16-bit PWM Min Typ Max Units Table 32. PWM AC Specifications Parameter Description TPWMFREQ Operating frequency FCLK - 48 MHz TPWMPWINT Pulse width (internal) 2 x TCLK - - ns TPWMEXT Pulse width (external) 2 x TCLK - - ns TPWMKILLINT Kill pulse width (internal) 2 x TCLK - - ns TPWMKILLEXT Kill pulse width (external) 2 x TCLK - - ns TPWMEINT Enable pulse width (internal) 2 x TCLK - - ns TPWMENEXT Enable pulse width (external) 2 x TCLK - - ns TPWMRESWINT Reset pulse width (internal) 2 x TCLK - - ns TPWMRESWEXT Reset pulse width (external) 2 x TCLK - - ns Details/Conditions LCD Direct Drive Table 33. LCD Direct Drive DC Specifications Parameter ILCDLOW Description Operating current in low-power mode CLCDCAP LCD capacitance per segment/common driver Long-term segment offset LCDOFFSET ILCDOP1 LCD system operating current VBIAS = 3.3 V Min - Typ 17.5 Max - Units A - 500 5000 pF - 20 - mV - 2 - mA Min 10 Typ 50 Max 150 Units Hz Details/Conditions 16 x 4 small segment display at 50 Hz 32 x 4 segments 50 Hz at 25 C Table 34. LCD Direct Drive AC Specifications Parameter FLCD Description LCD frame rate Document Number: 002-11264 Rev. *G Details/Conditions Page 27 of 47 CYBLE-224110-00 Serial Communication Table 35. Fixed I2C DC Specifications Parameter II2C1 Description Min Typ Details/Conditions - Max 50 Units - A - Block current consumption at 100 kHz II2C2 Block current consumption at 400 kHz - - 155 A - II2C3 Block current consumption at 1 Mbps - - 390 A - - - 1.4 A - Min - Typ - Max 400 Units kHz Details/Conditions Description Min Typ Max Units Details/Conditions IUART1 Block current consumption at 100 kbps - - 55 A - IUART2 Block current consumption at 1000 kbps - - 312 A - Min - Typ - Max 1 Units Mbps Details/Conditions - II2C4 2 I C enabled in Deep-Sleep mode Table 36. Fixed I2C AC Specifications Parameter FI2C1 Description Bit rate Table 37. Fixed UART DC Specifications Parameter Table 38. Fixed UART AC Specifications Parameter FUART Description Bit rate Table 39. Fixed SPI DC Specifications Min Typ Max Units Details/Conditions ISPI1 Parameter Block current consumption at 1 Mbps Description - - 360 A - ISPI2 Block current consumption at 4 Mbps - - 560 A - ISPI3 Block current consumption at 8 Mbps - - 600 A - Min Typ Max Units Details/Conditions - - 8 MHz - Min - Typ - Max 18 Units ns Details/Conditions - 20 - - ns Full clock, late MISO sampling 0 - - ns Referred to Slave capturing edge Table 40. Fixed SPI AC Specifications Parameter FSPI Description SPI operating frequency (master; 6x over sampling) Table 41. Fixed SPI Master Mode AC Specifications Parameter TDMO TDSI THMO Description MOSI valid after SCLK driving edge MISO valid before SCLK capturing edge Full clock, late MISO sampling used Previous MOSI data hold time Table 42. Fixed SPI Slave Mode AC Specifications Parameter TDMI Description MOSI valid before SCLK capturing edge TDSO THSO MISO valid after SCLK driving edge MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V Previous MISO data hold time TSSELSCK SSEL valid to first SCK valid edge TDSO_ext Document Number: 002-11264 Rev. *G Min 40 Typ - Max - Units ns - - 42 + 3 x TSCB ns - - 50 ns 0 - - ns 100 - - ns Details/Conditions Page 28 of 47 CYBLE-224110-00 Memory Table 43. Flash DC Specifications Parameter Description VPE Erase and program voltage Min Typ Max Units Details/Conditions 1.71 - 5.5 V - TWS48 Number of Wait states at 32-48 MHz 2 - - CPU execution from flash TWS32 Number of Wait states at 16-32 MHz 1 - - CPU execution from flash TWS16 Number of Wait states for 0-16 MHz 0 - - CPU execution from flash Min Typ Max Table 44. Flash AC Specifications Parameter Description Units Details/Conditions TROWWRITE[10] TROWERASE[10] Row (block) write time (erase and program) - - 20 ms Row erase time - - 13 ms TROWPROGRAM[10] TBULKERASE[10] TDEVPROG[10] Row program time after erase - - 7 ms - Bulk erase time (256 KB) - - 35 ms - FEND Flash endurance FRET FRET2 FRET3 Total device program time Row (block) = 256 bytes - - - 25 seconds - 100 K - - cycles - Flash retention. TA 55 C, 100 K P/E cycles 20 - - years - Flash retention. TA 85 C, 10 K P/E cycles 10 - - years For 55 C TA 85 C Flash retention. TA 105 C, 10 K P/E cycles 3 - - years For TA 85 C System Resources Power-on-Reset (POR) Table 45. POR DC Specifications Min Typ Max Units Details/Conditions VRISEIPOR Parameter Rising trip voltage Description 0.80 - 1.45 V - VFALLIPOR Falling trip voltage 0.75 - 1.40 V - VIPORHYST Hysteresis 15 - 200 mV - Min Typ Max Units Details/Conditions - - 1 s - Description Min Typ Max Units Details/Conditions VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 - - V - VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 - - V - Min Typ Max Units Details/Conditions 1.1 - - V - Table 46. POR AC Specifications Parameter TPPOR_TR Description Precision power-on reset (PPOR) response time in Active and Sleep modes Table 47. Brown-Out Detect Parameter Table 48. Hibernate Reset Parameter VHBRTRIP Description BOD trip voltage in Hibernate Note 10. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-11264 Rev. *G Page 29 of 47 CYBLE-224110-00 Voltage Monitors (LVD) Table 49. Voltage Monitor DC Specifications Parameter VLVI1 Description LVI_A/D_SEL[3:0] = 0000b Min 1.71 Typ 1.75 Max 1.79 Units V Details/Conditions - VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V - VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V - VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V - VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V - VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V - VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V - VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V - VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V - VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V - VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V - VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V - VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V - VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V - VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V - VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V - LVI_IDD Block current - - 100 A - Min Typ Max Units Details/Conditions - - 1 s - Min Typ Max Units Details/Conditions - - 14 MHz SWDCLK 1/3 CPU clock frequency Table 50. Voltage Monitor AC Specifications Parameter TMONTRIP Description Voltage monitor trip time SWD Interface Table 51. SWD Interface Specifications Parameter Description F_SWDCLK1 3.3 V VDD 3.6 V F_SWDCLK2 2.0 V VDD 3.3 V - - 7 MHz SWDCLK 1/3 CPU clock frequency T_SWDI_SETUP T = 1/f SWDCLK 0.25 x T - - ns - T_SWDI_HOLD 0.25 x T - - ns - T_SWDO_VALID T = 1/f SWDCLK T = 1/f SWDCLK - - 0.5 x T ns - T_SWDO_HOLD 1 - - ns - T = 1/f SWDCLK Document Number: 002-11264 Rev. *G Page 30 of 47 CYBLE-224110-00 Internal Main Oscillator Table 52. IMO DC Specifications Parameter Description Min Typ Max Units Details/Conditions IIMO1 IMO operating current at 48 MHz - - 1000 A - IIMO2 IMO operating current at 24 MHz - - 325 A - IIMO3 IMO operating current at 12 MHz - - 225 A - IIMO4 IMO operating current at 6 MHz - - 180 A - IIMO5 IMO operating current at 3 MHz - - 150 A - Table 53. IMO AC Specifications Description Min Typ Max Units FIMOTOL3 Parameter Frequency variation from 3 to 48 MHz - - 2 % Details/Conditions FIMOTOL3 IMO startup time - - 12 s - Min Typ Max Units Details/Conditions - 0.3 1.05 A - With API-called calibration Internal Low-Speed Oscillator Table 54. ILO DC Specifications Parameter IILO2 Description ILO operating current at 32 kHz Table 55. ILO AC Specifications Min Typ Max Units Details/Conditions TSTARTILO1 Parameter ILO startup time Description - - 2 ms - FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz - Table 56. Recommended ECO Trim Value Parameter ECOTRIM Description 24-MHz trim value (firmware configuration) Value Details/Conditions 0X00005555 Recommended trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Table 57. UDB AC Specifications Parameter Description Min Typ Max Units FMAX-TIMER Max frequency of 16-bit timer in a UDB pair - - 48 MHz FMAX-ADDER Max frequency of 16-bit adder in a UDB pair - - 48 MHz FMAX_CRC Max frequency of 16-bit CRC/PRS in a UDB pair - - 48 MHz - - 48 MHz TCLK_OUT_UDB1 Prop. delay for clock in to data out at 25 C, Typical - 15 - ns TCLK_OUT_UDB2 Prop. delay for clock in to data out, Worst case - 25 - ns Details/Conditions Data Path performance PLD Performance in UDB FMAX_PLD Max frequency of 2-pass PLD function in a UDB pair Clock to Output Performance Document Number: 002-11264 Rev. *G Page 31 of 47 CYBLE-224110-00 Table 58. BLE Subsystem Parameter Description Min Typ Max Units Details/ Conditions RF Receiver Specification RXS, DIRTY RX sensitivity with dirty transmitter - -95 - dBm With LNA active RXS, LOWGAIN RX sensitivity in low-gain mode with idle transmitter - -87 - dBm LNA in bypass mode RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter - -95 - dBm With LNA active PRXMAX Maximum input power -10 -1 - dBm CI1 Cochannel interference, Wanted signal at -67 dBm and Interferer at FRX - 9 21 dB RF-PHY Specification (RCV-LE/CA/06/C) RF-PHY Specification (RCV-LE/CA/03/C) CI2 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 1 MHz - 4 - dB RF-PHY Specification (RCV-LE/CA/03/C) CI3 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 2 MHz - -23 - dB RF-PHY Specification (RCV-LE/CA/03/C) CI4 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 3 MHz - -34 - dB RF-PHY Specification (RCV-LE/CA/03/C) CI5 Adjacent channel interference Wanted Signal at -67 dBm and Interferer at Image frequency (FIMAGE) - -22 - dB RF-PHY Specification (RCV-LE/CA/03/C) CI6 Adjacent channel interference Wanted signal at -67 dBm and Interferer at Image frequency (FIMAGE 1 MHz) - -13 - dB RF-PHY Specification (RCV-LE/CA/03/C) OBB1 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 30-2000 MHz - -16 - dBm RF-PHY Specification (RCV-LE/CA/04/C) OBB2 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2003-2399 MHz - -16 - dBm RF-PHY Specification (RCV-LE/CA/04/C) OBB3 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2484-2997 MHz - -16 - dBm RF-PHY Specification (RCV-LE/CA/04/C) OBB4 Out-of-band blocking, Wanted signal a -67 dBm and Interferer at F = 3000-12750 MHz - -16 - dBm RF-PHY Specification (RCV-LE/CA/04/C) IMD Intermodulation performance Wanted signal at -64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel - -26 - dBm RF-PHY Specification (RCV-LE/CA/05/C) RXSE1 Receiver spurious emission 30 MHz to 1.0 GHz - - -57 dBm 100-kHz measurement bandwidth ETSI EN300 328 V2.1.1 RXSE2 Receiver spurious emission 1.0 GHz to 12.75 GHz - - -47 dBm 1-MHz measurement bandwidth ETSI EN300 328 V2.1.1 Document Number: 002-11264 Rev. *G Page 32 of 47 CYBLE-224110-00 Table 58. BLE Subsystem (continued) Parameter Description Min Typ Max Units Details/ Conditions RF Transmitter Specifications TXP, ACC RF power accuracy - 4 - dB TXP, RANGE RF power control range - 27 - dB TXP, 0dBm Output power, 0-dB Gain setting (PA7) - 0 - dBm PA in All Off mode TXP, MAX Output power, maximum power setting - 9.5 - dBm TXP, MIN - -18 - dBm 185 - - kHz 225 250 275 kHz EO Output power, minimum power setting (PA1) Average frequency deviation for 10101010 pattern Average frequency deviation for 11110000 pattern Eye opening = F2AVG/F1AVG PSoC 4 BLE silicon PA setting of -6 dBm PA/LNA in High Gain/High Sensitivity mode PA/LNA in All Off mode 0.8 - - FTX, ACC Frequency accuracy -150 - 150 kHz FTX, MAXDR Maximum frequency drift -50 - 50 kHz FTX, INITDR Initial frequency drift -20 - 20 kHz FTX, DR Maximum drift rate -20 - 20 In-band spurious emission at 2-MHz offset IBSE2 In-band spurious emission at 3-MHz offset TXSE1 Transmitter spurious emissions (average), <1.0 GHz TXSE2 Transmitter spurious emissions (average), >1.0 GHz RF Current Specifications - - -20 kHz/ 50 s dBm - - -30 dBm - - -55.5 dBm RF-PHY Specification (TRM-LE/CA/05/C) RF-PHY Specification (TRM-LE/CA/05/C) RF-PHY Specification (TRM-LE/CA/05/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/03/C) RF-PHY Specification (TRM-LE/CA/03/C) FCC-15.247 - - -41.5 dBm FCC-15.247 IRX Receive current in normal mode - 18.7 - mA IRX_RF Radio receive current in normal mode - 16.4 - mA IRX, HIGHGAIN Receive current in high-gain mode - 21.5 - mA ITX, 3dBm TX current at 3-dBm setting (PA10) - 20 - mA ITX, 0dBm TX current at 0-dBm setting (PA7) - 16.5 - mA ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) - 15.6 - mA ITX_RF, 0dBm Radio TX current at 0 dBm excluding Balun loss - 14.2 - mA Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled Guaranteed by design simulation F2AVG F1AVG IBSE1 Document Number: 002-11264 Rev. *G Page 33 of 47 CYBLE-224110-00 Table 58. BLE Subsystem (continued) Parameter Description Min Typ Max Units Details/ Conditions Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled Silicon Radio only, PA/LNA disabled TXP: +9.5 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange PA/LNA active TXP: +9.5 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange PA/LNA active ITX,-3dBm TX current at -3-dBm setting (PA4) - 15.5 - mA ITX,-6dBm TX current at -6-dBm setting (PA3) - 14.5 - mA ITX,-12dBm TX current at -12-dBm setting (PA2) - 13.2 - mA ITX,-18dBm TX current at -18-dBm setting (PA1) - 12.5 - mA Iavg_1sec, +9.5dBm Average current at 1-second BLE connection interval - 26.3 - A Iavg_4sec, +9.5dBm Average current at 4-second BLE connection interval - 14.3 - A 2400 - 2482 MHz General RF Specifications FREQ RF operating frequency CHBW Channel spacing - 2 - MHz DR On-air data rate - 1000 - kbps IDLE2TX BLE.IDLE to BLE. TX transition time - 120 140 s IDLE2RX BLE.IDLE to BLE. RX transition time - 75 120 s RSSI, ACC RSSI accuracy - 5 - dB RSSI, RES RSSI resolution - 1 - dB RSSI, PER RSSI sample period - 6 - s RSSI Specifications Document Number: 002-11264 Rev. *G Page 34 of 47 CYBLE-224110-00 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBLE-224110-00 module is certified under the following RF certification standards: FCC ID: WAP4110 CE IC: 7922A-4110 MIC: 203-JN0568 KC: MSIP-CRM-Cyp-4110 Safety Certification The CYBLE-224110-00 module complies with the following safety regulations: Underwriters Laboratories, Inc. (UL): Filing E331901 CSA TUV Environmental Conditions Table 59 describes the operating and storage conditions for the Cypress BLE module. Table 59. Environmental Conditions for CYBLE-224110-00 Description Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Minimum Specification Maximum Specification -40 C 105 C 5% 85% - 3 C/minute -40 C 110 C Storage temperature and humidity - 110 C at 85% ESD: Module integrated into system Components[11] - 15 kV Air 2.2 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 11. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-11264 Rev. *G Page 35 of 47 CYBLE-224110-00 Regulatory Information FCC FCC NOTICE: The device CYBLE-224110-00 complies with Part 15 of the FCC Rules. The device meets the requirements for the modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION: The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP4110. In any case the end product must be labeled exterior with "Contains FCC ID: WAP4110" ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 15. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7 on page 15, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBLE-224110-00 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-224110-00 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-11264 Rev. *G Page 36 of 47 CYBLE-224110-00 ISED Innovation, Science and Economic Development (ISED) Canada Certification CYBLE-224110-00 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada. License: IC: 7922A-4110 Manufacturers of mobile, fixed, or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 7 on page 15, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. ISED NOTICE: The device CYBLE-224110-00 including the built-in chip antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. L'appareil CYBLE-224110-00, y compris l'antenne integree, est conforme aux Regles RSS-GEN de Canada. L'appareil repond aux exigences d'approbation de l'emetteur modulaire tel que decrit dans RSS-GEN. L'operation est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interferences nuisibles, et (2) Cet appareil doit accepter toute interference recue, y compris les interferences pouvant entrainer un fonctionnement indesirable. ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil est conforme a la norme sur l'innovation, la science et le developpement economique (ISED) norme RSS exempte de licence. L'exploitation est autorisee aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioelectrique subi, meme si le brouillage est susceptible d'en compromettre le fonctionnement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 10 mm between the radiator and your body. Cet equipement est conforme aux limites d'exposition aux radiations ISED prevues pour un environnement incontrole. Cet equipement doit etre installe et utilise avec un minimum de 10 mm de distance entre la source de rayonnement et votre corps. LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notice above. The IC identifier is 7922A-4110. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-4110". Document Number: 002-11264 Rev. *G Page 37 of 47 CYBLE-224110-00 European Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-224110-00 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows: All versions of the CYBLE-224110-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. MIC Japan CYBLE-224110-00 is certified as a module with type certification number 203-JN0568. End products that integrate CYBLE-224110-00 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. KC Korea CYBLE-224110-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4110. Document Number: 002-11264 Rev. *G Page 38 of 47 CYBLE-224110-00 Packaging Table 60. Solder Reflow Peak Temperature Module Part Number Package CYBLE-224110-00 32-pad SMT Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles 260 C 30 seconds 2 Table 61. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number Package MSL CYBLE-224110-00 32-pad SMT MSL 3 The CYBLE-224110-00 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-224110-00. Figure 10. CYBLE-224110-00 Tape Dimensions Figure 11 details the orientation of the CYBLE-224110-00 in the tape as well as the direction for unreeling. Figure 11. Component Orientation in Tape and Unreeling Direction Document Number: 002-11264 Rev. *G Page 39 of 47 CYBLE-224110-00 Figure 12 details reel dimensions used for the CYBLE-224110-00. Figure 12. Reel Dimensions The CYBLE-224110-00 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-224110-00 is detailed in Figure 13. Figure 13. CYBLE-224110-00 Center of Mass (Seen from Top) Document Number: 002-11264 Rev. *G Page 40 of 47 CYBLE-224110-00 Ordering Information Table 62 lists the CYBLE-224110-00 part number and features. Table 63 lists the reel shipment quantities for the CYBLE-224110-00. Table 62. Ordering Information PWMs (using UDBs) I2S (using UDB) GPIO Package 4 SCB Blocks 4 TCPWM Blocks LP Comparators 12-bit SAR ADC Opamp (CTBm) 32 1 Msps 1 4 2 4 25 32-SMT Direct LCD Drive UDB 256 CapSense Low-Noise Amplifier (LNA) 48 Power Amplifier (PA) CYBLE-224110-00 SRAM (KB) MPN Flash (KB) Max CPU Speed (MHz) Features Table 63. Tape and Reel Package Quantity and Minimum Order Amount Description Minimum Reel Quantity Maximum Reel Quantity Reel Quantity 500 500 Minimum Order Quantity (MOQ) 500 - Order Increment (OI) 500 - Comments Ships in 500 unit reel quantities. The CYBLE-224110-00 is offered in tape and reel packaging. The CYBLE-224110-00 ships with a maximum of 500 units/reel. Part Numbering Convention The part numbers are of the form CYBLE-FATT##-SB where the fields are defined as follows. CY BLE - F A T T ## - S B Bluetooth Version: Integration Type: Device Identification Number: Temperature Range: EZ-BLE Module Type: Antenna Type: Flash Size: Marketing Code: Company ID: 0 = BT 4.1, 1 = BT 4.2, 2 = BT 5.0 0 = Full Integration With Shield, 1 = No Shield Unique sequential product number for each module 0 = Industrial, 1 = Extended Industrial 2/4 = PSoC4, 3 = WICED, 4 = PSoC6 0 = No Antenna, 1 = PCB Antenna, 2 = Chip Antenna 0 = 128KB, 2 = 256KB BLE = BLE Product Family CY = Cypress For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address Document Number: 002-11264 Rev. *G 198 Champion Court, San Jose, CA 95134 (408) 943-2600 http://www.cypress.com Page 41 of 47 CYBLE-224110-00 Acronyms Table 64. Acronyms Used in this Document Acronym Description ABUS analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus Table 64. Acronyms Used in this Document (continued) Acronym Description EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell ALU arithmetic logic unit FCC Federal Communications Commission AMUXBUS analog multiplexer bus FET field-effect transistor API application programming interface FIR finite impulse response, see also IIR APSR application program status register FPB flash patch and breakpoint ARM(R) advanced RISC machine, a CPU architecture FS full-speed ATM automatic thump mode GPIO BLE Bluetooth Low Energy general-purpose input/output, applies to a PSoC pin Bluetooth SIG Bluetooth Special Interest Group HCI host controller interface HVI high-voltage interrupt, see also LVI, LVD BW bandwidth IC integrated circuit CAN Controller Area Network, a communications protocol IDAC current DAC, see also DAC, VDAC CE European Conformity IDE integrated development environment CSA Canadian Standards Association 2C, I or IIC Inter-Integrated Circuit, a communications protocol CMRR common-mode rejection ratio IC Industry Canada CPU central processing unit IIR infinite impulse response, see also FIR CRC cyclic redundancy check, an error-checking protocol ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO DAC digital-to-analog converter, see also IDAC, VDAC DFB digital filter block DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. IPOR initial power-on reset interrupt program status register DMIPS Dhrystone million instructions per second IPSR DMA direct memory access, see also TD IRQ interrupt request DNL differential nonlinearity, see also INL ITM instrumentation trace macrocell DNU do not use KC Korea Certification DR port write data registers LCD liquid crystal display DSI digital system interconnect LIN Local Interconnect Network, a communications protocol. LNA low noise amplifier LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference Document Number: 002-11264 Rev. *G Page 42 of 47 CYBLE-224110-00 Table 64. Acronyms Used in this Document (continued) Acronym Description Table 64. Acronyms Used in this Document (continued) Acronym Description LVTTL low-voltage transistor-transistor logic SC/CT switched capacitor/continuous time MAC multiply-accumulate SCL I2C serial clock MCU microcontroller unit SDA I2C serial data MIC Ministry of Internal Affairs and Communications (Japan) S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SMT surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL SOC start of conversion Opamp operational amplifier SOF start of frame PA power amplifier SPI PAL programmable array logic, see also PLD Serial Peripheral Interface, a communications protocol PC program counter SR slew rate PCB printed circuit board SRAM static random access memory PGA programmable gain amplifier SRES software reset PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register (R) PSoC Programmable System-on-ChipTM PSRR power supply rejection ratio STN super twisted nematic SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion TIA transimpedance amplifier TN twisted nematic TRM technical reference manual TTL transistor-transistor logic TUV Germany: Technischer Uberwachungs-Verein (Technical Inspection Association) TX transmit UART Universal Asynchronous Transmitter Receiver, a communications protocol PWM pulse-width modulator UDB universal digital block QDID qualification design ID USB Universal Serial Bus RAM random-access memory USBIO RISC reduced-instruction-set computing USB input/output, PSoC pins used to connect to a USB port RMS root-mean-square VDAC voltage DAC, see also DAC, IDAC RTC real-time clock WDT watchdog timer RTL register transfer language WOL write once latch, see also NVL RTR remote transmission request RX receive SAR successive approximation register Document Number: 002-11264 Rev. *G WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Page 43 of 47 CYBLE-224110-00 Document Conventions Units of Measure Table 65. Units of Measure Symbol Unit of Measure C degrees Celsius dB decibel dBm decibel-milliwatts fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second A microampere F microfarad H microhenry s microsecond V microvolt W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number: 002-11264 Rev. *G Page 44 of 47 CYBLE-224110-00 Document History Page Document Title: CYBLE-224110-00 EZ-BLETM Creator XT/XR Module Document Number: 002-11264 Revision ECN Orig. of Change Submission Date ** 5144379 DSO 01/07/2016 Preliminary datasheet for CYBLE-224110-00 module. *A 5430311 DSO 09/10/2016 Added FCC, IC, MIC, and KC certification IDs in all instances across the document. Updated General Description: Updated description. Updated Module Description: Updated details corresponding to "Extended Range". Added Note 1 and Note 2. Updated details corresponding to "Bluetooth 4.1 qualified single-mode module" (added QDID and Declaration ID numbers). Updated Power Consumption: Replaced "Stop: 60 nA with XRES wakeup" with "Stop: 60 nA with GPIO (P2.2) or XRES wakeup" under "Low power mode support". Updated More Information: Added Knowledge Base Articles relevant to CYBLE-224110-00 module. Added link to CYBLE-224110-EVAL kit. Updated Recommended Host PCB Layout: Updated Table 5 (To remove COMP0_INN from P0.1 options (ajoining COMP0_INP is not routed out in this module)). Updated Power Supply Connections and Recommended External Components: Added Enabling Extended Range Feature section. Added Power Saving Measures with PA/LNA Operation section. Updated Electrical Specification: Updated System Resources: Updated Internal Low-Speed Oscillator: Updated Table 56 (Updated details in "Value" column corresponding to ECOTRIM parameter). Updated Environmental Specifications: Updated RF Certification: Added FCC, IC, MIC, and KC certification IDs. Added Safety Certification section. Updated Environmental Conditions: Updated Table 59: Changed maximum specification of "Storage temperature" from 105 C to 110 C. Changed maximum specification of "Storage temperature and humidity" from "105 C at 85%" to "110 C at 85%". Updated Packaging: Added Figure 10. Added Figure 11. Added Figure 12. Added Figure 13. Updated Ordering Information: No change in part numbers. Add Table 63 (To specify minimum and maximum reel quantities that ship for orders of the CYBLE-224110-00 module). Updated to new template. Document Number: 002-11264 Rev. *G Description of Change Page 45 of 47 CYBLE-224110-00 Document Title: CYBLE-224110-00 EZ-BLETM Creator XT/XR Module Document Number: 002-11264 *B 5514347 DSO 11/09/2016 Remove "Preliminary" document status. Updated Electrical Specification: Updated Table 58: Update "CI2" typical specification parameter from "TBD" to 4 dB. Update "CI3" typical specification parameter from "TBD" to -23 dB. Update "CI4" typical specification parameter from "TBD" to -34 dB. Update "CI5" typical specification parameter from "TBD" to -22 dB. Change "CI3" to "CI6" and update typical specification parameter from "TBD" to -13 dB. Update "OBB1" typical specification parameter from "TBD" to -16 dBm. Update "OBB2" typical specification parameter from "TBD" to -16 dBm. Update "OBB3" typical specification parameter from "TBD" to -16 dBm. Update "OBB4" typical specification parameter from "TBD" to -16 dBm. Update "IMD" typical specification parameter from "TBD" to -26 dBm. Update "RXSE1" maximum specification parameter from "TBD" to -57 dBm. Update "RXSE2" maximum specification parameter from "TBD" to -47 dBm. Update "TXSE1" maximum specification parameter from "TBD" to -55.5 dBm. Update "TXSE2" maximum specification parameter from "TBD" to -41.5 dBm. Update "IBSE1" maximum specification parameter from "TBD" to -20 dBm. Update "IBSE2" maximum specification parameter from "TBD" to -30 dBm. Update "EO" minimum specification parameter from "TBD" to 0.8. *C 5554670 DSO 12/15/2016 Updated Table 5: Port 2.x OPAMP definitions changed to CTBm0 instead of CTBm1. Updated Electrical Specification: Updated SAR ADC: Updated Table 25 to add Note 9 to specify under what conditions the maximum number of ADC channels can be achieved. *D 5709491 GNKK *E 5787527 DSO 04/24/2017 Updated the Cypress logo and copyright information. 06/27/2017 Updated Enabling Extended Range Feature on page 16 to state proper PA/LNA setting when not using Extended Range functionality. Update references using term "Trace Antenna" to "Chip Antenna". Updated power supply voltage range for VDD signal throughout document to 2.0 V to 3.6 V to due to CPS/CSD PA/LNA interface pins requiring input/output voltage in this range: Updated Power Connections on page 12; Updated Figure 8 on page 13; Updated Table 4, Table 5, Table 11, Table 12, Table 13, Table 14, Table 15, Table 16, Table 18, Table 19, Table 21, Table 23, Table 26, Table 33, and Table 51. Updated Innovation, Science and Economic Development (ISED) Canada Certification on page 37 to latest ISED documentation requirements. Updated European Declaration of Conformity on page 38 to latest European regulatory requirements. *F 6006702 DSO 12/27/2017 Updated reel dimensions in Figure 10 and Figure 12. *G 6091378 DSO 03/15/2018 Updated the Title as "EZ-BLETM Creator XT/XR Module" Updated the links of QDID and Declaration ID in Module Description section as "https://launchstudio.bluetooth.com/ListingDetails/2301" Updated "PSoC 4" to "Creator" throughout the document. Updated More Information section. Updated the term "IC" to "ISED". Added "This equipment should be installed and operated with a minimum distance of 10 mm between the radiator and your body" and "Cet equipement doit etre installe et utilise avec un minimum de 10 mm de distance entre la source de rayonnement et votre corps" in the ISED RADIATION EXPOSURE STATEMENT FOR CANADA section. Updated Part Numbering Convention. Updated the Copyright year. Document Number: 002-11264 Rev. *G Page 46 of 47 CYBLE-224110-00 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products Arm(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation, 2016-2018. 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Other names and brands may be claimed as property of their respective owners Document Number: 002-11264 Rev. *G Revised March 15, 2018 Page 47 of 47