- IN CATALYST SEMICONOUCTOAR CAT93C46A/56A/66A/86A 1K/2K/4K/16K-Bit Serial E7PROM FEATURES mw High Speed Operation: 1MHz @ Low Power CMOS Technology @ Wide Operating Voltage Range V,, = 4.5V to 5.5V . V.. = 2.7V to 6.0V V., = 2.5V to 6.0V V_, = 1.8V to 6.0V m Self-Timed Write Cycle with Auto-Clear w Hardware and Software Write Protection m Power-Up Inadvertant Write Protection @ 100,000 Program/Erase Cycles B 100 Year Data Retention mw Commercial and Industrial Temperature Ranges @ x16 Serial Memory DESCRIPTION The CAT93C46A/S6A/66A/86A is a 1K/2K/4K/16K-bit Serial E7PROM memory devices which are configured as registers of 16-bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46A/56A/66A/86A are manufactured using Catalysts advanced CMOS E2PROM floating gate tech- nology. The devices are designed to endure 100,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP or SOIC packages. PIN CONFIGURATION DIP Package (P) SOIC Package (J) NC ("PE) C91 81 NC Voc CI 2 7 [> G@No csc] 3 6 [> DO SKC] 4 51 Ol PE (only for 93CB6A) PIN FUNCTIONS Pin Name Function cs Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output Vcc +1.8V to 6.0V Power Supply GND Ground PE* Program Enable NC No Connect SOIC Package (S) SOIC Package (K) csCyje1 817 Voc cs (Jet 81 Voc sk (| 2 7 FO NC (PE) SKC] 2 7 1) NC (PE) bic 3 6 FNC bic 3 61> NC Doc] 4 517] GND DO] 4 512] GND 93CXXA FO1 BLOCK DIAGRAM Voc GND MEMORY ARRAY ORGANIZATION /e4 BeCObER 64/128/256/1024X16 ; DATA . REGISTER Di t OUTPUT BUFFER os MODE DECODE I > Se _ = Cc CLOCK DO SK *| GENERATOR sacaevseree Foe 1996 by Catalyst Serniconductor, Inc. 3-9 Characteristics subjeci to change without noticeCAT93C46A/56A/66A/86A ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias............0..... 55C to +126C Storage Temperature ........0... 65C to +150C Voltage on any Pin with *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those Respect to Ground!) ............ -2.0V to +Vcc +2.0V _isted in the operational sections of this specification is not Vce with Respect to Ground ............... -2.0V to +7.0V implied. Exposure to any absolute maximum rating for Co extended periods may affect device performance and Package Power Dissipation reliability Capability (Ta = 25C) 00. 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current ooo 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method Nenp) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 Tor) Data Retention 100 Years MIL-STD-883, Test Method 1008 Vzap(3} ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILtHO4) | Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS Voc = +1.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions loc Power Supply Current 3 mA DI = 0.0V, fsk = 1MHz (Operating) Vec = 5.0V, CS = 5.0V, Output Open Isa Power Supply Current 50 pA CS =0V (Standby) It Input Leakage Current 2 HA ILo Output Leakage Current 10 HA Vout = OV to Vcc, CS =0V Vii Input Low Voltage -0.1 0.8 Vv 4.5V<Vcc<5.5V VIH1 Input High Voltage 2 Vect+1 Vv ViL2 Input Low Voltage 0 VecX0.2 Vv 1.8V<Vec<2.7V ViH2 Input High Voltage VecXx0.7 Vec+1 Vv Vout Output Low Voltage 0.4 Vo | 4.5VsVcoc<5.5V Von Output High Voltage 2.4 Vv lo = 2.1mA lou = -400LA Vo.2 Output Low Voitage 0.2 Vv 1.8VsVcc<2.7V Vore Output High Voltage Vcc-0.2 Vv lol = 1mA lon = -100HA Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is Voc +0.5V, which may overshoot to Vcc +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to Voc +1V. 3-10CAT93C46A/S6A/66A/86A PIN CAPACITANCE Symbol Test Max. Units Conditions Cour OUTPUT CAPACITANCE (DO) 5 pF Vout=OV Cin INPUT CAPACITANCE (CS, SK, Dl) 5 pF Vin=OV Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. INSTRUCTION SET Instruction] Device | Start |Opcode Address Data Comments Type | Bit x16 x16 PE(1) READ 93C46A | 1 10 A5-A0 Read Address AN-AO 93C56A2)) 1 10 A7-A0 93C66A | 1 10 A7-A0 93C86A | 1 10 A9-A0 x ERASE | 93C46A] 1 11 A5-AO Clear Address AN~AO 93C56A2)) 1 11 A7-AO 93C66A | 1 11 A7-AO 93CB86A | 1 11 A9-A0 1 WRITE | 93C46A | 1 01 A5-AO D15-Do Write Address ANAO 93C56A@) 1 01 A7-A0 D15-DO 93C66A | 1 01 A7-A0 D15-B0 93C86A | 1 01 A9-A0 D15-Do 1 EWEN 93C46A 1 00 1AXXXX Write Enable 93C56A 1 00 1 1XXXXXX 93C66A 1 00 1 AXXXKXK 93C86A 1 00 FAXXXXXXXK x EWDS | 93C46A 1 00 OOXXXX Write Disable 93C56A 1 00 OOXXXXXX 93C66A 1 00 OOXXXXXX 93C86A 1 00 OOXXXXXXXX xX ERAL 93C46A 1 00 10XXXX Clear All Addresses 93C56A 1 00 TOXXXXXX 93CE66A 1 00 TOXXXXXX 93C86A 1 00 OXXXXXXXX 1 WRAL_ | 93C46A 1 00 O1XXXX D15-D0 Write All Addresses 93C56A 1 00 O1XXXXXX 015-D0 93C66A | 1 00 OIXXXXXX D15-D0 93C86A 1 00 O1XXXXXXXX D15-D0 1 Note: (1) Only applicable to S3CB6A (2) Address bit A7 is Don't Care bit, but must be kept at either a "1" or 0 for Read, Write and Erase Commands. 3-11CAT93C46A/56A/66A/86A A.C. CHARACTERISTICS Limits Voc = Voc = 2.7V -6V Voc = 1.8V-6V* Veco = 2.5V-6V| 4.5V-5.5V Test SYMBOL| PARAMETER Min. | Max. | Min. | Max. | Min. | Max. |UNITS | Conditions tcss CS Setup Time 200 100 50 ns tcsH CS Hold Time 0 0 0 ns tois DI Setup Time 400 200 100 ns to DI Hold Time 400 200 100 ns SB trp: Output Delay to 1 1 0.5 0.25 | us tppo Output Delay to 0 1 0.5 0.25 us Ci = 100pF taz!)) Output Delay to High-Z 400 200 100 ns tew Program/Erase Pulse Width 10 10 10 ms tcSmMIN Minimum CS Low Time 1 0.5 0.25 ys tSKHI Minimum SK High Time 1 0.5 0.25 ps tskLow Minimum SK Low Time 1 0.5 0.25 pS tsv Output Delay to Status Valid 1 0.5 0.25 ys SKmax Maximum Clock Frequency DC 250 DC 500 DC | 1000 | KHZ * Preliminary data for 93C56A/66A/86A. NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. 3-12CAT93C46A/56A/66A/86A DEVICE OPERATION The CAT93C46A/56A/66A/86A is a 1024/2048/4096/ 16384-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46A/ 56A/66A/86A is organized as registers of 16-bits. There- fore, seven 9-bit instructions for 93C46A; seven 11-bit instructions for S3C56A and 93C66A; seven 13-bit in- structions for 93C86A, control the reading, writing and erase operations of the device. The CAT93C46A/56A/ 66A/86A operates on a single supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of awrite operation by selecting the device (CS high) and polling the DO pin; DO tow indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy 1 into the Dl pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applica- tions where the Di pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a2-bit (or 4-bit) opcode, 6-bit (983C46A)/ B-bit (98C56A or 93C66A)/10-bit (93C86A) and for write operations a 16-bit data field. Figure 1. Sychronous Data Timing SK bis (ate) lk* kr *}+ 'skLow | na tcsH 'DIH NJ >'CSMIN o TERK COED cs tos >| bo x - 'ppo'pp1 040 FHD FO3 Figure 2. Read Instruction Timing sk UU UU UU Ue cs / DI 1 1 0 An AN-4 Ao xX \ \_J STANDBY HIGH-Z DO tyz DN DN-1 D1, Dg 5040 FHD FO4 3-13 3a) CAT93C46A/S6A/66A/86A Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C46A/ 56A/66A/86A will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggte on the rising edge of the SK clock and are stable after the specified time delay (tppo or tep1). Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tcsmin). The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clock- ing of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46A/S6A/66A/86A can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT nec- essary to erase a memory location before it is written into. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of 250ns (tcsmin). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the CAT93C46A/S6A/66A/86A can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical 1 state. Figure 3. Write Instruction Timing PLU UL ut XA AXA cs JS AN AN-1 Ao DN Do HIGH-Z DO *I'cs N J status \, STANDBY VERIFY < ve 'sv BUSY ~ tHz READY HIGH-Z +f EW 5040 FHD FOS Figure 4. Erase instruction Timing x PLPLPL XARA AAA cs JS STATUS VERIFY STANDBY > t AN AN-1 Ao cS DI 1 1 1 x_\ 45 'sv _ ~ tuz HIGH-Z bo 4% BUSY / READY wana be te yy w4 5040 FHD FO7 3-14Erase/Write Enable and Disable The CAT93C46A/56A/66A/86A powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enabie) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all write and clear instructions, and will prevent any acci- dental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/ disable status. Erase All Upon receiving an ERAL command, the CS (Chip Se- lect) pin must be deselected for a minimum of 250ns (tcsmin). The falling edge of CS will start the self clocking clear cycle of ail memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy CAT93C46A/56A/66A/86A status of the CAT93C46A/56A/66A/86A can be deter- mined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical 1 state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tcsmin). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the CAT93C46A/56A/66A/86A can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Note: This note is applicable only to 93C86A. The write, erase, write all and erase all instruction requires PE=1 for 93C86A. if PE is left floating, 93C86A is in program enabled mode. Figure 5. EWEN/EWDS Instruction Timing JTUUUUUUU UU UU UU UU cs _/ oo /\ 2 = XRD ENABLE=11 DISABLE=00 \ STANDBY 93C48/56/66 FO7 Figure 6. ERAL Instruction Timing sk PU LU XX KAMARA AAA it cs / BO ag STATUS VERIFY STANDBY ~ e-tos tgy "I ~ tz IGH-Z HIGH BUSY READY HIGH-Z }# 'ew 5040 FHO Foa 3-15CAT93C46A/S6A/66A/86A Figure 7. WRAL Instruction Timing sk PLL LILI LL LPL LLL IX cs / STATUS VERIFY |\STANDBY > cs o Ne 0 of 1 XXXXXXKXX ON X20 toy ol Je > tuz a 00 45 le al READY S HIGH-Z 93C-46/56/66 Foe ORDERING INFORMATION | Prefix | Device # | Suffix CAT 93C46A S i -2.5 TE7 Product Femperature Range Tape & Reel Number Blank = Commercial (0C to +70C) TE7: 500/Ree!l 93C46A: 1K | = Industrial (-40C to +85C) TE13: 2000/Reel 93C56A: 2K 93CE66A: 4K 93CB6A: 16K Package Operating Voltage P=PDIP Blank (V_=4.5 to 5.5V) S = SOIC (JEDEC) 27 Va =2.7 to 6.0V J = SOIC (JEDEC) 2.5 (V, <=? 5 to 6.0V K = SOIC (EIAJ) 1.8 (V.=1.8 to 6.0V 93C-46/56/66 F10 Notes: (1) The device used in the above example is a 93C46ASI-2.5TE7 (SOIC, Industrial Temperature, 2.5 Volt to 6 Volt Operating Voltage, Tape & Reel} 3-16