eat Vee AMD Am79Q06/061/062/063 Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices TABLE OF CONTENTS Distinctive Characteristics... 0... ete tees 4 General Description .. 0.0... ee teeta 4 Block Diagram... 0... nett tee 5 Ordering Information... 2.0... eee ae 6 Connection Diagrams ... 0... nents 7 Pin DeScriptionS .. 0... eee eee 9 Functional Description .. 0... . i eet t eee 12 Absolute Maximum RatingS ....... 2.0.00 ccc eee eae 13 Operating Ranges... 6... een ete 13 Electrical Characteristics... 0... eet tees 14 Transmission CharacteristicS 2.2... 0.0000. 15 Attenuation Distortion 2... 2... eee 16 Group Delay Distortion... 0... eee ae 16 Total Distortion, Including Quantizing Distortion. .... 0... 0... eee 18 Discrimination against Out-of-Band Input Signals ...... 0.0.0.0... cee eee 19 Discrimination against 12- and 16 kHz Metering Signals ................ 00020 a eae 20 Spurious Out-of-Band Signals at the Analog Output ........ 20... 0. eee ee 20 Overload Compression .. 0... 0.0.0 c eee 21 Switching Characteristics (PCM/MPI Mode)......... 0.0.00 eee 22 Microprocessor Interface... 1... ete eee 22 PCM Interface... 2... eee 22 Master Clock... eee 23 Auxiliary Output ClockS 2.0... tenes 23 Switching Waveforms ......0. 0.0 cee eae 23 Input and Output Waveforms for AC Tests... 0... eae 23 Master Clock TIMiNg .. 0.0... ce eee ee 23 Microprocessor Interface (Input Mode) .... 0.2... eae 24 Microprocessor Interface (Output Mode)... 6... 2 tees 24 PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) ................ 25 PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) ................. 26 Double PCLK PCM Timing ............ 0.0000: ett 27 GCI Timing Specifications ... 0.0... eee 28 GCI Waveforms ..... 0... eet 29 Operating the QSLAC Device... 1... tenes 31 Power-Up Sequence... ....... 0.0... eet eee 31 PCM and GCI State Selection .. 0.0... 0. cee ae 31 Channel Enable Register... 0.0.0.0... teens 31 SLIC Control and Data Lines ...... 0... ce tee eee 32 Clock Mode Operation... 00... eee 32 E1 Mulitplex Operation 2... eee eee 33 Debounce Filters Operation .. 0... 0... eee 35 Real-Time Data Register Operation .... 0.0... 0. cts 36 INCQMPUPT. 2 ee teeta 36 Interrupt Mask Register .. 0.0... eae 37 This document contains information on a product under development at Advanced Micro Devices. The information Publication# 21108 Rev: C Amendment: /0 sroduct without neice we tn's product. AMD reserves the right to change or discontinue work on this proposed Issue Date: October 1998PRELIMINARY Active State 2... eens 37 Inactive State 26... eee eae 37 Low Power State 2.0... 2. ee nee eae 37 Chopper Clock... .........0 00 ccc eee 37 Reset StateS 2... eee eee eae 37 Signal ProceSSiNg ......... cc eee 38 Overview of Digital Filters... 00... 2. tenes 38 Two-Wire Impedance Matching. ......... 0... eet 38 Frequency Response Correction and Equalization.... 0.0... 0.0.0... c cee eee 38 Transhybrid Balancing. ... 0.0... ene ee eee 38 Gain Adjustment .. 0.0... tees 38 Transmit Signal Processing. ..... 0.0.0... eee ae 39 Transmit PCM Interface (PCM/MPI Mode) .............0.0000 cece eee eee eee 39 Data Upstream Interface (GCI Mode)............. 000 ccc tees 39 Receive Signal Processing ...... 0... 00. ene 39 Receive PCM Interface (PCM/MPI Mode)..............2000 0: cece eee eee 40 Data Downstream Interface (GCI Mode).............0 000: tee 40 Analog Impedance Scaling Network (AISN) .. 0.0... 0.0... cee 40 Speech Coding .......... 0.00 eee eee 40 Double PCLK (DPCK} Operation (PCM/MPI Mode Only)............ 0.000 eee A1 Signaling on the PCM Highway (PCM/MPI Mode) ........... 00.00 cee eee eee A Robbed-Bit Signaling Compatibility (PCM/MPI Mode Only) ...............0 00a eee A Default Filter Coefficients .... 0.0.0... 0.00 tte 42 Command Description and Formats ......... 00... eee ae 42 Summary of MPI Commands*..........0000 00 cect 156 MPI Command Structure... 0... eee eee 45 General Circuit Interface (GCI) Specifications ...........0... 000 cece 62 GCl General Description... 0... eee 62 GCI Format and Command Structure 2... 0... eee 63 SC Channel 2.0... 0. ete 63 Monitor Channel . 0... 0... ce eens 65 Programming with the Monitor Channel ..........0 0.00 eee eae 68 Channel Identification Command (CIC) ........... 000 cee 69 General Structure of Other Commands ............0.0000 ccc eee eee eee nee 69 Summary of Monitor Channel Commands ..............000 ccc cee eee teens 70 TOP (Transfer Operation) Command ..............02 00: eects 71 SOP (Status Operation) Command... 1... 0.0.0... eee ee 71 SOP Control Byte Command Format .......... 00: eee 72 COP (Coefficient Operation) Command ..............0 000 cece eee eee 78 Details of COP, CSD Data Commands ......... cc eee ene 79 Programmable Filters... 0... eee eee 85 General Description of CSD Coefficients ............ 0.0.0.0 ccc eee 197 User Test Modes and Operating Conditions... 0.0... 0.0... cece 198 A-Law and u-Law Companding... 0... 0.0.0... eee eee 87 Applications 2.0.0... eee tte 89 Am7920 SLIC/QSLAC Application Circuit 2... 00... te eee 90 Am79Q06/061/062/063 Data SheetPRELIMINARY LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 LIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Attenuation DiStortion 00... ececciceereeeeettreee ee eitieee ere tiieeeeeeiieeeeeeeniieteeessnieeeeesenaas 16 Group Delay DIStortion ........ ccc entre eee eecneeeeeeenieeeeeesineeeeeeesiieeeeeetiieeeeeetea 16 A-Law/u-law Gain Tracking with Tone Input (Both Paths) ........ ee eeeeeeeee 17 A-law/u-law Total Distortion with Tone Input (Both Paths) oe 18 Discrimination against Out-of-Band Signals ............c:cccccceeecceeeeeeeeeteeeeeeeeeeeneeees 19 Spurious Out-of-Band Signals ...........ccccccecceeceeeceeeeeeeeeeeeeeceeeceeeeseceeeseeesscereesnaees 20 AJA Overload COMPpresSiOn ..........eccccececceeeeeeeeenteeeeeeeiteeeeeesnieeeeeeettineeseesnieeeeesenaas 21 Clock Mode Option (PCM/MPI Mode Only)... ccceeeeesteeeeeeeetteteeeeenteeeeeenaes 32 SLIC I/O, E1 Multiplex and Real-Time Data Register Operation 0.0.0... ee 34 E1 Multiplex Internal Timing ......... cc cccececeececeecceeeeeeeeeeeseeeereeeseeecaeeeseeenineeeseenanees 35 MPI Real-Time Data Register or GCI Upstream SC Channel Data .......... 36 QSLAC Device Block Diagram .........cececeeetceeteeeeteteeeeerenneeeeetiteeeerentineeeenenaes 38 Robbed-Bit Frame o.oo... eccceeeeceeeceeeeeeeeeeeeeceeeeeeeeeseeeeaeeeseeeceeeeseeeeeeseeneneeeesenneees 42 Time Slot Control and GCI Interface ........e.ceccceeeceeeeeeceeceeeeeeeeeeeceseeesereeetsneeseaes 62 Multiplexed GCI Time Slot Structure ...... cee eeceeeeceeeeeeeeeeeeeneeeeseencreeeeeenaneees 63 Security Procedure for C/I Downstream Byte ..........::ccccecceeseeeeeeeeeeeeeeteteeeeeneeees 64 Maximum Speed Monitor Handshake Timing ...........:cceeeseeeeeeeeeeeeeeeeeeteeeeeeenanees 65 Monitor Transmitter State Diagram .........ccccceecceeeeeeeeteeeeeeeeecneeeeeesnneeeeeeennieeeere 66 Monitor Receiver State Diagram 0... cceccccececceeeeeeeetneeeeetinieeeeeesnieeeeeetniieeeeree 67 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR .......... 15 POM/GCI State Selection ..... ec cccceeceeeceeeeeeeeeeeeeeeeeeceeeceeeeeseeeieeeeseentneeeesenneees 31 GCI Channel Assignment Codes o.oo... ecccecccceeeeeeeeeteeeeeeenneeeeeeeetineeeerenieeeeeeenaas 62 Generic Byte Transmission SEQUENCE 0.0... eeeceeeetereeeettteeeeeetneeeeeettteeerttneeeees 68 Byte Transmission Sequence for TOP Commang .........:::cccccceceeeeeteeeeteeeeeseeees 71 General Transmission Sequence of SOP Command ..........::::cccccceeeceeteteeeeeees 71 Generic Transmission Sequence for COP Command. .........::::csecceectetseeeeeeeees 78 A-Law: Positive Input Value ...... cc eccceeee ee enttee eee etie eee eeeicieeeeeetineeesenieeeeeeenaas 87 u-Law: Positive Input Value... eect entree eee tineeeeeetieeeeeeeieeeeeesieeeeren 88 SLAC Products 3AMDA PRELIMINARY DISTINCTIVE CHARACTERISTICS @ Pin Programmable PCM/MPI or GCI Interface @ Standard PCM/microprocessor interface (PCM/MPI) Single or Dual PCM ports available Time slot assigner Clock slot and transmit clock edge options Up to 128 channels (PCLK at 8.192 MHz) per PCM port Optional supervision on the PCM highway 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or 8.192 MHz master clock derived from MCLK or PCLK (PCM/MPI mode) uP access to PCM data Linear Data mode Real Time Data register with interrupt (open drain or TTL output) Broadcast mode M@ General Circuit Interface (GCI) Control and PCM data on a single port 2.048 Mbits/s data rate 2.048 MHz or 4.096 MHz clock option @ Performs the functions of four codec/filters @ A-law, p-law, or linear coding @ Software programmable: SLIC input impedance and Transhybrid balance Transmit and receive gains and Equalization Programmable Digital I/O pins with debouncing @ Built-in test modes with loopback and tone generation m@ Low-power, 5.0 V only CMOS Technology M@ Mixed mode (analog and digital) impedance scaling @ Performance characteristics guaranteed over a 12 dB gain range @ Supports multiplexed SLIC inputs M@ 256 kHz or 293 kHz chopper clock for AMD SLICs with switching regulator H Maximum channel bandwidth for V.34 modems GENERAL DESCRIPTION The Am79Q06/061/062/063 Quad Subscriber Line Audio-Processing Circuit (QSLAC) devices integrate the key functions of analog linecards into high- performance, very-programmable, four-channel codec- filter devices. The QSLAC devices are based on the proven design of AMDs reliable SLAC device families. The advanced architecture of the QSLAC devices implements four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable linecards. Submicron CMOS technology makes the Am79Q06/061/062/063 QSLAC device economical, with the functionality and low power consumption needed in linecard design, maximizing density at minimum cost. When used with four AMD SLICs, a QSLAC device provides a complete software- configurable solution to the BORSCHT function. The Am79Q06/061/062/063 device supports the feature set of the Am79Q02/021/031 device and provides a General Circuit Interface as a programmable option. 4 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD BLOCK DIAGRAM Quad SLAC Device GCI/PCM Interface VINy Signal Processing DXA/DU VOUT, Channel 1 (CH 1) PCM and GCI Interface DRA/DD & VIN2 Signal Processing Time Slot Assigner TSCA VOUT Channel 2 (CH 2) (TSA) DXB VIN DRB 3 Signal Processing VOUT3 Channel 3 (CH 3) TSCB VIN4 Signal Processing VOUT, Channel 4 (CH 4) VREF Clock CD1, & CD2, Reference C3, Circuits FS/FSC C4, C5, C6, C7, PCLK/DCL MCLK/E1 CD15 CD25 C3, C45 C55 C6, C7, SLIC Interface CD13 (SLI) CD23 DCLK/SO C33 CS/PG C43 GCI Control Logic & DIOv/s14 Cd Microprocessor Interface CB, (MPI) C75 Zz 4 a n 4 CDI, cb2, C3, C44 C6, C74 CHCLK 21108A-001 SLAC Products 5AMDA ORDERING INFORMATION Standard Products PRELIMINARY AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79Q06/061/062/063 c Lo TEMPERATURE RANGE *C = Commercial (0C to 70C; Relative Humidity= 15% to 95%) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) Am79Q06/061 Only 32-Pin Plastic Leaded Chip Carrier (PL 032) Am7/9Q062 V = 44-Pin Thin Quad Flat Pack (PQT 044) Am79Q06/061 Only 64-Pin Thin Quad Flat Pack (PQL 064) Am79Q063 Only DEVICE NUMBER/DESCRIPTION Am79Q06/061/062/063 Quad Subscriber Line Audio-Processing Circuit (QSLAC) Device Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly Valid Combinations Am79Q06 JC, VC Am79Q061 JC, VC Am79Q062 Jc Am79Q063 vc released combinations, and to obtain additional Note: data on AMDs standard military grade products. * Functionality of the device from OC to +70C is guaranteed by production testing. Performance from 40C to +85C is guaranteed by characterization and periodic sampling of production units. Am79Q06/061/062/063 Data SheetPRELIMINARY CONNECTION DIAGRAMS Top View ~SoO < Sieve tae 2ap OOO90OCO000 6 Zl 6 5 4 3 2 1 44 43 42 41 40 e VOUT; [] 7 39 DCLK/SO VIN; (1 8 38 DIO/S1 VOUT, [J 9 37 1] TSCA VIN> [J 10 36 TSCB VCCA [7] 11 35 DGND VREF [J 12 Am79Q06JC 34) PCLK/DCL AGND [J 13 33 vccb VINs [] 14 32 DXA/DU VOUT; [] 15 31 DXB VIN, [J 16 30 FS/FSC VOUT, [] 17 29 RST | 18 19 20 21 22 23 24 25 26 27 28 WWW UU UU Ue -~- WwW ynwtrri nan Ot oc Zz qaq009900 4 SE 21108A-002 oc QO 44-PinPLCC _ 32-Pin PLCC lu NON - Oo < 7 a BA SLSSATESO Serge OO00OO00000S 2289999, poo ooooon4 70000210 {6543 2 1 4443424140 ) aa VOUT, [7 . 39 1] CS/PG VINT|5 . 29H DCLK/SO VIN, 8 38 1) DCLK/So VOUT C16 281 Diovst vou? Oe 37 | DIO/S1 VIN2 [7 27] TSCA yong d 0 36 A TSCA VCCA [3 261] DGND VREF C19 Am79Q062JC 25 VREF [] 12 Am79Q061JC 34 J PCLK/DCL q H veep AGND Ff 13 33 A] vecb AGND [10 241) VINs O 14 32 1 DXA/DU VINg (]11 23] DXA/DU VOUT3 [J 15 310 FS/FSC VOUT, 112 2210 FS/FSC VIN4 C] 16 30 0) RST VIN, (13 10 RST vouT, O 17 29 HINT 1415 16 171819 20 18 192021 22 23 2425 262728 FP Pega E LIOILIO OLLI OO CLIC Daanadaer:s raoereraa yo a 21108A-003 Qooooesg AAddD GAAaAKoOA 08A-00 Q =21108A-004 OO OO i. oc QO Notes: 1. Pin 1 is marked for orientation. 2. RSVD = Reserved pin; do not connect externally to any signal or supply. SLAC ProductsAMDA PRELIMINARY CONNECTION DIAGRAMS (continued) Top View 44-PinTQFP 5, 44-PinTQFP = S2O 2 NN co so we a)! ~ OQ) a BA SPAR ATL OG BAS PHS ATESO O0O0O00000 O 20 OOCKDOOO0C0CO0COS 44.4342 41 40 39 38 37 36 35 34 ( 444342 41 4039 3837363534 VOUT, [] 1 33 H pcLK/so VOUT; [J 1 33 CS/PG VOUT. 3 31 0 TSCA VOUT, TJ 3 31 Diovst VIN G4 30 1 TSCB VIN2 [] 4 30 TSCA VCCA 1] 5 29 DGND VCCA [J 5 29] DGND VREF 6 Am79Q06VC_-_-28. F] PCLK/DCL VREF [J 6 Am79Q061VC =. 28 [1] PCLK/DCL AGND 7 27 vCCD AGND 7 2701 vccD VIN; [| 8 26 1 DXA/DU VIN, 8 26 DXA/DU vout, 25 H DXB VOUT; 1 9 25 1 FS/FSC VIN4 Of 10 24 FS/Fsc VIN4 G 10 24H RST vouT, A 11 93 RST VOUT, O 11 23 0 INT 12131415161718192021 22 12131415 1617 1819202122 OOOO OOOO Ooo SOO ooo we SOS ey oy 1 Olt 21108A-005 WPS Ona DTH Oo 21108A-006 BAGS4h866 oe BH00 6000068 OO OO i. OO OO { oc oc Qa Qa 64-Pin TQFP a s N ON -3r I< BASSE SNMSATT HSN LS O00 OOO OO OOO OO 0 O8s8 ooo oooonnnonin on 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VOUT, [J 1 481] CS/PG VIN, O 2 471] DCLK/so RSVD [] 3 46] piovs1 VOUT, [] 4 45(] TSCA VINo J 5 44] TSCB RSvD [J 6 431] DGND vccA [I] 7 421] DGND vccA (J 8 Am79Q063VC 411 PcLK/DCL VREF [J 9 401] RSVD AGND [10 3910 vccpb AGND [411 38(0 vccbD VIN3 [112 3710 DXA/DU VOUT; [113 360 DxB Rsvp [14 35] FS/FSC VINg (115 3410 RST VOUT, [116 33] INT | 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 OOOOOOOOOOUIOO OC on nm Om mwr tt + ++ + MOA 21108A-007 rT ana nvvroonrri nn nwtwoao ks roa QAADGOOOOnNAKnOOGOOO FE OO OO i. 5 Notes: 1. Pin 1 is marked for orientation. 2. RSVD = Reserved pin; should not be connected externally to any signal or supply. 3. Pins of same name on AmM79Q063VC internally connected (AGND, pins 10, 11; VCCA, pins 7, 8; VCCD, pins 38, 39; DGND, pins 42, 43). 8 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD PIN DESCRIPTIONS CD1,-CD14, CD2,-CD2, Control and Data (Inputs/Outputs) CD1 and CD2 are TTL compatible programmable Input or Output (I/O) ports. They can be used to monitor or control the state of SLIC or any other device associated with subscriber line interface. The direction, input or output, is programmed using MPI Command 22 or GC! Monitor channel Command 8. As outputs, CD1 and CD2 can be used to control relays, illuminate LEDs, or perform any other function requiring a latched TTL compatible signal for control. In PCM/MPI mode, the output state of CD1 and CD2 is written using MPI Command 20. In GCI mode, the output state of CD1 and CD2 is determined by the C1 and C2 bits contained in the down stream C/I channel for the respective channel. As inputs, CD1 and CD2 can be processed by the QSLAC device (if programmed to do so). CD1 can be debounced before it is made available to the system. The debounce time is programmable from 0 to 15 ms in 1 ms increments using MPI Command 45 and GCl monitor channel Command 11. CD2 can be filtered using the up/down counter facility and programming the sampling interval using MPI Command 52 or GCI SOP Command 12. Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing function. The E1 demultiplexing function of the QSLAC device was designed to interface directly to AMD SLICS supporting the ground key function. With the proper AMD SLIC and the E1 function of the QSLAC enabled, the CD1 bit can be demultiplexed into an Off-Hook/Ring Trip signal and Ground Key signal. In the demultiplex mode, the second bit, Ground Key, takes the place of the CD2 as an input. The demultiplexed bits can be debounced (CD1) or filtered (CD2) as explained previously. A more complete description of CD1, CD2, debouncing, and filtering functions is contained in the Operating the QSLAC Device section on page 31. Once the CD1 and CD2 inputs are processed (Debounced, Filtered and/or Demultiplexed) by the QSLAC device, the information can be accessed by the system in two ways in the PCM/MPI mode: 1) on a per channel basis along with C3, C4, and C5 of the specific channel using MPI Command 21, or 2) by using MPI Commands 16 and 17, which obtain the CD1 and CD2 bits from all four channels simultaneously. This feature reduces the processor overhead and the time required to retrieve time-critical signals from the line circuits, such as off-hook and ring trip. With this feature, hookswitch status and ring trip information, for example, can be obtained from all four channels of a QSLAC device with one read command. In the GCI mode, the processed CD1 and CD2 inputs are transmitted upstream on the CD1 and CD2 bits for the respective analog channel, 1 or 2, using the C/I channel. C3,-C34, C4,-C44, C5,-C5,4 Control (Inputs/Outputs) C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They can be used to monitor or control the state of SLIC or any other device associated with subscriber line interface. The direction, input or output, is programmed using MPI Command 22 or GCI Monitor channel Command 8. As outputs, C3, C4, and C5 can be used to control relays, illuminate LEDs, or perform any other function requiring a latched TTL compatible signal for control. In PCM/MPI mode, the output state of C3, C4, and C5 is written using MPI Command 20. In GCI mode, the output state of C3, C4, and C5 is determined by the C3, C4, and C5 bits contained in the down stream C/I channel for the respective analog channel. As inputs, C3, C4, and C5 can be accessed by the system in PCM/MPI| mode by using MPI Command 21. In GCI mode, C3 is transmitted upstream, along with CD1 and CD2, for the respective analog channel using C3 of the C/I channel. Also, in GCI mode, C3, C4, and C5 can be read along with CD1 and CD2 using Monitor channel Command 10. The Am79Q061 QSLAC device contains a single PCM highway or GCI Interface and five programmable I/Os per channel (CD1, CD2, C8, C4, and C5) in a 44-pin PLCC or TQFP package. In the Am79Q06 QSLAC device, the C5,, C55, C535, and C5, I/Os are eliminated, enabling dual PCM highways or a GCI interface and a chopper clock output in a 44-pin PLCC or TQFP package. In the Am79Q062 QSLAC device, the C34 C54, C35-C55, C33-C53, and C34-C5,4 I/Os are eliminated, enabling a single PCM highway or GCl Interface and two control and data I/Os (CD1, CD2) per channel in a 32-pin PLCC package. C6, C6,, C7, -C7, Control (Outputs) Two additional outputs per channel are available on the Am79Q063VC device. CHCLK Chopper Clock (Output) This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTL-compatible clock for use by up to four SLICs with built-in switching regulators. The CHCLK frequency is synchronous to MCLK/DCL (MCLK in PCM mode, DCL in GCI mode), but the phase relationship to MCLK/DCL is random. The chopper clock is not available in all package types. SLAC Products 9AMDA PRELIMINARY CS/PG Chip Select/PCM-GCI (Input) The CS/PG input along with the DCLK/SO input are used to determine the operating state of the programmable PCM/GCI interface. On power up, the QSLAC device will initialize to GCI mode if CS/PG is low and there is no toggling (no high to low or low to high transitions) of the DCLK/SO input. The device will initialize to the PCM/MPI mode if either CS is high or DCLK is toggling. Once the device is in PCM/MPI mode, it is ready to receive commands through its serial interface pins, DIO and DCLK. Once a valid command has been sent through the MPI serial interface, GCI mode cannot be entered unless a hardware reset is asserted or power is removed from the part. If a valid command has not been sent since the last hardware reset or power up, then GCI mode can be re-entered (after a delay of one PCM frame) by holding CS/PG low and keeping DCLK static. While the part is in GCIl mode, then CS/PG going high or DCLK toggling will immediately place the device in PCM/MPI mode. In the PCM/MPI mode, the Chip Select input (active Low) enables the device so that control data can be written to or read from the part. The channels selected for the write or read operation are enabled by writing 1s to the appropriate bits in the Channel Enable Register of the QSLAC device prior to the command. See EC1, EC2, EC3, and EC4 of the Channel Enable Register and Command 14 for more information. If Chip Select is held Low for 16 rising edges of DCLK, a hardware reset is executed when Chip Select returns High. DCLK/SO Data Clock (Input) In addition to providing both a data clock input and an SO GCI address input, DCLK/SO acts in conjunction with CS/PG to determine the operational mode of the system interface, PCM/MPI or GCI. See CS/PG for details. In the PCM/MPI mode, the Data Clock input shifts data into and out of the microprocessor interface of the QSLAC device. The maximum clock rate is 4.096 MHz and the minimum clock rate is 10 KHz. Select Bit 0 (Input) In GCI mode, SO is one of two inputs (SO, $1) that is decoded to determine which GCI channels the QSLAC transmit and receives data on. DIO/S1 Data Input Output (Input) In the PCM/MPI mode, control data is serially written into and read out of the QSLAC device via the DIO pin, most significant bit first. The Data Clock determines the data rate. DIO is high impedance except when data is being transmitted from the QSLAC device. Select Bit 1 (Input) In GCI mode, S1 is the second of two inputs (SO, $1) that is decoded to determine which GCI channels the QSLAC transmits and receives data on. DRA, DRB/DD PCM Data Receive (A/B) (Inputs) In the PCM/MPI mode, the PCM data for Channels 1, 2, 3, and 4 is serially received on either the DRA or DRB port during user-programmed time slots. Data is always received with the most significant bit first. For compressed signals, 1 byte of data for each channel is received every 125 us at the PCLK rate. In the Linear mode, 2 consecutive bytes of data for each channel are received every 125 us at the PCLK rate. DRB is not available on all package types. GCI Data Downstream (Input) In GCI mode, the B1, B2, Monitor and SC channel data is serially received on the Data Downstream input for all four channels of the QSLAC device. The QSLAC device requires two of the eight GCI channels for operation. The two GCI Channels, out of the eight possible, are determined by the SO and S1 inputs. Data is always received with the most significant bit first. 4 bytes of data for each GCI channel is received every 125 us at the 2.048 Mbit/s data rate. DXA, DXB/DU PCM Data Transmit (Outputs) In the PCM/MPI mode, the transmit data from Channels 1, 2, 3, and 4 is sent serially out on either the DXA or DXB port or on both ports during user-programmed time slots. Data is always transmitted with the most significant bit first. The output is available every 125 us and the data is shifted out in 8-bit (16-bit in Linear or PCM Signaling mode) bursts at the PCLK rate. DXA and DXB are High impedance between time slots, while the device is in the Inactive mode with no PCM signaling, or while the Cutoff Transmit Path bit (CTP) is on. DXB is not available on all package types. GCI Data Upstream (Output) In the GCI mode, the B1, B2, Monitor and SC channel data is serially transmitted on the Data Upstream output for all four channels of the QSLAC device. Which GCI channels the device uses is determined by the SO and $1 inputs. Data is always transmitted with the most significant bit first. 4 bytes of data for each GCI channel is transmitted every 125 us at the DCL rate. FS/FSC Frame Sync (Input) In the PCM/MPI mode, the Frame Sync (FS) pulse is an 8 kHz signal that identifies Time Slot 0 and Clock Slot 0 10 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD of a systems PCM frame. The QSLAC device references individual time slots with respect to this input, which must be synchronized to PCLK. Frame Sync (Input) In GCI mode, the Frame Sync (FSC) pulse is an 8 kHz signal that identifies the beginning of GCI channel 0 of a systems GCI frame. The QSLAC device references individual GCI channels with respect to this input, which must be synchronized to DCL. INT Interrupt (Output) INT is an active Low output signal, which is programmable as either TTL-compatible or open drain. The INT output goes Low any time one of the input bits in the Real Time Data register changes state and is not masked. It also goes Low any time new transmit data appears if this interrupt is armed. INT remains Low until the appropriate register is read via the microprocessor interface, or the QSLAC device receives either a software or hardware reset. The individual CDx, bits in the Real Time Data register can be masked from causing an interrupt by using MPI Command 26 or SOP Command 14. The transmit data interrupt must be armed with a bit in the Operating Conditions Register. MCLK/E1 Master Clock (Input)/Enable CD1 Multiplex (Output) In PCM/MPI mode only, the Master Clock can be a 1.536 MHz, 1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor. MCLK may be asynchronous to PCLK. If the internal clock is derived from the PCM Clock Input (PCLK) or if GCI mode is selected, this pin can be used as an E1 output to control AMD SLICs having multiplexed switchhook and ground key detector outputs. PCLK/DCL PCM Clock (Input) In the PCM/MPI mode, the PCM clock determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for dual PCM highway versions and 256 kHz for single PCM highway versions. The minimum clock rate must be doubled if Linear mode or PCM signaling is used. PCLK frequencies between 1.03 MHz and 1.53 MHz are not allowed. The PCLK clock may be asynchronous to MCLK. Optionally, the digital signal processor clock can be derived from PCLK rather than MCLK. In PCM/MPI mode, PCLK can be operated at twice the PCM data rate in the Double PCLK mode (bit 1 of PCM/MPI Command 45). GCI Data Clock (Input) In GCI mode, DCL is either 2.048 MHz or 4.096 MHz, which is an integer multiple of the frame sync frequency. Circuitry internal to the QSLAC device monitors this input to determine which frequency is being used, 2.048 MHz or 4.096 MHz. When 4.096 MHz clock operation is detected, internal timing is adjusted so that DU and DD operate at the 2.048 Mbit/s rate. RST Reset (Input) A logic Low signal at this pin resets the QSLAC device to its default state. TSCA, TSCB Time Slot Control (Outputs) The Time Slot Control outputs are open drain outputs (requiring pull-up resistors to Vpcc) and are normally inactive (high impedance). In the PCM/MPI mode, TSCA or TSCB is active (low) when PCM data is transmitted on the DXA or DXB pin respectively. In GCI mode, TSCA is active (low) during the two GCI time slots selected by the S1 and SO. TSCB is not available on all package types. VIN,-VIN, Analog (Inputs) The analog voice band signal is applied to the VIN input of the QSLAC device. The VIN input is biased at VREF by a large internal resistor. The audio signal is sampled, digitally processed and encoded, and then made available at the TTL-compatible PCM output (DXA or DXB) or in the B1 and B2 of the GCI channel. If the digitizer saturates in the positive or negative direction, VIN is pulled by a reduced resistance toward AGND or VCCD, respectively. VIN, is the input for Channel 1, VINo is the input for Channel 2, VINg is the input for Channel 3, and VIN, is the input for Channel 4. VOUT,-VOUT, Analog (Outputs) The received digital data at DRA/DRB or DD (GCI mode) is processed and converted to an analog signal at the VOUT pin. VOUT, is the output from Channel 1, VOUTs is the output for Channel 2, VOUT is the output from Channel 3, and VOUT, is the output for Channel 4. The VOUT voltages are referenced to VREF. SLAC Products 11AMDA PRELIMINARY VREF Analog Voltage Reference (Output) The VREF output is provided in order for an external 0.1 pF capacitor to be connected from VREF to ground, filtering noise present on the internal voltage reference. VREF is buffered before it is used by internal circuitry. The voltage on VREF is nominally 2.1 V, and the output resistance is 100 kQ +30%. The leakage current in the capacitor must be less than 20 nA. Power Supply for the Am79Q06X AGND Analog Ground DGND Digital Ground VCCA +5 V Analog Power Supply vccD +5 V Digital Power Supply Two separate power supply inputs allow for noise isolation and proper power supply decoupling techniques; however, the two pins have a low impedance connection inside the part. For best performance, connect all of the +5 V power supply pins together at the connector of the printed circuit board, and all of the grounds should be connected together at the connector of the printed circuit board. FUNCTIONAL DESCRIPTION The QSLAC device performs the codec/filter and two- to four-wire conversion functions required of the subscriber line interface circuitry in telecommunications equipment. These functions involve converting audio signals into digital PCM samples and converting digital PCM samples back into audio signals. During conversion, digital filters are used to band limit the voice signals. All of the digital filtering is performed in digital signal processors operating from a master clock, which can be derived either from PCLK or MCLK in the PCM/MPI mode and DCL in the GCI mode. Four independent channels allow the QSLAC device to function as two DSLAC devices. In the PCM/MPI mode, each channel has its own enable bit (EC1, EC2, EC3, and EC4) to allow individual channel programming. If more than one Channel Enable bit is High or if all Channel Enable bits are High, all channels enabled will receive the programming information written; therefore, a Broadcast mode can be implemented by simply enabling all channels in the device to receive the information. The Channel Enable bits are contained in the Channel Enable Register, which is written and read using Commands 14 and 15. The Broadcast mode is useful in initializing QSLAC devices in a large system. In GCI mode, one GC! channel controls two channels of the QSLAC device. The Monitor channel and SC channel within the GCI channel are used to read/write filter coefficient data, read/write operating conditions and to read/write data to/from the programmable I/O ports of the two channels. Two consecutive GCl channels control all four channels of the QSLAC device. The two GCI channels used, of the eight total available, are determined by SO and $1 inputs. The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All programmable digital filter coefficients can be calculated using the AMSLAC4 or WinSLAC software. In PCM/MPI mode, Data transmitted or received on the PCM highway can be 8-bit companded code (with an optional 8-bit signaling byte in the transmit direction) or 16-bit linear code. The 8-bit codes appear 1 byte per time slot, while the 16-bit code appears in two consecutive time slots. The compressed PCM codes can be either 8-bit companded A-law or p-law. The PCM data is read from and written to the PCM highway in user-programmable time slots at rates of 128 kHz to 8.192 MHz. The transmit clock edge and clock slot can be selected for compatibility with other devices that can be connected to the PCM highway. In GCI mode, two 8-bit companded codes are received or transmitted per GCI channel. The compressed PCM codes can be either 8-bit companded A-law or u-law. There is no Signaling or Linear mode available when GCI mode is selected. Three configurations of the QSLAC device are offered with single or dual PCM highways (PCM/MPI mode) in PLCC packages, shown in Connection Diagrams on page 7 and page 8. The Am/79QO06JC and Am79Q061JC, with dual and single PCM highways, respectively, are available in the 44-pin PLCC package. The Am79Q062 is a single PCM highway version in a 32-pin package. All 32- and 44-pin packaging options include the programmable GCI interface as an option. PCM/GCI Highway Programmable I/O Chopper Clock Package Part Number Dual/Single* Four Yes 44 PLCC/TQFP Am79Q06V, JC Single/Single Five No 44 PLCC/TQFP Am79Q061V, JC Single/Single Two No 32 PLCC Am79Q062JC Dual/Single Seven Yes 64 TQFP Am79Q063VC Note: * Dual PCM highways in PCM mode. Single GCI interface in GCI mode. 12 Am79Q06/061/062/063 Data SheetPRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature ........ eee 60C < Ta <4+125C Ambient Operating Temperature .......... 40C < Ta < +85C Ambient Relative Humidity...... 5% to 95% (non condensing) VCCA with respect to AGND ....... eee 0.4 V to +7.0 V VCCA with respect tO VOCD...... ee eeeeeesteeeeeenneeteees +50 mV VCCD with respect to DGND......... eee 0.4V to +7.0V VIN with respect to AGND ........ 0.4 V to VCCA +0.4 V AGND with respect to DGND...... ee eeeeeereeeeeee 04 V Other pins ...... with respect to DGND-0.4 V to VCCD +0.4 V Total combined CD1C5 current per device: Source froM VOCD......ccccccecsccececceeeseeeeseeeeesteeeeees 40 mA Sink into DGND .........ccecceececeeeeeeeeeeeeeeeeeeeeeeeeeetes 40 mA Latch-up immunity (any pin) 0.0... eeeeeee eee +30 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. AMDA OPERATING RANGES VCOCA, Analog Supply ....... eee eeeeeesnreeeeees +5.0 V 40.25 V VCCA, Analog Supply ........eeeeeeseeesnreeeeees VCCD +10 mV VCCD, Digital Supply ...... eee eeeeeeeerees +5.0 V 40.25 V DGND..oo.eeeceeeeceeeeeeeeeete eee eeeee ene eeeae seers ea aeenaeeeneeeteeeeeeenaeee OV AGND Wee ec ceee cence eeeeeee eee eeeeeenaeeeaeseeeeseeeseeeeeeeeaes +50 mV Ambient Temperature ........ eee 0C < Ta < +70C Ambient Relative Humidity... cesses 15% to 95% Operating Ranges define those limits between which functionality of the device is guaranteed by production testing. Functionality of the device from 0C to +70C is guaranteed by production testing. Performance from 40C to +85C is guaranteed by characterization and periodic sampling of production units. SLAC Products 13AMDA PRELIMINARY ELECTRICAL CHARACTERISTICS over operating range (unless otherwise noted) Typical values are for T, = 25C and nominal supply voltages. Minimum and maximum specifications are over the temperature and supply voltage ranges shown in Operating Ranges. Symbol Parameter Descriptions Min Typ Max Unit Vit Input Low voltage 0.8 Vv Vin Input High voltage 2.0 Nie Input leakage current 10 +10 HA Output Low voltage CD1-C7 (Io, = 4 mA) 0.4 VoL CD1-C7 (Io, = 8 mA) (Note 1) 0.8 TSCA, TSCB (Io, =14 mA) 0.4 Other digital outputs (Io, = 2 MA) 0.4 Vv Output High voltage Vv CD1-C7 (Ioyq=4 mA) VCCcD-0.4V OH CD1-C7 (Ioy= 8 mA! VCCD - 0.8 V Other digital outputs (Ioy = 400 pA) 2.4 lot Output leakage current (H; = Z State) -10 10 HA Vv Analog input voltage range (AX = 0 dB) +1.584 Vok IR | (Relative to VREF) (AX = 6.02 dB) +0.792 P Vios | Offset voltage allowed on VIN 50 50 mV ZIN Analog input impedance to VREF300 to 3400 Hz 0.43 3.4 MQ lip Current into analog input for input voltages 3.8 V to 5.0 ve 54 170 lin Current out of analog input for input voltages 0 V to 0.5 ve 50 170 pA Zout | VOUT output impedance 1 10 Q lout VOUT output current (F< 3400 Hz)? -4 4 mA Zrer | VREF output impedance (F < 3400 Hz) 70 130 kQ VOUT voltage range (AR = 0 dB) +1.584 Vor Vpk (Relative to VREF) (AR = 6.02 dB) +0.792 Voos | VOUT offset voltage (AISN off) 40 40 Voosa | VOUT offset voltage (AISN on)* 80 80 mv LINaisn | Linearity of AISN circuitry (input = 0 dBm0) 0.25 0.25 LSB Power dissipation All channels active 200 260 PD 1 channel active 70 130 mW All channels inactive, (in normal state) 18 25 All channels inactive (in low power state, see Note 5) 6 12 C; Input capacitance (Digital) 15 oF Co Output capacitance (Digital) 15 Power supply rejection ratio PSRR (1.02 KHz. 100 Ven either path, GX=GR=0 dB) 40 dB Notes: 1. The CD1, CD2, C3-C7 outputs are resistive for less than a 0.8 V drop. Total current musi not exceed absolute maximum ratings. 2. When the digitizer saturates, a resistor of 50 kQ +20 kQ. is connected either to DGND or to VCCD (1 diode drop) as appropriate to discharge the coupling capacitor. 3. When the QSLAC device is in the Inactive mode, the analog output presents a VREF DC output level through a 15 kQ. resistor. . If there is an external DC path from VOUT to VIN with a gain of Gpc and the AISN has a gain of hajsn, then the output offset is multiplied by 1/[1(hyaisn * Gp). 5. Power dissipation in the Inactive mode is measured with all digital inputs at Vij = Voc and Vy, = DGND and with no load con- nected to VOUT,, VOUT2, VOUT, or VOUT 4. 14 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD Transmission Characteristics Table 1. dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR Signal at Digital Interface Transmit Receive Unit A-law digital mW or equivalent (0 dBm0) 0.7804 0.7804 p-law digital mW or equivalent (0 dBm0) 0.7746 0.7746 Vrms +22,827 peak linear coded sine wave 0.7804 0.7804 When relative levels (dBm0) are used in the following transmission specifications, the specification holds for any setting of the AX + GX gain from 0-12 dB and the AR + GR loss from 0-12 dB. Description Test Conditions Min Typ Max Unit Note Gain accuracy D/A or A/D 0 dBmo, 1014 Hz AX =AR=0dB 0 to 85C 0.25 +0.25 40C 0.30 +0.30 AX = +6.02 dB and /or AR =-6.02 dB 0 to 85C 0.30 +0.30 a6 40C 0.40 +0.40 Gain accuracy digital-to-digital 0.25 +0.25 Gain accuracy analog-to-analog -0.25 +0.25 Attenuation distortion 300 Hz to 3 kHz 0.125 +0.125 1 Single frequency distortion 46 2 Idle channel noise Analog out Digital looped back weighted -68 dBm0p 3 unweighted 55 dBmo 3 Digital input = 0 A-law -78 dBm0p 3 Digital input = 0 p-law 0 12 dBrnco 3,6 Digital out Analog Viy = 0 VAC A-law -68 dBm0p 3 Analog Viy = 0 VAC p-law 0 16 dBrncO 3,6 Crosstalk same channel TX to RX 0 dBm0300 Hz to 3400 Hz 75 RX to TX 0 dBm0300 Hz to 3400 Hz 75 dBmo Crosstalk between channels 0 dBm0 TX or RX to TX 1014 Hz, Average -76 4 TX or RX to RX 1014 Hz, Average -78 End-to-end group delay B=Z=0;X=Re=1 678 us 5 Notes: 1. Also see Figure 1 and Figure 2. 2. 0dBm0 input signal, 300 Hz to 3400 Hz; measurement at any other frequency, 300 Hz to 3400 Hz. 3. No single frequency component in the range above 3800 Hz may exceed a level of -55 dBm0d. 4. The weighted average of the crosstalk is defined by the following equation, where C(f) is the crosstalk in dB as a function of frequency, fy = 3300 Hz, f; = 300 Hz, and the frequency points (f, j = 2..N) are closely spaced: 1 59 F ap Ch) . y 10 +10 log [ Ae faq Average = 20 e log J (9 1 5. The End-to-End Group Delay is the sum of the transmit and receive group delays (measured using same time and clock slot). 6. Typical values not tested in production. SLAC Products 15AMDA PRELIMINARY Attenuation Distortion ____sQSLAC Device Specification Transmit curve 1.8 dB Attenuation (dB) Receive curve 1 dB 0.75 dB 4 Transmit only 200 300 3000 3400 Frequency (Hz) 21108A-008 Figure 1. Attenuation Distortion Group Delay Distortion For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum value of the group delay is taken as the reference. The signal level should be 0 dBm0. 420 2 QSLAC Device Specification (Either Path) Delay (us) 150 90 + |_| | | | 0 I I I I 500 600 1000 2600 2800 Frequency (Hz) 21108A-009 Figure 2. Group Delay Distortion 16 Am79Q06/061/062/063 Data SheetPRELIMINARY Variation of Gain with Input Level The gain deviation relative to the gain at 10 dBm0 is within the limits shown in Figure 3 for either transmission path when the input is a sine wave signal of frequency 1014 Hz. AMDaA 1.5 0.55 0.25 Gain 0 dB 0.25 0.55 -1.5 1.4 0.45 0.25 Gain 0 dB 0.25 0.45 -1.4 a. QSLAC Device Specification a. A-law ae QSLAC Device Specification b. u-law Input Level dBmo 21108A-010 Input Level dBmo 21108A-011 Figure 3. A-Law/u-law Gain Tracking with Tone Input (Both Paths) SLAC Products 17AMDA PRELIMINARY Total Distortion, Including Quantizing Distortion The signal-to-total distortion will exceed the limits shown in Figure 4 for either transmission path when the input is a sine wave signal of frequency 1014 Hz. @ QSLAC Device Specification 35.5 35.5 Signal-to-Total 30 Distortion (dB) 2 |_ | -45 -40 -30 0 Input Level (dBm0) 21108A-012 a. A-law 2 QASLAC Device Specification 35.5 35.5 Signal-to-Total 31 Distortion (dB) 27 | | 45 -40 -30 0 Input Level (dBm0) 21108A-013 b. u-law Figure 4, A-law/u-law Total Distortion with Tone Input (Both Paths) 18 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD Discrimination against Out-of-Band Input Signals When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency components below 4 kHz at the digital output, which are caused by the out-of-band signal. These components are at least the specified dB level below the level of a signal at the same output originating from a 1014 Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are shown in the following table. Frequency of Out-of-Band Signal Amplitude of Out-of-Band Signal Level below A 16.6 Hz <f< 45 Hz 25 dBm0 < A< 0 dBm0 18 dB 45 Hz <f < 65 Hz 25 dBm0 < A< 0 dBm0 25 dB 65 Hz <f < 100 Hz 25 dBm0 < A< 0 dBm0 10 dB 3400 Hz < f < 4600 Hz -25 dBm0 < A< 0 dBm0 see Figure 5 4600 Hz <f < 100 kHz 25 dBm0 < A< 0 dBm0 32 dB Level (dB) o gy & QSLAC Device Specification -10 KH 20k 28 dBm 30 _ wae 32 dB, -25 dBm0 < input < 0 dBm0 40 50 | ] ] l I I 3.4 4.0 4.6 21108A-014 Frequency (KHz) Note: The atienuation of the waveform below amplitude A between 3400 Hz and 4600 Hz is given by the formula: m(4000 f) 1200 Attenuation (db) = 14- 14sin Figure 5. Discrimination against Out-of-Band Signals SLAC Products 19AMDZ PRELIMINARY Discrimination against 12- and 16 kHz Metering Signals If the QSLAC device is used in a metering application where 12 kHz or 16 kHz tone bursts are injected onto the telephone line toward the subscriber, a portion of these tones also may appear at the VIN terminal. These out-of-band signals may cause frequency components to appear below 4 kHz at the digital output. For a 12 kHz or 16 kHz tone, the frequency components below 4 kHz are reduced from the input by at least 70 dB. The sum of the peak metering and signal voltages must be within the analog input voltage range. Spurious Out-of-Band Signals at the Analog Output With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below. Frequency Level 4.6 kHz to 40 kHz -32 dBm0 40 kHz to 240 kHz 46 dBm0o 240 kHz to 1 MHz -36 dBm0 With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to the digital input, the level of the signals at the analog output are below the limits in Figure 6. The amplitude of the spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula: A = 14 14sin 24-40%) a mo 1200 @ QSLAC Device Specification Ley Level (dBm0) 28 dB 3.4 4.0 4.6 Frequency (KHz) 21108A-015 Figure 6. Spurious Out-of-Band Signals 20 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD Overload Compression Figure 7 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The conditions for this figure are: M@ 1.2dB<GX<12dB M -12dB<GR<-1.2dB Mm PCM output connected to PCM input M@ Measurement analog-to-analog Fundamental Output Power 5L (dBm0) Acceptable Region | | | | | | | | J 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) 21108A-016 Figure 7. A/A Overload Compression SLAC Products 21AMDA PRELIMINARY SWITCHING CHARACTERISTICS (PCM/MPI MODE) over operating range unless otherwise noted Min and max values are valid for all digital outputs with a 150 pF load, except CD1-C5 with a 30 pF load. Microprocessor Interface No. Symbol Parameter Min Typ Max Units 1 tocy Data clock period 244 100,000 2 tocH Data clock High pulse width 97 3 toc Data clock Low pulse width 97 4 tpcr Rise time of clock 25 ns 5 tocr Fall time of clock 25 6 ticss Chip select setup time, Input mode 70 tpcy 10 7 ticsH Chip select hold time, Input mode 0 tpcH 20 8 ticsL Chip select pulse width, Input mode 8tpcy 9 ticso Chip select off time, Input mode (Note 1) 2.5 ys 10 tips Input data setup time 30 11 tipH Input data hold time 30 12 toLH SLIC output latch valid 1000 ng 13 tocss Chip select setup time, Output mode 70 tocy -10 14 tocsuy Chip select hold time, Output mode 0 tpcH -20 15 tocsL Chip select pulse width, Output mode 8tocy 16 tocso Chip select off time, Output mode (Note 1) 2.5 us 17 topp Output data turn on delay (Note 2) 50 18 topuy Output data hold time 0 ng 19 topor Output data turn off delay 50 20 topc Output data valid 0 50 21 trst Reset pulse width 50 us PCM Interface PCLK not to exceed 8.192 MHz, pull-up resistors of 360 Q are attached to TSCA and TSCB. No. Symbol Parameter Min Typ Max Units 22 tpcy PCM clock period (Note 3) 122 23 tecy PCM clock High pulse width 48 24 tec PCM clock Low pulse width 48 25 tpcr Fall time of clock 15 26 tpcr Rise time of clock 15 27 tess FS setup time 25 tpcy50 28 tesH FS hold time 50 29 tesy FS or PCLK jitter time -68 +68 ns 30 ttsp Delay to TSC valid (Note 4) 5 80 31 ttso Delay to TSC off (Note 4, 5) 5 80 32 toxp PCM data output delay 5 70 33 toxy PCM data output hold time 5 70 34 tpxz PCM data output delay to High-Z (Note 6) 5 70 35 tors PCM data input setup time 25 36 tory PCM data input hold time 5 22 Am79Q06/061/062/063 Data SheetPRELIMINARY Master Clock No. Symbol Parameter Min Typ Max Unit 37 Aucy Master clock accuracy 100 +100 ppM 38 tucr Rise time of clock 15 39 tuce Fall time of clock 15 ng 40 tucH MCLK High pulse width 48 41 tc. MCLK Low pulse width 48 Auxiliary Output Clocks No. Symbol Parameter Min Typ Max Unit 40 foup Chopper clock frequency CHP =0 256 CHP = 1 292.57 kHz 43 fey E1 output frequency (CMODE = EE1 = 1) 4.923 44 tey E1 pulse width (CMODE = EE1 = 1) 31.25 Us Notes: 1. If CFAIL = 1 (Command 23), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating all channels or switching them to default coefficients; otherwise, a chip select off time of 25 us is required. 2. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last. 3. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 8.192 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 128 kHz in Companded mode and 256 kHz in Linear mode or PCM Signaling mode. The minimum PCM clock rates should be doubled for paris with only one PCM highway in order to allow simultaneous access to all four channels. 4. TSC is delayed from FS by a typical value of Ntpcy, where N is the value stored in the time/clock-slot register. 5. trgo is defined as the time at which the output achieves the open circuit condition. 6. There is a special conflict detection circuitry that prevents high-power dissipation from occurring when the DXA/DU or DXB pins of two QSLAC devices are tied together and one QSLAC device siaris to transmit before the other has gone into a high-impedance state. SWITCHING WAVEFORMS Input and Output Waveforms for AC Tests 2.4 2.0 Test 2.0 Points 0.45 0.8 0.8 21108A-017 Master Clock Timing @+ Vin wl N &) <_> + > - 21108A-018 SLAC Products 23PRELIMINARY AMDA Microprocessor Interface (Input Mode) { 5 D r Data Wh Data Data vo | Valid J Valid Valid a a Outputs C5-C1 Data Valid Microprocessor Interface (Output Mode) iy 4 X a Data Valid 21108-019 Vin DCLK Vit r__/ Oho cs (45) td \ a @ 4 <>+(18) Dio Three-State Vou FF Data ONE Data Xx Data Three-State [_ | _{ : Vol + Valid _ Valid Valid SV y \ 21108A-020 24 Am79Q06/061/062/063 Data SheetPRELIMINARY PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) Time Slot Zero Same point in Clock Slot Zero previous frame > PCLK of \ / \ TY FS TSCA/ TSCB ' cc | f +) en Vou 4 ae DXA/DXB 4 First Bit X Y X 7 r oc VoL @)1->1 HG) Vin C5) First . Second DRA/DRB Bit | Bit VIL 21108A-021 SLAC Products 25AMDA PRELIMINARY PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) Same point in Time Slot Zero previous frame Clock Slot Zero > PCLK \ / aw FS } 6) 22 e @) TSCA/ TSCB - >? ae | @ @) Vou | +>} >> DXA/DXB {First Bit k Y \ S 4 3) VoL ss &)> >i [CD First Second | DRA/DRB Bit Psi | VIL 21108A-022 26 Am79Q06/061/062/063 Data SheetPRELIMINARY Double PCLK PCM Timing PCLK | FS _____}+_1 | | io. First Bit DXA/DXB, | | Second Bit < DRA/DRB bee ee eee 4 Detail Below eu eT Tassos 1 28) tpcr tace 2) - > << re o oe J t t t P PCH | le PCY | le PCL FS --- @) | | | | | | | | | | | ! tess tesH | | | | | | | | | | | | = tors toRH (36) DRA/DRB | | | | | | | | | | | | | | | | | | | | | | SLAC Products 27AMDA PRELIMINARY GCI Timing Specifications Symbol Signal Parameter Min Typ Max Units tr t DCL Rise/fall time 60 ns hoo. | vce | DOtsewaH Foes zag | ro wo |p toot DCL Period Foc. = 2.048 kHz 488 Foc. = 4.096 kHz 244 twH bw DCL Pulse width 90 tr t FS Rise/fall time 60 tsE FS Setup time 70 tpcL 50 the FS Hold time 50 ns twFH FS High pulse width 130 tupc DU Delay from DCL edge 100 tuDF DU Delay from FS edge 150 tsp DD Data setup twH + 20 tho DD Data hold 50 Note: The Data Clock (DCL) can be stopped in the high or low state without loss of information. 28 Am79Q06/061/062/063 Data SheetPRELIMINARY GCI Waveforms 4.096 MHz DCL Operation DCL 4.096 MHz | FS _____}__ | | Bit 7 DD, DU | | Bit 6 < eee al Detail Below : t, S| te : TS DCL MOK twH P toc. 1 vl 1 FS | tgF the : $_> twFH : > tube : +__> tsp tho 21108A-023 4.096 MHz DCL Operation SLAC Products 29AMDA PRELIMINARY 2.048 MHz DCL Operation DCL 2.048 MHz | | | x Bit 7 x Bit 6 x DD, DU | | t < Pp| tt |<_ : - : DCL NS : twH toc twL <_">| k ple > la FS | t t SF te <4 twFH > tape > x >_ tupc tsp tho ' + ___>- DD 21108A-024 2.048 MHz DCL Operation 30 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD OPERATING THE QSLAC DEVICE The following sections describe the operation of the four independent channels of the QSLAC device. The description is valid for Channel 1, 2, 3, or 4; consequently, the channel subscripts have been dropped. For example, VOUT refers to either VOUTy, VOUT, VOUT3, or VOUT4. Power-Up Sequence The recommended QSLAC device power-up sequence is to apply: 1. Ground first 2. VCC, signal connections, and Low on RST 3. High on RST The software initialization should then include: Wait 1 ms. 2. For PCM/MPI mode, select master clock frequency and source (Commands 12 and 13). This should turn off the CFAIL bit (Command 23) within 400 ps. While the CFAIL bit is on, normal programming can proceed, but no channels should be activated. In GCI mode, DCL is the clock source. The CFAIL bit (GCI Command SOP 8) is set to 1 until the device has determined and synchronized to the DCL frequency, 4.096 MHz or 2.048 MHz. While the CFAIL bit is on, normal programming can proceed, but no channels should be activated. If channels are activated while CFAIL is a 1, no device damage will occur, but high audible noise may appear on the line. Also, CD1, CD2, C3, C4, and C5 bit may not be stable. 3. Program filter coefficients and other parameters as required. 4. Activate (MPI Command 5, GC| Command SOP 04). If the power supply (VCCD) falls below approximately 1.0 V, the device is reset and requires complete reprogramming with the above sequence. A reset can be initiated by connection of a logic Low to the RST pin, or if chip select (CS) is held low for 16 rising edges of DCLK, a hardware reset is generated when CS returns high. The RST pin can be tied to VCCD if it is not used in the system. PCM and GCI State Selection The Am79Q06/061/062/063 QSLAC device can switch between PCM/MPI and GCI states. Table 2 lists the selection requirements. Table 2. PCM/GCI State Selection From State To State Requirement Power Onor | PCM CS =1 or DCLK has ac Hardware clock present Reset Power Onor | GCI CS = 0 and DCLK does Hardware not have ac clock Reset present GCl PCM CS = 1 or DCLK has ac clock present PCM GCI No commands yet sent in PCM state andCS =0 (for more than 2 FS) and DCLK does not have ac clock present PCM Power On or | Commands have been Hardware sent in PCM state and Reset Hardware Reset generated GCl Power Onor | Not allowed Hardware Reset Channel Enable Register In PCM/MPI mode, a channel enable register has been implemented in the QSLAC device in order to reduce the effort required to address individual or multiple channels of the QSLAC device. The register is written using MPI Command 14. Each bit of the register is assigned to one unique channel, bit 0 for Channel 1, bit 1 for Channel 2, bit 2 for Channel 3, and bit 3 for Channel 4. The channel or channels are enabled when their corresponding enable bits are High. All enabled channels receive the data written to the QSLAC device. This enables a Broadcast mode (all channels enabled) to be implemented simply and efficiently, and multiple channel addressing is accomplished without increasing the number of I/O pins on the device. The Broadcast mode can be further enhanced by providing the ability to select many chips at once; however, care should be taken not to enable more than one chip in the Read mode. This can lead to an internal bus contention, where excess power is dissipated. (Bus contention will not damage the device.) Most MPI commands defined for the DSLAC device are compatible with the QSLAC device, thereby minimizing the impact to existing system software. In GCI mode, the individual channels are controlled by their respective Monitor and SC channels embedded in the GCI channels selected by the device (SO, $1). SLAC Products 31AMDA PRELIMINARY SLIC Control and Data Lines The QSLAC device has up to five programmable Input/ Output pins per channel (CD1C5). Each of these pins can be programmed as either an input or an output using the I/O Direction Register (MPI Commands 22 and 23, GCI Command SOP 8). Also, the Am79Q063VC 64-pin package includes two additional output pins per channel, C6-C7 (see Figure 9). The output latches can be written with MPI Command 20 or through the Cl1 to Cl5 bits present in the downstream SC channel; however, only those bits programmed as outputs actually drive the pins. The inputs can be read with MPI Command 21, GCI Command SOP 10 or on the Upstream Cl bits, in the SC channel. If a pin is programmed as an output, the data read from it is the contents of the output latch. In the GCI mode, this data can be read using SOP 10, but the output bits are not sent upstream in the SC channel. Clock Mode Operation The QSLAC device operates with multiple clock signals. The master clock (MCLK) is used for internal timing including operation of the digital signal processing. In PCM/MPI mode, the master clock may be derived from either the MCLK or PCLK source. In GCI mode, the master clock is obtained from the DCL clock only. The source for the master clock must be essentially jitter free, but it can be asynchronous to PCLK in the PCM/ MPI mode. The allowed frequencies are listed under Commands 12 and 13 for PCM/MPI mode. In GCI mode, DCL can be only 2.048 MHz or 4.096 MHz. In PCM/MPI mode, the PCM clock (PCLK) is used for PCM timing and is an integer multiple of the frame sync frequency. The internal device clock (MCLK) can be optionally derived from the PCLK source by setting the CMODE bit (bit 4, commands 12 and 13, 46/47h) to one. In this mode, the MCLK/E1 pin is free to be used as an E1 signal output. In GCI mode, since the master clock is derived only from the DCL clock, this MCLK/E1 pin is always available as an E1 output. Clock mode options and E1 output functions are shown in Figure 8. PCLK MCLK/E1 + T (= 0/6 AS 4) ime = = Slot [47 / | Assigner E1 1) (= 0) CMODE----\/ (=1) Z (= 0) < +N g77 EET DSP Engine - CSEL E1 Pulses Pa E1P Notes: 1. CMODE = Command 12,13 Bit 4 2. CSEL = Command 12, 13 Bits 0-3 3. EE? = Command 45, 46 Bit 7 4. E1P=Command 45, 46 Bit Figure 8. Clock Mode Option (PCM/MPI Mode) 32 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD E1 Mulitplex Operation The QSLAC device can multiplex input data from the CD1 SLIC I/O pin into two separate status bits per channel (CD1 and CD1B bits in the SLIC Input/Output register, Commands 52/53h, and CDA and CDB bits in the Real Time Data register, Commands 4D/4Fh) using the E1 multiplex mode. This multiplex mode provides the means to accommodate dual detect states when connected to an AMD SLIC device, which also supports ground-key detection in addition to loop detect. AMD SLICs that support ground-key detect use their E1 pin as an input to switch the SLICs single detector (DET) output between internal loop detect or ground-key detect comparators. Using the E1 multiplex mode, a single QSLAC device can monitor both loop detect and ground-key detect states of all four connected SLICs without additional hardware. Although normally used for ground key detect, this multiplex function can also be used for monitoring other signal states. The E1 multiplex mode is selected by setting the EE1 bit (bit 7, Command C8/C9h) and CMODE bit (bit 4, Command 46/47h) in the QSLAC device. The CMODE bit must be selected (CMODE = 1) for the master clock to be derived from PCLK so that the MCLK/E1 pin can be used as an output for the E1 signal. The multiplex mode is then turned on by setting the EE1 bit. With the E1 multiplex mode enabled, the QSLAC device generates the E1 output signal. This signal is a 31.25 us (1/32 kHz) duration pulse occurring at a 4.923 kHz (64 kHz/13) rate. The polarity of this E1 output is selected by the E1P bit (bit 6, Command C8/ C9h) allowing this multiplex mode to accommodate all SLICs regardless of their E1 high/low logic definition. Figure 9 shows the SLIC Input/Output register, I/O pins, E1 multiplex hardware operation for one QSLAC device channel. It also shows the operation of the Real Time Register. The QSLAC device E1 output signal connects directly to the E1 inputs of all four connected SLICs and is used by those SLICs to select an internal comparator to route to the SLICs DET output. This E1 signal is also used internally by the QSLAC device for controlling the multiplex operation and timing. The CD1 and CD1B bits of the SLIC Input/Output register are isolated from the CD1 pin by transparent latches. When the E1 pulse is off, the CD1 pin data is routed directly to the CD1 bit of the SLIC I/O register and changes to the CD1B bit of that register are disabled by its own latch. When E1 pulses on, the CD1 latch holds the last CD1 state in its register. At the same time, the CD1B latch is enabled, which allows CD1 pin data to be routed directly to the CD1B bit. Therefore, during this multiplexing, the CD1 bit always has loop-detect status and the CD1B bit always has ground-key detect status. This multiplexing state changes almost instantaneously within the QSLAC device but the SLIC device may require a slightly longer time period to respond to this detect state change before its DET output settles and becomes valid. To accommodate this delay difference, the internal signals within the QSLAC device are isolated by 15.625 us before allowing any change to the CD1 bit and CD1B bit latches. This operation is further described by the E14 multiplex timing diagram in Figure 10. In this timing diagram, the E1 signal represents the actual signal presented to the E1 output pin. The GK Enable pulse allows CD1 pin data to be routed through the CD1B latch. The LD Enable pulse allows CD1 pin data to be routed through the CD1 latch. The uncertain states of the SLICs DET output, and the masked times where that DET data is ignored are shown in this timing diagram. Using this isolation of masked times, the CD1 and CD1B registers are guaranteed to contain accurate representations of the SLIC detector output. SLAC Products 33PRELIMINARY SLIC I/O Register MPI Command 20, 21 or GCI Upstream SC Channel Data C7} C6/CDIB/C5 | C4 | C3 ];CD2] CD1 I | DQ | -> | EN/HOLD | TL CD1 <>} CD2 > C3 +> C4 +> C5 +> ce <+* C7 <+l_, | | D Q __ > VO Direction | EN/HOLD Register +, (UL * VY, MPI Command 22| Output Latch MUX or GCI SOP LD Enable Command 8 J SLIC Output Data Register Ground Key Filter MPI Command 20 GK Enable qT >H4 (time set via or GCI Downstream Commands 52, 53) | | | | | SC Channel Data , | (Channel 1 Debounce EE1 Bit Shown) (time set via | Commands 45, 46) | 1 Source | (Internal) H ff Same for | _| { = Channels Delay fF 23.4 | (See Figure 10 MCLK/E14> <x [ for details) Real Time Data Register (MPI Command 16, 17 or GCI UpstreamSC Channel data) | | E1P I CDB,|CDA,| CDBs|CDAg | CDBa|CDA, |CDB, | CDA, nTe Fp Old Flag (CMD 47, Bit 0) Interrupt Mask Register ATI (MPI CMD 28, 29 (MPI Command 26, 27 or GCI SOP 5) or GCI Upstream SC Channel data) MCDB,|MCDA,|MCDBs| MCDA3| MCDB |MCDA| MCDB,| MCDA, Note: * Transparent latches: When enable input is high, Q output follows D input. When enable input goes low, Q output is latched at last siate. Figure 9. SLIC I/O, E1 Multiplex and Real-Time Data Register Operation 34 Am79Q06/061/062/063 Data SheetPRELIMINARY Pulse Period 203.125 us #-- - 3-3-3 Ss > 4.923 kHz (64 kHz/13) pulse rate = 31.25 us LD Enable : 115.625 us DET Output from SLIG DSK DOK (CD1 Pin Input) CD1 Pin Contains n | Contains | CDi Pin / Contains input Data Valid LD | State valid GK | State = Valid LD Status [Ignored =| Status_| ignored ~|_ Status Se Track Tracks Register rACKS Hold Last $ Operation DET State old Last State DET State CD1B Track Register Hold Last State | State | Hold Last State Operation DET State Figure 10. E1 Multiplex Internal Timing Debounce Filters Operation Each channel has two debounce filter circuits to buffer the logic status of the CD1 and CD2/CD1B bits of the SLIC I/O Data Register (MPI Commands 20 and 21 and GCI Command SOP 10, 52/53h) before providing filtered bit outputs to the Real-Time Data Register (MPI Commands 16 and 17 or GCI Command SOP 13, 4D/4Fh). One filter is for the CD1 bit. The other filter either acts upon the CD1B bit if E1 multiplexing is enabled or on the CD2 bit if the multiplexing is not enabled. The CD1 bit normally contains SLIC loop-detect status. The CD1 debouncing time is programmable with the Debounce Time Register (MPI Commands 45 and 46 or GCI Command SOP 11, C8/C9h), and even though each channel has its own filter, the programmed value is common to all four channels. This debounce filter is initially clocked at the frame sync rate of 125 us, and any occurrence of changing data at this sample rate resets a programmable counter. This programmable counter is clocked at a 1 ms rate, and the programmed count value of 0-15 ms, as defined by the Debounce Time Register, must be reached before updating the CDA bit of the Real Time Data register with the CD1 state. Refer to Figure 11a for this filters operation. The ground-key filter (Figure 11b) provides a buffering of the signal, normally ground-key detect, which appears in the CDB bit of the Real-Time Data Register and the SC upstream channel in GCI mode. Each channel has its own filter, and each filters time can be individually programmed. The input to the filter comes from either the CD2 bit of the SLIC I/O Data Register (52/53h), when E1 multiplexing is not enabled, or from the CD1B bit of that register when E1 multiplexing is enabled. The feature debounces ground-key signals before passing them to the Real Time Data Register, although signals other than ground-key status can be routed to the CD2 pin and then through the registers. The ground-key debounce filter operates as a duty- cycle detector and consists of an up/down counter that ranges between 0 and 6. This six-state counter is clocked by the GK timer at the sampling period of 1-15 ms, as programmed by the value of the four GK bits (GK3, GK2, GK1, GKO) of the Ground-Key Filter Data register (Commands 52 and 53 and GCI Command SOP 12, E8/E9h). This sampling period clocks the counter, which buffers the CD2/CD1B bits status before it is valid for presenting to the CDB bit of the Real Time Data Register. When the sampled value of the ground-key (or CD2) input is high, the counter is incremented by each clock pulse. When the sampled value is low, the counter is decremented. When the counter increments to 6, it sets a latch whose output is routed to the corresponding CDB bit. If the counter decrements to 0, this latch is cleared and the output bit is set to 0. All other times, the latch (and the CDB status) remains in its previous state without change. It therefore takes at least six consecutive GK clocks with the debounce input remaining at the same state to effect an output change. If the GK bit value is set to zero, the buffering is bypassed and the input status is passed directly to CDB. SLAC Products 35AMDA PRELIMINARY CD1 CDA Debounce Counter E * DSHODSH3 Debounce Period (0-15 ms) CK = 8 FS (8 kHz) Notes: * Transparent latch: Output follows input when EN is high; output holds last state when EN is low Debounce Counter: Output goes high after counting to programmed (DSH) number of 1 ms clocks; Counter is reset for CD1 input changes at 125 us sample period. DSHO-DSH3 programmed value is common for all 4 channels, but debounce counter is separate per channel a. Loop Detect Debounce Filter MUX CD2 or CD1B GK= GKO-GK3 4 _ CDB Ground-Key 4 UP/DN Sampling Interval Q GK#Q (1-15 ms) ~_] > GK 1 kHz S RST ~ Six-State Clock Divider Up/Down (1-15 ms Counter Notes: clock output) Programmed value of GKOGK3 determines clock rate (1-15 ms) of six-state counter. If GK value = 0, counter is bypassed and no buffering occurs. Six-slate up/down counter: Counts up when input is high; counts down when input is low. Output goes and stays high when maximum count is reached; output goes and stays low when counts down to zero. b. Ground-Key Filter Figure 11. MPI Real-Time Data Register or GCI Upstream SC Channel Data Real-Time Data Register Operation To obtain time-critical data such as off/on-hook and ring trip information from the SLIC with a minimum of processor time and effort, the QSLAC device contains an 8-bit Real Time Data register. This register contains CDA and CDB bits from all four channels. The CDA bit for each channel is a debounced version of the CD1 input. The CDA bit is normally used for switchhook. The CDB bit for each channel normally contains the CD2 input bit; however, if the E1 multiplex operation is enabled, the CDB bit will contain the debounced value of the CD1B bit. CD1 and CD2 can be assigned to off- hook, ring trip, ground key signals, or other signals. Frame sync is needed for the debounce and the ground-key signals. If Frame sync is not provided, the real-time register will not work. The register is read using MPI Commands 16 and 17 or GCI Command SOP 13 (4D/4Fh), and may be read at any time regardless of the state of the Channel Enable Register. This allows off/on-hook, ring trip, or ground key information for all four channels to be obtained from the QSLAC device with one read operation versus one read per channel. If these data bits are not used for supervision information, they can be accessed on an individual channel basis in the same way as C3-C5; however, CD1 and CD1B will not be debounced. This Real-Time Data register is available in both MPI and GCI modes. In the GCI mode, this real-time data is also available in the field of the upstream SC octet. Interrupt In addition to the Real Time Data register, an interrupt signal is provided by the QSLAC device. The Interrupt signal is an active Low output signal that pulls Low any time any of the unmasked CD bits changes state (Low to High or High to Low); or any time the transmit PCM 36 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDZ data changes on a channel where the Arm Transmit Interrupt (AT) bit is on. The interrupt control is shown in Figure 9. The interrupt remains Low until the appropriate register is read. This outout can be programmed as a TTL or open drain output by the INTM bit, MPI Command 12 or GCI Command SOP 6. When an interrupt is generated, all of the unmasked bits in the Real Time Data register are latched and remain latched until the interrupt is cleared. The interrupt is cleared by reading the register with MPI Command 17 or GCl Command SOP 13, by writing to the interrupt mask register (MPI Command 26 or GCI Command SOP 14), or by a reset. If any of the inputs to the unmasked bits in the Real Time Data register are different from the register bits at the time that the interrupt is cleared, a new interrupt is immediately generated with the new data latched into the Real Time Data register. For this reason, the interrupt logic in the controller should be level sensitive rather than edge sensitive. Interrupt Mask Register The Real Time Data register data bits can be masked from causing an interrupt to the processor using the interrupt mask register. The contents of the mask register can be written or read via the MP! Commands 26 and 27 or GCI Command SOP 14. Active State Each channel of the QSLAC device can operate in either the Active (operational) or Inactive (standby) mode. In the Active mode, individual channels of the QSLAC device can transmit and receive PCM or linear data and analog information. The Active mode is required when a telephone call is in progress. The Activate command, MPI Command 5, GCI Command SOP 4, puts the selected channels (see channel enable register for PCM/MPI Mode) into this state. Bringing a channel of the QSLAC device into the Active mode is only possible through the MPI command or the GCI Command. Inactive State All channels of the QSLAC device are forced into the Inactive mode by a power-up or hardware reset. Individual channels can be programmed into this mode by the deactivate command (MPI Command 1, GCI Command SOP 1) or by the software reset command (MPI Command 2, GCI Command 2). Power is disconnected from all nonessential circuitry, while the MPI remains active to receive commands. The analog output is tied to VREF through a resistor whose value depends on the VMODE bit. All circuits that contain programmed information retain their data in the Inactive mode. Low Power State lf all four channels are deactivated and Low Power mode is selected, the internal clock speed of the part will be reduced to 1/6 of its normal speed. When this happens, the CFAIL bit is set to 1, and the microprocessor interface works at 1/6 its normal speed. That is, the CS must be high six times as long between MPI commands. Chopper Clock The Am79Q06 and Am79Q063 devices provide a chopper clock output to drive the switching regulator on some AMD SLICs. The clock frequency is selectable as 256 or 292.57 kHz by the CHP bit (MPI Command 12/GC| Command SOP 6). The chopper output must be turned on with the ECH bit (MPI Command 45, GC! Command SOP 11). Reset States The QSLAC device can be reset by application of power, by an active Low on the hardware Reset pin (RST), by a hardware reset command, or by CS Low for 16 or more rising edges of DCLK. 1. A-law companding is selected. 2. Default filter values B, X, R, and Z are selected and the AISN is set to zero. 3. Default digital gain blocks, GX and GR, are selected. The analog gains, AX and AR, are set to 0 dB. 4. SLIC input/outputs CD1, CD2, C8, C4, and C5 are set to the Input mode. 5. All of the test modes in the Operating Conditions Register are turned off (Os). 6. All four channels are placed in the Inactive (standby) mode. 7. For PCM/MPI mode, transmit time slots and receive time slots are set to 0, 1, 2, and 3 for Channels 1, 2, 3, and 4, respectively. The clock slots are set to 0, with transmit on the negative edge. For GCI mode, operation is determined by SO and S1. 8. DXA/DU portis selected for all channels. 9. DRA/DD port is selected for all channels. 10. The master clock frequency in PCM/MPI mode is selected to be 8.192 MHz and is programmed to come from PCLK. In GCI mode, DCL is 2.048 or 4.096 MHz and is determined by the QSLAC device. 11. All four channels are selected in the Channel Enable Register for PCM/MPI mode. 12. Any pending interrupts are cleared, all interrupts are masked, and the Interrupt Output mode is set to open drain. 13. The supervision debounce time is set to 8 ms. 14. The previously programmed B, Z, X, R, GX, and GR filters are unchanged. 15. The chopper clock frequency is set to 256 kHz, but the chopper clock is turned off. 16. The E1 Multiplex mode is turned off and the polarity is set for high going pulses. 17. No signaling on the PCM highway (PCM/MPI mode). SLAC Products 37AMDA PRELIMINARY SIGNAL PROCESSING Overview of Digital Filters Several of the blocks in the signal processing section are user-programmable. These allow the user to optimize the performance of the QSLAC device for the system. Figure 12 shows the QSLAC device signal processing and indicates the programmable blocks. Cutoff r High Pass Filter (HPF) - 5 paremt l l VIN Deci- Deci- LPF Com- (CTP) ADC}H GXH X a mator mator |? & HPF pressor| <~_| TSA) ee- Digital t : TX : * * TSA Full + Loopback Digital | z Ix * (TLB) Loop ! DL) ; L Cutoff Receive ; Path (CRP) Inter- Inter- Ex- Digital oo! DACH -(+) GRH R WH LPF bee /__ Vout t . polator polator t pander rs TSA RX VREF * L * 0 1 kHz Tone ~ Lower Receive (TON) Gain (LRG) * programmable blocks 21108-027 Figure 12. QSLAC Device Block Diagram The advantages of digital filters are High reliability No drift with time or temperature Unit-to-unit repeatability Superior transmission performance Flexibility Maximum possible bandwidth for V.34 modems. Two-Wire Impedance Matching Two feedback paths on the QSLAC device synthesize the two-wire input impedance of the SLIC by providing a programmable feedback path from VIN to VOUT. The Analog Impedance Scaling Network (AISN) is a programmable analog gain of -0.9375 to +0.9375 from VIN to VOUT. The Z filter is a programmable digital filter providing an additional path and programming flexibility over the AISN in modifying the transfer function from VIN to VOUT. Together, the AISN and the Z-filter enable the user to synthesize virtually all required SLIC input impedances. Frequency Response Correction and Equalization The QSLAC device contains programmable filters in the receive (R) and transmit (X) directions that can be programmed for line equalization and to correct any attenuation distortion caused by the Z filter. Transhybrid Balancing The QSLAC devices programmable B filter is used to adjust transhybrid balance. The filter has a single pole IIR section (BIIR) and an eight-tap FIR section (BFIR), both operating at 16 kHz. Gain Adjustment The QSLAC device's transmit path has two programmable gain blocks. Gain block AX is an analog gain of 0 dB or 6.02 dB (unity gain or gain of 2.0), located immediately before the A/D converter. GX is a digital gain block that is programmable from 0 dB to +12 dB, with a worst-case step size of 0.1 dB for gain settings below +10 dB, and a worst-case step size of 0.3 dB for gain settings above +10 dB. The filters provide a net gain in the range of 0 dB to 18 cB. The QSLAC device receive path has two programmable loss blocks. GR is a digital loss block that is programmable from 0 dB to 12 dB, with a worst-case step size of 0.1 dB (unity gain or gain of 0.5). Loss block AR is an analog loss of 0 dB or 6.02 dB, located immediately after the D/A converter. This provides a net loss in the range of 0 dB to 18 dB. An additional 6 dB attenuation is provided as part of GR, which can be inserted by setting the RG bit of Command 70/71h. This allows writing of a single bit to introduce 6 dB of attenuation into the receive path without having to reprogram GR. This 6 dB loss is 38 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA implemented as part of GR and the total receive path attenuation must remain in the specified 0 to -12 dB range. If the RG bit is set, the programmed value of GR must not introduce more than an additional 6 dB attenuation. Transmit Signal Processing In the transmit path (A/D), the analog input signal (VIN) is A/D converted, filtered, companded (for A-law or p- law), and made available to the PCM highway or General Circuit Interface (GCI). Linear mode is only available in the PCM/MPI mode. If linear form is selected, the 16-bit data is transmitted in two consecutive time slots starting at the programmed time slot. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The B, X, and GX blocks are user- programmable digital filter sections with coefficients stored in the coefficient RAM, while AX is an analog amplifier that can be programmed for 0 dB or 6.02 dB gain. The B, X, and Gx filters can also be operated from an alternate set of default coefficients stored in ROM (MPI Command 24/25, GCI Command SOP 7). The decimator reduces the high input sampling rate to 16 kHz for input to the B, GX, and X filters. The X filter is a six-tap FIR section that is part of the frequency response correction network. The B filter operates on samples from the receive signal path to provide transhybrid balancing in the loop. The high-pass filter rejects low frequencies such as 50 Hz or 60 Hz, and can be disabled. Transmit PCM Interface (PCM/MPI Mode) In PCM/MPI mode, the transmit PCM interface transmits a 16-bit linear code (when programmed) or an 8-bit compressed code from the digital A-law or p-law compressor. Transmit logic controls the transmission of data onto the PCM highway through output port selection and time/clock slot control circuitry. The linear data requires two consecutive time slots, while a single time slot is required for A-law or p-law data. In the PCM Signaling mode (SMODE = 1), the transmit time slot following the A-law or ut-law data is used for signaling information. The two time slots form a single 16-bit data block. The frame sync (FS) pulse identifies time slot 0 of the transmit frame and all channels (time slots) are referenced to it. The logic contains user-programmable Transmit Time Slot and Transmit Clock Slot registers. The Time Slot register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) ina system. The data is transmitted in bytes, with the most significant bit first. The Clock Slot register is 3 bits wide and may be programmed to offset the time slot assignment by 0 to 7 PCLK periods to eliminate any clock skew in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a nonzero remainder, R, and when the transmit clock slot is greater than R. In that case, the R-bit fractional time slot after the last full time slot in the frame will contain random information and will have the TSC output turned on. For example, if the PCLK frequency is 1.544 MHz (R = 1) and the transmit clock slot is greater than 1, the 1-bit fractional time slot after the last full time slot in the frame contains random information, and the TSC output remains active during the fractional time slot. In such cases, problems can be avoided by simply not using the last time slot. The PCM data can be user programmed for output onto either the DXA or DXB port or both ports simultaneously. Correspondingly, either TSCA or TSCB or both are Low during transmission. The DXA/DXB and TSCA/TSCB outputs can be programmed to change either on the negative or positive edge of PCLK. Transmit data can also be read through the microprocessor interface using Command 47. Data Upstream Interface (GCI Mode) In the GCI mode, the Data Upstream (DU) interface transmits a total of 4 bytes per GCI channel. Two bytes are from the A-law or p-law compressor, one for voice channel 1, one for voice channel 2, a single Monitor channel byte, and a single SC channel byte. Transmit logic controls the transmission of data onto the GCI bus as determined by the frame synchronization signal (FSC) and the SO and S1 channel select bits. No signaling or Linear mode options are available when GCI mode is selected. The frame synchronization signal (FSC) identifies GC! channel 0 and all GCI channels are referenced to it. Upstream Data is always transmitted at a 2.048 MHz data rate. Receive Signal Processing In the receive path (D/A), the digital signal is expanded (for A-law or p-law), filtered, converted to analog, and passed to the VOUT pin. The signal processor contains an ALU, RAM, ROM, and Control logic to implement the filter sections. The Z, R, and GR blocks are user- programmable filter sections with their coefficients stored in the coefficient RAM, while AR is an analog amplifier that can be programmed for a 0 dB or 6.02 dB loss. The Z, R, and GR filters can also be operated from an alternate set of default coefficients stored in ROM (MPI Commands 24 and 25, GCI Command SOP 7}. The low-pass filter band limits the signal. The R filter is composed of a six-tap FIR section operating at a 16 kHz SLAC Products 39AMDA PRELIMINARY sampling rate and a one-tap IIR section operating at 8 kHz. It is part of the frequency response correction network. The Analog Impedance Scaling Network (AISN) is a user-programmable gain block providing feedback from VIN to VOUT to emulate different SLIC input impedances from a single external SLIC impedance. The Z filter provides feedback from the transmit signal path to the receive path and is used to modify the effective input impedance to the system. The interpolator increases the sampling rate prior to D/A conversion. Receive PCM Interface (PCM/MPI Mode) The receive PCM interface logic controls the reception of data bytes from the PCM highway, transfers the data to the A-law or p-law expansion logic for compressed signals, and then passes the data to the receive path of the signal processor. If the data received from the PCM highway is programmed for linear code, the A-law or p- law expansion logic is bypassed and the data is presented to the receive path of the signal processor directly. The linear data requires two consecutive time slots, while the A-law or w-law data requires a single time slot. The frame sync (FS) pulse identifies time slot 0 of the receive frame, and all channels (time slots) are referenced to it. The logic contains user-programmable Receive Time Slot and Receive Clock Slot registers. The Time Slot register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system. The Clock Slot register is 3 bits wide and can be programmed to offset the time slot assignment by 0 to 7 PCLK periods to eliminate any clock skews in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a nonzero remainder, R, and when the receive clock slot is greater than R. In this case, the last full receive time slot in the frame is not usable. For example, if the PCLK frequency is 1.544 MHz (R = 1), the receive clock slot can be only 0 or 1 if the last time slot is to be used. The PCM data can be user-programmed for input from either the DRA or DRB port. Data Downstream Interface (GCI Mode) The Data Downstream (DD) interface logic controls the reception of data bytes from the GCI highway. The GCI channels received by the QSLAC device is determined by the logic levels on SO and $1, the GCI channel select bits. The two compressed voice channel data bytes of the GCI channel are transferred to the A-law or p-law expansion logic. The expanded data is passed to the receive path of the signal processor. The Monitor channel and SC channel bytes are transferred to the GCI control logic for processing. The frame synchronization signal (FSC) identifies GC! channel 0 of the GCI frame, and all other GCI channels are referenced to it. Downstream Data is always received at a 2.048 MHz data rate. Analog Impedance Scaling Network (AISN) The AISN is incorporated in the QSLAC device to scale the value of the external SLIC impedance. Scaling this external impedance with the AISN (along with the Z filter) allows matching of many different line conditions using a single impedance value. Linecards can meet many different specifications without any hardware changes. The AISN is a programmable transfer function connected from VIN to VOUT of each QSLAC device channel. The AISN transfer function is used to alter the input impedance of the SLIC device to a new value (ZIN) given by: ZIN = ZSL (1 G44 hyisx)/ (1 G440 has) where G440 is the SLIC echo gain into an open circuit, G44 is the SLIC echo gain into a short circuit, and ZSL is the SLIC input impedance without the QSLAC device. The gain can be varied from 0.9375 to +0.9375 in 31 steps of 0.0625. The AISN gain is determined by the following equation: 4 Harsw = 0.0625 S AISNi 2! ~ 16 i=0 where AISN = 0 or 1 There are two special cases to the formula for hajsn: 1) a value of AISN = 00000 specifies a gain of 0 (or cutoff), and 2) a value of AISN = 10000 is a special case where the AISN circuitry is disabled and VOUT is connected internally to VIN with a gain of 0 dB. This allows a Full Digital Loopback mode where an input digital PCM signal is completely processed through the receive section, looped back, processed through the transmit section, and output as digital PCM data. During this test, the VIN input is ignored and the VOUT output is connected to VREF. Speech Coding The A/D and D/A conversion follows either the A-law or the p-law standard as defined in ITU-T Recommendation G.711. A-law or p-law operation is programmed using MPI Commands 24/25 or GC| Command SOP 7. Alternate bit inversion is performed as part of the A-law coding. In PCM/MPI mode, the QSLAC device provides linear code as an option on both the transmit and receive sides of the device. Linear code is selected using MPI Commands 24 and 25. Two successive time slots are required for linear code operation. The linear code is a 16-bit twos-complement 40 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD number that appears sign bit first on the PCM highway. Linear code occupies two time slots. Double PCLK (DPCK) Operation (PCM/MPI Mode) The Double PCLK Operation allows the PCM clock (PCLK) signal to be clocked at a rate of twice that of the PCM data. This mode provides compatibility of the QSLAC device with other existing system architectures, such as a GCI interface system in terminal mode operating at a 768 kHz data rate with a 1.536 MHz clock rate. The operation is enabled by setting the DPCK bit of Command 45 and 46 (C8/C9h). When set to zero, operation is unchanged from normal PCM clocking and the PCM data and clock rates are the same. When the bit is set to 1, clocking of PCM data is divided by two and occurs at one half of the PCLK PCM clock rate. The internal PLL used for synchronization of the master DSP clock (MCLK) receives its input from either the MCLK or PCLK pin, depending on the clock mode (CMODE) selection. If PCLK is used for MCLK (CMODE = 1}, then the clock input is routed to both the DSP clock input and to the time slot assigner. The timing division related to the double PCLK mode occurs only within the time slot assigner, and therefore, double PCLK operation is available with either CMODE setting. This allows the MCLK/E1 pin to be available for E1 multiplexing operation if both double PCLK and E1 multiplexing modes are simultaneously required. Specifications for Double PCLK Operation are shown in Switching Characteristics. Signaling on the PCM Highway (PCM/MPI Mode) If the SMODE bit is set in the Configuration Register, each data point occupies two consecutive time slots. The first time slot contains A-law or u-law data and the second time slot has the following information: Bit 7: Debounced CD1 bit (usually switchhook) Bit 6: CD2 bit or CD1B bit Bits 5-3: Reserved Bit 2: CFAIL Bits 1-0: Reserved Bit 7 of the signaling byte appears immediately after bit 0 of the data byte. A-law or t-law Companded mode must be specified in order to put signaling information on the PCM highway. The signaling time slot remains active, even when the channel is deactivated. Robbed-Bit Signaling Compatibility (PCM/MPI Mode) The QSLAC device supports robbed bit signaling compatibility. Robbed bit signaling allows periodic use of the least significant bit (LSB) of the receive path PCM data to be used to carry signaling information. In this scheme, separate circuitry within the line card or system intercepts this bit out of the PCM data stream and uses this bit to control signaling functions within the system. The QSLAC device does not perform any processing of any of the robbed bits during this operation; it simply allows for the robbed bit presence by performing the LSB substitution. If the RBE bit is set, then the robbed-bit signaling compatibility mode is enabled. Robbed-bit signaling is only available in the u-law companding mode of the device. Also, only the receive (digital-to-analog) path is involved. There is no change of operation to the transmit path and PCM data coming out of the QSLAC device will always contain complete PCM byte data for each time slot, regardless of robbed-bit signaling selection. In the absence of actual PCM data for the affected time slots, there is an uncertainty of the legitimate value of this bit to accurately reconstruct the analog signal. This bit can always be assumed to be a 1 or 0; hence, the reconstructed signal is correct half the time. However, the other half of the time, there is an unacceptable reconstruction error of a significance equal to the value weighting of the LSB. To reduce this error and provide compatibility with the robbed bit signaling scheme, when in the robbed-bit signaling mode, the QSLAC device ignores the LSB of each received PCM byte and replace its value in the expander with a value of half the LSBs weight. This then guarantees the reconstruction is in error by only half this LSB weight. In the expander, the eight bits of the companded PCM byte are expanded into linear PCM data of several more bits within the internal signal processing path of the device. Therefore, accuracy is not limited to the weight of the LSB, and a weight of half this value is realizable. When this robbed-bit mode is selected, not every frame contains bits for signaling, and therefore not every byte requires its LSB substituted with the half- LSB weight. This substitution only occurs for valid PCM time slots within frames for which this robbed bit has been designated. To determine which time slots are affected, the device monitors the frame sync (FS) pulse. The current frame is a robbed-bit frame and this half-LSB value is used only when this criteria is met: SLAC Products 41AMDA PRELIMINARY M@ The RBE bit is set, and M@ The device is in the p-law companding mode, and @ The current frame sync pulse (FS) is two PCLK cycles long, and @ The previous frame sync pulse (FS) was not two PCLK cycles long. The frame sync pulse is sampled on the falling edge of PCLK. As shown in Figure 18, if the above criteria is met, and if FS is high for two consecutive falling edges of PCLK then low for the third falling edge, it is considered a robbed-bit frame. Otherwise, it is a normal frame. PCLK FS v 4 Normal Frame (Not Robbed-Bit) PCLK FS Robbed-Bit Frame Figure 13. Robbed-Bit Frame Default Filter Coefficients The QSLAC device contains an internal set of default coefficients for the programmable filters. These coefficients were determined to allow reasonable system performance for initial power-up non- programmed situations, such as may exist before a system processor has opportunity to program any coefficients. The default filter coefficients are calculated assuming an Am7920 SLIC with 50 Q protection resistors, a 178 kQ transversal impedance (ZT), and a 90.5 kQ receive impedance (ZRX). This SLIC has a transmit gain of 0.5 (GTX) and a current gain of 500 (K1). The transmit relative level is set to +0.28 dBr, and the receive relative level is set to 4.39 dBr. The equalization filters (X and R) are not optimized. The balance filter was designed to give acceptable balance into a variety of impedances. The nominal input impedance was set to 815 . If the SLIC circuit differs significantly from this design, the default filters cannot be used and must be replaced by programmed coefficients. To obtain this above-system response, the default filter coefficients are set to produce these values: GX gain = +6 dB, GR gain = -8.984 dB AX gain = 0 dB, AR gain = 0 dB R filter: H(z) = 1, X filter: H(z) = 1 Z filter: H(z) = 0, B filter H(z) = 0 AISN = cutoff Notice that these default coefficient values are retained in a read-only memory area within the QSLAC device, and those values cannot be read back using any data commands. When the device is selected to use default coefficients, it obtains those values directly from the read-only memory area. The coefficient read operations access the programmable random access data memory only. If an attempt is made to read back any filter values without those values first being written with known programmed data, the values read back are totally random and do not represent the default or any other values. COMMAND DESCRIPTION AND FORMATS Microprocessor Interface Description When PCM/MPI mode is selected via the CS/PG and DCLK/SO pins, a microprocessor can be used to program the QSLAC device and control its operation using the Microprocessor Interface (MPI). Data programmed previously can be read out for verification. Commands are provided to assign values to the following channel parameters: TTS - Transmit time slot RTS - Receive time slot TCS - Transmit clock slot RCS - Receive clock slot GX - Transmit gain GR - Receive loss By, Bo - B-filter coefficients Xx - X-filter coefficients R - F-filter coefficients Z - Z-filter coefficients AISN - AISN coefficient CD1-C5 - Read/Write SLIC Input/Output lOD1-5 - SLIC Input/Output Direction A/a, C/L - Select A-law, p-law, or linear code TPCM, TAB -_ Select Transmit PCM Port A or B or both RPCM - Select Receive PCM Port A or B EB - Programmed/Default B filter EZ - Programmed/Default Z filter EX - Programmed/Default X filter ER - Programmed/Default R filter EGX - Programmed/Default GX filter EGR - Programmed/Default GR filter AX - Enable/disable AX amplifier AR - Enable/disable AR amplifier 42 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD TP - Cutoff Transmit Path CRP - Cutoff Receive Path HPF - Disable High Pass Filter LRG - Lower Receive Gain AT| - Arm Transmit Interrupt ILB - Interface Loopback FDL - Full Digital Loopback TON - 1kHz Tone On cs - Select Active or Inactive (standby) mode Commands are provided to read values from the following channel monitors: SLIC status XDAT - Transmit PCM data Commands are provided to assign values to the following global chip parameters: XE - Transmit PCM Clock Edge RCS - Receive Clock Slot TCS - Transmit Clock Slot INTM - Interrupt Output Drive Mode CHP - Chopper Clock Frequency ECH - Enable Chopper Clock Output SMODE - Select Signaling on the PCM Highway CMODE - Select Master Clock Mode CSEL - Select Master Clock Frequency EC - Channel Enable Register DSH - Debounce Time for CD1 EE4 - Enable E1 Output E1P - 1 Polarity MCDxy - Interrupt Mask Register Commands are provided to read values from the following global chip status monitors: CDxy - Real Time Data Register Pl - Power Interruption Bit CFAIL - Clock Failure Bit RCN - Revision Code Number The following description of the MPI (Microprocessor Interface) is valid for Channel 1, 2, 3, or 4. If desired, multiple channels can be programmed simultaneously with identical information by setting multiple Channel Enable bits. Channel enables are contained in the Channel Enable Register and are written or read using Commands 14 and 15. If multiple Channel Enable bits are set for a read operation, only data from the first enabled channel is read. The MPI physically consists of a serial data input/output (DIO), a data clock (DCLK), and a chip select (CS). Individual Channel Enable bits EC1, EC2, EC3, and EC4 are stored internally in the Channel Enable Register of the QSLAC device. The serial input consists of 8-bit commands that can be followed with additional bytes of input data, or can be followed by the QSLAC device sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. All data bytes are read or written one at atime, with CS going High for at least a minimum off period before the next byte is read or written. Only a single channel should be enabled during read commands. All commands that require additional input data to the device must have the input data as the next N words written into the device (for example, framed by the next N transitions of CS). All unused bits should be programmed as 0 to ensure compatibility with future parts. All commands that are followed by output data will cause the device to output data for the next N transitions of CS going Low. The QSLAC device will not accept any commands until all the data has been shifted out. The output values of unused bits are not specified. An MPI cycle is defined by transitions of CS and DCLK. lf the CS lines are held in the High state between accesses, the DCLK runs continuously with no change to the internal control data. Using this method, the same DCLK can be run to a number of QSLAC devices and the individual CS lines will select the appropriate device to access. Between command sequences, DCLK can stay in the High state indefinitely with no loss of internal control information regardless of any transitions on the CS lines. Between bytes of a multibyte read or write command sequence, DCLK can also stay in the High state indefinitely. DCLK can stay in the Low state indefinitely with no loss of internal control information, provided the CS lines remain at a High level. If a low period of CS contains less than 8 positive DCLK transitions, it is ignored. If it contains 8 to 15 positive transitions, only the last 8 transitions matter. If it contains 16 or more positive transitions, a hardware reset in the part occurs. If the chip is in the middle of a read sequence when CS goes Low, data will be present at the DIO pin even if DCLK has no activity. If CS is held low for two or more cycles of Frame Sync (FS) and DCLK is static (no toggling), then the QSLAC device switches to the General Circuit Interface mode of operation. SLAC Products 43AMDA PRELIMINARY Summary of MPI Commands* Number Hex Description 1 00 Deactivate (Standby Mode) 2 02 Software Reset 3 04 Hardware Reset 4 06 No Operation 5 OE Activate (Operational Mode) 6,7 40/41 Write/Read Transmit Time Slot and PCM Highway Selection 8,9 42/43 Write/Read Receive Time Slot and PCM Highway Selection 10,11 44/45 Write/Read REC & TX Clock Slot and TX Edge 12,13 46/47 Write/Read Configuration Register 14,15 4A/4B Write/Read Channel Enable & Operating Mode Register 16 4D Read Real Time Data Register 17 4F Read Real Time Data Register and Clear Interrupt 18,19 50/51 Write/Read AISN and Analog Gains 20,21 52/53 Write/Read SLIC Input/Output Register 22,23 54,55 Write/Read SLIC Input/Output Direction and Status Bits 24,25 60/61 Write/Read Operating Functions 26,27 6C/6D Write/Read Interrupt Mask Register 28,29 70/71 Write/Read Operating Conditions 30 73 Read Revision Code Number (RCN) 31,32 80/81 Write/Read GX Filter Coefficients 33,34 82/83 Write/Read GR Filter Coefficients 35,36 84/85 Write/Read Z Filter Coefficients (FIR and IIR) 37, 38 86/87 Write/Read B1 Filter Coefficients (FIR) 39, 40 88/89 Write/Read X Filter Coefficients 41, 42 8A/8B Write/Read R Filter Coefficients 43, 44 96/97 Write/Read B2 Filter Coefficients (IIR) 45, 46 C8/C9 Write/Read Debounce Time Register 47 CD Read Transmit PCM Data 48, 49 98/99 Write/Read Z Filter Coefficients (FIR only) 50, 51 9A/9B Write/Read Z Filter Coefficients (IIR only) 52,53 E8/E9h Write/Read Ground Key Filter Sampling Interval Note: *All codes not listed are reserved by AMD and should not be used. 44 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD MPI COMMAND STRUCTURE This section details each MPI command. Each command is shown along with the format of any additional data bytes that follow. For details of the filter coefficients of the form C,ym,y, refer to the Description of CSD Coefficients section on page 85. Unused bits are indicated by RSVD; 0s should be written to them, but 0s are not guaranteed when they are read. Default field values are marked by an asterisk. A hardware reset forces the default values. 1. Deactivate (Standby State) MPI Command (00h) D, De Ds Dy Ds Do D, Do Command 0 0 0 0 0 0 0 0 In the Deactivated mode: All programmed information is retained. The Microprocessor Interface (MPI) remains active. The PCM inputs are disabled and the PCM outputs are high impedance unless signaling on the PCM highway is programmed (SMODE = 1). The analog output (VOUT) is disabled and biased at 2.1 V. The channel status (CS) bit in the SLIC I/O Direction and Channel Status Register is set to 0. 2. Software Reset MPI Command (02h) D, De Ds D4 Ds Do D, Do Command 0 0 0 0 0 0 1 0 The action of this command is identical to that of the RST pin except that it only operates on the channels selected by the Channel Enable Register and it does not change clock slots, time slots, PCM highways, or global chip parameters. See the note under the hardware reset command that follows. 3. Hardware Reset MPI Command (04h) D; De Ds D4 Ds Do D, Do Command 0 0 0 0 0 1 0 0 Hardware reset is equivalent to pulling the RST on the device Low. This command does not depend on the state of the Channel Enable Register. Note: The action of a hardware reset is described in Reset States on page 31 of the section Operating the QSLAC Device. SLAC Products 45AMDA PRELIMINARY 4. No Operation MPI Command (06h) Dy De Ds Dg D3 Do Dy Do Command 0 0 0 0 0 1 1 0 5. Activate Channel (Operational Mode) MPI Command (OEh) D, De Ds Dy D3 Do Dy Do Command 0 0 0 0 1 1 1 0 This command places the device in the Active mode and sets CS = 1. No valid PCM data is transmitted until after the second FS pulse is received following the execution of the Activate command. 6, 7. Write/Read Transmit Time Slot and PCM Highway Selection MPI Command (40/41h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Ds Do D, Do Command 0 1 0 0 0 0 0 R/AW /O Data TPCM TTS6| TTS5|] TTS4] TTS3] TTS2} TTS1} TTSO Transmit PCM Highway TPCM = 0* Transmit on Highway A (see TAB in Commands 10, 11) TPCM = 1 Transmit on Highway B (see TAB in Commands 10, 11) Transmit Time Slot TTS = 0-127 Time Slot Number (TTSO is LSB, TTS6 is MSB) PCM Highway B is not available on the Am79Q061/062 QSLAC devices. * Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for Channels 1, 2, 3, and 4, respectively. 8, 9. Write/Read Receive Time Slot and PCM Highway Selection MPI Command (42/43h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Ds Do D, Do Command 0 1 0 0 0 0 1 R/AW /O Data RPCM | RTS6|] RTS5| RTS4} RTS3} RTS2} RTS1} RTSO Receive PCM Highway RPCM = 0* Receive on Highway A RPCM = 4 Receive on Highway B Receive Time Slot RTS = 0-127 Time Slot Number (RTSO is LSB, RTS6 is MSB) PCM Highway B is not available on the Am79Q061 and the Am79Q062 QSLAC devices. * Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for Channels 1, 2, 3, and 4, respectively. 46 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA 10, 11. Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge MPI Command (44/45h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Ds Do D, Do Command 0 1 0 0 0 1 0 R/AW /O Data TAB XE RCS2|] RCS1} RCSO|; TCS2) TCS1| TCSO Transmit on A and B TAB = 0* Transmit data on highway selected by TPCM (See Commands 6,7 on page 46). TAB = 1 Transmit data on both highways A and B Transmit Edge XE = 0* Transmit changes on negative edge of PCLK XE = 1 Transmit changes on positive edge of PCLK Receive Clock Slot RCS = 0*-7 Receive Clock Slot number Transmit Clock Slot TCS = 0*-7 Transmit Clock Slot number The XE bit and the clock slots apply to all four channels; however, they cannot be written or read unless at least one channel is selected in the Channel Enable Register. * Power Up and Hardware Reset (RST) Value = 00h. 12, 13. Write/Read Configuration Register MPI Command (46/47h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Ds Do D, Do Command 0 1 0 0 0 1 1 R/W /O Data INTM| CHP} SMODE| CMODE}] CSEL3} CSEL2) CSEL1} CSELO Interrupt Mode INTM =0 INTM = 1* Chopper Clock Control CHP = 0" CHP = 1 PCM Signaling Mode SMODE = 0* SMODE = 1 Clock Source Mode CMODE = 0 CMODE = 1* TTL-compatible output Open drain output Chopper Clock is 256 kHz (2048/8 kHz) Chopper Clock is 292.57 kHz (2048/7 kHz) No signaling on PCM highway Signaling on PCM highway MCLK used as master clock; no E1 multiplexing allowed PCLK used as master clock; E1 multiplexing allowed if enabled in commands 49, 50. The master clock frequency can be selected by CSEL. The master clock frequency selection affects all channels. SLAC Products 47PRELIMINARY Master Clock Frequency CSEL = 0000 CSEL = 0001 CSEL = 0010 CSEL = 0011 CSEL = 01xx CSEL = 10xx CSEL = 11xx CSEL = 1010* 1.536 MHz 1.544 MHz 2.048 MHz Reserved Two times the frequency specified above (2 x 1.536 MHz, 2x 1.544 MHz, or 2 x 2.048 MHz) Four times frequency specified above (4 x 1.536 MHz, 4x 1.544 MHz, or 4 x 2.048 MHz) Reserved 8.192 MHz is the default These commands do not depend on the state of the Channel Enable Register. * Power Up and Hardware Reset (RST) Value = 9Ah. 14, 15. Write/Read Channel Enable and Operating Mode Register MPI Command (4A/4B) R/W = 0: Write R/W = 1: Read D7 De Ds D4 D3 Dp Dy Do Command 0 1 0 0 1 0 1 R/W V/O Data RSVD| RBE | VMODE| LPM] EC4] EC3| EC2] EC RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Robbed-bit Mode RBE = 0* RBE = 1 VOUT Mode VMODE = 0* VMODE = 1 Low Power Mode LPM = 0* LPM = 1 Enable Channel 4 EC4=0 EC4 = 1* Enable Channel 3 EC3 =0 EC3 = 1* Enable Channel 2 EC2 =0 EC2 = 1* Enable Channel 1 EC1 =0 EC1 = 1" Robbed-bit Signaling mode is disabled. Robbed-bit Signaling mode is enabled on PCM receiver if jt-law is selected. VOUT = VREF through a resistor when channel is deactivated VOUT high impedance when channel is deactivated. Low Power mode off Low Power mode on while all channels are inactive Disabled, Channel 4 cannot receive commands Enabled, Channel 4 can receive commands Disabled, Channel 3 cannot receive commands Enabled, Channel 3 can receive commands Disabled, Channel 2 cannot receive commands Enabled, Channel 2 can receive commands Disabled, Channel 1 cannot receive commands Enabled, Channel 1 can receive commands * Power Up and Hardware Reset (RST) Value = OFh. 48 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA 16, 17. Read Real-Time Data Register MPI Command (4D/4Fh) C = 0: Do not clear interrupt C = 1: Clear interrupt This register writes/reads real-time data with or without clearing the interrupt. D, De Ds D4 Ds Do D, Do Command 0 1 0 0 1 1 Cc 1 Output Data CDB4 | CDA4| CDB3|) CDA3) CDB2| CDA2| CDB1} CDA Real Time Data CDA1 Debounced data bit 1 on Channel 1 CDB1 Data bit 2 or multiplexed data bit 1 on Channel 1 CDA2 Debounced data bit 1 on Channel 2 CDB2 Data bit 2 or multiplexed data bit 1 on Channel 2 CDA3 Debounced data bit 1 on Channel 3 CDB3 Data bit 2 or multiplexed data bit 1 on Channel 3 CDA4 Debounced data bit 1 on Channel 4 CDB4 Data bit 2 or multiplexed data bit 1 on Channel 4 This command does not depend on the state of the Channel Enable Register. 18, 19. Write/Read AISN and Analog Gains MPI Command (50/51h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Ds Do D, Do Command 0 1 0 1 0 0 0 R/AW /O Data RSVD AX AR AISN4| AISN3|) AISN2| AISN1| AISNO RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Transmit Analog Gain AX = 0* 0 dB gain AX = 1 6.02 dB gain Receive Analog Loss AR = 0* 0 dB loss AR = 1 6.02 dB loss AISN coefficient AISN = 0*-31 See below (Default value = 0) The Impedance Scaling Network (AISN) gain can be varied from 0.9375 to 0.9375 in multiples of 0.0625. The gain coefficient is decoded using the following equation: Harsn = 0.0625[(16 AISN4 +8 AISN3 +4 AISN2 +2 AISN1 + AISNO) 16] where haisn is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopback mode and a value of AISN = 0000 indicates a gain of 0 (cutoff). * Power Up and Hardware Reset (RST) Value = 00h. SLAC Products 49AMDA PRELIMINARY 20, 21. Write/Read SLIC Input/Output Register MPI Command (52/53h) R/W = 0: Write R/W = 1: Read D, De Ds Dy D3 Do Dy Do Command 0 1 0 1 0 0 1 R/W V/O Data C7 c | CD1IB] C5 C4 c3_ | cb2| cpt Pins CD1, CD2, and C3 through C7 are set to 1 or 0. The data appears latched on the CD1, CD2, and C3 through C5 SLIC I/O pins, provided they were set in the Output mode (see Command 22). The data sent to any of the pins set to the Input mode is latched, but does not appear at the pins. The CD1B bit is only valid if the E1 Multiplex mode is enabled (EE1 = 1). C7 and C6 are outputs only and are not available on all package types. * Power Up and Hardware Reset (RST) Value = 00h 22, 23. Write/Read SLIC Input/Output Direction, Read Status Bits MPI Command (54/55h) D, De Ds D4 D3 Do D, Do Command 0 1 0 1 0 1 0 R/W Input Data RSVD | CSTAT] CFAIL] IOD5| 10D4] 10D3] 1!0D2] 10D1 RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Channel Status (Read status only, write as 0) CSTAT = 0 Channel is inactive (Standby mode). CSTAT = 1 Channel is active. Clock Fail (Read status only, write as 0) CFAIL* = 0 The internal clock is synchronized to frame synch. CFAIL = 1 The internal clock is not synchronized to frame synch. The CFAIL bit is independent of the Channel Enable Register. I/O Direction (Read/Write) IOD5 = 0* C5 is an input lIOD5 = 1 C5 is an output lIOD4 = 0* C4 is an input lIOD4 = 1 C4 is an output IOD3 = 0* C3 is an input lIOD3 = 1 C3 is an output lIOD2 = 0* CD2 is an input lOD2 = 1 CD2 is an output 1IOD1 = 0* CD1 is an input lIOD1 = 1 CD1 is an output Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually. Pins C3-C5 are not available on the Am79Q062 QSLAC device, and C5 is available only on the Am79Q061 QSLAC device. * Power Up and Hardware Reset (RST) Value = 00h 50 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDaA 24, 25. Write/Read Operating Functions MPI Command (60/61h) R/W = 0: Write R/W = 1: Read D, De Ds D4 Ds Do D, Do Command 0 1 1 0 0 0 0 R/AW /O Data C/L A/u EGR EGX EX ER EZ EB Linear Code C/L = 0* Compressed coding C/L=14 Linear coding A-law or p-law A/p = 0* A-law coding A/u = 1 U-law coding GR Filter EGR = 0* Default GR filter enabled EGR = 1 Programmed GR filter enabled GX Filter EGX = 0* Default GX filter enabled EGX = 1 Programmed GxX filter enabled X Filter EX = 0* Default X filter enabled EX = 1 Programmed X filter enabled R Filter ER = 0* Default R filter enabled ER = 1 Programmed R filter enabled Z Filter EZ = 0* Default Z filter enabled EZ = 1 Programmed Z filter enabled B Filter EB = 0* Default B filter enabled EB = 1 Programmed B filter enabled * Power Up and Hardware Reset (RST) Value = 00h. SLAC Products 51AMDA 26, 27. Write/Read Interrupt Mask Register PRELIMINARY MPI Command (6C/6Dh) R/W = 0: Write R/W = 1: Read D, De Ds D4 Ds Do D, Do Command 0 1 1 0 1 1 0 R/W /O Data MCDB4|] MCDA4} MCDB3|] MCDA3|] MCDB2| MCDA2} MCDB1| MCDA1 Mask CD Interrupt MCDxy =0 CDxy bit is NOT MASKED MCDxy = 1* CDxy bit is MASKED X Bit number (A or B) y Channel number (1 through 4) Masked: A change does not cause the Interrupt Pin to go Low. This command does not depend on the state of the Channel Enable Register. * Power Up and Hardware Reset (RST) Value = FFh. 28, 29. Write/Read Operating Conditions MPI Command (70/71h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Ds Do D, Do Command 0 1 1 1 0 0 0 R/W /O Data CTP CRP HPF LRG ATI ILB FDL TON Cutoff Transmit Path CTP =0* Transmit path connected CTP = 1 Transmit path cut off Cutoff Receive Path CRP = 0* Receive path connected CRP = 1 Receive path cutoff (see note) High Pass Filter HPF = 0* Transmit Highpass filter enabled HPF = 14 Transmit Highpass filter disabled Lower Receive Gain LRG = 0* 6 dB loss not inserted LRG = 1 6 dB loss inserted Arm Transmit Interrupt ATI = 0* Transmit Interrupt not Armed ATl = 1 Transmit Interrupt Armed Interface Loopback ILB = 0* TSA loopback disabled ILB = 1 TSA loopback enabled Full Digital Loopback FDL = 0* Full digital loopback disabled FDL = 1 Full digital loopback enabled 52 Am79Q06/061/062/063 Data SheetPRELIMINARY 1 kHz Receive Tone TON = 0* 1 kHz receive tone off TON = 1 1 kHz receive tone on * Power Up and Hardware Reset (RST) Value = 00h. The B Filter is disabled during receive cutoff. 30. Read Revision Code Number (RCN) MPI Command (73h) D, De Ds Dy Ds Do D, Do Command 0 1 1 1 0 0 1 1 V/O Data RCN7 | RCN6 | RCN5|} RCN4]} RCN3 | RCN2 |] RCN1| RCNO This command returns an 8-bit number (RCN) describing the revision number of the QSLAC device. This command does not depend on the state of the Channel Enable Register. 31, 32. Write/Read GX Filter Coefficients MPI Command (80/81h) R/W = 0: Write R/W = 1: Read D; Dg Ds D4 D3 Do D, Do Command 1 0 0 0 0 0 0 R/W /O Data Byte 1 C40 m4o0 C30 m30 /O Data Byte 2 C20 m20 C10 m10 The coefficient for the GX filter is defined as: Hox = 1+(C10 0 2741 + C20 0 27 "11 + C300 2 "(1 + C40 0 2) Power Up and Hardware Reset (RST) Values = A9FO (Hex) (Hex = 1.995 (6 dB)). Note: The default value is contained in a ROM register separate from the programmable coefficient RAM. There is a filter enable bit in Operating Functions Register to switch between the default and programmed values. 33, 34. Write/Read GR Filter Coefficients MPI Command (82/83h) R/W = 0: Write R/W = 1: Read Dz Dg Ds D4 Dg Do D, Do Command: 1 0 0 0 0 0 1 R/W /O Data Byte 1 C40 m4o0 C30 m30 /O Data Byte 2 C20 m20 C10 m10 The coefficient for the GR filter is defined as: Hop = C1002 414020027 "11 + C3002 "(1 + C400 2) Power Up and Hardware Reset (RST) Values = 23A1 (Hex) (Hep = 0.35547 (-8.984 dB)). See note under Commands 31 and 32. SLAC Products 53AMDA PRELIMINARY 35, 36. Write/Read Z Filter Coefficients (FIR and IIR) MPI Command (84/85h) R/W = 0: Write R/W = 1: Read This command writes and reads both the FIR and IIR filter sections simultaneously. Dz Dg Ds D4 Dg Do D, Do Command 1 0 0 0 0 1 0 R/AW /O Data Byte 1 C40 m4o0 C30 m30 /O Data Byte 2 C20 m20 C10 m10 /O Data Byte 3 C41 m41 C31 m31 I/O Data Byte 4 C21 m21 C11 m1 /O Data Byte 5 C42 m42 C32 m32 /O Data Byte 6 C22 m22 C12 mi2 I/O Data Byte 7 C43 m43 C33 m33 /O Data Byte 8 C23 m23 C13 mi13 /O Data Byte 9 C44 m44 C34 m34 /O Data Byte 10 C24 m24 C14 m14 /O Data Byte 11 C45 m45 C35 m35 /O Data Byte 12 C25 m25 C15 m15 /O Data Byte 13 C26 m26 C16 mi6 /O Data Byte 14 C47 m47 C37 m37 /O Data Byte 15 C27 m27 C17 mi7 The Z-transform equation for the Z filter is defined as: -l H,(z) =) tZ, 92 42,07 $2407 47,07 Ft 1-z,e Zz Sample rate = 32 kHz Fori=Oto5and7 =mli m2i m3i z, = Clie2 {1+ C2ie2 [1403182 (14. C4ie2 )]} Ze = C1602 {14+ C2602} Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex) (H,(Z) = 0) See note under Commands 31 and 32. Note: Z, is used for IIR filter scaling only. lis value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first increased by a gain of 1/Z,, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied by Zg to normalize the overall gain. Zs is the actual IIR filter gain value defined by the programmed coefficients, but it also includes the initial 1/Z, gain. The theoretical effective IIR gain, without the Z, gain and normalization, is actually Z5/Zg. 54 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA 37, 38. Write/Read B1 Filter Coefficients MPI Command (86/87h) R/W = 0: Write R/W = 1: Read Dz Dg Ds D4 Dg Do D, Do Command 1 0 0 0 0 1 1 R/AW I/O Input Data Byte 1 C32 m32 C22 m22 I/O Input Data Byte 2 C12 mi2 C33 m33 I/O Input Data Byte 3 C23 m23 C13 m13 I/O Input Data Byte 4 C34 m34 C24 m24 I/O Input Data Byte 5 C14 m14 C35 m35 I/O Input Data Byte 6 C25 m25 C15 m15 I/O Input Data Byte 7 C36 m36 C26 m26 I/O Input Data Byte 8 C16 m16 C37 m37 I/O Input Data Byte 9 C27 m27 C17 m17 I/O Input Data Byte 10 C38 m38 C28 m28 I/O Input Data Byte 11 C18 m18g C39 m39 I/O Input Data Byte 12 C29 m29 C19 m19 I/O Input Data Byte 13 C310 m310 C210 m210 I/O Input Data Byte 14 C110 mi10 RSVD RSVD The Z-transform equation for the B filter is defined as: -10 = Bip Z H,(z) = B ez +...+Byez + 1-B,,ez" Sample rate = 16 kHz The coefficients for the FIR B section and the gain of the IIR B section are defined as: Fori = 2 to 10, mili m2i B, = Clie2 [1+ C2ie2 "(14+ C3ie2)] The feedback coefficient of the IIR B section is defined as: -mlll m211 m311 m411 B,, = Clille2 {1+C2112 [1+C311l2 (1+ C411 2 dt Refer to Commands 43, 44 for programming the B,, coefficient. Power Up and Hardware Reset (RST) Values = 36 AB B8 22 93 AB 2B 6C 46 2C 63 B6 9F 60 (Hex) (Hg(z) = 0.254ez 0,891 z 0.656z 0.090ez > +0.013 ez +0.017z 10 +0.014 07 40.013 e794 2.01602 10.97656z See note under Commands 31 and 32. RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. SLAC Products 55AMDA PRELIMINARY 39, 40. Write/Read X Filter Coefficients MPI Command (88/89h) R/W = 0: Write R/W = 1: Read Dz Dg Ds D4 Dg Do D, Do Command 1 0 0 0 1 0 0 R/AW I/O Input Data Byte 1 C40 m4o0 C30 m30 I/O Input Data Byte 2 C20 m20 C10 m10 I/O Input Data Byte 3 C41 m41 C31 m3 I/O Input Data Byte 4 C21 m21 C11 m1 I/O Input Data Byte 5 C42 m42 C32 m32 I/O Input Data Byte 6 C22 m22 C12 mi2 I/O Input Data Byte 7 C43 m43 C33 m33 I/O Input Data Byte 8 C23 m23 C13 m13 I/O Input Data Byte 9 C44 m44 C34 m34 I/O Input Data Byte 10 C24 m24 C14 mi4 I/O Input Data Byte 11 C45 m45 C35 m35 I/O Input Data Byte 12 C25 m25 C15 m15 The Z-transform equation for the X filter is defined as: u _ -1 2 3 4 5 x(Z) =XgtXZ FXoZ +X3Z +XyZ +X5Z Sample rate = 16 kHz For i = 0 to 5, the coefficients for the X filter are defined as: m3i =mli m2i Xi=Clie2 ~~ {1+C2ie2 "[1+C3ie2 (1+C4ie2 yy Power Up and Hardware Reset (RST) Values = 0111 0190 0190 0190 0190 0190 (Hex) (H,(Z) = 1) See note under Commands 31 and 32. 56 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDaA 41, 42. Write/Read R Filter Coefficients MPI Command (8A/8Bh) R/W = 0: Write R/W = 1: Read Dz Dg Ds D4 Dg Do D, Do Command 1 0 0 0 1 0 1 R/AW I/O Input Data Byte 1 C46 m46 C36 m36 I/O Input Data Byte 2 C26 m26 C16 m16 I/O Input Data Byte 3 C40 m4o0 C30 m30 I/O Input Data Byte 4 C20 m20 C10 m10 I/O Input Data Byte 5 C41 m41 C31 m3 I/O Input Data Byte 6 C21 m21 C11 m1 I/O Input Data Byte 7 C42 m42 C32 m32 I/O Input Data Byte 8 C22 m22 C12 mi2 I/O Input Data Byte 9 C43 m43 C33 m33 I/O Input Data Byte 10 C23 m23 C13 m13 I/O Input Data Byte 11 C44 m44 C34 m34 I/O Input Data Byte 12 C24 m24 C14 mi4 I/O Input Data Byte 13 C45 m45 C35 m35 I/O Input Data Byte 14 C25 m25 C15 m15 HR = Hyp Here The Z-transform equation for the IIR filter is defined as: -1 1-z Hig = 1-(R,ez) Sample rate = 8 kHz The coefficient for the IIR filter is defined as: ml6 m26 m36 m46 Rg = C1602 f14+C26 02 [1+C3602 "(14+ C46 02 dt The Z-transform equation for the FIR filter is defined as: Hyrp(z) = Ro +R\z +Roz +R,z +Ryz-+R,z Sample rate = 16 kHz For i = 0 to 5, the coefficients for the R2 filter are defined as: mli ming 4C3ie yom R, = Clie2 "414+ C2ie2 (1+C4ie2r yy Power Up and Hardware Reset (RST) Values = 2E01 0111 0190 0190 0190 0190 0190 (Hex) (Heir (Z) =1, Re = 0.9902) See note under Commands 31 and 32. SLAC Products 57AMDA PRELIMINARY 43, 44. Write/Read B2 Filter Coefficients (IIR) MPI Command (96/97h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Dy Do D, Do Command 1 0 0 1 0 1 1 RAW /O Data Byte 1 C411 m411 C311 m311 /O Data Byte 2 C211 m211 C111 mit This function is described in Write/Read B?1 Filter Coefficients (FIR) on page 55. Power Up and Hardware Reset (RST) Values = ACO1 (Hex) (By; = 0.97656) See note under Commands 31 and 32. 45, 46. Write/Read Debounce Time Register** MPI Command (C8/C9h) R/W = 0: Write R/W = 1: Read D; De Ds D4 Ds Do D, Do Command 1 1 0 0 1 0 0 R/AW /O Data EE1 E1P | DSH3] DSH2|) DSH1| DSHO) DPCK| ECH Enable E1 EE1 = 0* E1 multiplexing turned off EE1 = 1 E1 multiplexing turned on E1 Polarity E1P = 0* E1 is a high-going pulse E1P=14 E1 is a low-going pulse There is no E1 output unless CMODE = 1. Debounce for Switchhook DSH = 0-15 Debounce period in ms DSH contains the debouncing time (in ms) of the CD1 data (usually switchhook) entering the Real Time Data register described earlier. The input data must remain stable for the debouncing time in order to change the appropriate real time bit. Double PCLK Operation DPCK = 0* Double PCLK operation is off. PCLK and PCM data at same rate. DPCK = 1 Double PCLK enabled. PCLK operates at twice the PCM data rate. Enable Chopper ECH = 0* Chopper output (CHCLK) turned off ECH = 1 Chopper output (CHCLK) turned on * Power Up and Hardware Reset (RST) Value = 20h. This command applies to all channels and does not depend on the state of the Channel Enable Register. 58 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA 47. Read Transmit PCM Data (PCM/MPI Mode Only) MPI Command (CDh) D7 De Ds D4 Dg Do Dy Do Command 1 1 0 0 1 1 0 1 Output Data Byte 1} XDAT7 | XDAT6|} XDAT5|} XDAT4|] XDAT3}] XDAT2|] XDAT1 | XDATO Output Data Byte2] RSVD RSVD RSVD RSVD RSVD RSVD RSVD OLD RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Upper Transmit Data XDAT contains A-law or w-law transmit data in Companded mode. XDAT contains upper data byte in Linear mode with sign in XDAT7. Old Data Flag OLD =0 Transmit data byte contains new data. OLD = 1 Transmit data byte contains old data. This command will return the 2 byte GCI channel ID if GCI mode is selected. 48, 49. Write/Read FIR Z Filter Coefficients (FIR only) MPI Command (98/99h) R/W = 0: Write R/W = 1: Read This command writes and reads only the FIR filter section without affecting the IIR. D; Dg Ds D4 D3 Do D, Do Command 1 0 0 1 1 0 0 R/AW /O Data Byte 1 C40 m4o0 C30 m30 /O Data Byte 2 C20 m20 C10 m10 /O Data Byte 3 C41 m41 C31 m31 I/O Data Byte 4 C21 m21 C11 m1 /O Data Byte 5 C42 m42 C32 m32 /O Data Byte 6 C22 m22 C12 mi2 I/O Data Byte 7 C43 m43 C33 m33 /O Data Byte 8 C23 m23 C13 mi13 /O Data Byte 9 C44 m44 C34 m34 /O Data Byte 10 C24 m24 C14 m14 The Z-transform equation for the Z filter is defined as: -1 -1 2 3 4 Zo%2692,Z H,(Z) =Zy+Z,@Z +2,Z +2,Z +2,Z + 1-z,e z" Sample rate = 32 kHz Fori=Oto5and7 z, = Clie 2 {14C2ie2 [14+ C310 2 (14+ C4ie 2 )]} m16 Ze = C1602 {14+ C2602} Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex) (H,(Z) = 0) SLAC Products 59PRELIMINARY See note under Commands 31 and 32. Note: Z, is used for IIR filter scaling only. lis value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first increased by a gain of 1/Zg, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied by Zg to normalize the overall gain. Zs is the actual IIR filter gain value defined by the programmed coefficients, but it also includes the initial 1/Z, gain. The theoretical effective IIR gain, without the Z, gain and normalization, is actually Z5/Z,. 50, 51. Write/Read IIR Z Filter Coefficients (IIR only) MPI Command (9A/9Bh) R/W = 0: Write R/W = 1: Read This command writes/reads the IIR filter section only, without affecting the FIR. D; De Ds D4 Ds Do D, Do Command 1 0 0 1 1 0 1 R/AW /O Data Byte 11 C45 m45 C35 m35 /O Data Byte 12 C25 m25 C15 m15 /O Data Byte 13 C26 m26 C16 m16 /O Data Byte 14 C47 m47 C37 m37 /O Data Byte 15 C27 m27 C17 m17 The Z-transform equation for the Z filter is defined as: -1 -l 2 3 4 Zo%262,Z H,(Z) =Zy+Z,@Z +2,Z +2,Z +2,2Z + 1-z, ez Sample rate = 32 kHz Fori=Oto5and7 =mli m2i m3i Zz, = Clie2 {14+C2ie2 ~[1+C3ie2 (1+C4ie2y]3 m16 Ze = C1602 {14+ C2602} Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex) (H,(z) = 0) See note under Commands 31 and 32. Note: Z, is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first increased by a gain of 1/Zg, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied by Z, to normalize the overall gain. Z. is the actual IIR filler gain value defined by the programmed coefficients, but it also includes the initial 1/Z, gain. The theoretical effective IIR gain, without the Z, gain and normalization, is actually Z5/Zg. 60 Am79Q06/061/062/063 Data SheetPRELIMINARY 52, 53. Write/Read Ground Key Filter AMDA MPI Command (E8/E9h) R/W = 0: Write R/W = 1: Read D, De Ds D4 Ds Do D, Do Command 1 1 1 0 1 0 0 RAW /O Data RSVD| RSVD| RSVD| RSVD GK3 GK2 GK1 GKO Filter Ground Key GK = 0-15 Filter sampling period in 1 ms GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the Real Time Data register described earlier. A value of 0 disables the Ground Key filter for that particular channel. Power Up and Hardware Reset (RST) Value = 00h. RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. SLAC Products 61AMDA PRELIMINARY GENERAL CIRCUIT INTERFACE (GCI) SPECIFICATIONS GCI General Description When the CS/PG device pin is connected to GND and DCLK/SO is static (not toggling), GCI operation is selected. The QSLAC device conforms to the GCI standard where data for eight GCI channels are combined into one serial bit stream. A GCI channel contains the control and voice data for two analog channels of the QSLAC device. Two GCI channels are required to access all four channels of the QSLAC device. The QSLAC device sends Data Upstream out of the DU pin and receives Downstream Data on the DD pin. Data clock rate and frame synchronization information goes to the QSLAC device on the DCL (Data Clock) and FSC input pins, respectively. Two of eight GCI channels are selected by connecting the SO and S11 channel selection pins on the QSLAC device to GND or VCC as shown in Table 3. Table 3. GCI Channel Assignment Codes In the time slot control block (shown in Figure 14), the Frame Sync (FSC) pulse identifies the beginning of the Transmit and Receive frames and all GCI channels are referenced to it. Voice (B1 and B2), C/I, and mon- itor data are sent to the Upstream Multiplexer where they are combined and serially shifted out of the DU pin during the selected GCI Channels. The Down- stream Demultiplexer uses the same channel control block information to demultiplex the incoming GC| channels into separate voice (B1 and B2), C/I, and monitor data bytes. The QSLAC device supports an eight GC! channel bus (16 analog channels). The external clock applied to the DCL pin is either 2.048 MHz or 4.096 MHz. The QSLAC device determines the incoming clock frequency and adjusts internal timing automatically to accommodate single or double clock rates. $1 So GCI Channels # GND GND 0&1 GND VCC 2&3 VCC GND 4&5 VCC VCC 6&7 Voice data for B1 byte _-> Voice data for B2 byte + Upstream DU C/l Data) ] Multiplexer Monitor Data . a FS Control si Yr y Voice data for B1 byte ___ Voice data for B2 byte ____+ Downstream C/l Data ~ Demultiplexer ++ DD Monitor Data 21108A-028 Figure 14. Time Slot Control and GCI Interface 62 Am79Q06/061/062/063 Data SheetPRELIMINARY GCI Format and Command Structure The GCI interface provides communication of both control and voice data between the GCI highway and subscriber line circuits over a single pair of pins on the QSLAC device. A complete GCI frame is sent upstream on the DU pin and received downstream on the DD pin every 125 us. Each frame consists of eight 4 byte GC! channels (CHNO to 7) that contain voice and control information for eight pairs of channels. A particular channel pair is identified by its position within the frame (see Figure 15). Therefore, a total of 16 voice channels can be uniquely addressed each frame. The overall structure of the GCI frame is shown in Figure 15. AMD The 4 byte GCI channel contains the following: M 2 bytes; B1 and B2 for voice channels 1 and 2. MH One Monitor (M) byte for reading/writing control data/coefficients to the QSLAC for both channels. M One Signaling and Control (SC) byte containing a 6-bit Command/Indicate (C/I) channel for control information and a 2-bit field with Monitor Receive and Monitor Transmit (MR, MX) bits for handshaking functions for both channels. All principal signaling (real-time critical) information is carried on the C/I channel. The QSLAC device utilizes the full C/I channel capacity of the GCI channel. rs || PL 0-3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 DU, DD CHNO CHN1 CHN2 CHN3 CHN4 CHN5 CHN6 CHN7 8 8 8 8 B1 B2 M Sc 0 1 2 3 C/I MR MX Figure 15. Multiplexed GCI Time Slot Structure 21108A-029 SC Channel The upstream and downstream SC channels are continuously carrying I/O information every frame to and from the QSLAC device in the C/I field. This allows the upstream processor to have immediate access to the output (downstream) and input (upstream) data present on the QSLAC devices programmable |/O port. 32-pin packages do not have provisions for pin connections to accommodate all SLIC outputs, which otherwise are available on the higher pin count devices. For the 32-pin and 44-pin package devices, the downstream SC octet is defined as: noon nnn anna Downstream SC Octet ------------------ > The MR and MxX bits are used for handshaking during data exchanges on the monitor channel. MSB LSB 7 6 5 4 3 2 1 0 Downstream C/I Channel | A C5, C4, C3, CD2,| obi, | MR MX The QSLAC device receives the MSBs first. ; | <------------------- C/I Field ------------------- >| The downstream C/I channel SC octet definition depends on the device package type. The 44-pin and SLAC Products 63AMDA PRELIMINARY For the 64-pin packages, this octet is defined as: <on-n nanan Downstream SC Octet ------------------ > MSB LSB 7 6 5 4 3 2 1 0 | A | cz, | ce, | C5, | cD4,} cD3,] MR | Mx | a C/l Field ------------------- >| A: Channel Address Bit 0: Selects CH 1 as the downstream data destination 1: Selects CH 2 as the downstream data destination C5,-CD2,, CD1,: Output bits 5-1 for CHx of the channel selected by A. (32- and 44-pin packages) C7,-C3,: SLIC output bits 7-3 of the channel selected by A. (64-pin packages) x = 1 or 2, the channel selected by A If the QSLAC device's programmable I/O ports, CD1, CD2, and C3 are programmed for Input mode, then data is obtained through the Upstream C/I channel. Figure 16 shows the transmission protocol for the downstream C/I. Whenever the received pattern of C/I bits 6-1 is different from the pattern currently in the C/I input register, the new pattern is loaded into a secondary C/l register and a latch is set. When the next pattern is received (in the following frame) while the latch is set, the following rules apply: 1. Ifthe received pattern corresponds to the pattern in the secondary register, the new pattern is loaded into the C/I register for the addressed channel and the latch is reset. The updated C/I register data appears at the programmable |/O pins of the device one frame (125 is) later if they are programmed as outputs. 2. lf the received pattern is different from the pattern in the secondary register and different from the pattern currently in the C/I register, the newly received pattern is loaded into the secondary C/I register and the latch remains set. The data at the PI/O port remains unchanged. 3. If the received pattern is the same as the pattern currently in the C/I register, the C/I register is unchanged and the latch is reset. v A Receive New C/| Code Store inS I: C/l Register Contents y S: C/l Secondary Register Contents Receive New C/l Code Yes Load C/I Register >| with New Code A Yes 21108A-030 Figure 16. Security Procedure for C/I Downstream Bytes 64 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD Upstream C/I Channel The SC channel, which includes the six C/I channel bits, is transmitted upstream every frame. The bit definitions for the upstream C/I channel are shown below. These bits are transmitted by the QSLAC device (Most significant bit first). GCI Format on on ranean nnn nnn Upstream SC Octet ------------------ > MSB LSB 7 6 5 4 3 2 1 0 | c3, | cDB,| CDA;| C35 | CDBs| CDA,| MR | Mx | | cennneneneeeeeeeeeecenes C/l FIELD ------------- >| Upstream Bit Definitions of the C/I field require the programmable I/O ports to be programmed as inputs. Otherwise, these bits follow the downstream C/I bits for CD1,, CD2,, and C3,. CDA,: Debounced CD1, bit of channel x. CDB,: The filtered CD2, bit of channel x in non-E1 demultiplexed mode or the filtered CD1B, bit in the E1 demultiplexed mode. C3,-C3, of channel x. The logic state of the CDA, CDB, and C3 device pins are read and transmitted in the upstream C/I channel only if they are programmed as an Input. In GCI mode, C4 and C5 are not available as upstream C/I data but can be obtained by reading the SLIC I/O register. Monitor Channel The Monitor Channel (see Figure 17) is used to read and write the QSLAC device's coefficient registers, to read the status of the device and the contents of the internal registers, and to provide supplementary signaling. Information is transferred on the Monitor Channel using the MR and MxX bits of the SC channel, providing a secure method of data exchange between the upstream and downstream devices. The Monitor byte is the third byte in the 4 byte GCI channel and is received every 125 us over the DU or DD pins. A Monitor command consists of one address byte, one or more command bytes, and is followed by additional bytes of input data as required. The command may be followed by the QSLAC device sending data bytes upstream via the DU pin. Monitor Channel Protocol ist Byte <_+-q 2nd Byte _pid 31d Byte MX LY Loy i q Transmitter 4 \ EOM MX \ (4 MR {5 Vv Vv Receiver Y MR ACK ACK ACK 1st Byte 2nd Byte 3rd Byte p} 125 us e Figure 17. Maximum Speed Monitor Handshake Timing 21108A-031 SLAC Products 65AMDA PRELIMIN ARY @ Aninactive (high) MX and MR pair bit for two or more consecutive frames shows an idle state on the monitor channel and the end of message (EOM). @ Figure 17 shows that transmission is initiated by the transition of the transmitter MX bit from the inactive to the active state. The transition coincides with the beginning of the first byte sent on the monitor channel. The receiver acknowledges the first byte by setting MR bit to active and keeping it active for at least one more frame. M@ The same byte is sent continuously in each of the succeeding frames until either a new byte is transmitted, the end of message, or an abort. M@ Any false MX or MR bit received by the receiver or transmitter leads to a request for abort or an abort, respectively. mM Thesame data must be received in two consecutive frames in order to be accepted by the receiver. HM Abus collision resolution mechanism is implemented in the transmitter. Before a device can send a monitor channel message, it must detect the idle condition (MR and MX both high). @ Any abort command leads to a reset of any pending commands in the QSLAC device. The device remains in the previous configuration and is ready to receive a new command. @ For maximum data transfer speed, the transmitter anticipates the falling edge of the receiver's acknowledgment, as shown in Figure 17. Figure 18 and Figure 19 are state diagrams that define the operation of the monitor transmitter and receiver sections in the QSLAC device. nth Byte Initial State + ACK, MX = 1 MR # RQT MR @ RQT Wait for ACK, MX =0 MR: MR bit received MR: MR bit calculated and expected on the DU line MXR: MX - bit sampled on the DU line CLS/ABT t Any State 21108A-032 CLS: Collision within the monitor byte RQT: Request for transmission from internal source ABT: Abort request/indication Figure 18. Monitor Transmitter State Diagram 66 Am79Q06/061/062/063 Data SheetPRELIMINARY Initial State 1st Byte Received MR =0 Wait for LL MR=0 nth Byte Received MR = 1 Wait for LL MR=0 New Byte MR = 1 MX MR: MR bit transmitted on DU line MX: MX bit received on DD line LL: Last look at monitor byte received ABT: Abort indication from internal source Figure 19. Monitor Receiver State Diagram 21108A-033 SLAC Products 67AMDA PRELIMINARY Programming with the Monitor Channel The QSLAC device uses the monitor channel for the transfer of status or mode information to and from higher level processors. The messages transmitted in the monitor channel have different data structures. The first byte of monitor channel data indicates the address of the device either sending or receiving the data. All Monitor channel messages to and from the QSLAC device begin with the following address byte:: Bit 7 6 5 4 3 2 0 1 0 0 A B 0 0 Cc A = 0; Channel 1 is the source (upstream) or destination (downstream) A = 1; Channel 2 is the source (upstream) or destination (downstream) B = 0; Data destination determined by A B = 1; Both channels, 1 and 2, receive the data C = 0; Address for channel identification command C = 1; Address for all other commands The monitor channel address byte is followed by acommand byte. If the command byte specifies a write, then from 1 to 14 additional data bytes may follow (see Table 4). If the control byte specifies a read, additional data bytes may follow. The QSLAC device responds to the read command by sending up to 14 data bytes upstream containing the information requested by the upstream controller. Shown next is the generic byte transmission sequence over the GC! monitor channel. Table 4. Generic Byte Transmission Sequence GCI Monitor Channel Downstream Upstream ADDRESS Control byte, write Data byte 1* e Data byte m* ADDRESS Control byte, read Data byte 1 e Data Byte n m<14 n<14 Note: * May or may not be present 68 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD Channel Identification Command (CIC) When the monitor channel address byte is 80H or 90H, a command of OOH is interpreted by the QSLAC device as a two byte Channel Identification Command (CIC). The format for this command is shown next.: Bit 7 6 5 4 3 2 1 0 Address Byte Command Byte 0 0 0 0 0 0 0 0 B=0 Channel 1 is the destination B=1 Channel 2 is the destination Immediately after the last bit of the CIC command is received, the QSLAC device responds with the 2 byte channel ID code: Bit 7 6 5 4 3 2 1 0 Byte 1 1 0 0 B CONF| CONF| CONF] CONF Byte 2 DT DT 0 0 0 1 1 0 B=0 Channel 1 is the source B=1 Channel 2 is the source CONF Configuration value is always 0000 for the QSLAC device DT Device Type value is always 1,0: Analog Transceiver. Other types are defined as: Bit 7 Bit 6 Description 0 0 U Transceiver 0 1 S Transceiver 1 0 Analog Transceiver 1 1 Future General Structure of Other Commands When the QSLAC device has completed transmission of the channel ID information, it sends an EOM (MX = 1 for two successive frames) on the upstream C/I channel. The QSLAC device also expects an EOM to be received on the downstream C/I channel before any further message sequences are received. When the monitor channel address byte is 81H, 89H, 91H, or 99H, the command byte is interpreted by the QSLAC device as either a Transfer Operation (TOP), Status Operation (SOP), or a Coefficient Operation (COP). Bit 7 6 5 4 3 2 1 0 Address Byte 1 0 0 A B 0 0 A = 0; Channel 1 is the destination A = 1; Channel 2 is the destination B = 0; Data destination determined by A B = 1; Both channels 1 and 2 receive the data Commands are sent to the QSLAC device to: @ Read the status of the system without changing its operation (Transfer Operation (TOP) command) M Write/read the QSLAC operating state (Status Operation (SOP) command) M@ Write/read filter coefficients (Coefficient Operation (COP) command). SLAC Products 69AMDA PRELIMINARY SUMMARY OF MONITOR CHANNEL COMMANDS GCI COMMANDS Commands C# Hex Binary Description Transfer Operation 04 00 00000000 see byte (20m, 80h) (CIC); Requires unique Commands (TOP) 02 73 01110011 Read revision code number 01 00 00000000 Deactivate channel 02 02 00000010 Software Reset 03 04 00000100 Hardware Reset 04 OE 00001110 Activate channel 05 70/71 0111011W/R Write/Read Operating Conditions (Configuration Register 1, CR1) 06 46/47 0100011W/R Write/Read Configuration Register 2, CR2 status Operation 07 60/61 0110011W/R Rogister 3, cn) Functions (Configuration Commands (SOP) i irecti i 03 | sats | orororowr | Coniguration Register, CR4) 09 AN/4B 0100101W/R Write/Read Operating Mode (Configuration Register 5, CR5) 10 53 01010011 Read SLIC I/O Register 11 C8/C9 1100100W/R Write/Read Debounce Time Register 12 E8/E9 1110100W/R Write/Read Ground Key Filter Sampling Interval 13 AD/4F 010011W/R1 Read Real-Time Data Register 14 6C/6D 0110110W/R Write/Read Interrupt Mask Register 01 50/51 0101000W/R Write/Read AISN & Analog gains 02 80/81 1000000W/R Write/Read GX Filter Coefficients 03 82/83 1000001W/R Write/Read GR Filter Coefficients 04 98/99 1001100W/R Write/Read Z Filter Coefficients (FIR) coonnclent de (COP) 05 86/87 | 1000011W/R | Write/Read B1 Filter Coefficients (FIR) 06 88/89 1000000W/R Write/Read X Filter Coefficients 07 8A/8B 1000101W/R Write/Read R Filter Coefficients 08 96/97 1001011W/R | Write/Read B2 Filter Coefficients (IIR) 09 9A/9B 1001101W/R | Write/Read Z Filter (IIR) 70 Am79Q06/061/062/063 Data SheetPRELIMINARY TOP (Transfer Operation) Command The TOP (transfer operation) command is used when no status modification of the QSLAC device is required. The byte transmission sequence for a TOP command is shown in Table 5. AMDA GCI Command Table 5. Byte Transmission Sequence for TOP Command GCI Monitor Channel Downstream Upstream ADDRESS Control byte, TOP read TOP Byte 14 e e TOP Byte n n<14 TOP 2.Read Revision Code Number (RCN) GCI Command (73h) Bit 7 6 5 4 3 2 1 0 Command RCN7} RCN6} RCN5|} RCN4] RCN3| RCN2| RCN1) RCNO SOP (Status Operation) Command GCI Command To modify or evaluate the QSLAC device status, the contents of configuration registers CR1CR5 and the SLIC I/O register can be transferred to and from the QSLAC device. This is done by a SOP (Status Operation) command. The general transmission sequence of the SOP command is shown in Table 5. Table 6. General Transmission Sequence of SOP Command GCI Monitor Channel Downstream Upstream ADDRESS Control byte, SOP write CR1 e e CRm SOP Read CR1 e e CRn ms<7 n<8 SLAC Products 71AMDA PRELIMINARY SOP Control Byte Command Format SOP 1.Deactivate Channel (Standby Mode) GCI Command (00h) Bit In the Deactivated mode: All of the programmed information is retained. The upstream and downstream Monitor and SC channels remain active. The B channel for a deactivated channel is idle, no data is received or transmitted. The analog output (VOUT) is disabled and biased at 2.1 V. The Channel Status (CS) bit in the SLIC I/O and Status Bits register is set to 0. SOP 2.Software Reset GCI Command (02h) Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 1 The action of this command is identical to that of the RST pin except it only operates on the address channel. SOP 3.Hardware Reset GCI Command (04h) Bit 7 6 5 4 3 2 0 0 0 0 0 1 0 0 The Hardware reset command is equivalent to pulling the RST pin on the device low. This command resets all four channels of the device. The action of the Hardware reset function is described in Reset States on page 31. SOP 4.Activate Channel (Operational Mode) GCI Command (OEh) Bit 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 This command places the addressed channel of the device in the Active mode. No valid B- Channel data is transmitted until after the second FSC pulse is received following the execution of the Activate command. SOP 5.Write/Read Operating Conditions GCI Command (70/71h) Operating Conditions (Configuration Register 1, CR1) Bit 7 6 5 4 3 2 1 0 CTP CRP HPF RG ATI ILB FDL TON Configuration register CR1 enables or disables test features and controls feeding states. The reset value of CR1 = 04H Cutoff Transmit Path CTP =0* Transmit path connected CTP = 1 Transmit path disconnected Cutoff Receive Path** CRP = 0* Receive path connected CRP = 1 Receive path cutoff 72 Am79Q06/061/062/063 Data SheetPRELIMINARY High Pass Filter HPF = 0* Transmit Highpass filter enabled HPF = 14 Transmit Highpass filter disabled Lower Receive Gain RG = 0* 6 dB loss not inserted RG = 1 6 cB loss inserted Arm Transmit Interrupt ATI = 0* Transmit interrupt not armed ATl = 1 Transmit interrupt armed Interface Loop Back ILB = 0* Interface (GCI) loopback disabled ILB = 1 Interface (GCI) loopback enabled Full Digital Loopback FDL = 0* Full Digital Loopback disabled FDL = 1 Full Digital Loopback enabled 1 kHz Receive Tone TON = 0* 1 kHz receive tone off TON = 1 1 kHz receive tone on Power Up and Hardware Reset (RST) Value = 00h *B Filter is disabled during receive cutoff. SOP 6.Write/Read Configuration Register 2, CF2 GCI Command (46/47h) Operating Conditions (Configuration Register 2, CR2) Bit 7 6 5 4 3 2 1 0 INTM} CHP |} RSVD} RSVD} RSVD} RSVD} RSVD} RSVD Interrupt Mode INTM = 0 TTL-compatible output INTM = 1 Open drain output Cutoff Transmit Path CHP = 0* Chopper Clock is 256 kHz (2048/8 kHz) CHP = 1 Chopper Clock is 292.57 kHz (2048/7 kHz) RSVD: Reserved for future use. Always write as 0, but 0 is not guaranteed when read. * Power Up and Hardware Reset (RST) Value = 9Ah SOP 7.Write/Read Operating Functions GCI Command (60/61h) Operating Functions (Configuration Register 3, CR3) Bit 7 6 5 4 3 2 1 0 RSVD| A/u EGR EGX EX ER EZ EB RSVD: Reserved for future use. Always write as 0, but 0 is not guaranteed when read. A-law/p-law A/u = 0* A-law coding A/u = U-law coding SLAC Products 73PRELIMINARY GR filter EGR = 0* GR filter default coefficients used: EGR = 1 GR filter programmed coefficients used GX filter EGX = 0* GX filter default coefficients used EGX = 1 GX filter programmed coefficients used X filter EX = 0* X filter default coefficients used EX = 1 X filter programmed coefficients used R filter ER = 0* R filter default coefficients used ER = 1 R filter programmed coefficients used Z filter EZ = 0* Z filter default coefficients used EZ = 1 Z filter programmed coefficients used B filter EB = 0* B filter default coefficients used EB = 1 B filter programmed coefficients used *Power Up and Hardware Reset (RST) Value = 00h SOP 8.Write/Read SLIC I/O Direction and Status Bits GCI Command (54/55h) SLIC I/O Direction and Status Bits (Configuration Register 4, CR4) Bit 7 6 5 4 3 2 1 0 RSVD| CSTAT| CFAIL] IOD5] 10D4] IOD3] IlOD2] IOD1 Pins CD1, CD2 and C3 through C5 are set to Input or Output modes individually. Pin C5 is not available on the Am79Q06 and Pins C3-C5 are not available on the Am79Q062 QSLAC devices. RSVD: Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Channel Status (Read only, write as 0) CSTAT = 0 Channel is inactive (Standby mode) CSTAT = 1 Channel is active Clock Fail (Read only, write as 0) CFAIL = 0 The internal clock is synchronized to frame sync CFAIL = 1 The internal clock is not synchronized to frame sync The CFAIL bit is universal for the QSLAC device and is independent of the channel addressed. lOD1-lOD5 Programmable I/O direction control (CD1, CD2, C3, C4, C5 pins) *O = Pin is set as an input port 1 = Pin is set as an output port *Power Up and Hardware Reset (RST) Value = 00h 74 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA SOP 9.Write/Read Operating Mode GCI Command (4A/4Bh) Operating Mode (Configuration Register 5, CR5) Bit 7 | 6 5 4 3 | 2] 1] ~o RSVD VMODE| LPM RSVD RSVD: Reserved for future use. Always write as 0, but 0 is not guaranteed when read. VOUT Mode VMODE = 0* VOUT = VREF through a resistor when channel is deactivated VMODE = 1 VOUT high impedance when channel is deactivated. Low Power Mode LPM = 0* Low Power mode off LPM = 1 Low Power mode on while all channels are inactive Power Up and Hardware Reset (RST) Value = OFh SOP 10.Read SLIC Input/Output RegisterGCI Command (53h) Bit 7 6 5 4 3 2 1 0 C7 C6 CD1B C5 C4 C3 CcD2 cD1 The logic states present on the CD1, CD2, C3, C4, and C5 pins of the QSLAC device for the addressed channel are read using this command, independent of their programmed direction (see SLIC I/O Direction Register). CD1B is the multiplexed CD1 bit and is valid only if the E1 multiplexing mode is enabled (EE = 1). IfCD1, CD2, C3, C4, and C5 are programmed as inputs, then the logic states reported are determined by the external driving signal. In addition, CDA (the debounced state of CD1) and CDB (the debounced state of CD2, non-E1 multiplexed mode) or CD1B (E1 multiplexed mode), and the logic state present on the C3 pin of the device are sent directly upstream on the C/I bits of the upstream SC channel. If the CD1, CD2, C3, C4, and C5 pins are programmed as outputs then the logic states of these pins are controlled directly by the bits present in the C/I portion of the downstream SC channel and are not sent directly upstream in the SC channel. This command is normally used only to read the bit status via Command 53h. Itis also possible although not recommended, if the CD1, CD2, and C3-C7 pins are programmed as outputs, to write the output state as Command 52h. The register is programmed upon execution of Command 52h but the status is overwritten when the next C/| portion of the downstream SC channel is received. SLAC Products 75AMDA PRELIMINARY SOP 11.Write/Read Debounce Time Register* GCI Command (C8/C9h) Bit 7 6 5 4 3 2 1 0 EE1 E1P | DSH3] DSH2|) DSH1| DSHO|) RSVD| ECH Enable E1 EE1 = 0* E1 Multiplexing is turned off EE1 = 1 E1 Multiplexing is turned on E1 Polarity E1P = 0* E1 is a high-going pulse E1P=14 E1 is a low-going pulse Debounce for Switchhook DSH = 0-15 Debounce period in ms DSH contains the debouncing time in ms of the CD1 data (usually switchhook) entering the CD1B bit of the read SLIC Input/Output register and the CD1B transmitted on the C/| bit of the upstream SC channel. The input data on CD1 must remain stable for the debounce time in order for the state of CD1B to change. RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Enable Chopper ECH = 0* Chopper clock output is turned off. ECH = 1 Chopper clock output is turned on. Power Up and Hardware Reset (RST) Value = 20h Note: * This command applies for all four channels of the device. SOP 12.Write/Read Ground Key Filter Sampling IntervalGCI Command (E8/E9h) R/W = 0: Write R/W = 1: Read Bit 7 6 5 4 3 2 1 0 Command 1 1 1 0 1 0 0 R/AW /O Data RSVD| RSVD| RSVD} RSVD} GK3 GK2 GK1 GKO Filter Ground Key GK = 0-15 Filter sampling period in ms GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the upstream C/I channel described earlier. RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Power Up and Hardware Reset (RST) Value = 00h. 76 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA SOP 13.Read Real-Time Data Register GCI Command (4D/4Fh) C = 0: Do not clear interrupt C = 1: Clear interrupt This register writes/reads real-time data with or without closing the interrupt. Bit D7 Dg Ds D4 Dg Do D, Do Command 0 1 0 0 1 1 Cc 1 /O Data CDB4| CDA4| CDB3|) CDA3|] CDB2| CDA2| CDB1} CDA1 Real Time Data CDA1 Debounced data bit 1 on Channel 1 CDB1 Data bit 2 or multiplexed data bit 1 on Channel 1 CDA2 Debounced data bit 1 on Channel 2 CDB2 Data bit 2 or multiplexed data bit 1 on Channel 2 CDB3 Debounced data bit 1 on Channel 3 CDA3 Data bit 1 on Channel 3 CDB4 Debounced data bit 1 on Channel 4 CDA4 Data bit 2 or multiplexed data bit 1 on Channel 4 This data is also available in the C/I field of the upstream SC channel. SOP 14.Write/Read Interrupt Mask Register GCI Command (6C/6Dh) R/W = 0: Write R/W = 1: Read Bit D; De Ds D4 Ds Do D, Do Command 0 1 1 0 1 1 0 R/AW /O Data MCDB4| MCDA4|] MCDB3} MCDA3| MCDB2| MCDA2|} MCDB1] MCDAt1 Mask CD Interrupt MCDxy = 0 CDxy bit is NOT MASKED MCDxy = 1* CDxy bit is MASKED X Bit number (A or B) y Channel number (1 through 4) Masked A change does not cause the Interrupt Pin to go Low. *Power Up and Hardware Reset (RST) Value = FFh SLAC Products 77AMDA PRELIMINARY COP (Coefficient Operation) Command GCI Command The COP command writes or reads data related to filter coefficients. Filter coefficient data is used by the voice processors within the QSLAC device to configure the various filters in the voice channel. In this case, 1 to 14 coefficient bytes follow the command byte. The QSLAC device interprets the bytes as canonic signed digital (CSD) data and sets the coefficients accordingly. The QSLAC device responds to the read coefficient command by sending up to 14 CSD bytes upstream. These bytes contain the coefficients requested by the upstream controller. For diagnostic purposes, various RAM locations containing data to which the QSLAC device has access can also be read back by this command. The generic transmission sequence for the COP command is shown in Table 7. Table 7. Generic Transmission Sequence for COP Command Downstream Upstream ADDRESS Command byte, COP write Data e e Data, Control byte, COP read Data, e e Data, n<14 m<14 The following tables show the format of the COP bytes that follow a downstream address byte. Bit D7 D6 D5 D4 D3 D2 D1 DO COMMAND CMD |} CMD} CMD} CMD] CMD| CMD | CMD | CMD DATA DATA| DATA| DATA| DATA} DATA| DATA] DATA| DATA e DATA | DATA| DATA| DATA| DATA] DATA| DATA] DATA| DATA The format in the upstream direction is the same except that the command byte is omitted. 78 Am79Q06/061/062/063 Data SheetPRELIMINARY AMD Details of COP, CSD Data Commands This section describes in detail each of the monitor channel COP commands. Each of the commands is shown along with the format of any additional data bytes that follow. For details of the filter coefficients of the form C,ym,y, please refer to the Description of Coefficients section. COP 1.Write/Read AISN Coefficients and Analog Gains GCI Command (50/51h) R/W = 0: Write R/W = 1: Read Bit D7 D6 D5 D4 D3 D2 D1 DO Command 0 1 0 1 0 0 0 W/R Data RSVD AX AR AISN4| ASIN3|] AISN2| AISN1| AISNO RSVD: Reserved for future use. Reset to 0. Always write as 0, but 0 is not guaranteed when read. Transmit analog gain AX = 0*: 0 dB gain AX = 1: 6.02 dB gain Receive Analog Loss AR = 0*: 0 dB loss AR =1: 6.02 dB loss AISN coefficient AISN = 0*-31 See below (Default value = 0) The Analog Impedance Scaling Network (AISN) gain can be varied from 0.9375 to 0.9375 in multiples of 0.0625. The gain coefficient is decoded using the following equation: haisn = 0.0625 ((AISN4 24 + AISNS 23 + AISN2 2 + AISN1 2! + AISNO 2) 16) where Najsn is the gain of the AISN. A value of AISN = '10000' turns on the Full Digital Loopback mode. * Power Up and Hardware Reset (RST) Value = 00h COP 2.Write/Read GX Filter Coefficients GCI Command (80/81h) R/W = 0: Write R/W = 1: Read Bit D7 D6 D5 D4 D3 D2 D1 DO Command 1 0 0 0 0 0 0 W/R Coefficient Byte 1 C40 m4o0 C30 m30 Coefficient Byte 2 C20 m20 C10 m10 The coefficient for the GX filter is defined as: m20 m30 m40 mmo (1+ C30027(14+.C40 02 Hex = (1+ (C102 "(1+ C202 ))))) Power Up and Hardware Reset (RST) Value = A9FOh, (Hex = 1.995, or +6 dB) SLAC Products 79AMDA PRELIMINARY COP 3.Write/Read GR Filter Coefficients GCI Command (82/83h) R/W = 0: Write R/W = 1: Read Bit D7 D6 D5 D4 D3 D2 D1 DO Command 1 0 0 0 0 0 1 W/R Coefficient Byte 1 C40 m4o0 C30 m30 Coefficient Byte 2 C20 m20 C10 m10 The coefficient for the GR filter is defined as: m1l0 m20 m30 m40 Hg = (C102 (1 +2002 "(1+ C3002 (1 + C40 0 2 ))) Power Up and Hardware Reset (RST) Value = 23A1h, (Hep = 0.35547, or -8.984 dB) COP 4.Write/Read Z Filter FIR Coefficients GCI Command (98/99h) R/W = 1: Read R/W = 0: Write This command writes and reads only the FIR portion of the Z filter without affecting the IIR. Bit D7 D6 D5 D4 D3 D2 D1 DO Command 1 0 0 1 1 0 0 RAW /O Data Byte 1 C40 m4o0 C30 m30 /O Data Byte 2 C20 m20 C10 m10 /O Data Byte 3 C41 m41 C31 m3 I/O Data Byte 4 C21 m2 C11 m1 /O Data Byte 5 C42 m42 C32 m32 /O Data Byte 6 C22 m22 C12 mi2 I/O Data Byte 7 C43 m43 C33 m33 /O Data Byte 8 C23 m23 C13 m13 /O Data Byte 9 C44 m44 C34 m34 /O Data Byte 10 C24 m24 c14 mi4 The Z-transform equation for the Z filter is defined as: -l H,(Z) = Zp tZ, OZ FZ OZ +2502 +2,07 $ oe 1-z,e z" Sample rate = 32 kHz For i = 0-5 and 7 mli m2i m3i Zz, = Clie2 {14+ C2ie2 [14 C3ie 2 (14 Chie 2) Ze = C1602 514+ C2602} Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex) (H(z) = 0) Note: Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first increased by a gain of 1/26, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied by Z6 to normalize the overall gain. 25 is the actual IIR filter gain value defined by the programmed coefficients, but it also includes the initial 1/26 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually 25/Z6. 80 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDA COP 5.Write/Read B1 Filter Coefficients 1-14 GCI Command (86/87h) R/W = 1: Read R/W = 0: Write Bit D7 D6 D5 D4 D3 D2 D1 DO Command 1 0 0 1 1 0 0 R/W /O Data Byte 1 C32 m32 C22 m22 /O Data Byte 2 C12 mi2 C33 m33 /O Data Byte 3 C23 m23 C13 mi3 /O Data Byte 4 C34 m34 C24 m24 /O Data Byte 5 C14 m14 C35 m35 /O Data Byte 6 C25 m25 C15 m15 /O Data Byte 7 C36 m36 C26 m26 /O Data Byte 8 C16 mi6 C37 m37 /O Data Byte 9 C27 m27 C17 mi7 /O Data Byte 10 C38 m38s C28 m28 /O Data Byte 11 C18 mig C39 m39 /O Data Byte 12 C29 m29 C19 mig /O Data Byte 13 C310 m310 C210 m210 /O Data Byte 14 C110 mi110 RSVD * ignored The Z-transform equation for the B filter is defined as: -10 - - Big &Z H,(z) =B,ez +...+B ez + 1-B,,ez" Sample rate = 16 kHz The coefficients for the FIR B section and the gain of the IIR B section are defined as: m2i [1+C2ie2- mi Fori=2to 10, B; = Clie2 (1+C3ie2*)] The feedback coefficient of the IIR B section is defined as: -mlll m211 m311 m411 B,, = Clile2 {1+C2112 [1+C3112 (1+ C411 2 dt Refer to Command COP8 for programming the By, coefficients. Power Up and Hardware Reset (RST) Values = 36 AB B8 22 93 AB 2B 6C 46 2C 63 B6 9F 60 (Hex) (Hg(z) =0.254 ez 0.891 z 0.656 ez 0,090 ez > +0.013 ez +0.017 ez 0.016ez + 0.01407 +0.013 ez + ) 1-0.97656z" RSVD: Reserved for future use. Reset to 0. Always write as 0, but 0 is not guaranteed when read. SLAC Products 81AMDA PRELIMINARY COP 6.Write/Read X Filter Coefficients GCI Command (88/89h) R/W = 1: Read R/W = 0: Write Bit D7 D6 D5 D4 D3 D2 D1 DO Command 1 0 0 0 1 0 0 W/R Coefficient Byte 1 C40 m4o0 C30 m30 Coefficient Byte 2 C20 m20 C10 m10 Coefficient Byte 3 C41 m41 C31 m3 Coefficient Byte 4 C21 m21 C11 m1 Coefficient Byte 5 C42 m42 C32 m32 Coefficient Byte 6 C22 m22 C12 mi2 Coefficient Byte 7 C43 m43 C33 m33 Coefficient Byte 8 C23 m23 C13 m13 Coefficient Byte 9 C44 m44 C34 m34 Coefficient Byte 10 C24 m24 C14 mi4 Coefficient Byte 11 C45 m45 C35 m35 Coefficient Byte 12 C25 m25 C15 m15 The Z-transform equation for the X filter is defined as: H,(z) =X +X Zz +X5z +X,z+Xyz+Xsz Sample rate = 16 kHz For i = 0 to 5, the coefficients for the X filter are defined as: mli m2i m3i Xi=Clie2 ~(14+C2ie2 ~(1+C3ie2 (1+ C4ie 2))) Power Up and Hardware Reset (RST) Values = 0111 0190 0190 0190 0190 0190h H(z) = 1 82 Am79Q06/061/062/063 Data SheetPRELIMINARY AMDaA COP 7.Write/Read R Filter Coefficients GCI Command (8A/8Bh) R/W = 1: Read R/W = 0: Write Bit D7 D6 D5 D4 D3 D2 D1 DO Command 1 0 0 0 1 0 1 W/R Coefficient Byte 1 C46 m46 C36 m36 Coefficient Byte 2 C26 m26 C16 m16 Coefficient Byte 3 C40 m4o0 C30 m30 Coefficient Byte 4 C20 m20 C10 m10 Coefficient Byte 5 C41 m41 C31 m3 Coefficient Byte 6 C21 m21 C11 m1 Coefficient Byte 7 C42 m42 C32 m32 Coefficient Byte 8 C22 m22 C12 mi2 Coefficient Byte 9 C43 m43 C33 m33 Coefficient Byte 10 C23 C23 C13 m13 Coefficient Byte 11 C44 m44 C34 m34 Coefficient Byte 12 C24 m24 C14 mi4 Coefficient Byte 13 C45 m45 C35 m35 Coefficient Byte 14 C25 m25 C15 m15 HR = Hye * Here The Z-transform equation for the IIR filter is defined as: -1 1-z AiR = 1-(Rgez) Sample rate = 8 kHz The coefficient for the IIR filter is defined as: Rg = C160 2751 4+ C26 0 21 + C36 0 2 (1 + C46 0 2} The Z-transform equation for the FIR filter is defined as: Hyrp(z) =Ry +R z +R.z +R,z +Ryz +Roz Sample rate = 16 kHz For i = 0 to 5, the coefficients for the R2 filter are defined as: mli ming 4C3ie yom R, = Clie2 "414+ C2ie2 (1+C4ie2r yy Power Up and Hardware Reset (RST) Values = 2E01 0111 0190 0190 0190 0190 0190 (Hex) (Heir (Z) = 1, Re = 0.9902) SLAC Products 83AMDA PRELIMINARY COP 8.Write/Read B2 Filter Coefficients 1516 GCI Command (96/97h) R/W = 1: Read R/W = 0: Write Bit D7 D6 D5 D4 D3 D2 D1 DO Command 1 0 0 1 0 1 1 W/R Coefficient Byte 15 C411 m411 C311 m311 Coefficient Byte 16 C211 m211 C111 mi11 This function is described in Write B1 Filter Coefficients on page 81. Power Up and Hardware Reset (RST) Value = ACO1h (By4 = 0.97656) COP 9.Write/Read IIR Z Filter Coefficients GCI Command (9A/9B) R/W = 0: Write R/W = 1: Read This command writes and reads only the IIR portion of the Z filter without affecting the FIR. Dz Dg Ds D4 Dg Do D, Do Command 1 0 0 1 1 0 1 R/AW /O Data Byte 1 C45 m45 C35 m35 /O Data Byte 2 C25 m25 C15 m15 /O Data Byte 3 C26 m26 C16 mi6 I/O Data Byte 4 C47 m47 C37 m37 /O Data Byte 5 C27 m27 C17 m17 The Z-transform equation for the Z filter is defined as: ZoZ,2Z,0Z -l 2 3 4 H,(z) =Z+Z,Z +2,Z +2,Z +2z,zZ +2 7 -l 1l-z, *z Sample rate = 32 kHz Fori = 0-5 and 7 mli m2i m3i Zz, = Clie2 {14+ C2ie2 [14 C3ie 2 (14 Chie 2) Ze = C1602 f1 4026023 Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex) (H(Z) = 0) Note: Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first increased by a gain of 1/26, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied by Z6 to normalize the overall gain. 25 is the actual IIR filter gain value defined by the programmed coefficients, but it also includes the initial 1/26 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually 25/Z6. 84 Am79Q06/061/062/063 Data SheetPRELIMINARY PROGRAMMABLE FILTERS General Description of CSD Coefficients The filter functions are performed by a series of multiplications and accumulations. A multiplication is accomplished by repeatedly shifting the multiplicand and summing the result with the previous value at that summation node. The method used in the QSLAC device is known as Canonic Signed Digit (CSD) multiplication and splits each coefficient into a series of CSD coefficients. Each programmable FIR filter section has the following general transfer function: HF(z) =hy+h,z +h,z +...+h,z Equation 1 where the number of taps in the filter = n+ 1. The transfer function for the IIR part of Z and B filters is: 1 HI(z) = Equation 2 -1 1 Bay 2 The transfer function of the IIR part of the R filter is: -l HI(z) = |-z Equation 3 -l 1hen 4 12 The values of the user-defined coefficients (hj) are assigned via the MPI. Each of the coefficients (h;) is defined in the following general equation: -M, M, My . h, = B,2 +B,2 +...+By2 Equation 4 where: M; = the number of shifts = Mj < Mj+ 1 Bj = sign = +1 N = number of CSD coefficients The value of h, in Equation 4 represents a decimal number that is broken down into a sum of successive values of: +1.0 multiplied by 20 or a1 or2? 27 or +1.0 multiplied by 1, or 1/2, of 1/4... 1128... The limit on the negative powers of two is determined by the length of the registers in the ALU. The coefficient h; in Equation 4 can be considered to be a value made up of N binary 1s in a binary register where the left part represents whole numbers, the right part represents decimal fractions, and a decimal point separates them. The first binary 1 is shifted M, bits to the right of the decimal point; the second binary 1 is shifted Mp bits to the right of the decimal point; the third binary 1 is shifted Mz bits to the right of the decimal point, and so on. When M, is 0, the resulting value is a binary 1 in front of the decimal point, that is, no shift. If Mz is also 0, the result is another binary 1 in front of the decimal point, giving a total value of binary 10 in front of the decimal point (that is, a decimal value of 2.0). The value of N, therefore, determines the range of values the coefficient h, can take (for example, if N = 3 the maximum and minimum values are +3, and if N = 4 the values are between +4). Detailed Description of QSLAC Device Coefficients The CSD coding scheme in the QSLAC device uses a value called mi, where m1 represents the distance shifted right of the decimal point for the first binary 1. m2 represents the distance shifted to the right of the previous binary 1, and m3 represents the number of shifts to the right of the second binary 1. Note that the range of values determined by N is unchanged. Equation 4 is now modified (in the case of N = 4) to: M, M, M, M, h, = B,2 '+B,2 +B,2 +B,2 1 h, = h, = Cle2 4140202 [14+03 02 (14+ C402 )]} where: My,=m1 By=C1 Ms =m1+m2 Bo =C1C2 Mz=m1+m2+m3 Bg =C1C2eC3 Ma=m1+m2+m3+m4 By=C1C2eC3C4 Equation 5 Cl e gm + Cl eC2e atm +m2) + Cl eC2eC3e 3 -(ml + m2 + m3) + Cl 0C2eC3eC4e 3 -Oml + m2 + m3 +m4) Equation 6 Equation 7 SLAC Products 85AMDA PRELIMINARY In the QSLAC device, a coefficient, h;, consists of NCSD coefficients, each being made up of 4 bits and formatted as Cxy mxy, where Cxy is 1 bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows: Cxy is the sign bit (0 = positive, 1 = negative). mxy is the 3-bit shift code. It is encoded as a binary number as follows: 000: O shifts 001: 1 shifts 010: 2 shifts 011: 3 shifts 100: 4 shifts 101: 5shifts 110: 6 shifts 111: 7 shifts y is the coefficient number (the i in hj). X is the position of this CSD coefficient within the h; coefficient. The most significant binary 1 is represented by x = 1. The next most significant binary 1 is represented by x = 2, and so on. Thus, C13 m13 represents the sign and the relative shift position for the first (most significant) binary 1 in the fourth (hg) coefficient. The number of CSD coefficients, N, is limited to four in the GR, GX, R, X, and Z filters; four in the IIR part of the B filter; three in the FIR part of the B filter; and two in the post-gain factor of the Z-IIR filter. Note also that the GX filter coefficient equation is slightly different from the other filters. higx = 1+h; Equation 8 Please refer to the Summary of MPI Commands section for complete details on programming the coefficients. User Test Modes and Operating Conditions The QSLAC device supports testing by providing test modes and special operating conditions as shown in Figure 12 (see Operating Conditions Register). Cutoff Transmit Path (CTP): When CTP = 1, DX and TSC are High impedance and the transmit time slot does not exist. This mode takes precedence over the TSA Loopback (TLB) and Full Digital Loopback (FDL) modes. Cutoff Receive Path (CRP): When CRP = 1, the receive signal is forced to 0 just ahead of the low pass filter (LPF) block. This mode also blocks Full Digital Loopback (FDL), the 1 KHz receive tone, and the B-filter path. High Pass Filter Disable (HPF): When HPF = 1, all of the High pass and notch filters in the transmit path are disabled. Lower Receive Gain (LRG): When LRG = 1, an extra 6.02 dB of loss is inserted into the receive path. Arm Transmit Interrupt (ATI) and Read Transmit PCM Data (PCM/MPI mode only): The read transmit PCM data command, Command 47, can be used to read transmit PCM data through the microprocessor interface. If the ATI bit is set, an interrupt is generated whenever new transmit data appears in the channel and is cleared when the data is read. When combined with Tone Generation and Loopback modes, this allows the microprocessor to test channel integrity. Interface Loopback (ILB): When ILB = 1, data from the receive/downstream path is looped back to the transmit/ Upstream path. Any other data in the transmit path is overwritten. Full Digital Loopback (FDL): When FDL = 1, the VOUT output is turned off and the analog output voltage is routed to the input of the receive path, replacing the voltage from VIN. The AISN path is temporarily turned off. This test mode can also be entered by writing the code 10000 into the AISN register. 1 kHz Receive Tone (TON): When TON = 1, a 1 kHz digital mW is injected into the receive path, replacing any receive or downstream signal. 86 Am79Q06/061/062/063 Data SheetPRELIMINARY A-Law and u-Law Companding Table 8 and Table 9 show the companding definitions used for A-law and -law PCM encoding. Table 8. A-Law: Positive Input Values 1 2 3 4 5 6 7 8 Character Signal pre ; #\Intervals | Value at | Decision | Decision |!nversion of uanuized Decoder Segment | , interval Segment Value Value x,, Even Bits falue (at Output Number | Size | End Points | Number n | (See Note 1) Decoder | Value No. Bit No. | Output) y, 12345678 4096 (128) (4096) frtt tty 44444444 127 3068 4082 128 7 16x 128 ; cooNoie? : 113 2176 ' ' 2048 112 2048 11110000l- 2112 113 : : See Note 2 : : 6 16x64 : : : : 97 1088 11100000L 1056 97 1024 96 1024 See Note 2 ; 5 16x32 ' ' : : 81 544 512 20 sj2 [t1010000;- 528 81 See Note 2 ; 4 16x16 ' : : 65 272 256 6A 256 11000000} 264 65 ' : See Note 2 : : 16x8 ' : ' $ x 49 136 108 48 jog 10110000; 132 49 : See Note 2 : : 16x4 ' : 2 33 68 6A 30 eA 10100000 6& 33 See Note 2 ; ; 1 22x2 1 10000000 = 1 | 0 0 Notes: 1. 4096 normalized value units correspond to TMAX = 3.14 dBmo. 2. The character signals are obtained by inverting the even bits of the signals of column 6. Before this inversion, the character signal corresponding to positive input values between two successive decision values numbered n and n+1 (see column 4) is 128+n, expressed as a binary number. . Xn_1 +n 3. The value at the decoder output is y, = forn = 1,...127, 128. 4. X40g |S a virtual decision value. 5. Bit 1 is a O for negative input values. SLAC Products 87PRELIMINARY Table 9. u-Law: Positive Input Values 1 2 3 4 5 6 7 8 Character Signal pre ; # Intervals | Value at Decision | Decision |!nversion of Quantized | Decoder Segment | x interval | Segment | Value Value x, | Even Bits | Value(at |) Output Number Size _| End Points | Number n | (See Abie 1) Decoder | Value No. Bit No, | Output) y, 12345678 8159 (128) (8159) fort 4 127 sog3 10000000} Boat 127 8 TEX 256 See Note 2 113 4319 , ' A063 112 10001111+- 2112 112 : i See Note 2 : . 7 16x 128 : : : : 97 2143 10011111 1056 96 2015 96 2015 See Note 2 6 16x&4 " ' " : 81 1055 101011141b 901 80 991 $28 80 : See Note 2 : : 5 16x32 " ' ' 65 511 10111114 479 64 479 264 64 : : See Note 2 : : 16x16 : : 4 * 49 239 3 48 23 11001111- 122 48 16x8 ' . : s 33 108 11011111F 99 32 95 22 95 See Note 2 2 16x4 17 35 : 31 16 31 11101111+ 33 16 See Note 2 ; ; 1 15x2 : : ; 2 3 141111110 2 1 { 1x1 1 1 * 11111111F O 0 0 0 Notes: 1. 8159 normalized value units correspond to TMAX = 3.17 dBmo. 2. The character signal corresponding to positive input values between two successive decision values numbered n and n+1 (see column 4) is 255-n, expressed as a binary number. i Xn +1 + Xn 3. The value at the decoder is yp = Xp = O forn=0, andy, = a forn = 1, 2,...127. 4. X40g |S a virtual decision value. 5. Bit 1 is a O for negative input values. 88 Am79Q06/061/062/063 Data SheetPRELIMINARY APPLICATIONS The QSLAC device performs a programmable codec/ filter function for four telephone lines. It interfaces to the telephone lines through an AMD SLIC device or a transformer with external buffering. The QSLAC device provides latched digital I/O to control and monitor four SLICs and provides access to time-critical information, such as off/on-hook and ring trip, for all four channels via a single read operation or via the upstream C/I bits in the GCI SC channel. When various country or transmission requirements must be met, the QSLAC device enables a single SLIC design for multiple applications. The line characteristics (such as apparent impedance, attenuation, and hybrid balance) can be modified by programming each QSLAC device channels coefficients to meet desired performance. The QSLAC device may require an external buffer to drive transformer SLICs. In PCM/MPI mode, connection to a PCM back plane is implemented by means of a simple buffer chip. Several QSLAC devices can be tied together in one bus interfacing the back plane through a single buffer. An intelligent bus interface chip is not required because each QSLAC device provides its own buffer control (TSXA/B). The QSLAC device is controlled through the microprocessor interface, either by a microprocessor on the linecard or by a central processor. In GCI mode, the QSLAC device decodes the SO and S1 inputs and determines the DCL frequency, 2.048 MHz or 4.096 MHz automatically. The QSLAC device transmits and receives the GCI channel information in accordance with SO, S1 and DCL, synchronized by Frame Sync. (FSC). Up to four QSLAC devices can be bussed together forming one bidirectional 16 channel GCI bus. A simple inexpensive buffer should be used between the GCI bus and the backplane of the system. Controlling the SLIC The Am79Q061 QSLAC device has five TTL-compatible I/O pins (CD1, CD2, C3, C4 and C5) for each channel. The Am79Q031 QSLAC device has only CD1 and CD2 available. The outputs are programmed using MPI Command 19 or the downstream C/I bits in the GCI SC channel. The logic states are read back using MPI Command 21 or GCI Command SOP 10. In GC! mode CD1 (debounced), CD2, and C3 are also present on the upstream C/I bits in the GCI SC channel. In PCM/MPI mode, CD1 and CD2 for all four channels can be read back using MPI Command 16. The direction of the I/O pins (input or output) is specified by programming the SLIC I/O direction register (MPI Commands 22, GC! Command SOP 9). Default Filter Coefficients The default filter coefficients were calculated assuming an Am7920 SLIC with 50 protection resistors, a 178 kQ transversal impedance (Z7), and a 90.5 kQ receive impedance (Zpx). This SLIC has a transmit gain of 0.5 (Gtx) and a current gain of 500 (K1). The transmit relative level was set to +0.28 dBr, and the receive relative level was set to 4.39 dBr. The equalization filters (X and R) were not optimized. The balance filter was designed to give acceptable balance into a variety of impedances. The nominal input impedance was set to 815 Q. If the SLIC circuit differs significantly from this design, the default filters cannot be used and must be replaced by programmed coefficients. Calculating Coefficients with WinSLAC Software WinSLAC software is a program that models the QSLAC device, the line conditions, the SLIC, and the linecard components to obtain the coefficients of the programmable filters of the QSLAC device and some of the transmission performance plots. The following parameters relating to the desired line conditions and the components/circuits used in the linecard are to be provided as input to the program: Line impedance or the balance impedance of the line is specified by the local PTT. 2. Desired two-wire impedance that is to appear at the linecard terminals of the exchange. 3. Tabular data for templates describing the frequency response and attenuation distortion of the design. 4. Relative analog signal levels for both the transmit and receive two-wire signals. 5. Component values and SLIC device selection for the analog portion of the line circuits. 6. Two-wire return loss template is usually specified by the local PTT. 7. Four-wire return loss template is usually specified by the local PTT. The output from the WinSLAC software includes the coefficients of the GR, GX, Z, R, X, and B filters as well as transmission performance plots of two-wire return loss, receive and transmit path frequency responses, and four-wire return loss. The software supports the use of the AMD SLICs or allows entry of a SPICE netlist describing the behavior of any type of SLIC circuit. SLAC Products 89AMDZ Am7920 SLIC/QSLAC APPLICATION CIRCUIT Shared Ring Threshold PRELIMINARY RING RATHI Vee +5V Vee u2 BUS VVWV DA ul RD ee Am7920 q CBP1 Am79Q061 RAI S RDS +=cp = > ~ RSsRI SLIC < T T QSLAC PCM/MPI WV DB Agnd -$- Agnd1 Fe ara CAD Vix i+ == Vint MODE RTS cx TIP WA +4 AX s [ Iref Mok/E1 MCLK/E1 oc] SN } wv Vout Pdk/DCL L__ pcLk Ll aper & ARE CRO S| Dgnd FS/FSC FS RING KAR ares HPB RDC _ DXA/DU [___ DxA ee + WV BX ote > DRADD |___ DRA Rr KX 3 a : 7 cp21, C31 DiIo/s1 [____ blo Test RDO, RYO1,2 DO C44 Dek/SO |___ DCLK BGND D1 C51 Capa |__ CS0 (Normally High) ne von OEE con st [Ast TMG VNEG Los C ett +5V itn Lt CFIL Tt wi - = GCI MODE Mclk/E1 E1 TP Pdk/DCL L____ pc / FS/FSC L___ Fsc SLIC1 a DXA/DU J DU RING DRAYDD L___ DD Dios1 L__ s1 Dek/So L___ so TIP TSPG / rt SLIC2 / AST P RST RING 7 ZL TIP f, SLIC3 RING 21108A-034 Revision B to C * Frame sync information was added to the first paragraph on page 36. 90 Am79Q06/061/062/063 Data Sheet