1
DATASHEET
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC. 2011, 2015. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
Dual, 256-Tap, Low Voltage Digitally Controlled
Potentiometer (XDCP™)
ISL23325
The ISL23325 is a volatile, low voltage, low noise, low power,
256-Tap, dual digitally controlled potentiometer (DCP) with an
I2C Bus™ interface. It integrates two DCP cores, wiper switches
and control logic on a monolithic CMOS integrated circuit.
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the I2C
bus interface. Each potentiometer has an associated volatile
Wiper Register (WRi, i = 0, 1) that can be directly written to and
read by the user. The contents of the WRi controls the position
of the wiper. When powered on, the wiper of each DCP will
always commence at mid-scale (128 tap position).
The low voltage, low power consumption, and small package
of the ISL23325 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23325 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23325 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
Applications
• Power supply margining
• Trimming sensor circuits
• Gain adjustment in battery powered instruments
• RF power amplifier bias compensation
Features
• Two potentiometers per package
• 256 resistor taps
•10kΩ 50kΩ or 100kΩ total resistance
•I
2C serial interface
- No additional level translator for low bus supply
- Three address pins allow up to eight devices per bus
• Maximum supply current without serial bus activity
(standby)
- 3µA @ VCC and VLOGIC = 5V
- 1.7µA @ VCCand VLOGIC = 1.7V
•Shutdown Mode
- Forces the DCP into an end-to-end open circuit and RWi is
connected to RLi internally
- Reduces power consumption by disconnecting the DCP
resistor from the circuit
•Power supply
-V
CC = 1.7V to 5.5V analog power supply
-V
LOGIC = 1.2V to 5.5V I2C bus/logic power supply
• Wiper resistance: 70Ω typical @ VCC = 3.3V
• Power-on preset to mid-scale (128 tap position)
• Extended industrial temperature range: -40°C to +125°C
• 14 Ld TSSOP or 16 Ld µTQFN packages
• Pb-free (RoHS Compliant)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10kΩ DCP
FIGURE 2. VREF ADJUSTMENT
0
2000
4000
6000
8000
10000
TAP POSITION (DECIMAL)
RESISTANCE (Ω)
0 64 128 192 256
VREF_M
ISL28114
1 DCP
OF
ISL23325
+
-
VREF
RL1
RW1
RH1
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Block Diagram
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
I/O
BLOCK
VCC
GND
SCL
SDA
A0
A1
RH0
RL0RW0
RH1
RL1RW1
WR0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
A2
VLOGIC
LEVEL
SHIFTER
Pin Configurations
ISL23325
(14 LD TSSOP)
TOP VIEW
ISL23325
(16 LD µTQFN)
TOP VIEW
SDA
VLOGIC
A0
VCC
SCL
GND
RL1
RW1
RH1
A1
RL0
A2
RH0
RW0
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A2 VLOGIC
RH1
GND
NC
RL1
RW1
VCC
A1
RW0
SCL RH0
RL0
SDA
A0
1
3
4
15
16
14
13
2
12
10
9
11
6
5
7
8
GND
Pin Descriptions
TSSOP µTQFN SYMBOL DESCRIPTION
1 6, 15 GND Ground pin
216V
LOGIC I2C bus/logic supply. Range 1.2V to
5.5V
3 1 SDA Logic Pin - Serial bus data
input/open drain output
4 2 SCL Logic Pin - Serial bus clock input
5 3 A0 Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
6 4 A1 Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
7 5 A2 Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
8 8 RL1 DCP1 “low” terminal
9 9 RW1 DCP1 wiper terminal
10 10 RH1 DCP1 “high” terminal
11 11 RH0 DCP0 “high” terminal
12 12 RW0 DCP0 wiper terminal
13 13 RL0 DCP0 “low” terminal
14 14 VCC Analog power supply.
Range 1.7V to 5.5V
7NCNot Connected
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Ordering Information
PART NUMBER
(Note 5) PART MARKING
RESISTANCE
OPTION
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL23325TFVZ (Notes 1, 3) 23325 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173
ISL23325UFVZ (Notes 1, 3)
(No longer available, recommended
replacement: ISL23325TFRUZ-TK)
23325 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173
ISL23325WFVZ (Notes 1, 3) 23325 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173
ISL23325TFRUZ-T7A (Notes 2, 4) GBF 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A
ISL23325TFRUZ-TK (Notes 2, 4) GBF 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A
ISL23325UFRUZ-T7A (Notes 2, 4)
(No longer available, recommended
replacement: ISL23325TFRUZ-TK)
GBE 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A
ISL23325UFRUZ-TK (Notes 2, 4)
(No longer available, recommended
replacement: ISL23325TFRUZ-TK)
GBE 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A
ISL23325WFRUZ-T7A (Notes 2, 4) GBD 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A
ISL23325WFRUZ-TK (Notes 2, 4) GBD 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A
NOTES:
1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23325. For more information on MSL please see techbrief TB363.
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Absolute Maximum Ratings Thermal Information
Supply Voltage Range
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper Current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .4.5kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
14 Ld TSSOP Package (Notes 6, 7) . . . . . . 112 40
16 Ld µTQFN Package (Notes 6, 7) . . . . . . 110 64
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. Fo r JC, the “case temp” location is the center top of the package.
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
RTOTAL RH to RL Resistance W option 10 kΩ
U option 50 kΩ
T option 100 kΩ
RH to RL Resistance Tolerance -20 ±2 +20 %
End-to-End Temperature Coefficient W option 125 ppm/°C
U option 65 ppm/°C
T option 45 ppm/°C
VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0V
CC V
RW Wiper Resistance RH - floating, VRL = 0V, force IW current
to the wiper,
IW = (VCC - VRL)/RTOTAL,
VCC = 2.7V to 5.5V
70 200 Ω
VCC = 1.7V 580 Ω
CH/CL/CWTerminal Capacitance See “DCP Macro Model” on page 9 32/32/32 pF
ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 <0.1 0.4 µA
Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz
Wiper at middle point, U option 49 nV/√Hz
Wiper at middle point, T option 61 nV/√Hz
Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point -65 dB
PSRR Power Supply Reject Ratio Wiper output change if VCC change
±10%; wiper at middle point
-75 dB
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VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL
(Note 13)
Integral Non-linearity, Guaranteed
Monotonic
W option -1.0 ±0.5 +1.0 LSB
(Note 9)
U, T option -0.5 ±0.15 +0.5 LSB
(Note 9)
DNL
(Note 12)
Differential Non-linearity, Guaranteed
Monotonic
W option -1 ±0.4 +1 LSB
(Note 9)
U, T option -0.4 ±0.1 +0.4 LSB
(Note 9)
FSerror Full-scale Error W option -5 -2 0LSB
(Note 9)
U, T option -2 -0.5 0LSB
(Note 9)
ZSerror
(Note 10)
Zero-scale Error W option 025LSB
(Note 9)
U, T option 00.4 2LSB
(Note 9)
Vmatch
(Note 22)
DCP to DCP Matching DCPs at same tap position, same
voltage at all RH terminals, and same
voltage at all RL terminals
-2 ±0.5 2LSB
(Note 9)
TCV
(Notes 14)
Ratiometric Temperature Coefficient W option, Wiper Register set to 80 hex 8 ppm/°C
U option, Wiper Register set to 80 hex 4 ppm/°C
T option, Wiper Register set to 80 hex 2.3 ppm/°C
tLS_Settling Large Signal Wiper Settling Time From code 0 to FF hex, measured from
0 to 1 LSB settling of the wiper
300 ns
fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz
Wiper at middle point U option 250 kHz
Wiper at middle point T option 120 kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
RINL
(Note 18)
Integral Non-linearity, Guaranteed
Monotonic
W option; VCC = 2.7V to 5.5V -2.0 ±1 +2.0 MI
(Note 15)
W option; VCC = 1.7V 10.5 MI
(Note 15)
U, T option; VCC = 2.7V to 5.5V -1.0 ±0.3 +1.0 MI
(Note 15)
U, T option; VCC = 1.7V 2.1 MI
(Note 15)
RDNL
(Note 17)
Differential Non-linearity, Guaranteed
Monotonic
W option; VCC = 2.7V to 5.5V -1 ±0.4 +1 MI
(Note 15)
W option; VCC = 1.7V ±0.6 MI
(Note 15)
U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI
(Note 15)
U, T option; VCC = 1.7V ±0.35 MI
(Note 15)
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
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Roffset
(Note 16)
Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V 035.5 MI
(Note 15)
W option; VCC = 1.7V 6.3 MI
(Note 15)
U, T option; VCC = 2.7V to 5.5V 00.5 2MI
(Note 15)
U, T option; VCC = 1.7V 1.1 MI
(Note 15)
Rmatch
(Note 23)
DCP to DCP Matching Any two DCPs at the same tap position
with the same terminal voltages
-2 2 LSB
(Note 9)
TCR
(Note 19)
Resistance Temperature Coefficient W option; Wiper register set between
32 hex and FF hex
170 ppm/°C
U option; Wiper register set between
32 hex and FF hex
80 ppm/°C
T option; Wiper register set between
32 hex and FF hex
50 ppm/°C
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V,
fSCL = 400kHz (for I2C active read and
write)
200 µA
VLOGIC = 1.2V, VCC = 1.7V,
fSCL = 400kHz (for I2C active read and
write)
5µA
ICC VCC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V 18 µA
VLOGIC = 1.2V, VCC = 1.7V 10 µA
ILOGIC SB VLOGIC Standby Current VLOGIC = VCC = 5.5V,
I2C interface in standby
1µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
0.5 µA
ICC SB VCC Standby Current VLOGIC = VCC = 5.5V,
I2C interface in standby
2µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
1.2 µA
ILOGIC
SHDN
VLOGIC Shutdown Current VLOGIC = VCC = 5.5V,
I2C interface in standby
1µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
0.5 µA
ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V,
I2C interface in standby
2µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
1.2 µA
ILkgDig Leakage Current, at Pins A0, A1, A2,
SDA, SCL
Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA
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tDCP Wiper Response Time SCL rising edge of the acknowledge bit
after data byte to wiper new position
(Changes from 10% to 90% FS)
W, U, T options specified top to bottom
0.4 µs
1.5 µs
3.5 µs
tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit
after ACR data byte to wiper recalled
position and RH connection
1.5 µs
VCC,
VLOGIC
Ramp
(Note 21)
VCC ,VLOGIC Ramp Rate Ramp monotonic at any level 0.01 50 V/ms
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
VIL Input LOW Voltage -0.3 0.3 x VLOGIC V
VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V
Hysteresis SDA and SCL Input Buffer
Hysteresis
VLOGIC > 2V 0.05 x VLOGIC V
VLOGIC < 2V 0.1 x VLOGIC V
VOL SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V
IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V
Cpin SDA, SCL Pin Capacitance 10 pF
fSCL SCL Frequency 400 kHz
tsp Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed
50 ns
tAA SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30%
of VLOGIC, until SDA exits the
30% to 70% of VLOGIC window
900 ns
tBUF Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VLOGIC
during a STOP condition, to
SDA crossing 70% of VLOGIC
during the following START
condition
1300 ns
tLOW Clock LOW Time Measured at the 30% of
VLOGIC crossing
1300 ns
tHIGH Clock HIGH Time Measured at the 70% of
VLOGIC crossing
600 ns
tSU:STA START Condition Set-up Time SCL rising edge to SDA falling
edge; both crossing 70% of
VLOGIC
600 ns
tHD:STA START Condition Hold Time From SDA falling edge
crossing 30% of VLOGIC to SCL
falling edge crossing 70% of
VLOGIC
600 ns
tSU:DAT Input Data Set-up Time From SDA exiting the 30% to
70% of VLOGIC window, to SCL
rising edge crossing 30% of
VLOGIC
100 ns
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tHD:DAT Input Data Hold Time From SCL falling edge crossing
70% of VLOGIC to SDA entering
the 30% to 70% of VLOGIC
window
0ns
tSU:STO STOP Condition Set-up Time From SCL rising edge crossing
70% of VLOGIC, to SDA rising
edge crossing 30% of VLOGIC
600 ns
tHD:STO STOP Condition Hold Time for Read
or Write
From SDA rising edge to SCL
falling edge; both crossing
70% of VLOGIC
1300 ns
tDH Output Data Hold Time From SCL falling edge crossing
30% of VLOGIC, until SDA
enters the 30% to 70% of
VLOGIC window.
IOL =3mA,V
LOGIC > 2V.
IOL = 0.5mA, VLOGIC < 2V
0ns
tRSDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns
tFSDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF
tSU:A A2, A1, A0 Setup Time Before START condition 600 ns
tHD:A A2, A1, A0 Hold Time After STOP condition 600 ns
NOTES:
8. Typical values are for TA = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)0/LSB.
11. FS error = [V(RW)255 – VCC]/LSB.
12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255
14. For i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00
hex respectively.
16. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW255/MI, when measuring between RW and RH.
17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.
18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255.
19. for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC
first followed by the VCC.
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 1 and y = 0 to 1.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255 , x = 0 to 1 and y = 0 to 1.
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
TCV
Max V RW
i
Min V RW
i
–
VRW
i+25°C
------------------------------------------------------------------------------106
+165°C
---------------------
=
TCR
Max RiMin Ri–
Ri +25°C
-------------------------------------------------------106
+165°C
---------------------
=
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DCP Macro Model
Timing Diagrams
SDA vs SCL Timing
A0, A1, and A2 Pin Timing
32pF
RH
RTOTAL
CH
32pF
CW
CL
32pF
RW
RL
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tFtLOW
tBUF
tAA
tRtsp
tHD:A
SCL
SDA
A0, A1, A2
tSU:A
CLK 1
START STOP
ISL23325
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Typical Performance Curves
FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C
-0.4
-0.2
0
0.2
0.4
0 64 128 192 256
DNL (LSB)
TAP POSITION (DECIMAL)
-0.08
-0.04
0.00
0.04
0.08
0 64 128 192 256
DNL (LSB)
TAP POSITION (DECIMAL)
-0.80
-0.40
0.00
0.40
0.80
0 64 128 192 256
INL (LSB)
TAP POSITION (DECIMAL)
-0.16
-0.08
0.00
0.08
0.16
0 64 128 192 256
INL (LSB)
TAP POSITION (DECIMAL)
-0.40
-0.20
0.00
0.20
0.40
0 64 128 192 256
RDNL (MI)
TAP POSITION (DECIMAL)
-0.10
-0.05
0.00
0.05
0.10
0 64 128 192 256
RDNL (MI)
TAP POSITION (DECIMAL)
ISL23325
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FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V
FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V
Typical Performance Curves (Continued)
-0.80
-0.40
0.00
0.40
0.80
0 64 128 192 256
RINL (MI)
TAP POSITION (DECIMAL)
-0.14
-0.07
0.00
0.07
0.14
0 64 128 192 256
RINL (MI)
TAP POSITION (DECIMAL)
0
20
40
60
80
100
0 64 128 192 256
WIPER RESISTANCE ()
TAP POSITION (DECIMAL)
+125°C
-40°C
+25°C
0
20
40
60
80
100
120
0 64 128 192 256
WIPER RESISTANCE ()
TAP POSITION (DECIMAL)
+125°C
-40°C
+25°C
0
100
200
300
400
15 63 111 159 207 255
TCv (ppm/°C)
TAP POSITION (DECIMAL)
0
20
40
60
80
15 63 111 159 207 255
TCv (ppm/°C)
TAP POSITION (DECIMAL)
ISL23325
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FIGURE 15. 10kΩ TCr vs TAP POSITION FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V
FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V
FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH
Typical Performance Curves (Continued)
0
200
400
600
800
15 63 111 159 207 255
TCr (ppm/°C)
TAP POSITION (DECIMAL)
0
50
100
150
200
250
15 63 111 159 207 255
TCr (ppm/°C)
TAP POSITION (DECIMAL)
0
10
20
30
40
50
15 63 111 159 207 255
TCv (ppm/°C)
TAP POSITION (DECIMAL)
0
30
60
90
120
150
15 63 111 159 207 255
TCr (ppm/°C)
TAP POSITION (DECIMAL)
SCL CLOCK
RW PIN
CH1: 1V/DIV, 1µs/DIV
CH2: 10mV/DIV, 1µs/DIV
CH1: 20mV/DIV, 2µs/DIV
CH2: 2V/DIV, 2µs/DIV
SCL
WIPER
9TH CLK OF THE
DATA BYTE (ACK)
ISL23325
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Functional Pin Descriptions
Potentiometers Pins
RHI AND RLI
The high (RHi, i = 0, 1) and low (RLi, i = 0,1) terminals of the
ISL23325 are equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative position
of the wiper and not the voltage potential on the terminals. With
WRi set to 255 decimal, the wiper will be closest to RHi, and with
the WR set to 0, the wiper is closest to RLi.
RWI
RWi (i = 0,1) is the wiper terminal, and it is equivalent to the
movable terminal of a mechanical potentiometer. The position of
the wiper within the array is determined by the WRi register.
VCC
Power terminal for the potentiometer section analog power
source. Can be any value needed to support voltage range of DCP
pins, from 1.7V to 5.5V, independent of the VLOGIC voltage.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bi-directional serial data input/output pin for I2C
interface. It receives device address, wiper address and data
from an I2C external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of the
serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Typical Performance Curves (Continued)
9TH CLOCK OF THE
DATA BYTE (ACK)
1V/DIV
0.2µs/DIV
SCL
WIPER
0.5V/DIV
20µs/DIV VCC
WIPER
0.5V/DIV, 0.2µs/DIV
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
CH1: RH TERMINAL
CH2: RW TERMINAL
0
0.2
0.4
0.6
0.8
1.0
1.8
-40 -15 10 35 60 85 110
STANDBY CURRENT I
CC
(µA)
TEMPERATURE (°C)
VCC = 5.5V, VLOGIC = 5.5V
VCC = 1.7V, VLOGIC = 1.2V
1.6
1.4
1.2
ISL23325
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SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set the least significant 3 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23325. A
maximum of eight ISL23325 devices may occupy the I2C serial
bus (see Table 3).
VLOGIC
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I2C logic source.
Principles of Operation
The ISL23325 is an integrated circuit incorporating two DCPs with
its associated registers and an I2C serial interface providing direct
communication between a host and the potentiometer. The resistor
array is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap positions.
Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC
level at any conditions during power-up and normal operation.
The VLOGIC pin is the terminal for the logic control digital power
source. It should use the same supply as the I2C logic source
which allows reliable communication with a wide range of
microcontrollers and is independent from the VCC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
Each DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are equivalent
to the fixed terminals of a mechanical potentiometer (RHi and RLi
pins). The RWi pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Register (WRi). When the WRi
of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal
(RWi) is closest to its “Low” terminal (RLi). When the WRi register
of a DCP contains all ones (WRi[7:0] = FFh), its wiper terminal
(RWi) is closest to its “High” terminal (RHi). As the value of the WRi
increases from all zeroes (0) to all ones (255 decimal), the wiper
moves monotonically from the position closest to RLi to the
position closest to RHi. At the same time, the resistance between
RWi and RLi increases monotonically, while the resistance
between RHi and RWi decreases monotonically.
While the ISL23325 is being powered up, both WR0 and WR1
are reset to 80h (128 decimal), which positions RWi at the center
between RLi and RHi.
The WRi can be read or written to directly using the I2C serial
interface as described in the following sections.
Memory Description
The ISL23325 contains three volatile 8-bit registers: Wiper
Register WR0, Wiper Register WR1, and Access Control Register
(ACR). Memory map of the ISL23325 is shown in Table 1. The
Wiper Register WR0 at address 0, contains current wiper position
of DCP0; The Wiper Register WR1 at address 1 contains current
wiper position of DCP1. The Access Control Register (ACR) at
address 10h contains information and control bits described in
Table 2.
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor as shown in Figure 25. Default value of the
SHDN bit is 1.
When the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2 to 0.4µs, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
TABLE 1. MEMORY MAP
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10 ACR 40
1WR1 80
0WR0 80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 76543210
NAME/
VALUE
0SHDN
000000
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
2kΩ
RW
RL
RH
ISL23325
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I2C Serial Interface
The ISL23325 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23325 operates as a slave device
in all applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 27). On
power-up of the ISL23325, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
ISL23325 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 28).
The ISL23325 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Address Byte. The ISL23325 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 1010 as the four MSBs, and
the following three bits are matching the logic values present at
pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1”
for a Read operation and “0” for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
POWER-UP
USER PROGRAMMED
MID SCALE = 80H
SHDN ACTIVATED SHDN RELEASED
AFTER SHDN
WIPER VOLTAGE, VRW (V)
SHDN MODE
TIME (s)
WIPER RESTORE TO
THE ORIGINAL POSITION
0
1010A2A1A0R/W
(MSB) (LSB)
LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
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Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23325 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and the
device enters its standby state (see Figures 28 and 29).
It is possible to perform a sequential Write to all DCP channels
via a single Write operation. The command is initiated by sending
an additional Data Byte after the first Data byte instead of
sending a STOP condition.
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23325 responds
with an ACK; then the ISL23325 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
A
C
K
10100
A
C
K
WRITE
SIGNAL AT SDA 000
A0A1
FIGURE 29. BYTE WRITE SEQUENCE
A2
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
10100
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
000
A0A1 A0A1
FIGURE 30. READ SEQUENCE
A
C
K
A2 A21010
READ
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Applications Information
VLOGIC Requirements
VLOGIC should be powered continuously during normal operation.
In a case where turning VLOGIC OFF is necessary, it is
recommended to ground the VLOGIC pin of the ISL23325.
Grounding the VLOGIC pin or both VLOGIC and VCC does not affect
other devices on the same bus. It is good practice to put a 1µF
cap in parallel to 0.1µF as close to the VLOGIC pin as possible.
VCC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
EFh to FFh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
ISL23325
18
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7870.1
September 23, 2015
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
DATE REVISION CHANGE
9/23/15 FN7870.1 Updated the Ordering Information table on page 3.
Replaced the Products section with the About Intersil section.
Updated Package Outline Drawing L16.2.6x1.8A to the latest revision. Changes are as follows:
-Changed in Note 5 0.30 to 0.25.
6/21/11 FN7870.0 Initial Release
ISL23325
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Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
B
A
17
8
14
C
PLANE
SEATING
0.10 C0.10 CBA
H
PIN #1
I.D. MARK
5.00 ±0.10
4.40 ±0.10
0.25 +0.05/-0.06
6.40
0.20 C B A
0.05
0°-8°
GAUGE
PLANE
SEE
0.90 +0.15/-0.10
0.60 ±0.15
0.09-0.20
5
2
31
3
1.00 REF
0.65
1.20 MAX
0.25
0.05 MIN
0.15 MAX
(1.45)
(5.65)
(0.65 TYP) (0.35 TYP)
DETAIL "X"
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
NOTES:
END VIEW
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Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
C
0.05 CA
0.10 C
A1
SEATING PLANE
INDEX AREA
21
N
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NX (b)
SECTION "C-C" e
CC
5
C
L
TERMINAL TIP
(A1)
L
0.10 C
2X
e
L1
NX L
21
0.10 M CAB
0.05 M C
5
NX b
(DATUM B)
(DATUM A)
PIN #1 ID
16X
3.00
1.40
2.20
0.40
0.50
0.20
0.40
0.20
0.90
1.40
1.80
LAND PATTERN
10
K
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.45 0.50 0.55 -
A1 - - 0.05 -
A3 0.127 REF -
b 0.15 0.20 0.25 5
D 2.55 2.60 2.65 -
E 1.75 1.80 1.85 -
e 0.40 BSC -
K0.15 - - -
L 0.35 0.40 0.45 -
L1 0.45 0.50 0.55 -
N162
Nd 4 3
Ne 4 3
0-12
4
Rev. 6 1/14
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.