Preliminary UL62H1616A Low Voltage Automotive Fast 64K x 16 SRAM Features Description ! 65536 x 16 bit static CMOS RAM ! 15, 20 and 35 ns Access Time ! Common data inputs and The UL62H1616A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Lower / Upper Byte Read - Word Read - Lower / Upper Byte Write - Word Write - Standby - Data Retention The memory array is based on a 6-Transistor cell. The circuit is activated by the falling edge of E. The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. During the active state E = L and W = H each address data outputs ! Three-state outputs ! Standby current < 150 A at 125C ! TTL/CMOS-compatible ! Power supply voltage 3.3 V ! Operating temperature range ! ! ! ! K-Type:-40 C to 85 C A-Type:-40 C to 125 C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity >100 mA Package: TSOP II 44 (400 mil) Pin Configuration A4 A3 A2 A1 A0 E DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 W A15 A14 A13 A12 n.c. 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 36 9 35 10 34 11 12 SOJ 33 TSOPII 32 13 31 14 15 30 29 16 28 17 18 27 19 26 20 25 21 24 22 23 Pin Description A5 A6 A7 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 n.c. A8 A9 A10 A11 n.c. BGA LB G A0 A1 A2 n.c. DQ8 UB A3 A4 E DQ0 DQ9 DQ10 A5 A6 DQ1 DQ2 VSS DQ11 n.c. A7 DQ3 VCC DQ12 n.c. n.c. DQ14 DQ13 A14 DQ15 n.c. n.c. A8 Signal Name Signal Description A0 - A15 Address Inputs DQ0 - DQ15 Data In/Out E Chip Enable VCC G Output Enable VSS W UB Write Enable DQ4 A15 DQ5 DQ6 LB Lower Byte Enable A12 A13 W DQ7 VCC Power Supply Voltage VSS Ground A9 A10 A11 n.c. n.c. not connected Top View Top View October 20, 2003 change leads to a new Read cycle. In a Read cycle, the data outputs are activated by the falling edge of G. If LB = L the data lower byte will be available at the outputs DQ0DQ7, on UB = L the data upper byte appear at the outputs DQ8DQ15. After the address change, the data outputs go High-Z until the new information is available. The data outputs have no preferred state. The Read cycle is finished by the falling edge of W, or by the rising edge of E, respectively. Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. 1 Upper Byte Enable UL62H1616A Preliminary Row Decoder DQ1 DQ2 512 Rows x 128 x 16 Columns DQ3 DQ4 Sense Amplifier/ Write Control Logic Common Data I/O Column Decoder A10 A11 A12 A13 A14 A9 A15 DQ0 Memory Cell Array DQ5 Column Address Inputs A0 A1 A2 A3 A4 A5 A6 A7 A8 Row Address Inputs Block Diagram DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 Address Change Detector DQ13 Clock Generator DQ14 DQ15 VCC VSS E W G UB LB Truth Table Operating Mode E W G LB UB DQ0-DQ7 DQ8-DQ15 Standby/not selected H * * * * High-Z High-Z L H H * * High-Z High-Z L * * H H High-Z High-Z Lower Byte Read L H L L H Data Outputs Low-Z High-Z Upper Byte Read L H L H L High-Z Data Outputs Low-Z Word Read L H L L L Data Outputs Low-Z Data Outputs Low-Z Lower Byte Write L L * L H Data Inputs High-Z High-Z Upper Byte Write L L * H L High-Z Data Inputs High-Z Word Write L L * L L Data Inputs High-Z Data Inputs High-Z Internal Read * H or L 2 October 20, 2003 Preliminary UL62H1616A Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage. Absolute Maximum Ratings a Symbol Min. Max. Unit VCC -0.3 4.6 V Input Voltage VI -0.5 VCC + 0.5 b V Output Voltage VO -0.5 VCC + 0.5 b V Power Dissipation PD - 1 W Ta -40 -40 85 125 C Tstg -65 150 C 100 mA Power Supply Voltage Operating Temperature K-Type A-Type Storage Temperature Output Short-Circuit Current at VCC = 3.3 V and VO = 0 V c a b c d | IOS | Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 4.6 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Symbol Power Supply Voltage Conditions Min. Max. Unit VCC 3.0 3.6 V Input Low Voltage d VIL -0.3 0.8 V Input High Voltage VIH 2.0 VCC + 0.3 V -2 V at Pulse Width 10 ns October 20, 2003 3 UL62H1616A Preliminary 15 Electrical Characteristics Symbol ICC(OP) Supply Current Standby Mode (CMOS level) ICC(SB) Supply Current Standby Mode (LVTTL level) ICC(SB)1 Output High Voltage VOH Output Low Voltage VOL Input High Leakage Current IIH Input Low Leakage Current IIL Output High Current IOH Output Low Current IOL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ e 35 Unit Min. Supply Current Operating Mode 20 Conditions VCC VIL VIH tcW tcW tcW tcW tcW = = = = = = = = 3.6 V 0.8 V 2.0 V 15 ns 20 ns 35 ns 55 ns 70 ns VCC VE K-Type A-Type = 3.6 V = VCC - 0.2 V VCC VE K-Type A-Type = 3.6 V = 2.0 V VCC IOH VCC IOL = 3.0 V = -0.5 mA = 3.0 V = 0.5 mA VCC VIH VCC VIL = 3.6 V = 3.6 V = 3.6 V = 0V VCC VOH VCC VOL = = = = VCC VOH VCC VOL = 3.6 V = 3.6 V = 3.6 V = 0V 3.0 V 2.2 V 3.0 V 0.4 V Max. Min. Min. Max. 65 55 e 40 e 30 e 20 e 55 40 e 30 e 20 e 40 30 e 20 e mA mA mA mA mA 1000 1000 1000 1000 100 150 A A 1 2 1 2 1 2 mA mA 2.2 2.2 2.2 V 0.4 0.4 0.4 V 2 2 2 A -2 -2 -0.5 0.5 -2 -0.5 0.5 2 -2 Max. -0.5 0.5 2 -2 A mA 2 -2 mA A A This parameter is guaranteed, but not tested. 4 October 20, 2003 Preliminary Switching Characteristics Read Cycle UL62H1616A Symbol 15 20 35 Unit Alt. IEC Min. Read Cycle Time tRC tcR 15 Address Access Time to Data Valid tAA ta(A) 15 20 35 ns Chip Enable Access Time to Data Valid tACE ta(E) 15 20 35 ns G LOW to Data Valid tOE ta(G) 7 9 15 ns LB, UB LOW to Data Valid tB ta(B) 7 9 15 ns E HIGH to Output in High-Z tHZCE tdis(E) 7 8 12 ns G HIGH to Output in High-Z tHZOE tdis(G) 7 8 12 ns LB, UB HIGH to Output in High-Z tHZB tdis(B) 7 8 12 ns E LOW to Output in Low-Z tLZCE ten(E) 4 4 5 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 0 ns LB, UB LOW to Output in Low-Z tLZB ten(B) 0 0 0 ns Output Hold Time from Address Change tOH tv(A) 3 3 3 ns E LOW to Power-Up Time tPU 0 0 0 ns E HIGH to Power-Down Time tPD Switching Characteristics Write Cycle Max. Min. Max. 20 Max. 35 15 Symbol Min. ns 20 15 35 20 35 ns Unit Alt. IEC Min. Write Cycle Time tWC tcW 15 20 35 ns Write Pulse Width tWP tw(W) 10 12 20 ns Write Setup Time tWP tsu(W) 10 12 20 ns Address Setup Time tAS tsu(A) 0 0 0 ns Address Valid to End of Write tAW tsu(A-WH) 10 12 20 ns Chip Enable Setup Time tCW tsu(E) 10 12 25 ns Byte Enable Setup Time tBW tsu(B) 10 12 25 ns Pulse Width Chip Enable to End of Write tCW tw(E) 10 12 25 ns Pulse Width Byte Enable to End of Write tBW tw(B) 10 12 25 ns Data Setup Time tDS tsu(D) 7 9 15 ns Data Hold Time tDH th(D) 0 0 0 ns Address Hold from End of Write tAH th(A) 0 0 0 ns W LOW to Output in High-Z tHZWE tdis(W) 7 8 15 ns G HIGH to Output in High-Z tHZOE tdis(G) 7 8 12 ns W HIGH to Output in Low-Z tLZWE ten(W) 3 3 3 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 0 ns October 20, 2003 5 Max. Min. Max. Min. Max. UL62H1616A Preliminary Data Retention Mode E - controlled VCC 3.0 V VCC(DR) 1.5 V 2.0 V tsu(DR) trec Data Retention 2.0 V E 0V VCC(DR) - 0.2 V VE(DR) VCC(DR) + 0.3 V Data Retention Characteristics Symbol Alt. Conditions IEC Min. VCC(DR) Data Retention Supply Current ICC(DR) VCC(DR) = 1.5 V VE = VCC(DR) - 0.2 V tCDR tsu(DR) tR trec See Data Retention Waveforms (above) Operating Recovery Time Max. Unit 3.6 V 30 A 1.5 Data Retention Supply Voltage Data Retention Setup Time Typ. 0 ns tcR ns Test Configuration for Functional Check VIL 1) VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSS Simultaneous measurement of all 16 output pins VIH Input level according to the relevant test measurement 3.3 V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 E W G LB UB 481 VO 30 pF1) 255 In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF. 6 October 20, 2003 Preliminary UL62H1616A Capacitance Conditions Input Capacitance VCC VI f Ta Output Capacitance Symbol = 3.3 V = V SS = 1 MHz = 25 C Min. Max. Unit CI 7 pF Co 7 pF All pins not under test must be connected with ground by capacitors. IC Code Numbers UL62H1616A T A 15 Internal Code Type Package T = TSOP II 44 (400 mil) J = SOJ 44 (400 mil) f K = BGA 48 (6 x 8) f f Operating Temperature Range K = -40 to 85 C A = -40 to 125 C Access Time 15 = 15 ns 20 = 20 ns 35 = 35 ns on special request The date of manufacture is given by the last 4 digits of the third line of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. Assembly location and trace code are shown in line 4. October 20, 2003 7 UL62H1616A Preliminary Read Cycle 1: Ai-controlled (during Read Cycle : E = G = V IL, W = VIH) tcR Ai DQi Address Valid ta(A) Previous Data Valid Output Output Data Valid tv(A) Read Cycle 2: G-, E-, LB-, UB-controlled (during Read Cycle: W = VIH) tcR Ai E Address Valid tsu(A) G Output ta(G) tdis(G) ta(B) tdis(B) ten(G) LB, UB DQi tdis(E) ta(E) ten(E) ten(B) High-Z Output Data Valid tPD tPU ICC(OP) ICC(SB) 50 % 50 % Write Cycle1: W-controlled tcW Ai Address Valid tsu(E) th(A) E tsu(B) LB, UB tsu(A-WH) tw(W) W tsu(A) tsu(D) DQi Input DQi th(D) Input Data Valid tdis(W) ten(W) High-Z Output G 8 October 20, 2003 Preliminary UL62H1616A Write Cycle 2: E-controlled tcW Ai E tsu(A) Address Valid tw(E) th(A) tsu(B) LB, UB tsu(W) W tsu(D) th(D) DQi Input ten(E) Input Data Valid tdis(W) DQi High-Z Output tdis(G) G Write Cycle 3: LB-, UB-controlled tcW Ai Address Valid tsu(E) E LB, UB tsu(A) th(A) tw(B) tsu(W) W tsu(D) DQi Input DQi Output ten(B) th(D) Input Data Valid tdis(W) High-Z tdis(G) G undefined L- to H-level H- to L-level The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. October 20, 2003 9 Preliminary UL62H1616A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. October 20, 2003 Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de