PS005303-0907
Z85230/Z80230
Product Specification
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
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©2007 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
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Warning:
PS005303-0907 Revision History
Z85230/Z80230
Product Specification
iii
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
Date
Revision
Level Description Page No
September 2007 03 Updated Figure 38 and Implemented Style
Guide
All
November 2002 02 Editorial Updates All
August 2001 01 Original Issue All
PS005303-0907 Table of Contents
Z85230/Z80230
Product Specification
iv
Table of Contents
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins Common to Both the Z85230 and Z80230 . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions Exclusive to the Z85230 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions Exclusive to the Z80230 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/Output Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESCC Data Communications Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 15
Z80230/Z85230 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4-Byte Transmit FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8-Byte Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Write Register 7 PRIME (WR7’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CRC Reception in SDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TxD Forced High in SDLC with NRZI Encoding When Marking Idle . . . . . . 26
Improved Transmit Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DPLL Counter Tx Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Register 0 Status Latched During Read Cycle . . . . . . . . . . . . . . . . . 27
Software Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Fast SDLC Transmit Data Interrupt Response . . . . . . . . . . . . . . . . . . . . . . 28
SDLC FIFO Frame Status Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FIFO Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FIFO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FIFO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SDLC Status FIFO Anti-Lock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Initializing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Z80230 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Z80230 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Z80230 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Z80230 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 71
Z85230 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Z85230 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Z85230 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Z85230 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 74
PS005303-0907 Table of Contents
Z85230/Z80230
Product Specification
v
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Z85230 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Z80230/Z85230 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
IUS Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
IUS Problem Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
RTS Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
RTS Problem Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Automatic TxD Forced High Problem Description . . . . . . . . . . . . . . . . . . . 101
Automatic TxD Forced High Problem Solutions . . . . . . . . . . . . . . . . . . . . 102
SDLC FIFO Overflow Problem Description . . . . . . . . . . . . . . . . . . . . . . . . 102
SDLC FIFO Overflow Problem Solution . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Default RR0 Value Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Default RR0 Value Problem Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Default RR10 Value Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . 103
Default RR10 Value Problem Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
CRC Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
CRC Problem Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Z85230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Part Number Suffix Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PS005303-0907 Pin Descriptions
Z85230/Z80230
Product Specification
1
Pin Descriptions
The Enhanced Serial Communication ControllerTM (ESCC) pins are divided into seven
functional groups:
•
Address/Data
•
Bus Timing and Reset
•
Device Control
•
Interrupt
•
Serial Data (both channels)
•
Peripheral Control (both channels)
•
Clocks (both channels)
Figure 1 on page 2 and Figure 2 on page 2 illustrate the pins in each functional group for
both the Z80230 and Z85230. The pin functions are unique to each bus interface version in
the Address/Data group, Bus Timing and Reset group, and Device Control group.
The Address/Data group consists of the bidirectional lines used to transfer data between
the CPU and the ESCC (addresses in the Z80230 are latched by AS). The direction of
these lines depends on whether the operation is a Read or Write operation.
The Timing and Control groups designate the type of transaction to occur and the timing
of the occurrence. The interrupt group provides inputs and outputs for handling and prior-
itizing interrupts. The remaining groups are divided into Channel A and Channel B groups
for:
•
Serial Data (Transmit or Receive)
•
Peripheral Control (Such as DMA or modem)
•
Input and Output Line for the Receive and Transmit Clocks
PS005303-0907 Pin Descriptions
Z85230/Z80230
Product Specification
2
Figure 1. Z85230 Pin Functions
Figure 2. Z80230 Pin Functions
TxDA
RxDA
TRxCA
RTxCA
SYNCA
W/REQA
DTR/REQA
RTSA
CTSA
DCDA
TxDB
RxDB
TRxCB
RTxCB
SYNCB
W/REQB
DTR/REQB
RTSB
CTSB
DCDB
D7
D6
D5
D4
D3
D2
D1
D0
RD
WR
A/B
CE
INT
INTACK
IEI
IEO
D/C
Z85230
Serial
Data
Channel
Clocks
Channel
Controls
for modem,
DMA and
Other
Channel
Controls
for modem,
DMA and
Other
Channel
Clocks
Serial
Data
Data Bus
Bus Timing
and Reset
Control
Interrupt
Channel A
Channel B
+5V GND PCLK
TxDA
RxDA
TRxCA
RTxCA
SYNCA
W/REQA
DTR/REQA
RTSA
CTSA
DCDA
TxDB
RxDB
TRxCB
RTxCB
SYNCB
W/REQB
DTR/REQB
RTSB
CTSB
DCDB
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AS
DS
R/W
CS1
INT
INTACK
IEI
IEO
CS0
Z80230
Serial
Data
Channel
Clocks
Channel
Controls
for modem,
DMA and
Other
Channel
Controls
for modem,
DMA and
Other
Channel
Clocks
Serial
Data
Data Bus
Bus Timing
and Reset
Control
Interrupt
Channel A
Channel B
+5V GND PCLK
PS005303-0907 Pin Descriptions
Z85230/Z80230
Product Specification
3
Figure 3 illustrates the Z85230 DIP and PLCC pin assignments, respectively. Figure 4
illustrates the Z80230 DIP and PLCC pin assignments.
Figure 3. Z85230 Pin Assignments
Figure 4. Z80230 Pin Assignments
D1
D3
D5
D7
INT
IEO
IEI
INTACK
VCC
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
DTR/REQA
RTSA
CTSA
DCDA
PCLK
1
20
D0
D2
D4
D6
RD
WR
A/B
CE
D/C
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
DTR/REQB
RTSB
CTSB
DCDB
40
21
Z85230
Z85230 DIP Pin Assignments
739
2917
18 28
IEO
IEI
INTACK
VCC
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
N/C
Z85230 PLCC Pin Assignments
A/B
CE
D/C
N/C
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
N/C
DTR/REQA
RTSA
CTSA
DCDA
PCLK
DCDB
CTSB
RTSB
DTR/REQB
N/C
INT
D7
D5
D3
D1
D0
D2
D4
D6
RD
WR
Z85230
6 1 40
AD1
AD3
AD5
AD7
INT
IEO
IEI
INTACK
VCC
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
RTSA
CTSA
DCDA
PCLK
1
20
AD0
AD2
AD4
AD6
DS
AS
R/W
CS0
CS1
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
DTR/REQB
RTSB
CTSB
DCDB
40
21
Z80230
Z80230 DIP Pin Assignments
61 40
39
29
7
17
18 28
IEO
IEI
INTACK
VCC
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
N/C
Z80230 PLCC Pin Assignments
R/W
CS0
CS1
N/C
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
N/C
DTR/REQA
RTSA
CTSA
DCDA
PCLK
DCDB
CTSB
RTSB
DTR/REQB
N/C
INT
AD7
AD5
AD3
AD1
AD0
AD2
AD4
AD6
DS
AS
Z80230
PS005303-0907 Pin Descriptions
Z85230/Z80230
Product Specification
4
Pins Common to Both the Z85230 and Z80230
The pin descriptions for pins common to both Z85230 and Z80230 are provided below:
CTSA, CTSB (Clear To Send (Inputs, Active Low)). These pins function as transmitter
enables if they are programmed for Auto Enable (WR3 bit 5 is 1), in which case a Low on
each input enables the respective transmitter. If not programmed as Auto Enable, the pins
may be used as general-purpose inputs. These pins are Schmitt-trigger buffered to accom-
modate slow rise-time inputs. The ESCC detects pulses on these pins and may interrupt
the CPU on both logic level transitions.
DCDA, DCDB (Data Carrier Detect (Inputs, Active Low)). These pins function as
receiver enables if they are programmed for Auto Enable (WR3 bit 5 is 1); otherwise, they
are used as general-purpose input pins. The pins are Schmitt-trigger buffered to accommo-
date slow rise-time signals. The ESCC detects pulses on these pins and may interrupt the
CPU on both logic level transitions.
RTSA, RTSB (Request To Send (Outputs, Active Low)). The RTS pins can be used as
general-purpose outputs or with the AUTO ENABLE feature. When AUTO-ENABLE is
off, these pins follow the inverse state of WR5 bit 1. When used with the AUTO-
ENABLE feature in ASYNCHRONOUS mode, this pin immediately goes Low when
WR5 bit 1 is 1. When WR5 bit 0 is 0, this pin remains Low until the transmitter is empty.
In Synchronous Data Link Control (SDLC) mode, the RTS pins can be programmed to be
deasserted when the closing flag of the message clears the TxD pin, if WR7’ bit 2 is 1,
WR10 bit 2 is 0, and WR5 bit 1 is 0.
SYNCA, SYNCB (Synchronization (Inputs Or Outputs, Active Low)). These pins can
act either as inputs, outputs, or as part of the crystal oscillator circuit. In the ASYNCHRO-
NOUS RECEIVE mode (crystal oscillator option not selected), these pins are inputs simi-
lar to CTS and DCD. In this mode, transition on these lines affect the state of the SYNC/
HUNT status bits in Read Register 0 but have no other function.
In EXTERNAL SYNCHRONIZATION mode, with the crystal oscillator not selected,
these lines also act as inputs. In this mode, SYNC is driven Low, two Rx clock cycles after
the last bit of the SYNC character is received. Character assembly begins on the rising
edge of the receive clock immediately preceding the activation of SYNC.
In the INTERNAL SYNCHRONIZATION mode (MONOSYNC and BISYNC) with the
crystal oscillator not selected, these pins act as outputs. These outputs go Low each time a
SYNC pattern is recognized, regardless of character boundaries. In SDLC mode, pins
switch from input to output when MONOSYNC, BISYNC, or SDLC is programmed in
WR4 and SYNC modes are enabled.
DTR/REQA, DTR/REQB (Data Terminal Ready/Request (Output, Active Low)). These
pins can be programmed (WR14 bit 2) to serve either as general-purpose outputs or as
DMA Request lines. When programmed for DTR function (WR14 bit 2 is 0), these out-
puts follow the inverse of the DTR bit of Write Register 5 (WR5 bit 7). When pro-
grammed for REQUEST mode these pins serve as DMA Requests for the transmitter.
PS005303-0907 Pin Descriptions
Z85230/Z80230
Product Specification
5
When used as DMA Request line (WR14 bit 2 is 1), the timing for the deactivation request
can be programmed in Write Register 7’ (WR7’) bit 4. If this bit is 1, the DTR/REQ pin is
deactivated with the same timing as the W/REQ pin. If 0, the deactivation timing of DTR/
REQ pin is four clock cycles, the same as in the Z80C30/Z85C30.
W/REQA, W/REQB (Wait/request (Output, Open-drain When Programmed For WAIT
Function, Driven High And Low When Programmed For Request Function)). These
dual-purpose outputs may be programmed as REQUEST lines for a DMA controller or as
WAIT lines to synchronize the CPU to the ESCC data rate. The reset state is WAIT.
RxDA, RxDB (Receive Data (inputs, active High)). These inputs receive serial data at
standard Transistor-Transistor Logic (TTL) levels.
RTxCA, RTxCB (Receive/Transmit Clocks (Input, Active Low)). These pins can be
programmed to several modes of operation. In each channel, RTxC may supply the fol-
lowing:
•
Receive clock and/or the transmit clock
•
Clock for the baud rate generator (BRG)
•
Clock for the Digital Phase-Locked Loop
These pins can also be programmed for use with the respective SYNC pins as a crystal
oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in ASYNCHRO-
NOUS modes.
TxDA, TxDB (Transmit Data (Output, Active High)). These output transmit serial data at
standard TTL levels.
TRxCA, TRxCB (Transmit/Receive Clocks (Input or Output, Active Low)).
These pins can be programmed in several different modes. When configured as an input,
the TRxC may supply the receive clock and/or the transmit clock. When configured as an
output, TRxC can echo the clock output of the Digital Phase-Locked Loop, the crystal
oscillator, the BRG or the transmit clock.
PCLK (Clock (Input)). This clock is the master ESCC clock used to synchronize internal
signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship
with the master system clock.
IEI (Interrupt Enable In (Input, Active High)). IEI is used with IEO to form an interrupt
daisy chain when there is more than one interrupt-driven device. A High IEI indicates that
no higher priority device has an Interrupt Under Service (IUS) or is requesting an
interrupt.
IEO (Interrupt Enable Out (Output, Active High)). IEO is High only if IEI is High and
the CPU is not servicing an ESCC interrupt. During an Interrupt Acknowledge Cycle, IEO
is also driven Low if the ESCC is requesting an interrupt. IEO can be connected to the
next lower priority device’s IEI input, and in this case inhibits interrupts from lower prior-
ity devices.
PS005303-0907 Pin Descriptions
Z85230/Z80230
Product Specification
6
INT (Interrupt (Output, Open-Drain, Active Low)). This pin activates when the ESCC
requests an interrupt. The INT is an open-drain output.
INTACK (Interrupt Acknowledge (Input, Active Low)). This pin is a strobe which indi-
cates that an Interrupt Acknowledge Cycle is in progress. During this cycle, the ESCC
interrupt daisy chain is resolved. The device can return an interrupt vector that may be
encoded with the type of interrupt pending. During the acknowledge cycle, if IEI is High,
the ESCC places the interrupt vector on the data bus when RD goes active for the Z85230,
or when DS goes active for the Z80230. INTACK is latched by the rising edge of PCLK.
Pin Descriptions Exclusive to the Z85230
The pin description for pins exclusive to Z85230 is provided below:
Pins D7–D0 (Data Bus (Bidirectional, tristate)). These pins carry data and commands to
and from the Z85230.
CE (Chip Enable (Input, Active Low)). This pin selects the Z85230 for a Read or Write
operation.
RD ((Read (input, Active Low)). This pin indicates a Read operation and, when the
Z85230 is selected, enables the Z85230’s bus drivers. During the Interrupt Acknowledge
cycle, RD gates the interrupt vector onto the bus if the Z85230 is the highest priority
device requesting an interrupt.
WR (Write (Input, Active Low)). When the Z85230 is selected, this pin denotes a Write
operation, which indicates that the CPU writes command bytes or data to the Z85230 write
registers.
WR and RD going Low simultaneously is interpreted as a Reset.
A/B (Channel A/Channel B (Input)). This pin selects the channel in which the Read or
Write operation occurs. A High selects Channel A and a Low selects Channel B.
D/C (Data/Control Select (Input)). This signal defines the type of information transferred
to or from the Z85230. A High indicates data transfer and a Low indicates a command
transfer.
Pin Descriptions Exclusive to the Z80230
The pin description for pins exclusive to Z80230 is provided below:
AD7–AD0 (Address/Data Bus (Bidirectional, Active High, tristate)). These multi-
plexed lines carry register addresses to the Z80230 as well as data or control information
to and from the Z80230.
R/W (Read/Write (Input, Read Active High)). This pin specifies if the operation to be
performed is a Read or Write operation.
Note:
PS005303-0907 Pin Descriptions
Z85230/Z80230
Product Specification
7
CS0 (Chip Select 0 (Input, Active Low)). This pin is latched concurrently with the
addresses on A7-A0 and must be Low for the intended bus transaction to occur.
CS1 (Chip Select 1 (Input, Active High)). This second chip select pin must be High
before and during the intended bus transaction.
DS (Data Strobe (Input, Active Low)). This pin provides timing for the transfer of data
into and out of the Z80230. If AS and DS are both Low, this condition is interpreted as a
RESET.
AS (Address Strobe (Input, Active Low)). Addresses on A7-A0 are latched by the rising
edge of this signal.
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
8
Functional Description
The architecture of the ESCC is described based on its functionality as a:
•
Data communications device which transmits and receives data in a wide variety of
protocols
•
Microprocessor peripheral in which the ESCC offers valuable features such as
vectored interrupts and DMA support
The details of the communication between the receive and transmit logic of the system bus
are illustrated in Figure 5 and Figure 6 on page 9. The features and data path for each of
the ESCC A and B channels are identical. For more information on SCC/ESCC and ISCC
Family of Products, refer to the respective User Manuals available for download from
www.zilog.com.
Figure 5. ESCC Transmit Data Path
WR7 WR6
SYNC Register
20-Bit TX Shift Register
Zero Insert
CRC-SDLC
CRC-Gen
From Receiver
SYNC Register
Internal Data Bus
WR8 TX FIFO
Internal TXD
ASYNC
SYNC
SDLC
Transmit Clock
Final Tx
MUX
NRZI Encode
Transmit
MUX and
2 Bit Delay
TXD
to Other Channel
4 Bytes
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
9
Figure 6. ESCC Receive Data Path
Input/Output Capabilities
System communication to and from the ESCC is accomplished using the
ESCC register set. There are 17 Write registers and 16 Read registers. Many of the fea-
tures on the ESCC are enabled through a new register in the ESCC: Write Register 7
Prime (WR7’). This new register can be accessed if bit 0 or WR15 is set to 1. Table 1 on
page 10 lists the Write registers and a brief description of their functions. Table 2 on page
11 describes the Read Registers.
Rec. Error Logic
CPU I/O
I/O Data Buffer
Internal Data Bus
Upper Byte (WR13)
Time Constant
Lower Byte (WR12)
Time Constant
BRG
Input
16 Bit Down Counter Div 2 BRG
Output
Status FIFO
10 x 19 Frame Rx Data FIFO
8 Bytes Deep
Rx Error FIFO
8 Bytes Deep
Hunt Mode (BISYNC)
14 Bit Counter
DPLL IN DPLL
Internal TXD
RxD 1 Bit MUX NRZI
and 0 Delete
SYNC Register
Decode MUX
OUT
Receive Shift
Register
3 Bits
CRC Delay
Register (8 Bits)
CRC Checker
SDLC-CRC CRC Result
SYNC
CRC
To Transmit Section
DPLL
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
10
Throughout this document the Write and Read registers are referenced with the following
notation: WR for Write Register, and RR for Read Register. For example:
WR4A – Write Register 4 for Channel A
RR3 – Read Register 3 for either or both channels
Table 1. ESCC Write Registers
Write Register Functions
WR0 Command Register; Select Shift Left/Right Mode, Cyclic
Redundancy Check (CRC) Initialization, and Resets for
Various Modes
WR1 Interrupt Conditions, Wait/DMA Request Control
WR2 Interrupt Vector, Accessed Through Either Channel
WR3 Receive and Miscellaneous Control Parameters
WR4 Transmit and Receive Parameters and Modes
WR5 Transmit Parameters and Controls
WR6 SYNC Character or SDLC Address Field
WR7 SYNC Character or SDLC Flag
WR7’ SDLC Enhancements Enable, Accessible if WR15 bit D0 is 1
WR8 Transmit FIFO, 4-Bytes Deep
WR9 Reset Commands and Master INT Enable, Accessible
Through Either Channel
WR10 Miscellaneous Transmit and Receive Controls
WR11 Clock Mode Control
WR12 Lower Byte of BRG Time Constant
WR13 Upper Byte of BRG Time Constant
WR14 Miscellaneous Controls and Digital Phase-Locked Loop
(DPLL) Commands
WR15 External Interrupt Control
Note:
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
11
There are 3 modes used to move data into and out of the ESCC:
•
POLLING
•
INTERRUPT (vectored and non-vectored)
•
BLOCK TRANSFER
The BLOCK TRANSFER mode can be implemented under CPU or DMA control.
POLLING
When POLLING, data interrupts are disabled, 3 registers in the ESCC are automatically
updated whenever any function is performed. For example, end-of-frame (EOF) in SDLC
mode sets a bit in one of these status registers. The purpose of POLLING is for the CPU to
periodically read a status register until the register contents indicate the need that data
requires transfer. RR0 is the only register that must be read to determine if data needs to be
transferred. An alternative to polling RR0 for each channel is to poll the Interrupt Pending
Table 2. ESCC Read Registers
Register Name Functions
RR0 Transmit, Receive and External Status
RR1 Special Receive Condition Status Bits
RR2A Unmodified Interrupt Vector
RR2B Modified Interrupt Vector
RR3A Interrupt Pending Bits
RR4 WR4 Mirror if WR7’ bit D6 equals 1
RR5 WR5 Mirror, if WR7’ bit D6 equals 1
RR6 SDLC Frame LSB Byte Count, if WR15 bit D2 equals 1
RR7 SDLC Frame 10 X 19 FIFO Status and MSB Byte Count, if
WR15 bit DS equals 1
RR8 Receive Data FIFO, 8 Bits Deep
RR9 WR9 Mirror, If WR7’ bit D6 Equals 1
RR10 Miscellaneous Status Bits
RR11 WR11 Mirror, if WR7’ bit D6 Equals 1
RR12 Lower Byte of BRG Time Constant
RR13 Upper Byte of BRG Time Constant
RR14 WR14 Mirror, if WR7’ bit D6 Equals 1
RR15 WR 15 Mirror, if WR7’ bit D6 Equals 1
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
12
register. Status information for both channels resides in one register. Only 1 register may
be read. Depending on its contents, the CPU performs one of the 3 operations listed below:
1. Write data
2. Read data
3. Continues processing
Two bits in the register indicate the requirement for data transfer.
INTERRUPT
The ESCC INTERRUPT mode supports vectored and nested interrupts. The fill levels at
which the transmit and receive FIFOs interrupt the CPU are programmable, allowing the
ESCC requests for data transfer to be tuned to the system interrupt response time.
Nested interrupts are supported with the interrupt acknowledge (INTACK) feature of the
ESCC. It allows the CPU to acknowledge the occurrence of an interrupt, and re-enable
higher priority interrupts. Since an INTACK cycle releases the INT pin from the active
state, a higher priority ESCC interrupt or another higher priority device can interrupt the
CPU. When an ESCC responds to INTACK signal from the CPU, it can place an interrupt
vector on the data bus. This vector is written in WR2 and may be read in RR2. To increase
the interrupt response time, the ESCC can modify 3 bits in this vector to indicate status. If
the vector is read in Channel A, status is not included. If it is read in Channel B, status is
included.
Each of the six sources of interrupts in the ESCC (Transmit, Receive, and External/Status
interrupts in both channels) has 3 bits associated with the interrupt source as listed below:
1. Interrupt Pending (IP)
2. Interrupt Under Service (IUS)
3. Interrupt Enable (IE)
If the IE bit is set for a given interrupt source, then that source can request interrupts.
However, when the Master Interrupt Enable (MIE) bit in WR9 is reset, no interrupts can
be requested. The IE bits are write-only. The other two bits are related to the interrupt pri-
ority chain (see Figure 7 on page 13). The ESCC can request an interrupt only when no
higher priority device is requesting an interrupt (that is, when IEI is High). If the device in
question requests an interrupt, it pulls down INT. The CPU then responds with INTACK,
and the interrupting device places a vector on the data bus.
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
13
Figure 7. ESCC Interrupt Priority Schedule
The ESCC can also execute an Interrupt Acknowledge cycle using software. Sometimes it
is difficult to create the INTACK signal with the necessary timing to acknowledge inter-
rupts and allow the nesting of interrupts. In such cases, interrupts can be acknowledged
with a software command to the ESCC. For more information, Z80230/Z85230 Enhance-
ments on page 22
Interrupt Pending (IP) bits signal a need for interrupt servicing. When an IP bit is 1 and the
IEI input is High, the INT output is pulled Low, requesting an interrupt. In the ESCC, if an
IE bit is not set, then the IP for that source is never set. The IP bits are read in RR3A.
The Interrupt Under Service (IUS) bits signal that an interrupt request is being serviced. If
IUS is set to 1, all interrupt sources of low priority in the ESCC and external to the ESCC
are prevented from requesting interrupts. The internal interrupt sources are inhibited by
the state of the internal daisy chain, while lower priority devices are inhibited by setting
IEO Low for subsequent peripherals. An IUS bit is set during an Interrupt Acknowledge
cycle if there are no higher priority devices requesting interrupt.
There are 3 type of interrupts as listed below:
1. Transmit
2. Receive
3. External/Status
Each interrupt type is enabled under program control with Channel A having higher prior-
ity than Channel B, and with Transmit, Receive, and External/Status interrupts prioritized
in that order within each channel. When the Transmit interrupt is enabled (WR1 bit 1 is 1),
the occurrence of the interrupt depends on the state of WR7’ bit 5. If WR7’ bit 5 is 0, the
CPU is interrupted when the top byte of the transmit FIFO becomes empty. If WR7’ bit 5
is 1, the CPU is interrupted when the transmit FIFO becomes completely empty. The
transmit interrupt occurs when the data in the exit location of the Transmit FIFO loads into
the Transmit Shift Register and the Transmit FIFO becomes completely empty. This con-
dition means that there must be at least one character written to the Tx FIFO for it to
become empty.
Peripheral Peripheral Peripheral
IEI A7–A0INT INTACKIEO IEI A7–A0 INT INTACK IEO IEI A7–A0INT INTACK
+5V
A7–A0
INT
INTACK
+5V
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
14
When the receiver is enabled, the CPU is interrupted in one of the following 3 methods:
1. Interrupt on First Receive Character or Special Receive Condition
2. Interrupt on All Receive Characters or Special Receive Conditions
3. Interrupt on Special Receive Conditions Only
If WR7’ bit 3 is 1, and the Special Receive Condition is selected, the Receive character
occurs when there are four bytes available in the Receive FIFO. This is most useful in syn-
chronous applications as the data is in consecutive bytes. Interrupt on First Character or
Special Condition and Interrupt on Special Condition Only are typically used with the
BLOCK TRANSFER mode. A special Receive Condition consists of one of the follow-
ing:
•
Receiver Overrun
•
Framing error in ASYNCHRONOUS mode
•
EOF in SDLC mode
•
Parity error (optional)
The Special Receive Condition interrupt is different from an ordinary receive character
available interrupt only by the status placed in the vector during the Interrupt Acknowl-
edge cycle. In Receive Interrupt on First Character or Special Condition mode, an inter-
rupt occurs from Special Receive Conditions any time after the first receive character
interrupt.
The primary function of the External/Status interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins. However, an External/Status interrupt is also caused by
any of the following:
•
A Transmit Underrun condition
•
A zero count in the BRG
•
A detection of a Break (ASYNCHRONOUS mode)
•
An ABORT (SDLC mode)
•
An End Of Poll (EOP) sequence in the data stream (SDLC LOOP mode)
The interrupt caused by the ABORT or EOP sequence has a special feature that allows the
ESCC to interrupt when the ABORT or EOP sequence is detected or terminated. This fea-
ture facilitates the proper termination of the current message, correct initialization of the
next message, and the accurate timing of the ABORT condition by external logic in SDLC
mode. SDLC LOOP mode allows secondary stations to recognize the primary station and
regain control of the loop during a poll sequence.
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
15
CPU/DMA BLOCK TRANSFER
The ESCC provides a BLOCK TRANSFER mode to accommodate CPU/DMA controller.
The BLOCK TRANSFER mode uses the WAIT/REQUEST output in conjunction with the
WA I T /REQUEST bits in WR1. The WAIT/REQUEST output can be defined as a WAIT
line in the CPU BLOCK TRANSFER mode or as a REQUEST line in the DMA BLOCK
TRANSFER mode.
To a DMA controller, the ESCC REQUEST output indicates that the ESCC is ready to
transfer data to or from memory.
To the CPU, the WAIT line indicates that the ESCC is not ready to transfer data, thereby
requesting the CPU to extend the I/O cycle.
The DTR/REQUEST line allows full-duplex operation under DMA control. The ESCC
can be programmed to deassert the DTR/REQUEST pin with the same timing as the
WA I T /REQUEST pin if WR7’ bit 4 is 1.
ESCC Data Communications Capabilities
The ESCC provides two independent full-duplex programmable channels for use in any
common ASYNCHRONOUS or SYNCHRONOUS data communication protocols (see
Figure 8). The channels have identical features and capabilities.
Figure 8. Various ESCC Protocols
Marking Line
Start Parity
Stop
Data
Asynchronous
SYNC
CRC1
CRC2
Monosync
Bisync
Signal
Flag Address Control Information Flag
CRC2
CRC2
CRC2
CRC1
CRC1
CRC1
SYNC
SYNC
Data Data
Data Data
DataData
Data Data
Marking Line
External Sync
SDLC/HDLC/X.25
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
16
ASYNCHRONOUS Mode
The ESCC has significant improvements over the standard Serial Communications Con-
troller (SCC). The addition of the deeper data FIFOs provide greater protection against
underruns and overruns as well as more efficient use of bus bandwidth. The deeper data
FIFOs are accessible regardless of the protocol used and they need not be enabled. For
information on these improvements, Z80230/Z85230 Enhancements on page 22
Send and Receive allow 5 to 8 bits per character, plus optional Even or Odd parity. The
transmitters can supply 1, one-and-a-half, or 2 stop bits per character and can provide
break indication. The receiver break-detection logic interrupts the CPU both at the start
and at the end of a received break. Reception is protected from spikes by start-bit valida-
tion that delays the signal for a length of time equal to one half the time period required to
process one bit of data after a Low level is detected on the receive data input (RxDA or
RxDB pins). If the Low level does not persist (that is, a transient), the character assembly
process does not start.
Framing errors and overrun errors are detected and buffered together with the character at
which they occur. Vectored interrupts allow fast servicing of error conditions. Further-
more, a built-in checking process avoids the interpretation of a framing error as a new start
bit. A framing error results in the addition of a delay of one half the amount of time
required to process one bit of data at the point at which the search for the next start bit
begins. Transmit and Receive clock can be selected from any of the several sources. In
ASYNCHRONOUS mode, the SYNC pin may be programmed as an input with interrupt
capability.
SYNCHRONOUS Mode
The ESCC supports both byte-oriented and bit-oriented SYNCHRONOUS communica-
tion. SYNCHRONOUS byte-oriented protocols are handled in several modes. They
enable character synchronization with a 6- or 8-bit SYNC character (MONOSYNC) or a
12-bit or 16-bit synchronization pattern (BISYNC), or with an external sync signal. Lead-
ing sync characters are removed without interrupting the CPU.
5- or 7-bit sync characters are detected from 8- or 16-bit patterns in the ESCC by overlap-
ping the larger pattern across multiple incoming sync characters as displayed in Figure 9.
Figure 9. Detecting 5- or 7-Bit Synchronous Characters
SYNC DataSYNC SYNC Data Data Data
5 Bits
8
16
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
17
CRC checking for SYNCHRONOUS BYTE-ORIENTED mode is delayed by one charac-
ter time so that the CPU may disable CRC checking on specific characters. This action
permits the implementation of protocols such as IBM BISYNC.
Both CRC-16 (X16 + X15 + X2 + 1) and CRC-CCITT (X16 + X12 + X5 + 1) error checking
polynomials are supported. Either polynomial may be selected in all synchronous modes.
You can preset the CRC generator and checker to all 1s or all 0s. The ESCC also provides
a feature that automatically transmits CRC data when no other data is available for trans-
mission. This feature enables high-speed transmissions under DMA control, with no need
for CPU intervention at the end of a message. When there is no data or CRC to send in the
SYNCHRONOUS mode, the transmitter inserts 6-, 8-, 12-, or 16-bit SYNC characters,
regardless of the programmed character length.
SDLC Mode
The ESCC supports SYNCHRONOUS bit-oriented protocols, such as SDLC and
High-Level Data Link Control (HDLC), by performing automatic flag sending, zero inser-
tion and CRC generation.
A special command is used to abort a frame which is in transmission. At the end of a mes-
sage, the ESCC automatically transmits the CRC and trailing flag when the transmitter
underruns. The transmitter may also be programmed to send an idle line consisting of con-
tinuous flag characters or a steady marking condition.
If a transmit underrun occurs in the middle of a message, an External/Status interrupt
warns the CPU of this status change so that an Abort command can be issued. The ESCC
may also be programmed to send an Abort command by itself, in the event of an
underrun, relieving the CPU of the task. The last character of a frame may consist of 1- to
8-bits, allowing reception of frames of any length.
The receiver automatically synchronizes on the leading flag of a frame in SDLC or HDLC
and provides a synchronization signal on the SYNC pin (an interrupt may also be pro-
grammed). The receiver may search for frames addressed by 1-byte or 4-bits within a byte
of a user-specified address or for a global broadcast address. Frames not matching either
the user-selected address or broadcast address are ignored.
The number of address bytes are extended under software control. To receive data, an
interrupt can be selected on the first received character, or on every character, or On Spe-
cial Condition Only (EOF). The receiver automatically deletes all zeros inserted by the
transmitter during character assembly. CRC is also calculated and is automatically
checked to validate frame transmission. At the end of transmission, the status of a received
frame is available in the status registers. In SDLC mode, the ESCC must be programmed
to use the CRC-CCITT polynomial, but the generator and checker may be pre-set to all 1s
or all 0s. The CRC data is inverted before transmission and the receiver checks against the
bit pattern 0001110100001111.
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
18
NRZ, NRZI, or FM coding may be used in any 1X mode. The parity options available in
ASYNCHRONOUS mode are also available in SYNCHRONOUS mode. However, parity
checking is not normally used for SDLC because CRC checking is more robust.
SDLC LOOP Mode
The ESCC supports SDLC LOOP mode as well as normal SDLC. In SDLC LOOP mode,
a primary controller station manages the message traffic flow on the loop and any number
of secondary stations. In SDLC LOOP mode, the ESCC performs the functions of a sec-
ondary station. An ESCC operation in regular SDLC mode may act as a controller (see
Figure 10). SDLC LOOP mode is selected by setting WR10 bit 1 to 1.
Figure 10. SDLC LOOP mode
A secondary station in an SDLC LOOP mode always monitors the messages sent around
the loop and passes these messages to the rest of the loop, retransmitting them with a one-
bit time delay. The secondary station places its own message in the loop only at specific
times. The controller indicates that the secondary stations can transmit messages by send-
ing a special character, called EOP, around the loop. The EOP character has a bit pattern
11111110, the same pattern as an Abort character in normal HDLC. This bit pattern is
unique and easily recognized, because of the zero insertion in the message.
When a secondary station has a message to transmit and recognizes an EOP on the line, it
changes the last binary 1 of the EOP to a 0 before transmission. This action changes the
EOP into a flag sequence. The secondary station now places its message on the loop and
terminates the message with an EOP. Any secondary stations further down the loop with
messages to transmit appends their messages to the message of the first secondary station
using the same process. Secondary stations without any messages to transmit merely echo
the incoming message. All secondary stations are prohibited from placing messages on the
loop except upon recognizing an EOP. In SDLC LOOP mode, NRZ, NRZI or FM coding
can be used.
Controller
Secondary #1
Secondary #2 Secondary #3
Secondary #4
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
19
SDLC Status FIFO
The ESCC’s ability to receive high speed back-to-back SDLC frames is maximized by a
10-bit deep by 19-bit wide status FIFO buffer. When enabled (through WR15 bit 2 is 1),
the storage area enables DMA to continue data transfer into the memory so that the CPU
examines the message later. For each SDLC frame, 14 counter bits and 5 Status/Error bits
are stored. The byte count and status bits are accessed through Read Registers, RR6 and
RR7. RR6 and RR7 are only used when the SDLC FIFO buffer is enabled. The 10 x 19
status FIFO buffer is separate from the 8-byte receive data FIFO buffer.
Baud Rate Generator
Each channel in the ESCC contains a programmable BRG. Each generator consists of two
8-bit registers that form a 16-bit time constant, a 16-bit down counter, and a flip-flop on
the output, producing a square wave. At start-up, the flip-flop at the output is set High, the
value in the time constant register is loaded into the counter, and the count down begins.
When the BRG reaches zero, the output toggles, the counter is reloaded with the time con-
stant, and the process repeats. The time constant can be changed at any time, but the new
value does not take effect until the counter is loaded again.
The output of the BRG may be used as the Transmit clock, the Receive clock, or both. The
output can also drive the DPLL. For more information, Digital Phase-Locked Loop on
page 19.
If the receive clock or the transmit clock is not programmed to come from the TRxC pin,
the output of the BRG may be echoed out by the TRxC pin.
The following formula relates the time constant to the baud rate. PCLK or RTxC is the
clock input to the BRG. The clock mode is 1, 16, 32, or 64, as selected in WR 4 bits 6 and
7.
Digital Phase-Locked Loop
The ESCC contains a DPLL to recover clock information from a data stream with NRZI or
FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM)
times the data rate. The DPLL uses this clock, along with the data stream, to construct a
clock for the data. This clock is then used as the ESCC receive clock, the transmit clock,
or both. When the DPLL is selected as the transmit clock source, it provides a jitter-free
clock output. The clock output is the DPLL input frequency divided by the appropriate
divisor for the selected encoding technique.
For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the
32x clock is counted, the DPLL searches the incoming data stream for edges (either 1 to 0
or 0 to 1). When a transition is detected the DPLL makes a count adjustment (during the
next counting cycle), producing a terminal count closer to the center of the bit cell.
PCLK or RTxC Frequency
Time Constant = 2(Baud Rate) (Clock Mode) -2
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
20
For FM encoding, the DPLL counts from 0 to 32, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock edges in the data stream occurs between
counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a
time centered on the 15 to 16 counting transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input or
the output of the BRG. The DPLL output is programmed to be echoed out the ESCC by the
TRxC pin (if this pin is not being used as an input).
Data Encoding
Data encoding allows the transmission of clock and data information over the same
medium. This capability saves the need to transmit clock and data over separate medium
as is normally required tor synchronous data. The ESCC provides four different data
encoding methods, selected by bits 6 and 5 in WR10. Examples of these 4 encoding meth-
ods is illustrated in Figure 11. Any encoding method is used in any X1 mode in the ESCC,
ASYNCHRONOUS or SYNCHRONOUS. The data encoding selected is active even if
the transmitter or receiver is idling or disabled.
Figure 11. Data Encoding Methods
Table 3 describes the four encoding methods, their levels, and values.
Table 3. Data Encoding Descriptions
Code Type Level Value
NRZ High
Low
1
0
NRZI No Change
Change
1
0
Data
NRZ
NRZI
FM1
FM0
110010
PS005303-0907 Functional Description
Z85230/Z80230
Product Specification
21
In addition to the 4 methods, ESCC can be used to decode Manchester (biphase level) data
using DPLL in the FM mode and programming the receiver for NRZ data. Manchester
encoding always produces a transition at the center of the bit cell. If the transition is 0 to 1,
the bit is a 0. If the transition is 1 to 0, the bit is a 1.
Auto Echo and Local Loopback
The ESCC is capable of automatically echoing everything it receives. This feature is use-
ful mainly in ASYNCHRONOUS modes, but works in SYNCHRONOUS and SDLC
modes as well. AUTO ECHO mode (TxD is RxD) is used with NRZI or FM encoding
with an additional delay because the data stream is not decoded before retransmission. In
AUTO ECHO mode, the CTS input is ignored as a transmitter enable, (although transi-
tions for this input can cause interrupts if programmed to do so). In this mode, the trans-
mitter is actually bypassed and the programmer is responsible for disabling transmitter
interrupts and Wait/Request on transmit.
The ESCC is also capable of LOCAL LOOPBACK. In this mode the internal transmit
data is tied to the internal receive data and RxD is ignored. The CTS and DCD inputs are
also ignored as transmit and receive enables. However, transitions on these inputs can
cause interrupts. LOCAL LOOPBACK works in ASYNCHRONOUS, SYNCHRO-
NOUS, and SDLC modes with NRZ, NRZI or FM coding of the data stream.
FM1 (biphase mark) Additional Transition at the Center of the Bit Cell
No Additional Transition at the Center of the Bit
Cell
1
0
FM0 (biphase
space)
A transition occurs at the beginning of every bit
call. A 0 is represented by an additional transition
at the center of the bit cell.
A 1 is represented by no additional transition at
the center of the bit cell.
0
1
Table 3. Data Encoding Descriptions (Continued)
Code Type Level Value
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
22
Z80230/Z85230 Enhancements
A detailed description of the enhancements to the Z80230/Z85230 ESCC that differentiate
it from the standard SCC is provided below:
4-Byte Transmit FIFO Buffer
The ESCC has a 4-byte transmit buffer with programmable interrupt and DMA request
levels. It is not necessary to enable the FIFO buffer as it is always available. You can set
the Transmit Buffer Empty (TBE) interrupt and DMA Request on Transmit command to
be generated either when the top byte of transmit FIFO is empty or only when the FIFO is
completely empty. A hardware or channel reset clears the transmit shift register, flushes
the transmit FIFO, and sets WR7’ bit 5 to 1.
If the transmitter generates the interrupt or DMA request for data when the top byte of the
FIFO is empty (WR7’ bit 5 is 0), the system allows for a long response time to the data
request without underflowing. The interrupt service routine (ISR) writes one byte and then
tests RR0 bit 2. The DMA Request on Transmit in this mode is set to 0 after each data
Write (that is, TBE), RR0 bit 2, is set to 1 when the top byte of the FIFO is empty. WR7’
bit 5 resets to 1.
In applications for which the interrupt frequency is important, the transmit ISR can be
optimized by programming the ESCC to generate the TBE interrupt only when the FIFO is
completely empty (WR7’ bit 5 is 1) and, writing four bytes to fill the FIFO. When WR7’
bit 5 is 1, only one DMA request is generated, filling the bottom of the FIFO. However,
this may be advantageous for applications where the possible reassertion of the DMA
request is not required. The TBE status bit, RR0 bit 2, is set to 1 when the top byte of the
FIFO is empty. WR7’ bit 5 is set to1 after a hardware or channel reset.
8-Byte Receive FIFO
The ESCC has an 8-byte receive FIFO with programmable interrupt levels. It is not neces-
sary to enable the 8-byte FIFO as it is always available. A hardware or channel reset clears
the Receive Shift register and flushes the Receive FIFO. The Receive Character Available
interrupt is generated as selected by WR7’ bit 3. The Receive Character Available bit,
RR0 bit 0 is set to 1 when at least one byte is available at the top of the FIFO (independent
of WR7’ bit 3).
A DMA Request on Receive, if enabled, is generated whenever one byte is available in the
receive FIFO independent of WR7’ bit 3. If more than one byte is available in the FIFO,
the Wait/Request pin becomes inactive and becomes active when the FIFO is emptied.
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
23
By resetting WR7’ bit 3 to 0, applications which have a long latency to interrupts can gen-
erate the request to read data from the FIFO when one byte is available. The application
can then test the Receive Character Available bit to determine if more data is available.
By setting WR7’ bit 3 to 0, the ESCC can issue an interrupt when the receive FIFO is half
full (4 bytes available), allowing the frequency of interrupts to be reduced. If WR7’ bit 3 is
1, the Receive Character Available interrupt is generated when there are four bytes avail-
able. If the ISR reads four bytes during each routine, the frequency of interrupts is
reduced.
If WR7’ bit 3 is 1 and Receive Interrupt on All Characters and Special Conditions is
enabled, the receive character available interrupt is generated when four characters are
available. However, when a character is detected to have a special condition, an interrupt
is generated when the character is loaded into the top four bytes of the FIFO. Therefore,
the Special Condition ISR must be RR1 before reading the data to determine which byte
has the special condition.
Write Register 7 PRIME (WR7’)
A new register, WR7’, has been added to the ESCC to enable the programming of six new
features. The format of this register is represented in Table 4.
Table 4. Write Register 7 Prime (WR7’)
Bit 7 6 5 4 3 2 1 0
R/W WWW/W W WWW
Reset 0000 0 000
Note: R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 W 0 Reserved, must be 0
6 W Extended Read Enable
5 W Transmit FIFO Int Level
4W DTR
/REQ Timing Mode
3 W Receive FIFO Int Level
2 W Auto RTS Deactivation
1 W Auto EOM Reset
0 W Auto Transmit Flag
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
24
WR7’ is written by first setting Bit 0 of Write Register 15 (WR15 bit 0) to 1 and then
accessing WR7. All write commands to register 7 are to WR7’ while WR15 bit 0 is set to
1. WR15 bit 0 must be reset to 0 to address the SYNC character in register WR7. If bit 6 of
WR7’ is set to 1, then WR7’ can be read by performing a read cycle to RR14. The WR7’
features remain enabled until specifically disabled or by a hardware or software reset. Bit
5 is set to 1 and all other bits are reset to 0 after a reset.
For applications which use either the Zilog Z8X30SCC or Z80230, these two device types
can be identified in software with the following test:
1. Write 01H to Write Register 15
2. Read Register 15
If bit 0 is set to 0, the device is Z8X30SCC. If bit 0 is set to 1, it is a Z80C30. If the device
is Z8XC30, a write to WR15 is required before proceeding. If the device is Z80230, all
writes to address 7 are to WR7’ until WR15 is set to 0.
The WR7 register bits are described below:
Bit 7 (Not used)
This bit must always be 0.
Bit 6 (Extended Read Enable)
Setting this bit to 1 enables WR3, WR4, WR5, WR7’ and WR10 to be read by issuing a
READ command for RR9 (WR3) RR4, RR5, RR14 (WR7’) and RR11 (WR10), respec-
tively.
Bit 5 (Transmit FIFO Interrupt Level)
If this bit is set to 1, the TBE interrupt is generated when the transmit FIFO is completely
empty. If this bit is set to 0, the TBE interrupt is generated when the top byte of the trans-
mit FIFO is empty. This bit is set following a hardware or channel reset.
In DMA REQUEST ON TRANSMIT mode, when using either the W/REQ or DTR/REQ
pins, the request is asserted when the Tx FIFO is completely empty if WR7’ bit 5 is set to
1. The request is asserted when the top byte of the FIFO is empty if bit 5 is reset.
Bit 4 (DTR/REQ Timing)
If this bit is set to 1 and the DTR/REQ pin is used for REQUEST mode (WR14 bit 2 is 1),
the deactivation of the DTR/REQ pin is identical to the W/REQ pin as illustrated in
Figure 12 on page 25. If this bit is reset, the deactivation time is 4TcPc.
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
25
Figure 12. DMA Request on Transmit Deactivation Timing
Bit 3 (Receive FIFO Interrupt Level)
This bit sets the interrupt level of the receive FIFO. If this bit is set to 1, the receive data
available bit is asserted when the receive FIFO is half full (4 bytes available). If this bit is
reset to 0, the Receive Data Available interrupt is requested when all bytes are set. For
more information, see 8-Byte Receive FIFO on page 22.
Bit 2 (Automatic RTS Pin Deassertion)
This bit controls the timing of the deassertion of the RTS pin in SDLC mode. If this bit is
1 and WR5 bit 1 is set to 0 during the transmission of an SDLC frame, the deassertion of
the RTS pin is delayed until the last bit of the closing flag clears the TxD pin. The RTS pin
is pulled High after the rising edge of the transmit clock cycle from the last bit of the clos-
ing flag. This action implies that the ESCC must be programmed for Flag on Underrun
(WR10 bit 2 is 0) for the RTS pin to deassert at the end of the frame. This feature works
independently of the programmed Transmitter Idle state. In SYNCHRONOUS mode other
than SDLC, the RTS pin immediately follows the state programmed into WR5 bit 1. When
WR7’ bit 2 is set to 0, the RTS follows the state of WR5 bit 1.
Bit 1 (Automatic EOM Reset)
If this bit is 1, the ESCC automatically resets the Tx Underrun/EOM latch and presets the
transmit CRC generator to its programmed preset state (per values set in WR5 bit 2 and
WR10 bit 7). Therefore, it is not necessary to issue the Reset Tx Underrun/EOM Latch
command when this feature is enabled.
Bit 0 (Automatic Tx SDLC Flag)
If this bit is 1, the ESCC automatically transmits an SDLC flag before transmitting data.
This action removes the requirement to reset the Mark Idle bit (WR10 bit 3) before writing
data to the transmitter.
WR
D7–D0
DTR/REQ
WAIT/REQ
Transmit Data
WR7 bit 4 =1
WR7 bit 4 = 0
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
26
Historically, the SCC latched the databus on the falling edge of WR. However, as many
CPUs do not guarantee that the databus is valid when the WR pin goes Low, Zilog modi-
fied the databus timing to allow a maximum delay of 20 nS from the WR signal going
active Low to the latching of the databus.
CRC Reception in SDLC Mode
In SDLC mode, the entire CRC is clocked into the receive FIFO. The ESCC completes
clocking in the CRC to allow it to be retransmitted or manipulated software. In the SCC,
when the closing flag is recognized, the contents of the receive shift register are immedi-
ately transferred to the receive FIFO, resulting in the loss of the last two bits of the CRC.
In the ESCC, it is not necessary to program this feature. When the closing flag is detected,
the last two bits of the CRC are transferred into the receive FIFO. In all other
SYNCHRONOUS mode, the ESCC does not clock in the last two CRC bits (same as the
SCC).
TxD Forced High in SDLC with NRZI Encoding When Marking Idle
When the ESCC is programmed for SDLC mode with NRZI data encoding and Mark Idle
(WR10 bit 6 is 0, bit 5 is 1, bit 3 is 1), the TxD pin is automatically forced High when the
transmitter enters the Mark Idle state. There are several different ways for the transmitter
to enter the Idle state. In each of the following cases the TxD pin is forced High when the
Mark Idle condition is reached:
•
Data, CRC, flag, and Idle
•
Data, flag, and Idle
•
Data, abort (on underrun), and Idle
•
Data, abort (command), and Idle
•
Idle flag and command to Idle Mark
The Force High feature is disabled when the Mark Idle bit is set to 0.
This feature is used in combination with the automatic SDLC opening flag transmission
feature, WR7’ bit 0 is 1, to assure that data packets are formatted correctly. In this case, the
CPU is not required to issue any commands. If WR7’ bit 0 is 0, as on the SCC, the Mark
Idle bit (WR10 bit 3), is set to 1, to enable flag transmission before an SDLC packet trans-
mits.
Improved Transmit Interrupt Handling
The ESCC latches the TBE interrupt because the CRC is loaded into the Transmit Shift
register even if the TBE interrupt, due at the last data byte, has not been reset. The end of a
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
27
synchronous frame is guaranteed to generate two TBE interrupts even if a Reset Transmit
Buffer Interrupt command for the data created interrupt is issued after the CRC interrupt
occurs (Time A in Figure 13). Two Reset TBE commands are required. The TxIP latches
if the EOM latch resets before the end of the frame.
Figure 13. TxIP Latching
DPLL Counter Tx Clock Source
When the DPLL is selected as the transmit clock source, the DPLL counter output is the
DPLL source clock divided by the appropriate divisor for the programmed data encoding
format. In FM mode (FM0 or FM1), the DPLL counter output signal is the input frequency
divided by 16.
In NRZI mode, the DPLL counter output signal is the input clock cycle divided by 32.
This feature provides a jitter-free output signal that replaces the DPLL transmit clock out-
put as the transmit clock source. This action has no effect on the use of the DPLL as the
receive clock source (see Figure 14).
Figure 14. DPLL Outputs
Read Register 0 Status Latched During Read Cycle
The contents of Read Register 0, RR0 is latched during a Read operation. The ESCC pre-
vents the contents of RR0 from changing during a Read operation. But, the SCC allows
the status of RR0 to change while reading the register and may require reading RR0 twice.
The contents of RR0 is updated after the rising edge of RD signal.
Data Data CRC1 CRC2 Flag
TxBE
TxIP Bit
TxIP 1 TxIP 2
Time A
DPLL CLK DPLL DPLL Output to Receiver
DPLL Counter DPLL Output to Transmitter
Input Frequency Divided by 16 (FM0 or FM1)
Input Clock Cycle Divided by 32 for NRZI
Input
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
28
Software Interrupt Acknowledge
The Z80230/Z85230 interrupt acknowledge cycle can be initiated using software. If Write
Register 9 (WR9 bit 5 is 1), Read Register 2 (RR2) results in an interrupt INTACK cycle,
a software acknowledgment causes the INT pin to go High. The IEO pin goes Low. The
Interrupt Under Service (IUS) latch is set to the highest priority pending interrupt.
When a hardware INTACK signal is desired, a software acknowledge cycle requires that a
Reset Highest IUS command be issued in the ISR. If RR2 is read from Channel A, the
unmodified vector is returned. If RR2 is read from Channel B, then the vector is modified
to indicate the source of the interrupt. The Vector Includes Status (VIS) and No Vector
(NV) bits in WR9 are ignored when WR9 bit 5 is set to 1.
If the INTACK and IEI pins are not used, they are pulled up to VCC through a resistor
(2.2 k?, typical).
Fast SDLC Transmit Data Interrupt Response
To more easily facilitate the transmission of back-to-back SDLC frames with a single
shared flag between frames, the ESCC allows data for a second frame to be written to the
transmit FIFO after the Tx Underrun/EOM interrupt occurs. This feature allows applica-
tion software more time to write the data to the transmitter while allowing the current
frame to conclude with CRC and flag. The SCC required that data not be written to the
transmitter until a TBE interrupt is generated after the CRC completed transmission.
If data is written to the transmit FIFO after the Transmit Underrun/EOM interrupt is issued
but before the TBE interrupt is issued, the Automatic EOM Reset function is enabled
(WR7’ bit 1 is 1). Consequently, the commands Reset Tx/Underrun EOM Latch and Reset
Tx CRC Generator must never be used.
SDLC FIFO Frame Status Enhancement
When used with a DMA controller, the ESCC SDLC Frame Status FIFO enhancement
maximizes the ESCC’s ability to receive high-speed, back-to-back SDLC messages. It
minimizes frame overruns due to CPU latencies in responding to interrupts. The feature
(illustrated in Figure 15) includes a:
•
10-bit deep by 19-bit wide status FIFO
•
14-bit receive byte counter
•
Control logic
The 10 x 19 bits status FIFO is separate from the 8-byte receive data FIFO.
When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for
the SDLC frame are stored in the 10- x 19-bit status FIFO. This action allows the DMA
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
29
controller to transfer the next frame into memory while the CPU verifies the previously
received frame.
Figure 15. SDLC Frame Status FIFO
1. All Sent bypasses MUX and equals contents of SCC Status Register.
2. Parity bits bypass MUX and equals contents of SCC Status Register.
3. EOF is set to 1 whenever reading from the FIFO.
Summarizing the operation: data is received, assembled, and loaded into the 8-byte FIFO
before transferring to memory by the DMA controller.
Interface
to SCC
2 Bits 6 Bits
RR1 Bit Bit
6Bits
5-0 RR6
6-Bit MUX
5 Bits EOF=1 6 Bits
7
FIFO Array
10- by 19- Bits
5 Bits 14 Bits
8 Bits
RR1
SCC Status Register
Residue Bits (3)
Overrun, CRC Error
Byte Counter
Frame Status FIFO Circuitry
Reset on Flag Detect
Increment on
Each Received Character
Enable Count in SDLC
EOF Signal
Status Read Complete
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
4-Bit Comparator
Over Equal
EN
FIFO
Enable
WR15 Bit 2
Set Enables
Status FIFO
RR7 5 - 0 + RR6 7-0
14-Bit Byte Counter
(16 KB Maximum Count)
RR7 Bit 7
FIFO data-available status bit
(1 during read)
RR7 Bit 7
FIFO Overflow Status Bit
(1 on overflow)
See Notes:, next.
Notes:
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
30
When a flag is received at the end of an SDLC frame, the frame byte count from the 14-bit
counter and five status bits are loaded into the status FIFO for verification by the CPU.
The CRC checker is automatically reset in preparation for the next frame, which starts
immediately.
Because the byte count and status are saved for each frame, the message integrity can be
verified at a later time. Status information for up to 10 frames is stored before a status
FIFO overrun occurs.
If a frame is terminated with an Abort command, the byte count and status is loaded to
the status FIFO and the counter is reset for the next frame.
FIFO Enable/Disable
This FIFO buffer is enabled when WR15 bit 2 is 1 and the ESCC is in the SDLC/HDLC
mode. Otherwise, the status register contents bypass the FIFO and transfer directly to the
bus interface (the FIFO pointer logic is reset either when disabled or by a channel or
power-on reset). When the FIFO mode is disabled, the ESCC is downward-compatible
with the NMOS Z8030/Z8530. The FIFO mode is disabled on power-up (WR15 bit 2 set
to 0 on reset). The effects of backward compatibility on the register set are that RR4 is an
image of RR0, RR5 is an image of RR1, RR6 is an image of RR2 and RR7 is an image of
RR3. For information on the added registers, see Read Registers on page 53. The status of
the FIFO Enable signal is read at RR15 bit 2. If the FIFO is enabled, the bit is set to 1; oth-
erwise it is reset to 0.
FIFO Read Operation
When WR15 bit 2 is 1 and the FIFO is not empty, the next read status register RR1 or the
additional registers RR7 and RR6, reads the FIFO. Reading status register RR1 causes one
location of the FIFO to empty, so status is read after reading the byte count; otherwise the
count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer
is switched to allow status to read directly from the status register. In this state, reads from
RR7 and RR6 are undefined bit 6 of RR7 (FIFO Data Available) status data is coming
from the FIFO or directly from the status register, because it is set to 1 whenever the FIFO
is not empty.
Since all status bits are not stored in the FIFO, the All Sent, Parity, and EOF bits bypass
the FIFO. The status bits sent through the FIFO are the three Residue Bits, Overrun, and
CRC Error.
The correct sequence for polling the byte count and FIFO logic is RR7, RR6, then RR1
(reading RR6 is optional). Additional logic prevents the FIFO from emptying by multiple
reads from RR1. The read from RR7 latches the FIFO empty/full status bit (bit 6) and
steers the status multiplexer to read the ESCC megacell instead of the status FIFO
PS005303-0907 Z80230/Z85230 Enhancements
Z85230/Z80230
Product Specification
31
(because the status FIFO is empty). The read from RR1 allows an entry to be read from the
FIFO (if the FIFO is empty, the logic prevents a FIFO underflow condition).
FIFO Write Operation
When the end of an SDLC frame is received and the Status FIFO is enabled, the contents
of the status and byte-count registers load into the FIFO. The EOF signal increments the
FIFO. If the FIFO overflows, the RR7 bit 7 (FIFO overflow) is set, indicating the over-
flow. This bit and the FIFO control logic is reset by disabling and re-enabling the FIFO
control bit (WR15 bit 2). For details about FIFO control timing during an SDLC frame,
see Figure 16.
Figure 16. SDLC Byte Counting Detail
SDLC Status FIFO Anti-Lock Feature
When the Frame Status FIFO is enabled and the ESCC is programmed for Special Receive
Condition Only (WR1 bit 4 = bit 3=1), the data FIFO is not locked when a character with
EOF status is read.When EOF status is at the top of the FIFO, an interrupt with a vector
for receive data is generated. The command Reset Highest IUS must be issued at the
end of the ISR regardless of whether an Interrupt Acknowledge cycle was executed (hard-
ware or software).
This action allows the DMA to complete the transfer of the received frame to memory,
then interrupt the CPU that a frame was completed, without locking the FIFO. Because in
the RECEIVE INTERRUPT ON SPECIAL CONDITION ONLY mode the interrupt vec-
tor for receive data is not used, it indicates that the last byte of a frame has been read from
the receive FIFO. Reading the frame status (CRC, byte count and other status stored in the
status FIFO) determines that EOF is not required.
When a character with a special receive condition other than EOF is received (receiver
overrun or parity), a special receive condition interrupt is generated after the character is
read from the FIFO and the receive FIFO is locked until the Error Reset command is
issued.
0123 5674 0123 56740
FADD DCDFADD DCCDF
Do not load
counter on
first flag.
reset byte
counter here
Internal byte strobe
increments counter
Reset byte
counter, then
load counter
into FIFO and
increment PTR.
Internal byte strobe
increments counter
Reset byte
counter, then
load counter
into FIFO and
increment PT
R
F
C
PS005303-0907 Programming
Z85230/Z80230
Product Specification
32
Programming
The ESCC contains write registers in each channel that are programmed by the system
separately to configure the function of each channel.
In the Z85230 ESCC, the data FIFOs are directly accessible by selecting a High on the
D/C pin. Except WR0 and RR0, programming the write registers requires two write oper-
ations and reading a read register requires a write and a read operation. The first Write is to
WR0 which contains bits that point to the selected register. If the next operation is a Write
the selected write register is written. If the next operation is a read, the selected read regis-
ter is read. The pointer bits are automatically cleared after the second operation so the next
read or write comes from RR0 or goes to WR0. It is not necessary to write 00 to WR0 to
access WR0 or RR0.
For the Z80230 ESCC, the registers are directly addressable. A command issued to WR0B
determines how the ESCC decodes the address placed on the address/data bus at the
beginning of a Read or Write cycle. In Shift Right mode the channel select A/B is taken
from AD0 and the state of AD5 is ignored. In Shift Left mode, the channel select A/B is
taken from AD5 and the state of AD0 is ignored. AD7 and AD6 are always ignored as
address bits and the register address itself occupies AD4–AD1.
Initializing
The software first issues a series of commands to initialize the basic mode of operation.
These commands are followed by other commands to qualify conditions within the
selected mode. For example, in the ASYNCHRONOUS mode, character length, clock
rate, number of stop bits, and even and odd parity is set first. Next, the INTERRUPT mode
is set. Finally, the receiver and transmitter are enabled.
Write Registers
The ESCC contains 16 write registers (17 counting the transmit buffer) in each channel.
These write registers are programmed to configure the function of the channel. There are
two registers (WR2 and WR9) shared by the two channels, which can be accessed through
either of them. WR2 contains the interrupt vector for both channels. WR9 contains the
interrupt control bits and reset commands. Register WR7’ can be written to if WR15 bit 0
is 1.
Z80X20 Register Access
The Z80230 registers are addressed using the address on AD7–AD0 which are latched by
the rising edge of AS. The Shift Right/Shift Left bit in the Channel B WR0 controls which
PS005303-0907 Programming
Z85230/Z80230
Product Specification
33
bits are decoded to form the register address. This bit is placed in this register to simplify
programming when the current state of the Shift right/Shift Left bit is not known.
A hardware reset forces SHIFT LEFT mode where the address is decoded from
AD5–AD0. In SHIFT RIGHT mode, the address is decoded from AD4–AD0. The Shift
Right/Shift Left bit is written using a command to make the software writing to WR0 inde-
pendent of the state of the Shift Right/Shift Left bit.
While in the SHIFT LEFT mode, the register address is placed on AD4–AD0 and the
Channel Select bit A/B, is decoded from AD5. In SHIFT RIGHT mode, the register
address is again placed on AD4–AD1 but the Channel Select A/B is decoded from AD0.
Since Z80230 does not contain 16 read registers, the decoding of the read registers is not
complete; this state is indicated in Tables 4 and 5 by parentheses around the register name.
These addresses may also be used to access the read registers. The Z80230 contains only
one WR2 and WR9; these registers may be written from either channel.
SHIFT LEFT mode is used when Channel A and B are programmed differently. Using
SHIFT LEFT mode allows the software to sequence through the registers of one channel
at a time. The SHIFT RIGHT mode is used when the channels are programmed the same.
By incrementing the address, the user can program the same data value into both Channel
A and Channel B registers.
Table 5 provides details of the Z80X30 Register Map in SHIFT LEFT Mode.
Table 5. Z80230 Register Map (Shift Left Mode)
AD5 AD4 AD3 AD2 AD1 Write
80230
WR15 D2=0
80230
WR15 D2=1
80230
WR15 D2=1
WR7’ D6=1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
WR08
WR1B
WR2
WR3B
RR0B
RR1B
RR2B
RR3B
RR0B
RR1B
RR2B
RR3B
RR08
RR1B
RR2B
RR3B
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
WR4B
WR5B
WR6B
WR7B
(RR0B)
(RR1B)
RR6B
RR7B
(RR0B)
(RR1B)
(RR2B)
(RR3B)
(WR4B)
(WR5B)
RR6B
RR7B
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
WR8B
WR9
WR10B
WR11B
RR8B
(RR13B)
RR10B
(RR15B)
RR8B
(RR13B)
RR10B
(RR15B)
RR8B
(WR3B)
RR10B
(WR10B)
PS005303-0907 Programming
Z85230/Z80230
Product Specification
34
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
WR12B
WR13B
WR14B
WR15B
RR12B
RR13B
RR14B
RR15B
RR12B
RR13B
RR14B
RR15B
RR12B
RR13B
(WR7’B)
RR15B
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
WR0A
WR1A
WR2
WR3A
RR0A
RR1A
RR2A
RR3A
RR0A
RR1A
RR2A
RR3A
RR0A
RR1A
RR2A
RR3A
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
WR4A
WR5A
WR6A
WR7A
(RR0A)
(RR1A)
(RR2A)
(RR3A)
(RR0A)
(RR1A)
RR6A
RR7A
(WR4A)
(WR5A)
RR6A
RR7A
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
WR8A
WR9
WR10A
WR11A
RR8A
(RR13A)
RR10A
(RR15A)
RR8A
(RR13A)
RR10A
(RR15A)
RR8A
(WR3A)
RR10A
(WR10A)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
WR12A
WR13A
WR14A
WR15A
RR12A
RR13A
RR14A
RR15A
RR12A
RR13A
RR14A
RR15A
RR12A
RR13A
(WR7’A)
RR15A
Notes:
1. The register names in ( ) are the values read out from that register location.
2. WR15 bit D2 enables status FIFO function (not available on NMOS).
3. WR7’ bit D6 enables extend read function (only on ESCC).
Table 5. Z80230 Register Map (Shift Left Mode) (Continued)
AD5 AD4 AD3 AD2 AD1 Write
80230
WR15 D2=0
80230
WR15 D2=1
80230
WR15 D2=1
WR7’ D6=1
PS005303-0907 Programming
Z85230/Z80230
Product Specification
35
Table 6 provides details of the Z80X30 Register Map in SHIFT RIGHT mode.
Table 6. Z80X30 Register Map (Shift Right Mode)
AD4 AD3 AD2 AD1 AD0 Write
80230
WR15 D2=0
80230
WR15 D2=1
80230
WR15 D2=1
WR7’ D6=1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
WR08
WR0A
WR1B
WR1A
RR0B
RR0A
RR1B
RR1A
RR0B
RR0A
RR1B
RR1A
RR0B
RR0A
RR1B
RR1A
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
WR2
WR2
WR3B
WR3A
RR2B
RR2A
RR3B
RR3A
RR2B
RR2A
RR3B
RR3A
RR2B
RR2A
RR3B
RR3A
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
WR4B
WR4A
WR5B
WR5A
(RR0B)
(RR0A)
(RR1B)
(RR1A)
(RR0B)
(RR0A)
(RR1B)
(RR1A))
(WR4B)
(WR4A)
(WR5B)
(WR5A)
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
WR6B
WR6A
WR7B
WR7A
(RR2B)
(RR2A)
(RR3B)
(RR3A)
RR12B
RR13B
RR14B
RR15B
RR12B
RR13B
(WR7’B)
RR15B
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
WR8B
WR8A
WR9
WR9
RR8B
RR8A
(RR13B)
(RR13A)
RR8B
RR8A
(RR13B)
(RR13A)
RR8B
RR8A
(WR3B)
(WR3A)
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
WR10B
WR10A
WR11B
WR11A
RR10B
RR10A
(RR15B)
(RR15A)
RR10B
RR10A
(RR15B)
(RR15A)
RR10B
RR10A
(WR10B)
(WR10A)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
WR12B
WR12A
WR13B
WR13A
RR12B
RR12B
RR13B
RR13A
RR12B
RR12B
RR13B
RR13A
RR12B
RR12B
RR13B
RR13A
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
WR14B
WR14A
WR15B
WR15A
RR12B
RR12B
RR13B
RR13A
RR12B
RR12B
RR13B
RR13A
(WR7’B)
(WR7’B)
RR13B
RR13A
Notes:
1. The register names in ( ) are the values read out from that register location.
2. WR15 bit D2 enables status FIFO function (not available on NMOS).
3. WR7’ bit D6 enables extend read function (only on ESCC).
PS005303-0907 Programming
Z85230/Z80230
Product Specification
36
Bits 2–0 of WR0 select registers 0–7. With the Point High command, Registers 8–15 are
selected.Table 7 provides details of the Z8530 Register Map.
Table 7. Z85230 Register Map
A/B PNT2 PNT1 PNT0 Write
85230
WR15 D2=0
85230
WR15 D2=1
85230
WR15 D2=1
WR7’ D6=1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
WR0B
WR1B
WR2
WR3B
RR0B
RR1B
RR2B
RR3B
RR0B
RR1B
RR2B
RR3B
RR0B
RR1B
RR2B
RR3B
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
WR4B
WR5B
WR6B
WR7A
(RR0B)
(RR1B)
(RR2B)
(RR3B)
(RR0B)
(RR1B)
RR6B
RR7B
(WR4B)
(WR5B)
RR6B
RR7B
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
WR0A
WR1A
WR2
WR3A
RR0A
RR1A
RR2A
RR3A
RR0A
RR1A
RR2A
RR3A
RR0A
RR1A
RR2A
RR3A
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
WR4A
WR5A
WR6A
WR7A
(RR0A)
(RR1A)
(RR2A)
(RR3A)
(RR0A)
(RR1A)
RR6A
RR7A
(WR4A)
(WR5A)
RR6A
RR7A
With Point High Command
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
WR8B
WR9
WR10B
WR11B
RR8B
(RR13B)
RR10B
(RR15B)
RR8B
(RR13B)
RR10B
(RR15B)
RR8B
(WR3B)
RR10B
(WR10B)
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
WR12B
WR13B
WR14B
WR15B
RR12B
RR13B
RR14B
RR15B
RR12B
RR13B
RR14B
RR15B
RR12B
RR13B
(WR7’B)
RR15B
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
WR8A
WR9
WR10A
WR11A
RR8A
(RR13A)
RR10A
(RR15A)
RR8A
(RR13A)
RR10A
(RR15A)
RR8A
(WR3A)
RR10A
(WR10A)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
WR12A
WR13A
WR14A
WR15A
RR12A
RR13A
RR14A
RR15A
RR12A
RR13A
RR14A
RR15A
RR12A
RR13A
(WR7’A)
RR15A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
WR0B
WR1B
WR2
WR3B
RR0B
RR1B
RR2B
RR3B
RR0B
RR1B
RR2B
RR3B
RR0B
RR1B
RR2B
RR3B
Notes:
1. The register names in ( ) are the values read out from that register location.
2. WR15 bit D2 enables status FIFO function (not available on NMOS).
3. WR7’ bit D6 enables extend read function (only on ESCC).
PS005303-0907 Programming
Z85230/Z80230
Product Specification
37
Table 8 through Table 24 describe the format of each write register.
Table 8. Write Register 0
Bit 7 6 5 4 3 2 1 0
R/W W
Reset 00000000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7, 6 W 00
01
10
11
Null Code
Reset Tx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
5, 4, 3 000
001
010
011
100
101
110
111
Null Code
Point High
Reset Ext/Status Interrupts
Send Abort (SDLC)
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
2, 1, 0 000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8 (with Point High)
Register 9 (with Point High)
Register 10 (with Point High)
Register 11 (with Point High)
Register 12 (with Point High)
Register 13 (with Point High)
Register 14 (with Point High)
Register 15 (with Point High)
For the 80230, bits 1 and 0 are accessible only through Channel B.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
38
Table 9. Write Register 1
Bit 7 6 5 4 3 2 1 0
R/W W
Reset 00X00X00
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7
0
1
WAIT/DMA Request Enable
Disabled
Enabled
6
0
1
WAIT/DMA Request Function
Wait
Request
5
0
1
WAIT/DMA Request on Receive/Transmit
Transmit
Receive
4, 3 00
01
10
11
Receive Interrupt Disable
Rec Int on First Character or Special Condition
Int on all Rx Characters or Special Condition
Rx Int on Special Condition Only
2 Parity is Special condition
1Tx Int Enable
0 Ext Int Enable
PS005303-0907 Programming
Z85230/Z80230
Product Specification
39
Table 10. Write Register 2
Bit 7 6 5 4 3 2 1 0
R/W W
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 V7–Interrupt Vector
6 V6–Interrupt Vector
5 V5–Interrupt Vector
4 V4–Interrupt Vector
3 V3–Interrupt Vector
2 V2–Interrupt Vector
1 V1–Interrupt Vector
0 V0–Interrupt Vector
PS005303-0907 Programming
Z85230/Z80230
Product Specification
40
Table 11. Write Register 3
Bit 7 6 5 4 3 2 1 0
R/W W
Reset X XXXXXX0
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7, 6 00
01
10
11
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 bits/Character
5 Auto Enable
4 Enter HUNT Mode
3 Rx CRC Enable
2 Address Search Mode (SDLC)
1 Sync Character Load Inhibit
0 Rx Enable
PS005303-0907 Programming
Z85230/Z80230
Product Specification
41
Table 12. Write Register 4
Bit 7 6 5 4 3 2 1 0
R/W W
Reset X XXXX1X0
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7, 6 00
01
10
11
X1 Clock Mode
X16 Clock Mode
Z32 Clock Mode
X64 Clock Mode
5, 4 00
01
10
11
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
3, 2 00
01
10
11
Sync Modes Enable
1 Stop Bit/Character
1.5 Stop Bits/Character
2 Stop Bits/Character
1
0
1
Parity EVEN/ODD
Odd
Even
0 Parity Enable
PS005303-0907 Programming
Z85230/Z80230
Product Specification
42
Table 13. Write Register 5
Bit 7 6 5 4 3 2 1 0
R/W W
Reset 0 XX0000X
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7DTR
6, 5 00
01
10
11
Tx 5 Bits (or less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
4 Send Break
3 Tx Enable
2
0
1
CRC-16/CRC-CCITT
CRC-CCITT
CRC-16
1RTS
0 Tx CRC Enable
PS005303-0907 Programming
Z85230/Z80230
Product Specification
43
Table 14. Write Register 6
Bit 7 6 5 4 3 2 1 0
R/W W
Reset XX X X X X X X
R = Read W = Write X = Indeterminate
Bit
Position R/W Value
Description
Monosync 8
Bits
Monos
ync 6
Bits
Bisync
16 Bits
Bisync
12 Bits SDLC
SDLC
(Address
Range)
7 Sync7 Sync1 Sync7 Sync3 ADR7 ADR7
6 Sync6 Sync0 Sync6 Sync2 ADR6 ADR6
5 Sync5 Sync5 Sync5 Sync1 ADR5 ADR5
4 Sync4 Sync4 Sync4 Sync0 ADR4 ADR4
3 Sync3 Sync3 Sync3 1 ADR3 X
2 Sync2 Sync2 Sync2 1 ADR2 X
1 Sync1 Sync1 Sync1 1 ADR1 X
0 Sync0 Sync0 Sync0 1 ADR0 X
PS005303-0907 Programming
Z85230/Z80230
Product Specification
44
Table 15. Write Register 7
Bit 7 6 5 4 3 2 1 0
R/W W
Reset XXXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value
Description
This
column
contains
no data
Monosync 8
Bits
Monosync 6
Bits
Bisync 16
Bits
Bisync
12 Bits SDLC
7 Sync7 Sync5 Sync15 Sync11 0
6 Sync6 Sync4 Sync14 Sync10 1
5 Sync5 Sync3 Sync13 Sync9 1
4 Sync4 Sync2 Sync12 Sync8 1
3 Sync3 Sync1 Sync11 Sync7 1
2 Sync2 Sync0 Sync10 Sync6 1
1 Sync1 X Sync9 Sync5 1
0 Sync0 X Sync8 Sync4 0
PS005303-0907 Programming
Z85230/Z80230
Product Specification
45
Table 16. Write Register 7’
Bit 7 6 5 4 3 2 1 0
R/W W
Reset 0 0100000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 0 Not Used. Must be 0.
6 Extended Read Enable
5 Tx FIFO Int Level
4DTR
/REQ Timing Mode
3 Rx FIFO Int Level
2 Auto RTS Deactivation
1 Auto EOM Reset
0 Auto Tx Flag
PS005303-0907 Programming
Z85230/Z80230
Product Specification
46
Table 17. Write Register 8
Bit 7 6 5 4 3 2 1 0
R/W W
Reset 0 0100000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7D7
6D6
5D5
4D4
3D3
2D2
1D1
0D0
PS005303-0907 Programming
Z85230/Z80230
Product Specification
47
Table 18. Write Register 9
Bit 7 6 5 4 3 2 1 0
R/W W
Hardware
Reset
1 10000XX
Channel Reset X X0XXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7, 6 00
01
10
11
No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset
5 Software INTACK Enable
4
0
1
Status High/ Status Low
Low
High
3 Master Interrupt Enable
2 Disable Lower Chain
1 No Vector
0 Vector Includes Status
PS005303-0907 Programming
Z85230/Z80230
Product Specification
48
Table 19. Write Register 10
Bit 7 6 5 4 3 2 1 0
R/W W
Hardware
Reset
0 0000000
Channel Reset 0 XX00000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 CRC Preset I/O
6, 5 00
01
10
11
NRZ
NRZI
FM 1 (Transition = 1)
FM 0 (Transition = 0)
4 Go Active on Poll
3
0
1
Mark/Flag Idle
Flag Idle
Mark Idle
2
0
1
Abort/Flag on Underrun
Flag
Abort
1 Loop Mode
0
0
1
6-Bit/8-Bit sync
8-Bit
6-bit
PS005303-0907 Programming
Z85230/Z80230
Product Specification
49
Table 20. Write Register 11
Bit 7 6 5 4 3 2 1 0
R/W W
Hardware
Reset
0 0001000
Channel Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7
0
1
RTxC Xtal/No Xtal
No Xtal
RTxC Xtal
6, 5 00
01
10
11
Receive Clock = RTxC Pin
Receive Clock = TRxC Pin
Receive Clock = BRG Output
Receive Clock = DPLL Output
4, 3 00
01
10
11
Transmit Clock = RTxC Pin
Transmit Clock = TRxC Pin
Transmit Clock = BRG Output
Transmit Clock = DPLL Output
2
0
1
TRxC Input/Output
Output
Input
100
01
10
11
TRxC Out = Xtal Output
TRxC Out = Transmit Clock
TRxC Out = BRG Output
TRxC Out = DPLL Output
PS005303-0907 Programming
Z85230/Z80230
Product Specification
50
Table 21. Write Register 12
Bit 7 6 5 4 3 2 1 0
R/W W
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description (Lower Byte of Time Constant)
7TC7
6TC6
5TC5
4TC4
3TC3
2TC2
1TC1
0TC0
PS005303-0907 Programming
Z85230/Z80230
Product Specification
51
Table 22. Write Register 13
Bit 7 6 5 4 3 2 1 0
R/W W
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description (Upper Byte of Time Constant)
7TC15
6TC14
5TC13
4TC12
3TC11
2TC10
1TC9
0TC8
PS005303-0907 Programming
Z85230/Z80230
Product Specification
52
Table 23. Write Register 14
Bit 7 6 5 4 3 2 1 0
R/W W
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description (Upper Byte of Time Constant)
7, 6, 5 000
001
010
011
100
101
110
111
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set source - BRG
Set Source = RTxC
Set FM Mode
Set NRZI Mode
4 Local Loopback
3 Auto Echo
2 DTR/Request Generator Source
1BRG Source
0BRG Enable
PS005303-0907 Programming
Z85230/Z80230
Product Specification
53
Read Registers
The ESCC contains ten read registers (eleven, counting the receive buffer RR8) in each
channel. Four of these may be read to obtain status information (RR0, RR1, RR10 and
RR15).
Two registers, RR12 and RR13, are read to learn the BRG time constant. RR2 contains
either the unmodified interrupt vector, Channel A, or the vector modified by status infor-
mation, Channel B.
RR3 contains the Interrupt Pending (IP) bits for Channel A.
RR6 and RR7 contain the information in the SDLC Frame Status FIFO, but is only read
when WR15 bit 2 is 1. If WR7’ bit 6 is 1, Write Registers WR3, WR4, WR5, and WR10
can be read as RR9, RR4, RR5, and RR14, respectively. Table 25 through Table 40
describe the format of the read registers.
Table 24. Write Register 15
Bit 7 6 5 4 3 2 1 0
R/W W
Reset 1 1110000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 Break/Abort Interrupt Enable
6 Tx Underrun/EOM Interrupt Enable
5CTS
Interrupt Enable
4 Sync/Hunt
3 DCD Interrupt Enable
2 SDLC FIFO Enable
1 Zero Count Interrupt Enable
0 WR7’ SDLC Feature Enable
PS005303-0907 Programming
Z85230/Z80230
Product Specification
54
Table 25. Read Register 0
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X 1XXX100
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 Break/Abort
6 Tx Underrun/EOM
5CTS
4 Sync/Hunt
3 DCD Interrupt Enable
2 Tx Buffer Empty
1 Zero Count
0 Rx Character Available
PS005303-0907 Programming
Z85230/Z80230
Product Specification
55
Table 26. Read Register 1
Bit 7 6 5 4 3 2 1 0
R/W R
Reset 0 000011X
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7EOF (SDLC)
6 CRC/Framing Error
5 Rx Overrun Error
4Parity Error
3 Residue Code 0
2 Residue Code 1
1 Residue Code 2
0 All Sent
PS005303-0907 Programming
Z85230/Z80230
Product Specification
56
Table 27. Read Register 2
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description (Interrupt Vector)
7V7
6V6
5V5
4V4
3V3
2V2
1V1
0V0
These bits include status information when read from Channel B.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
57
Table 28. Read Register 3
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
70
60
5 Channel A Rx IP
4 Channel A Tx IP
3 Channel A Ext/Status IP
2 Channel B Rx IP
1 Channel B Tx IP
0 Channel B Ext/Status IP
Bits 5, 4, 3, 2, 1 and 0 are always 0 when read from Channel B.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
58
Table 29. Read Register 4
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7, 6 00
01
10
11
X1 Clock Mode
X16 Clock Mode
Z32 Clock Mode
X64 Clock Mode
5, 4 00
01
10
11
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
3, 2 00
01
10
11
Sync Modes Enable
1 Stop Bit/Character
1.5 Stop Bits/Character
2 Stop Bits/Character
1
0
1
Parity EVEN/ODD
Odd
Even
0 Parity Enable
This register reflects the contents of RR0 if WR7’ bit 6 is enabled.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
59
Table 30. Read Register 5
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7DTR
6, 5 00
01
10
11
Tx 5 Bits (or less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
4 Send Break
3 Tx Enable
2
0
1
CRC-16/CRC-CCITT
CRC-CCITT
CRC-16
1RTS
0 Tx CRC Enable
This register reflects the contents of RR1 if WR7’ bit 6 is enabled.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
60
Table 31. Read Register 6
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7BC7
6BC6
5BC5
4BC4
3BC3
2BC2
1BC1
0BC0
This register can be accessed only if WR15 bit 2 is 1. If this bit is not enabled this register reflects
RR2.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
61
Table 32. Read Register 7
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7
0
1
FOS: FIFO Status Overflow
FIFO Overflowed
Normal
6
0
1
FDA: FIFO Data Available
Status Reads from FIFO
Status Reads from ESCC
5BC13
4BC12
3BC11
2BC10
1BC9
0BC8
This register can be accessed only if WR15 bit 2 is 1. If this bit is not enabled this register reflects
RR3.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
62
Table 33. Read Register 8
Bit 7 6 5 4 3 2 1 0
R/W R
Reset 0 0100000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7D7
6D6
5D5
4D4
3D3
2D2
1D1
0D0
PS005303-0907 Programming
Z85230/Z80230
Product Specification
63
Table 34. Read Register 9
Bit 7 6 5 4 3 2 1 0
R/W R
Hardware Reset 110000XX
Channel Reset XX0XXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7, 6 00
01
10
11
No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset
5 Software INTACK Enable
4
0
1
Status High/Status Low
Low
High
3 Master Interrupt Enable
2 Disable Lower Chain
1No Vector
0 Vector Includes Status
To access this register WR7’ bit 6 must be enabled.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
64
Table 35. Read Register 10
Bit 7 6 5 4 3 2 1 0
R/W R
Reset 0 0100000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 One Clock Missing
6 Two Clocks Missing
50
4 Loop Sending
30
20
1 On Loop
00
PS005303-0907 Programming
Z85230/Z80230
Product Specification
65
Table 36. Read Register 11
Bit 76543210
R/W R
Hardware Reset 00000000
Channel Reset XXXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 CRC Preset I/O
6, 5 00
01
10
11
NRZ
NRZI
FM1 (Transition = 1)
FM0 (Transition = 0)
4 Go Active on Poll
3
0
1
Mark/Flag Idle
Flag Idle
Mark Idle
2
0
1
Abort Flag on Underrun
Flag
Abort
1 Loop Mode
0
0
1
6-Bit/8-Bit Sync
8-Bit Sync
6-Bit Sync
To access this register WR7’ bit 6 must be enabled. If this bit is not enabled, this register reflects
RR15.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
66
Table 37. Read Register 12
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description (Lower Byte of Time Constant)
7TC7
6TC6
5TC5
4TC4
3TC3
2TC2
1TC1
0TC0
PS005303-0907 Programming
Z85230/Z80230
Product Specification
67
Table 38. Read Register 13
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description (Upper Byte of Time Constant)
7TC15
6TC14
5TC13
4TC12
3TC11
2TC10
1TC9
0TC8
PS005303-0907 Programming
Z85230/Z80230
Product Specification
68
Table 39. Read Register 14
Bit 7 6 5 4 3 2 1 0
R/W R
Reset 0 0100000
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 0 Not Used. Must be 0.
6 Extended Read Enable
5 Tx FIFO Int Level
4DTR
/REQ Timing Mode
3 Rx FIFO Int Level
2 Auto RTS Deactivation
1 Auto EOM Reset
0 Auto Tx Flag
To access this register WR7’ bit 6 must be enabled. If this bit is not enabled this register reflects
RR10.
PS005303-0907 Programming
Z85230/Z80230
Product Specification
69
Table 40. Read Register 15
Bit 7 6 5 4 3 2 1 0
R/W R
Reset X XXXXXXX
R = Read W = Write X = Indeterminate
Bit
Position R/W Value Description
7 Break/Abort Interrupt Enable
6 Tx Underrun/EOM Interrupt Enable
5CTS
Interrupt Enable
4 Sync/Hunt
3 DCD Interrupt Enable
2 SDLC FIFO Enable
1 Zero Count Interrupt Enable
0 WR7’ SDLC Feature Enable
PS005303-0907 Z80230 Interface Timing
Z85230/Z80230
Product Specification
70
Z80230 Interface Timing
Z80230 Write Cycle Timing
The Z-Bus compatible ESCC is suited for system applications with multiplexed address/
data buses.
Two control signals, AS and DS, are used by the Z80230 to control bus transactions. Addi-
tionally, four other control signals (CS0, CS1, RW, and INTACK) control the type of bus
transaction that occurs. A bus transaction is initiated by AS. The rising edge latches the
register address on the Address/Data bus and the state of INTACK and CS0.
In addition to bus transactions, the interrupt section uses the AS to set Interrupt Pending
(IP) bits. Therefore, AS must be kept cycling for the interrupt section to function.
The Z80230 generates internal control signals in response to a register access. Because AS
and DS have no defined phase relationship with PCLK, the circuitry generating these
internal control signals provide time for metastable conditions to disappear. This action
results in a recovery time related to PCLK.
This recovery time applies only to transactions involving the Z80230, and any intervening
transactions are ignored. This recovery time is four PCLK cycles, measured from the fall-
ing edge of DS for one access to the ESCC, to the falling edge of DS for a subsequent
access. Figure 17 illustrates the Write cycle timing.
Figure 17. Z80230 Write Cycle Timing
AS
CS0
INTACK
A7–A0
R/W
CS1
DS
Address Data Valid
PS005303-0907 Z80230 Interface Timing
Z85230/Z80230
Product Specification
71
Z80230 Read Cycle Timing
The Read Cycle Timing for the Z80230 is illustrated in Figure 18. The register address on
A7-A0, as well as the state of CS0 and INTACK, are latched by the rising edge of AS.
R/W must be High before DS falls to indicate a Read cycle. The Z80230 data bus drivers
are enabled while CS1 is High and DS is Low.
Figure 18. Z80230 Read Cycle Timing
Z80230 Interrupt Acknowledge Cycle Timing
The Interrupt Acknowledge cycle timing for the Z80230 is illustrated in Figure 19 on page
72. The address on A7-A0 and the state of CS0 and INTACK are latched by the rising -
edge of AS. However, if INTACK is Low. The address on A7-A0, CS0, CS1 and R/W are
ignored for the duration of the interrupt acknowledge cycle.
The Z80230 samples the state of INTACK on the rising edge of AS, and AC parameters.
Parameters 7 and 8 of Table 44 on page 82, specify the setup and hold time requirements.
Between the rising edge of AS and the falling edge of DS, the internal and external daisy
chains settle, as specified in parameter 29). A system with no external daisy chain pro-
vides the time priority internal to the ESCC. Systems using an external daisy chain must
refer to Note 5 of Table 44, for the time required to settle the daisy chain.
If there is an interrupt pending in the ESCC, and IEI is High when DS falls, the acknowl-
edge cycle is intended for the ESCC. Consequently, the Z80230 sets the Interrupt Under
Service (IUS) latch for the highest priority pending interrupt, and places an interrupt vec-
AS
CS0
INTACK
A7–A0
R/W
CS1
DS
Address Data Valid
PS005303-0907 Z80230 Interface Timing
Z85230/Z80230
Product Specification
72
tor on A7-A0. WR9 bit 1 is set to 1 to disable the placing of a vector on a bus. The INT pin
also goes inactive in response to the falling edge of DS. There is only one DS per interrupt
acknowledge cycle.
IP bits in the Z80230 are updated by AS, which can delay interrupt requests if the proces-
sor does not supply AS strobes during the time in between accesses of the Z80230.
Figure 19. Z80230 Interrupt Acknowledge Cycle Timing
Z85230 Timing
The ESCC generates internal control signals from WR and RD that relate to PCLK.
Because PCLK had no defined phase relationship with WR and RD, the circuitry generat-
ing the internal control signals provides time for metastable conditions to disappear. This
causes a recovery time related to PCLK. The recovery time applies only to bus transac-
tions involving the ESCC. The recovery time required for proper operation is specified
AS
CS0
A7–A0
DS
INTACK
IEI
IEO
INT
Vector
PS005303-0907 Z80230 Interface Timing
Z85230/Z80230
Product Specification
73
from the falling edge of WR or RD in the first transaction involving the ESCC, to the fall-
ing edge of WR or RD in the second transaction. This time must be at least four PCLKs
regardless of which register or channel is accessed.
Z85230 Read Cycle Timing
Figure 20 illustrates Read Cycle timing. Addresses on A/B and D/C and the status on
INTACK must remain stable throughout the cycle. The effective RD time reduces if CE
falls after RD falls, or if it rises before RD rises.
Figure 20. Read Cycle Timing (Z85230)
Z85230 Write Cycle Timing
Figure 21 on page 74 illustrates Write Cycle timing. Addresses on A/B and D/C and the
status on INTACK must remain stable throughout the cycle. The effective WR time
reduces if CE falls after WR falls, or if it rises before WR rises. In Write Cycle timing, the
WR signal returns a High slightly before the Address goes invalid.
Because many popular CPUs do not guarantee that the databus is valid when WR is Low,
the ESCC no longer requires a valid databus when the WR pin is Low. For more informa-
tion, see AC characteristics parameter 29 available in Table 46.
A
/B, D/C Address Valid
INTACK
CE
D7–D0 Data Valid
RD
PS005303-0907 Z80230 Interface Timing
Z85230/Z80230
Product Specification
74
Figure 21. Write Cycle Timing (Z85230)
Z85230 Interrupt Acknowledge Cycle Timing
Figure 22 illustrates Interrupt Acknowledge Cycle timing. Between the time INTACK
goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle.
If there is an interrupt pending in the ESCC and IEI is High when RD falls, the Acknowl-
edge cycle is intended for the ESCC. In this case, the ESCC may be programmed to
respond to RD Low by placing its interrupt vector on D7–D0. It then sets the appropriate
IUS latch internally. If the external daisy chain is not used, then AC Parameter 38 is
required to settle the interrupt priority daisy chain internal to the ESCC. If the external
daisy chain is used, follow the equation in AC Characteristics Note 5 (Table 46 on
page 89) to calculate the required daisy chain settle time.
Figure 22. Interrupt Acknowledge Cycle Timing (Z85230)
A
/B, D/C Address Valid
INTACK
CE
D7–D0 Address Valid
WR
Vector
INTACK
RD
D7–D0
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
75
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in this section can cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition above those
indicated in the operational section of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods can affect reliability.
Standard Test Conditions
The DC Characteristics and capacitance sections apply for the following standard test
conditions, unless otherwise noted. All voltages reference GND. Positive current flows
into the referenced pin. Standard conditions are as follows:
•
+4.50 V≤ VCC≤ +5.50 V
•
GND = 0 V
•
TΑ as specified in Ordering Information
Figure 23 on page 76 illustrates typical test load configurations.
VCC Supply Voltage Range -0.3V to +7.0V
Voltages on All Pins with Respect to GND -0.3V to VCC +0.3V
Operating Ambient Temperature See Ordering Information on
page 106
Storage Temperatures -65º C to +150º C
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
76
Figure 23. Standard and Open-Drain Test Loads
Capacitance
Table 41 lists the capacitance parameters and contains the symbols and test conditions for
each.
Miscellaneous
Gate count—11,000 for both Z80230 and Z85230.
Table 41. Capacitance
Symbol Parameter Min Max Unit Test Condition
CIN Input Capacitance 10 pF Unmeasured Pins
Returned to Ground
COUT Output Capacitance 15 pF
CI/O Bidirectional Capacitance 20 pF
Note: f = 1MHz, over specified temperature range.
From Output
Under Test
100pf 250µA
2.1K
+5V
Standard Test Load
+5V
2.2K
From Output
50pf
Open-Drain Test Load
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
77
DC Characteristics
Table 42 lists the DC characteristics for the Z80230/Z85230 device.
AC Characteristics
Figure 24 on page 78 illustrates the Z80230 Read/Write timing diagram.
Table 42. DC Characteristics
Symbol Parameter Min. Typ. Max. Unit Condition
VIH Input High Voltage 2.2 VCC + 0.3 V
VIL Input Low Voltage – 0.3 0.8 V
VOH1 Output High Voltage 2.4 V IOH = - 1.6mA
VOH2 Output High Voltage VCC – 0.8 V IOH = -250μA
VOL Output Low Voltage 0.4 V IOL = +2.0 mA
IIL Input Leakage ± 10.0 µA 0.4 <VIN<+2.4 V
IOL Output Leakage ± 10.0 µA 0.4 <VOUT<+2.4 V
ICC1 VCC Supply Current 4
5
7
9
10 (8.5 MHz)
12 (10MHz)
15 (16MHz)
20 (20MHz)
mA
mA
mA
mA
VCC=5V,VIH=4.8,VIL=0.2V
Crystal oscillators off
ICC(OSC) Crystal OSC Current 6 mA Current for each oscillator
in addition to ICC1
Note: 1. Vcc=5V ± 10% unless otherwise specified, over specified temperature range.
Note: 2. Typical Icc was measured with oscillator off.
Note: 3. No Icc(osc) max is specified because of dependency on the external circuit.
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
78
Figure 24. Z80230 Read/Write Timing Diagram
12
34
56
14
78
910
11
12
10
13 18
15
15
16
16
17
19
20
21
23
22
24
25
26
27
43 44
42
41
40
28
AS
CS0
CS1
INTACK
R/W
Read
W/R
Write
DS
AD7-AD0
Write
AD7-AD0
Read
W/REQ
Request
DTR/REQ
Request
INT
PCLK
W/REQ
Wait
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
79
Figure 25 illustrates the Z80230 Interrupt Acknowledge timing diagram
Figure 25. Z80230 Interrupt Acknowledge Timing Diagram
Figure 26 illustrates the Z80230 Reset timing diagram
Figure 26. Z80230 Reset Timing Diagram
Table 44 describes the AC characteristics of the Z80230 and Table 46 describes the AC
characteristics of Z85230.
7
8
29 30
19 20
Active Valid
32
31 22
33
34 35
36
AS
INTACK
DS
AD7-AD0
IEO
INT
IEI
AS
DS
35
37 38
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
80
Figure 27 illustrates the Z80230 general timing diagram.
Figure 27. Z80230 General Timing Diagram
22
1
2
3
4567
89
10
11 12
13
14 15
16
17
22
21 21
20
19
18
PCLK
W/REQ
Request
W/REQ
Wait
C
TS/TRxC,
RTxC
Receive
RxD
SYNC
External
C
TS/TRxC,
RTxC
Transmit
TxD
CTS/TRxC
Output
RTxC
CTS/TRxC
C
TS/TRxC,
DCD
SYNC
Input
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
81
Table 43 describes the Z80230 general timing characteristics details.
Table 43. Z80230 General Timing Characteristics
No. Symbol Parameter
10 MHz 16 MHz
Notes
Min. Max. Min. Max.
1 TdPC(REQ) PCLK Low to W/REQ Valid 200 110 9
2 TsPC(W) PCLK Low to Wait Inactive 300 180 9
3 TsRXC(PC) RxC High to PCLK High Setup
Time
NA NA 1, 4, 9
4 TsRXD(RXCr) RxD to RxC High Setup Time 0 0 1,9
5 ThRXD(RxCr) RxD to RxC High Hold Time 125 60 1,9
6 TsRXD(RXCf) RxD to RxC Low Setup Time 0 0 1, 5, 9
7 ThRXD(RXCf) RxD to RxC Low Hold Time 125 60 1, 5, 9
8 TsSY(RXC) SYNC to RxC High Setup Time -150 -100 1, 9
9 ThSY(RXC) SYNC to RxC High Hold Time 5 5 1, 10
10 TsTXC(PC) TxC Low to PCLK High Setup
Time
NA NA 2, 4, 9
11 TdTXCf(TXD) TxC Low to TxD Delay 150 85 2, 9
12 TdTxCr(TXD) TxC High to TxD Delay 150 85 2, 5, 9
13 TdTXD(TRX) TxD to TRxC Delay 140 80 9
14 TwRTXh RTxC High Width 120 80 6, 9
15 TwRTXI TRxC Low Width 120 80 6, 9
16a TcRTX RTxC Cycle Time 400 244 6, 7, 9
16b TxRX(DPLL) DPLL Cycle Time Minimum 50 31 7, 8, 9
17 TcRTXX Crystal Oscillator Period 100 1000 100 1000 3, 9
18 TwTRXh TRxC High Width 120 80 6, 9
19 TwTRXI TRxC Low Width 120 80 6, 9
20 TcTRX TRxC Cycle Time 400 244 6, 7, 9
21 TwEXT DCD or CTS Pulse Width 120 70 9
22 TwSY SYNC Pulse Width 120 70 9
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
82
Table 44 summarizes the Z80230 Read and Write AC characteristics.
Notes:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
3. Both RTxC and SYNC have 30 pf capacitors to ground connected to them.
4. Synchronization of RxC to PCLK is eliminated in divide by four operation.
5. Parameter applies only to FM encoding/decoding.
6. Parameter applies only for transmitter and receiver; DPLL and BRG timing requirements are identical to PCLK
requirements.
7. The maximum transmit or receive data rate is 1/4 PCLK.
8. Applies to the DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock must have a
50% duty cycle.
9. Units in nanoseconds (ns).
10. Units in TcPc.
Table 44. Z80230 AC Characteristics
No Symbol Parameter
10 MHz 16 MHz
NotesMin. Max. Min. Max
1TwAS AS
Low Width 30 20 8
2 TdDS(AS) DS Rise to AS Fall Delay 10 10 1, 8
3 TsCS0(AS) CS0 to AS Rise Setup Time 0 0 1, 8
4 ThCS0(AS) CS0 to AS Rise Hold Time 20 15 1, 8
5 TsCS1(DS) CS1 to DS Fall Setup Time 50 35 1, 8
6 ThCS1(DS) CS1 to DS Rise Hold Time 20 10 1, 8
7 TsIA(AS) INTACK to AS Rise Setup Time 10 10 8
8 ThIA(AS) INTACK to AS Rise Hold Time 125 100 8
9 TsRWR(DS) R/W (Read) to DS Fall Setup
Time
50 35 8
10 ThRW(DS) R/W to DS Rise Hold Time 0 0 8
11 TsRWW(DS) R/W (Write) to DS Fall Setup
Time
008
12 TdAS(DS) AS Rise to DS Fall Delay 20 15 8
Table 43. Z80230 General Timing Characteristics (Continued)
No. Symbol Parameter
10 MHz 16 MHz
Notes
Min. Max. Min. Max.
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
83
13 TwDSI DS Low Width 125 80 8
14 TrC Valid Access Recovery Time 4 4 2, 9
15 TsA(AS) Address to AS Rise Setup Time 10 10 1, 8
16 ThA(AS) Address to AS Rise Hold Time 20 10 1, 8
17 TsDW(DS) Write Data to DS Fall Setup Time 10 10 8
18 ThDW(DS) Write Data to DS Rise Hold Time 0 0 8
19 TdDS(DA) DS Fall to Data Active Delay 0 0 8
20 TdDSr(DR) DS Rise to Read Data Not Valid
Delay
008
21 TdDSf(DR) DS Fall to Data Active Delay 120 70 8
22 TdAS(DR) AS Rise to Read Data Valid Delay 190 110 8
23 TdDS(DRz) DS Rise to Read Data Float
Delay
35 20 3, 8
24 TdA(DR) Address Required Valid to Read
Data Valid Delay
210 100
25 TdDS(W) DS Fall to Wait Valid Delay 160 60 4, 8
26 TdDSf(REQ) DS Fall to W/REQ Not Valid
Delay
160 60 8
27 TdDSr(REQ) DS Fall to DTR/REQ Not Valid
Delay
449
28 TdAS(INT) AS Rise to INT Valid Delay 500 175
29 TdAS(DSA) AS Rise to DS Fall
(Acknowledge) Hold Time
225 50 5
30 TsDSA DS (Acknowledge) Low Width 125 75 8
31 TdDSA(DR) DS Fall (Acknowledge) to Read
Data Valid Delay
120 70 8
32 TsIEI(DSA) IEI to DS Fall (Acknowledge)
Setup time
80 50 8
33 ThIEI(DSA) IEI to DS Rise (Acknowledge)
Hold Time
008
Table 44. Z80230 AC Characteristics (Continued)
No Symbol Parameter
10 MHz 16 MHz
NotesMin. Max. Min. Max
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
84
Figure 28 illustrates the Z80230 system timing diagram.
34 TdIEI(IEO) IEI to IEO Delay 90 45 8
35 TdAS(IEO) AS Rise to IEO Delay 175 80 6
36 TdDSA(INT) DS Fall (Acknowledge) to INT
Inactive Delay
450 200 4, 8
37 TdDS(ASQ) DS Rise to AS Fall Delay for No
Reset
15 10 8
38 TdASQ(DS) AS Rise to DS Fall Delay for No
Reset
15 10 8
39 TwRES AS and DS Coincident Low for
Reset7
100 75 8
40 TwPCl PCLK Low Width 40 100 26 1000 8
41 TwPCh PCLK High Width 40 1000 26 1000 8
42 TcPc PCLK Cycle Time 100 2000 61 2000 8
43 TrPC PCLK Rise Time 10 5 8
44 TfPC PCLK Fall Time 10 5 8
Note:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Parameter applies only between transactions involving the ESCC.
3. Float delay is defined as the time required for a ±0.5V change in the output with a maximum DC load and a min-
imum AC load.
4. Open-drain output, measured with open-drain test load.
5. Parameter is system-dependent. For any Zilog ESCC in the daisy chain. TdAS(DSA) must be greater than the
sum of TdAS(IEO) for the highest priority device in the daisy chain. TsIEI(DSA) for the Zilog ESCC, and
TdIEI(IEO) for each device separating them in the daisy chain.
6. Parameter applies only to a Zilog ESCC pulling INT Low at the beginning of the Interrupt Acknowledge transac-
tion.
7. Internal circuitry allows for the reset provided by the Z8 to be recognized as a reset by the Z-ESCC. All timing
references assume 2.0V for a 1 and 0.8V for a logic 0.
8. Units in nanoseconds (ns).
9. Units inTcPc
Table 44. Z80230 AC Characteristics (Continued)
No Symbol Parameter
10 MHz 16 MHz
NotesMin. Max. Min. Max
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
85
Figure 28. Z80230 System Timing Diagram
1
2
3
4
5
6
7
8
9
10
RTxC,TRxC
Receive
W/REQ
Request
W/REQ
Wait
SYNC
Output
INT
TRxC,RTxC
Transmit
W/REQ
Request
W/REQ
Wait
DTR/REQ
Request
INT
CTS,DCD
SYNC
Input
INT
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
86
Table 45 describes the Z80230 system timing parameter details.
Z85230 AC Characteristics
Figure 29 on page 87 illustrates the Z85230 Read and Write Timing Diagram. Figure 30
on page 88 illustrates the Z85230 Reset Timing Diagram. Figure 31 on page 88 illustrates
the Z85230 Interrupt Acknowledge Timing Diagram. Figure 32 on page 88 illustrates the
Z85230 Cycle Timing Diagram.
Table 45. Z80230 System Timing Table
No. Symbol Parameter
10 MHz 16 MHz
NotesMin. Max. Min. Max.
1 TdRXC(REQ) RxC High to W/REQ Valid 13 17 13 17 2, 5
2 TdRXC(W) RxC High to Wait Inactive 13 19 13 19 1, 2, 5
3 TdRXC(SY) RxC High to SYNC Valid 9 12 9 12 2, 5
4 TdRXC(INT),
Z80230
RxC High to INT Valid 13
2
17
3
13
2
17
3
1, 2, 4
5 TdTXC(REQ) TxC Low to W/REQ Valid 11 14 11 14 3, 5
6 TdTXC(W) TxC Low to Wait Inactive 8 14 8 14 1, 3, 5
7 TdTXC(DRQ) TxC Low to DTR/REQ Valid 3, 5
8 TdTXC(INT),
Z80230
TxC Low to INT Valid 7
2
9
3
7
2
9
3
1, 3, 4
9 TdSY(INT) SYNC to INT Valid 2
+2
6
+3
2
+2
6
+3
1, 5
10 TdEXT(INT),
Z80230
DCD or CTS to INT Valid 23 381, 4
Notes:
1. Open-drain output, measured with open-drain test load.
2. RxC is RTxC or TRxC, whichever is supplying the receive clock.
3. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
4. Units equal to AS.
5. Units equal to TcPc.
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
87
Figure 29. Z85230 Read/Write Timing Diagram
1
234
5
6
7
89
10
11 12
10 13 14 15
16
17
18
19 20 21
22
23 24
25 26
27
28
303129
32
33
35
34
36
37
INT
DTR/REQ
Request
W/REQ
Request
W/REQ
Wait
D7–D0
Write
WR
D7–D0
Read
RD
CE
INTACK
A/B, D/C
PCLK
Active Valid
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
88
Figure 30. Z85230 Reset Timing Diagram
Figure 31. Z85230 Interrupt Acknowledge Timing Diagram
Figure 32. Z85230 Cycle Timing Diagram
46 47
48
WR
RD
10 15
14
10 38
39
23
41 40 26
42
43 44
45
24
PCLK
INTACK
RD
D 7–D0
IEI
IEO
INT
Active Valid
49
CE
RD or WR
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
89
Table 46 describes the Z85230 Read and Write AC characteristics details.
Table 46. Z85230 AC Characteristics
No Symbol Parameter
8.5 MHz 10 MHz 16 MHz 20 MHz
NotesMin Max Min Max Min Max Min Max
1 TwPCl PCLK Low Width 45 1000 40 1000 26 1000 22 1000 6
2 TxPCh PCLK High Width 45 1000 40 1000 26 1000 22 1000 6
3 TfPC PCLK Fall Time 10 10 5 5 6
4 TrPC PCLK Rise Time 10 10 5 5 6
5 TcPc PCLK Cycle Time 118 2000 100 2000 61 2000 50 2000 6
6 TsA Address to WR fall
Setup Time
66 50 35 30 6
7 ThA(WR) Address to WR
Rise Hold Time
00006
8 TsA(RD) Address to RD Fall
Setup Time
66 50 35 30 6
9 ThA(RD) Address to RD
Rise Hold Time
00006
10 TsIA(PC) INTACK to PCLK
Rise Setup Time
20 20 15 15 6
11 TsIAi(WR) INTACK to WR
Fall Setup Time
140 130 70 65 1, 6
12 ThIA(WR) INTACK to WR
Rise Hold Time
00006
13 TsIAi(RD) INTACK to RD Fall
Setup Time
140 130 70 65 1, 6
14 ThIA(RD) INTACK to RD
Rise Hold Time
00006
15 ThIA(PC) INTACK to PCLK
Rise Hold Time
38 30 15 15 6
16 TsCEI(WR) CE Low to WR Fall
Setup Time
00006
17 ThCE(WR) CE to WR Rise
Hold Time
00006
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
90
18 TsCEh(WR) CE High to WR
Fall Setup Time
58 58 38 25 6
19 TsCEI(RD) CE Low to RD Fall
Setup Time
00001, 6
20 ThCE((RD) CE to RD Rise
Hold Time
00001, 6
21 TsCEh(RD) CE High to RD Fall
Setup Time
58 50 30 25 1, 6
22 TwRDI RD Low Width 145 125 70 65 1, 6
23 TdRD(DRA) RD Fall to Read
Data Active Delay
00006
24 TdRDr(DR) RD Rise to Data
Not Valid Delay
00006
25 TdRDI RD Fall to Read
Data Valid Delay
135 120 70 65 6
26 TdRD(DRz) RD Rise to Read
Data Float Delay
38 35 30 30 6
27 TdA(DR) Addr to Read Data
Valid Delay
210 180 100 90 6
28 TwWRI WR Low Width 145 125 75 65 6
29 TdWR(DW) WR Fall to Write
Data Valid Delay
20 20 20 20 6
30 ThDW(WR) Write Data to WR
Rise Hold Time
00006
31 TdWR(W) WR Fall to Wait
Valid Delay
168 100 50 50 3, 6
32 TdRD(W) RD Fall to Wait
Valid Delay
168 100 50 50 3, 6
33 TdWRf(REQ
)
WR Fall to W/REQ
not Valid Delay
168 100 50 50 6
34 TdRDf(REQ) RD Fall to WR/
REQ Not Valid
Delay
168 100 50 50 5,6
Table 46. Z85230 AC Characteristics (Continued)
No Symbol Parameter
8.5 MHz 10 MHz 16 MHz 20 MHz
NotesMin Max Min Max Min Max Min Max
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
91
35a TdWRr(REQ
)
WR Fall to DTR/
REQ Not Valid
44447
35b TdWRr(REQ
)
WR Fall to DTR/
REQ Not Valid
168 100 50 50 5, 6
36 TdRDr(REQ) RD Rise to DTR/
REQ Not Valid
Delay
NA NA NA NA 6
37 TdPC(INT) PCLK Fall to INT
Valid Delay
500 320 175 160 6
38 TdIAi(RD) INTACK to RD Fall
(ACK) Delay
1459050454, 6
39 TwRDA RD (Acknowledge)
Width
145 125 75 65 6
40 TdRDA(DR) RD Fall (ACK) to
Read Data Valid
Delay
135 120 70 60 6
41 TsIEI(RDA) IEI to RD Fall
(ACK) Setup Time
95 95 50 45 6
42 ThIEI(RDA) IEI to RD Rise
(Ack) Hold Time
00006
43 TdIEI(IEO) IEI to IEO Delay
Time
95 90 45 40 6
44 TdPC(IEO) PCLK Rise to IEO
Delay
195 175 80 80 6
45 TdRDA(INT) RD Fall to INT
Inactive Delay
480 320 200 180 3, 6
46 TdRD(WRQ) RD Rise to WR
Fall Delay for No
Reset
15 15 10 10 6
47 TdWRQ(RD) WR Rise to RD
Fall Delay for No
Reset6
15 15 10 10 6
48 TwRES WR and RD Low
for Reset
145 100 75 65 6
Table 46. Z85230 AC Characteristics (Continued)
No Symbol Parameter
8.5 MHz 10 MHz 16 MHz 20 MHz
NotesMin Max Min Max Min Max Min Max
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
92
49 Trc Valid Access
Recovery Time
44442, 7
Note:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Parameter applies only between transactions involving the ESCC.
3. Open-drain output, measured with open-drain test load.
4. Parameter is system-dependent. For any ESCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsIEI(RDA) for the ESCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies to enhanced Request mode only (WR7’ bit 4=1)
6. Units in nanoseconds.
7. Units in TcPc.
Table 46. Z85230 AC Characteristics (Continued)
No Symbol Parameter
8.5 MHz 10 MHz 16 MHz 20 MHz
NotesMin Max Min Max Min Max Min Max
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
93
Figure 33 illustrates the Z85230 General Timing Diagram
Figure 33. Z85230 General Timing Diagram
1
2
3
45 6 7
89
10
11 12
13
14 15
16
17
18 19
20
21 22
23 24
SYNC
Input
CTS,DCD
TRxC
RTxC
TRxC
Output
TxD
T
RxC,RTxC
Transmit
SYNC
External
RxD
R
TxC,TRxC
Receive
W/REQ
Wait
W/REQ
Request
PCLK
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
94
Table 47 describes the Z85230 general timing characteristics details. Table 48 describes
the Z85230 Read/Write Timing characteristics details.
Table 47. Z85230 General Timing Table
No Symbol Parameter
8.5 MHz 10 MHz 16 MHz 20 MHz
Min Max Min Max Min Max Min Max Notes
1 TdPC(REQ) PCLK to W/REQ
Valid
250 200 80 70 9
2 TdPC(W) PCLK to Wait
Inactive
350 300 180 170 9
3 TsRXC(PC) RxC to PCLK
Setup Time
NA NA NA NA 1, 4, 9
4 TsRXD(RXCr
)
RxD to RXC
Setup Time
00001, 9
5 ThRXD(RxCr
)
RxD to RXC
Hold Time
150 125 50 45 1, 9
6 TsRXD(RXCf
)
RxD to RXC
Setup Time
00001, 5, 9
7 ThRXD(RXCf
)
RXD to RXC
Hold Time
150 125 50 45 1, 5, 9
8 TsSY(RXC) SYNC to RXC
Setup Time
–200 –150 –100 –90 1, 9
9 ThSY(RXC) SYNC to RXC
Hold Time
55551, 10
10 TsTXC(PC) TxC to PCLK
Setup Time2,4
NA NA NA NA
11 TdTXCf(TXD
)
TxC to TxD
Delay
190 150 80 70 2, 9
12 TdTxCr(TXD) TxC to TxD
Delay
190 150 80 70 2, 5, 9
13 TdTXD(TRX) TxD to TRxC
Delay
200 140 80 70 9
14 TwRTXh RTxC High
Width
130 120 80 70 6, 9
15 TwRTXI RTxC Low Width 130 120 80 70 6, 9
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
95
16a TcRTX RTxC Cycle
Time
472 400 244 200 6, 7, 9
16b TxRX(DPLL) DPLL Cycle
Time Min.
50 50 31 31 7, 8, 9
17 TcRTXX Crystal Osc.
Period
125 1000 100 1000 61 1000 61 1000 3, 9
18 TwRTXh TRxC High
Width
130 120 80 70 5, 9
19 TwTRXI TRxC Low Width 130 120 80 70 6, 9
20 TcTRX TRxC Cycle
Time
472 400 244 200 6, 7, 9
21 TwEXT DCD or CTS
Pulse Width
200 120 70 60 9
22 TwSY SYNC Pulse
Width
200 120 70 60 9
Note:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
3. Both RTxC and SYNC have 30pF capacitors to ground connected to them.
4. Synchronization of RxC to PCLK is eliminated in divide by four operation.
5. Parameter applies only to FM encoding/decoding.
6. Parameter applies only for transmitter and receiver; DPLL and BRG timing requirements are identical to case
PCLK requirements.
7. The maximum receive or transmit data rate is 1/4 PCLK.
8. Applies to the DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock must have a
50% duty cycle.
9. Units in nanoseconds.
10. Units in TcPc.
Table 47. Z85230 General Timing Table (Continued)
No Symbol Parameter
8.5 MHz 10 MHz 16 MHz 20 MHz
Min Max Min Max Min Max Min Max Notes
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
96
Figure 34 illustrates the Z85230 System Timing Diagram. Table 48 on page 97 describes
the Z85230 System Timing Characteristics.
Figure 34. Z85230 System Timing Diagram
RTxC,TRxC
Receive
W/REQ
Request
W/REQ
Wait
SYNC
Output
INT
RTxC,TRxC
Transmit
W/REQ
Request
W/REQ
Wait
DTR/REQ
Request
INT
CTS,DCD
SYNC
Input
INT
1
2
3
4
5
6
7
8
9
10
PS005303-0907 Electrical Characteristics
Z85230/Z80230
Product Specification
97
Table 48. Z85230 System Timing Characteristics
No Symbol Parameter
8.5 MHz 10 MHz 16 MHz 20 MHZ
MinMaxMinMaxMinMaxMinMaxNotes
1 TdRXC(REQ) RxC to W/REQ
Valid
13 17 13 17 13 17 13 18 2, 4
2 TdRXC(W) RxC to Wait
Inactive
13 17 13 17 13 17 13 18 1, 2, 4
3 TdRXC(SY) RxC to SYNC
Valid2
47 47 47 48 2, 4
4 TdRXC(INT) RxC to INT Valid 15 21 15 21 15 21 15 22 1, 2, 4
5 TdTXC(REQ) TxC to W/REQ
Valid
8 11 8 11 8 11 8 12 3, 4
6 TdTXC(W) TxC to Wait
Inactive
8 14 8 14 8 14 8 15 1, 3, 4
7 TdTXC(DRQ) TxC to DTR/REQ
Valid
7 10 7 10 7 10 7 11 3, 4
8 TdTXC(INT) TxC to INT Valid 9 13 9 13 9 13 9 14 1, 3, 4
9 TsSY(INT) SYNC to INT Valid26 26 26 27 1, 4
10 TdEXT(INT) DCD or CTS to
INT Valid
38 38 38 39 1, 4
Notes:
1. Open-drain output, measured with open-drain test load.
2. RxC is RTxC or TRxC, whichever is supplying the receive clock.
3. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
4. Units in TcPc.
PS005303-0907 Z80230/Z85230 Errata
Z85230/Z80230
Product Specification
98
Z80230/Z85230 Errata
The current revision of Zilog’s ESCC has six known bugs. This section identifies these
bugs and provides workarounds.
IUS Problem Description
The IUS problem occurs under the following conditions:
•
SDLC 10x19 Status FIFO is enabled
•
Interrupts on Receive Special Conditions Only
This mode is intended for an application where received characters are read by a DMA
controller. EOF is treated differently from other special conditions (for example, parity
error, overrun error and CRC error).
When EOF is detected, the following conditions occur:
•
A Receive Character Available (RCA) interrupt is generated, rather than the Special
Conditions interrupt, as in other operating modes.
•
The data FIFO is not locked, as in other operating modes, and is known as the Anti-
Lock feature.
This feature allows the processor to service the EOF interrupt with more latency. Immedi-
ate attention from the processor is not necessary because the data FIFO is not locked.
Incoming data can still be delivered to the Receive FIFO and not get lost. It also allows for
operation with no servicing of the interrupt.
When the EOF interrupt (RCA interrupt) is serviced, the processor must use the Reset
Highest IUS command to clear the EOF.
If an EOF interrupt occurs when another lower priority interrupt is enabled (for example,
Ext/Status interrupt is being serviced) the Reset Highest IUS command issued by the
lower priority ISR (to clear out the pending interrupt) can accidentally clear the pending
EOF interrupt.
The Reset Highest IUS command clears the IP bit related to the EOF (in this mode, the
RCA IP bit) regardless of the priorities of the pending interrupts. This action causes errors
under the following circumstances:
•
Another ESCC interrupt is being serviced (for example, an Ext/Status interrupt for
Transmitter Underrun in Full Duplex operation)
•
The DMA reads a byte marked with EOF. The corresponding IP bit is set to 1 and the
INT line goes Low (highest priority interrupt in the daisy chain).
PS005303-0907 Z80230/Z85230 Errata
Z85230/Z80230
Product Specification
99
•
The processor does not acknowledge this interrupt because it is servicing another
interrupt.
•
The processor finishes servicing the other interrupt and uses the Reset Highest IUS
command.
•
The IP bit reset corresponding to the EOF, and the EOF interrupt is lost.
IUS Problem Solutions
The following methods can be used to work around the previously described problems.
•
Alternate Operating Mode–A similar operating mode can be used to achieve the same
functionality with minimum code modifications. The ESCC must operate in Receive
Interrupts on First Character and Special Condition, instead of Receive Interrupt on
Special Condition Only.
In this mode, the Anti-Lock feature is not enabled. The FIFO is locked after the last
character of a frame has been transferred, and the interrupt condition does not
disappear until after an Error Reset command is issued to the ESCC. No Reset
Highest IUS command can clear any IP bit.
•
Daisy Chain– This workaround uses the following two conditions:
–
The EOF interrupt is the highest priority interrupt if only one channel is used.
–
Channel A is the only channel issuing interrupts.
If both conditions are satisfied, allowing nested interrupts can solve the problem.
The processor servicing an interrupt on the daisy chain must be interruptible again
from another interrupt of higher priority on that same daisy chain.
•
RR7 Register–This workaround is applicable if the EOF interrupt is used only to
notify another part of the software that there has been another frame received:
–
Read RR7 after issuing the Reset IUS command.
–
Check bit 6 of RR7. This bit, when set, indicates that the SDLC frame
FIFO contains a valid frame. Although one interrupt might have been lost
(IP reset) by the Reset IUS command, bit 6 of RR7 always indicates that at
least one frame is available in the frame FIFO. If bit 6 of RR7 is 1, notify
the concerned part of the software that at least one frame is available in
the frame FIFO.
When the SDLC FIFO is enabled and Receive Interrupts on Special Conditions Only is
selected, software checks that there is a Receive Character Available interrupt, which is
generated by DMA reading an EOF character, and before issuing the Reset Highest
IUS command. Otherwise, the EOF interrupt conditions are cleared by that command.
PS005303-0907 Z80230/Z85230 Errata
Z85230/Z80230
Product Specification
100
Figure 35 illustrates the procedure for resetting highest IUS.
Figure 35. Resetting Highest IUS from Lower Priority
RTS Problem Description
The ESCC (Z80230/Z85230) contains a functional problem in Automatic RTS Deactiva-
tion (see Figure 36 on page 101).
This mode is intended for SDLC applications where the RTS signal from the ESCC is used
to enable a line driver in multi-drop line communications.
Before the frame transmission, RTS is asserted by an Activate RTS command (ER5 bit1
equals 0).
After the last data bit of a frame is sent, a Transmit Underrun interrupt is requested. A
Deactivate RTS command is issued (WR5 bit 1 equals 1) to deactivate the RTS signal to
turn off the line driver after the multiple-frame packet is sent.
On the SCC, the processor must monitor the data line to ensure that the frame has been
sent before it issues the Deactivate RTS command.
On the ESCC, RTS can be programmed to deactivate automatically after the frame is sent.
If the following sequence is performed, additional monitoring is not required:
1. Enable Automatic RTS Deactivation (WR7’ bit 2 equals 1).
INT
Ext/Status IP
RCA IP
Ext/Status IUS
Ext/Status
Interrupt
DMA read
EOF
Reset Highest
IUS from
Ext/Status
Handler
Resetting highest IUS from lower priority interrupt clears the EOF (RCA) interrupt.
PS005303-0907 Z80230/Z85230 Errata
Z85230/Z80230
Product Specification
101
2. Enable the CRC/Flag on Underrun (WR10 bit 2 equals 0).
3. Issue a Deactivate RTS command in the Transmit Underrun ISR. The RTS signal
deactivates automatically after the closing flag disappears.
The Automatic RTS Deactivation command works for a single frame and for two
consecutive frames back-to-back. This command does not work with more than two back-
to-back frames.
In the latter condition, if the Deactivate RTS command is issued at the beginning of the
Transmit Underrun ISR. RTS is deactivated after the CRC is gone, but before the clos-
ing flag is sent. The final frame is not concluded, and is corrupted.
RTS Problem Solutions
A workaround for the RTS problem is not to send back-to-back frames. Idle time is
inserted between frames.
There is, however, a limitation to this workaround in that the system throughput is reduced
by the idle time inserted between the frames.
Figure 36 illustrates Automatic RTS Deactivation.
Figure 36. Automatic RTS Deactivation
Automatic TxD Forced High Problem Description
If WR10 is programmed with bits 6 and 5 equal to 01 (NRZI), bit 3 equals 1 (Mark Idle)
and WR4 bits 5 and 4 equal 10 (SDLC), the TxD pin is forced High after detecting the last
bit of the closing flag at the falling edge of TxC. This feature does not work if back-to-
RTS Frame n-1 Frame n
TxD Flag Frame n-1 CRC Flag Frame n CRC Flag
RTS Frame n-1 Frame n
TxD Flag Frame n-1 CRC Flag Frame n CRC Flag
RTS deactivates correctly (after the closing flag)
if only one back-to-back frame is sent.
RTS deactivates too soon, after the CRC, but before the closing
flag if more than two back-to-back frames are sent.
RTS must deactivate
after the last closing
flag is gone.
PS005303-0907 Z80230/Z85230 Errata
Z85230/Z80230
Product Specification
102
back frames are sent. The TxD output is automatically forced High for eight bit-times and
the first byte of the second frame is corrupted. In a multiple-frame transmission, a zero (0)
bit is inserted before the opening flag of the second frame.
Automatic TxD Forced High Problem Solutions
Send back-to-back frames in FLAG IDLE mode, because the Automatic TxD Forced High
feature creates problems only if all the following conditions are true:
•
Back-to-back frame transmission
•
NRZI
•
Mark Idle
Setting the system in Flag Idle mode (WR10 bit 3 equals 0) in frame transmission allows
back-to-back frames to be sent without any data corruption.
SDLC FIFO Overflow Problem Description
In SDLC mode, bit 7 of RR7 (FIFO Overflow status bit) is set if an 11th frame ends while
the FIFO is full (that is, 10 frames have accumulated in the Status FIFO and have not yet
been read by the processor). Under this circumstance, the status FIFO is locked and no
data can be written to the Status FIFO until bit 7 of RR7 is reset.
If the ESCC is set up in ANTI-LOCK mode (that is, the SDKC FIFO is used when
Receive Interrupts on Special Condition Only is enabled), the only method of resetting bit
7 of RR7(the FIFO Overflow bit) is to reset and set WR15 bit 2 (SDLC FIFO Enable Bit).
This action causes the SDLC FIFO to reset and all the SDLC frame information is lost.
With no Anti-Lock feature, the FIFO Overflow status bit is reset if the SDLC FIFO is
read.
If the ESCC is in NRZI and Mark Idle in back-to-back frame transmission, (one the FIFO
Overflow bit RR7 bit 7) is set, the only method of resetting the status is to reset and set
WR15 bit 2. This action causes the SDLC FIFO to reset and the unprocessed frame infor-
mation stored in the SDLC FIFO is lost.
SDLC FIFO Overflow Problem Solution
Do not use Receive Interrupts on Special Conditions Only and Mark Idle if there is a pos-
sibility of Status FIFO Overflow.
Default RR0 Value Problem Description
RR7 bit 7, the Break/Abort status bit, does not always clear after reset.
Default RR0 Value Problem Solution
Ignore the first bit 7 value read from RR0 after reset.
PS005303-0907 Z80230/Z85230 Errata
Z85230/Z80230
Product Specification
103
Default RR10 Value Problem Description
RR10 bit 6, the 2 clock missing bit, is sometimes erroneously set to indicate that the DPLL
detects a clock edge in two successive tries after hardware reset.
Default RR10 Value Problem Solution
Ignore the first bit 7 value Read from RR10 after reset.
CRC Problem Description
The CRC can not be interpreted from the Receive FIFO when one or two residue bits are
sent. The CRC value is received and checked correctly but is not loaded to the Receive
FIFO. The two types of CRC problems are described below:
•
Two Residue bits (Residue code is 000)
The last three bytes of the Receive FIFO read:
Bits 6 and 7 of the CRC are lost.
•
One Residue Bit (Residue code is 111)
The last three bytes of the Receive FIFO read:
Bit 7 of the CRC is lost.
The CRC is received and loaded into the Receive FIFO in other situations (that is, the 0, 3,
4, 5, 6, and 7 residue bits).
The Residue code, RR1 bits 3, 2, and 1, is reported independently of the number of residue
bits sent.
CRC Problem Solution
Ignore the CRC value read from the Receive FIFO if one or two residue bits are sent.
D7 D6 D5 D4 D3 D2 D1 D0
C5 C4 C3 C2 C1 C0 D9 D8
C15C14C13C12C11C10C9 C8
D7 D6 D5 D4 D3 D2 D1 D0
C6 C5 C4 C3 C2 C1 C0 D8
C15C14C13C12C11C10C9 C8
PS005303-0907 Package Information
Z85230/Z80230
Product Specification
104
Package Information
Figure 37 illustrates the 40-pin Dual-Inline Package (DIP) and Figure 38 on page 105
illustrates the 44-pin Plastic Leaded Chip Carrier (PLCC) package.
Figure 37. 40-Pin DIP Package Diagram
1
20
21 40
E1
D
SBB1
Q1
A1
A2
L
E
eA
SYMBOL
MILLIMETER INCH
MIN MAX MIN MAX
A1 0.51 0.81 .020 .032
A2 3.25 3.43 .128 .135
B 0.38 0.53 .015 .021
B1 1.02 1.52 .040 .060
C 0.23 0.38 .009 .015
D 52.07 52.58 2.050 2.070
E 15.24 15.75 .600 .620
E1 13.59 14.22 .535 .560
2.54 TYP .100 TYP
eA 15.49 16.51 .610 .650
L 3.18 3.81 .125 .150
Q1 1.52 1.91 .060 .075
S 1.52 2.29 .060 .090
Controlling Dimensions: Inch
E
E
C
PS005303-0907 Package Information
Z85230/Z80230
Product Specification
105
Figure 38. 44-Pin PLCC Package Diagram
0.020/0.014
0.045/0.025
0.032/0.026
R 1.14/0.64
.028/.020
0.51/0.36
0.81/0.66
D2
EE1
3. DIMENSION : MM
2. LEADS ARE COPLANAR WITHIN 0.004".
1. CONTROLLING DIMENSION : INCH
NOTES:
17
18
INCH
29
28
D
D1
61
7
45° 40
39
A1
A
0.71/0.51
1.321/1.067
0.052/0.042
e
DIM. FROM CENTER TO CENTER OF RADII
C
h
M
D/E
0.650
0.600
D1/E1
e
D2
1.27 BSC
16.51
15.24 16.00
16.66
0.050 BSC
0.630
0.656
MIN
0.168
0.095
0.685
SYMBOL
A1
A
MILLIMETER
4.27
2.41
17.40
MIN
2.92
17.65
4.57
MAX
0.115
0.695
0.180
INCH
MAX
M
PS005303-0907 Ordering Information
Z85230/Z80230
Product Specification
106
Ordering Information
Order the required ESCC from Zilog using the following part details. For more informa-
tion on ordering, please consult your local Zilog sales offices. The Zilog website
(www.zilog.com) lists all the regional offices and provides additional product information.
Z85230
Z80230
Z85230 Available Packages
8 MHz Z85230 Z8523008PSG
Z8523008VSG
Z8523008PEG
Z8523008VEG
10 MHz Z85230 Z8523010PSG
Z8523010VSG
Z8523010PEG
Z8523010VEG
16 MHz Z85230 Z8523016PSG
Z8523016VSG
Z8523016PEG
Z8523016VEG
20 MHz Z85230 Z8523020PSG
Z8523020VSG
Z80230 Available Packages
10 MHz Z80230 Z8023010PSG
Z8023010VSG
16 MHz Z80230 Z8023016PSG
Z8023016VSG
PS005303-0907 Ordering Information
Z85230/Z80230
Product Specification
107
Part Number Suffix Designation
Z 80230 16 P S G
Environmental Flow
G = Green Plastic Packaging
Compound
Temperature
E = -40°C to +100°C
S = 0°C to +70°C
Package
P = Plastic DIP (PDIP)
V = Plastic LCC (PLCC)
Speed
8 = 8.0 MHz
10 = 10.0 MHz
16 = 16.384 MHz
20 = 20 MHz
Product Number
Zilog Prefix
Z85230/Z80230
Product Specification
PS005303-0907 Index
108
Index
A
abort character 18
absolute maximum ratings 75
AC characteristics 77
AC characteristics table, Z85230 89
AC characteristics, Z85230 86
asynchronous receive mode 4
auto echo and logical loopback 21
auto enable 4
automatic EOM reset 28
B
baud rate generator 19
bisync 4, 16
block transfer, CPU/DMA 15
C
capacitance 76
character
abort 18
EOP 18
code
NRZ 18
NRZI 18
command
reset highest IUS 28
reset Tx CRC generator 28
reset Tx/underrun latch 28
counter
transmit clock 5
CRC problem
description 103
solution 103
CRC reception in SDLC mode 26
Customer Feedback Form 112
D
data communications capabilities 15
data encoding 20
DC characteristics 77
default RR0 value problem
description 102
solution 102
default RR10 value problem
description 103
solution 103
device type identification 24
diagram
40-pin DIP package 104
44-pin PLCC package 105
automatic RTS deactivation 101
cycle timing, Z85230 88
data encoding methods 20
detecting 5-or 7-bit characters 16
DPLL Outputs 27
ESCC protocols 15
general timing, Z80230 80
general timing, Z85230 93
interrupt acknowledge cycle timing,
Z80230 72
interrupt acknowledge cycle timing,
Z85230 74
interrupt acknowledge timing, Z80230 79
interrupt acknowledge timing, Z85230 88
interrupt priority schedule 13
read cycle timing, Z80230 71
read cycle timing, Z85230 73
read/write timing, Z80230 78
read/write timing, Z85230 87
receive data path 9
reset timing, Z80230 79
reset timing, Z85230 88
resetting highest IUS from lower priority
100
SDLC frame status FIFO 29
SDLC loop 18
standard and open-drain test conditions 76
Z85230/Z80230
Product Specification
PS005303-0907 Index
109
system timing, Z80230 85
system timing, Z85230 97
transmit data path 8
TxIP latching 27
write cycle timing,Z85230 74
Z80230 pin assignments 3
Z80230 pin functions 2
Z85230 pin assignments 3
Z85230 pin functions 2
digital phase-locked loop 5, 19
DPLL counter Tx clock source 27
E
encoding, data 20
end of poll (EOP) character 18
enhancements
receive FIFO, 8 bytes 22
transmit FIFO, 4 bytes 22
Z80230 and Z85230 22
EOP 18
errata 98
ESCC
programming 32
read registers 53
write registers 32
external synchronization 4
F
FIFO
anti-lock feature 31
enable/disable 30
read operation 30
write operation 31
functional description 8
G
general timing characteristics table, Z80230 81
general timing table, Z85230 94
I
identification, device types 24
IE 12
input/output capabilities 9
INTACK 13
interface timing, Z80230 70
internal synchronization 4
interrupt acknowledge cycle timing
Z80230 71
Z85230 74
interrupts 12
external/status 13, 14
interrupt cknowledge (INTACK) 13
interrupt enable (IE) 12
interrupt on all receive characters or special
receive conditions 14
interrupt on first receive character or spe-
cial receive condition 14
interrupt on special receive conditions only
14
interrupt pending (IP) 12, 13
interrupt under service (IUS) 12, 13
receive 13
receive character available 22
transmit 13
transmit buffer empty 22, 24
Tx underrun/EOM 28
IUS latch 28
IUS problem
description 98
solutions 99
L
latch
ISU 28
RR0 27
TxIP 26
local loopback 21
Z85230/Z80230
Product Specification
PS005303-0907 Index
110
M
mark idle 26
mode
1x 18
asynchronous receive 4
auto echo 21
request on transmit 24
SDLC 17
SDLC loop 18
SDLC status FIFO 19
synchronous 16
monosync 4, 16
N
no vector (NV) 28
NV 28
O
ordering information 106
P
package information 104
part number descriiption 107
pin assignments
Z80230 3
Z85230 3
pin descriptions 1
pin functions
Z80230 2
Z85230 2
pins, common
CTSA 4
CTSB 4
DCDA 4
DCDB 4
DTR/REQA 4
DTR/REQB 4
IEI 5
IEO 5
INT 6
INTACK 6
PCLK 5
RTSA 4
RTSB 4
RTxCA 5
RTxCB 5
RxDA 5, 16
RxDB 5, 16
SYNCA 4
SYNCB 4
TRxCA 5
TRxCB 5
TxDA 5
TxDB 5
W/REQA 5
W/REQB 5
pins, Z80230 exclusive
A7-A0 6
AS 7
CS0 7
CS1 7
DS 7
R/W 6
pins, Z85230 exclusive
CE 6
Channels A/B 6
D/C 6
D7-D0 6
RD 6
WR 6
polynomial, SDLC CRC 17
R
ratings, absolute maximum 75
read cycle timing
Z80230 71
Z85230 73
read register (RR) 10
read registers 53
Z85230/Z80230
Product Specification
PS005303-0907 Index
111
receive conditions 14
request on receive 22
request on transmit 22
request on transmit mode 24
reset highest IUS command 28
reset Tx CRC generator command 28
reset Tx/underrun EOM latch 28
RR 10
RR0 latch 27
RTS problem
description 100
solutions 101
S
SDLC
CRC polynomial 17
FIFO frame status enhancement 28
loop mode 18
mode, CRC reception 26
mode, TxD forced high 26
status FIFO 19
status FIFO anti-lock feature 31
transmit data interrupt response 28
SDLC FIFO overflow problem
description 102
solutions 102
SDLC mode 17
software interrupt acknowledge 28
standard test conditions 75
synchronization
external 4
internal 4
synchronous modes 16
system timing characteristics table, Z85230 97
T
timing, Z85230 72
transmit buffer empty interrupt 22
transmit clock counter 5
Tx underrun/EOM interrupt 28
TxD forced high in SDLC mode 26
TxD forced high problem
description 101
solutions 102
TxIP latch 26
V
vector includes status (VIS) 28
VIS 28
W
WR 10
WR7’ 9, 23
write cycle timing
Z80230 70
Z85230 73
write register (WR) 10
write register 7 prime (WR&’) 23
write register 7 prime (WR7’) 9
bit 0 25
bit 1 25
bit 2 25
bit 3 25
bit 4 24
bit 5 24
bit 6 24
bit 7 24
write registers 32
PS005303-0907 Customer Support
Z85230/Z80230
Product Specification
112
Customer Support
For answers to technical questions about the product, documentation, or any other
issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at
http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, please visit
Zilog’s Technical Support at http://support.zilog.com.
