TPA5051
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FEATURES APPLICATIONS
DESCRIPTION
SIMPLIFIED APPLICATION DIAGRAM
BCLK1
LRCLK1
DATA1 DATA_OUT1
3
3.3V
BCLK1
LRCLK1
DATA1
TPA5051
Digital Amplfiier
SCLK
AudioProcessor
SCLK
BCLK1
LRCLK1
DATA1
SDA
SCL
ADDx
(2:0)
I CDelay
Control
2
VDD
GND
DATA2
DATA2
BCLK2
BCLK2
LRCLK2LRCLK2
DATA2
BCLK2
LRCLK2
DATA_OUT2
TAS5504A
+TAS5122
TAS3108
or
ATSC
Processor
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I
2
C CONTROL
•High Definition Lip-Sync Delay•Digital Audio Format: 16-24-bit I
2
S,Right-Justified, Left-Justified
•Flat Panel TV Lip-Sync Delay•Home Theater Rear Channel Effects•I
2
C Bus Controlled
•Wireless Speaker Front-Channel•Dual Serial Input Ports
Synchronization•Delay Time: 85 ms/ch at fs = 48 kHz•Delay Resolution: One Sample•Delay Memory Cleared on Power-Up or After
The TPA5051 accepts two serial audio inputs,Delay Changes
buffers the data for a selectable period of time, and– Eliminates Erroneous Data on Output
outputs the delayed audio data on two serial outputs.One device allows delay of up to 85 ms/ch (fs = 48•3.3 V Operation With 5 V Tolerant I/O and I
2
C
kHz) to synchronize the audio stream to the videoControl
stream in systems with complex video processing•Supports Audio Bit Clock Rates of 32 to 64 fs
algorithms. If more delay is needed, the devices canwith fs = 32 kHz–192 kHz
be connected in series. Independent clocks can be•No External Crystal or Oscillator Required
used for each audio input.– All Internal Clocks Generated From theAudio Clock•Independent Clocks for Each Audio Input•Surface Mount 4mm ×4mm, 16-pin QFNPackage
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PIN DESCRIPTIONS
BCLK1
DATA_OUT1
GND
VDD
ADD1
LRCLK1
SCL
DATA_OUT2
ADD0
ADD2
GND
DATA1
7
5
6
11
9
10
12
16
15
14
13
3
1
2
4
SDA
8
DATA2
LRCLK2
BCLK2
RSA (QFN)PACKAGE
(TOP VIEW)
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
ADD0 10 I I
2
C address select pin – LSB. 5V tolerant input.ADD1 11 I I
2
C address select pin. 5V tolerant input.ADD2 12 I I
2
C address select pin – MSB. 5V tolerant input.BCLK1
(1)
16 I Audio data bit clock input for serial input 1. 5V tolerant input.BCLK2
(1)
8 I Audio data bit clock input for serial input 2. 5V tolerant input.DATA1 2 I Audio serial data input for serial input 1. 5V tolerant input.DATA2 6 I Audio serial data input for serial input 2. 5V tolerant input.DATA_OUT1 15 O Delayed audio serial data output for channel 1.DATA_OUT2 9 O Delayed audio serial data output for channel 2.GND 5, 14 P Ground – All ground terminals must be tied to GND for proper operationLRCLK1
(1)
1 I Channel 1 left and right serial audio sampling rate clock (fs). 5V tolerant input.LRCLK2
(1)
7 I Channel 2 left and right serial audio sampling rate clock (fs). 5V tolerant input.SCL 3 I I
2
C communication bus clock input. 5V tolerant input.SDA 4 I/O I
2
C communication bus data input. 5V tolerant input.VDD 13 P Power supply interface.Connect to ground. Must be soldered down in all applications to properly secure device on theThermal Pad -
PCB.
(1) Left and right channels may use different BCLK frequencies as well as different LRCLK (fs) frequencies.
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FUNCTIONAL BLOCK DIAGRAM
DATA1
BCLK1
LRCLK1
INPUT
BUFFER
OUTPUT
BUFFER
DATA_OUT1
CONTROL
2
3
I C
2
ADDx(2:0)
DELAY
MEMORY
DELAY
MEMORY
DATA2
BCLK2
LRCLK2
DATA_OUT2
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
over operating free-air temperature (unless otherwise noted)
(1)
VALUE UNIT
V
DD
Supply voltage –0.3 to 3.6 VV
I
Input voltage DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] –0.3 to 5.5 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range –40 to 85 °CT
J
Operating junction temperature range –40 to 125 °CT
stg
Storage temperature range –65 to 125 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operations of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE T
A
≤25 °C DERATING T
A
= 70 °C T
A
= 85 °CPOWER RATING FACTOR POWER RATING POWER RATING
RSA 2.5 W 25 mW/ °C 1.375 W 1.0 W
(1) This data was taken using 1 oz trace copper and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal padmust be soldered to a thermal land on the printed-circuit board. See TI technical briefs SCBA01 D and SLUA271 for more informationabout using the QFN thermal pad.
MIN MAX UNIT
V
DD
Supply voltage VDD 3 3.6 VV
IH
High-level input voltage DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, SDA, 2 VADD[2:0]V
IL
Low-level input voltage DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, SDA, 0.8 VADD[2:0]T
A
Operating free-air temperature –40 85 °C
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DC CHARACTERISTICS
TIMING CHARACTERISTICS
(1) (2)
SCL
SDA
tw(H) tw(L)
tsu1 th1
SCL
SDA
th2 t(buf)
tsu2 tsu3
StartCondition StopCondition
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
T
A
= 25 °C, V
DD
= 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
DD
Supply current V
DD
= 3.3 V, fs = 48 kHz, BCLK = 32 ×fs 1.8 3 mAI
OH
High-level output current DATA_OUT1 = DATA_OUT2 = 2.6 V 5 13 mAI
OL
Low-level output current DATA_OUT1 = DATA_OUT2 = 0.4 V 5 13 mADATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL,
20 µASDA, Vi = 5.5V, VDD = 3VI
IH
High-level input current
ADD[2:0], Vi = 3.6V, VDD = 3.6V 5 µADATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, µAI
IL
Low-level input current 1SDA, ADD[2:0], Vi = 0V, VDD = 3.6V
For I
2
C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
Frequency, SCL No wait states 400 kHzt
w(H)
Pulse duration, SCL high 0.6 µst
w(L)
Pulse duration, SCL low 1.3 µst
su1
Setup time, SDA to SCL 100 nst
h1
Hold time, SCL to SDA 10 nst
(buf)
Bus free time between stop and start condition 1.3 µst
su2
Setup time, SCL to start condition 0.6 µst
h2
Hold time, start condition to SCL 0.6 µst
su3
Setup time, SCL to stop condition 0.6 µs
(1) V
Pull-up
= V
DD(2) A pull-up resistor ≤2 k Ωis required for a 5 V I
2
C bus voltage.
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions Timing
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Serial Audio Input Ports
APPLICATION INFORMATION
AUDIO SERIAL INTERFACE
AUDIO DATA FORMATS AND TIMING
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLKIN
Frequency, BCLK 32 ×fs, 48 ×fs, 64 ×fs 1.024 12.288 MHzt
su1
Setup time, LRCLK to BCLK rising edge 10 nst
h1
Hold time, LRCLK from BCLK rising edge 10 nst
su2
Setup time, DATA to BCLK rising edge 10 nst
h2
Hold time, DATA from BCLK rising edge 10 nsLRCLK frequency 32 48 192 kHzBCLK duty cycle 50%LRCLK duty cycle 50%BCLK rising edges between LRCLK rising edges LRCLK duty cycle = 50% 32 64 BCLK edges
Figure 3. Serial Data Interface Timing
The audio serial interface for the TPA5051 consists of two 3-wire synchronous serial ports. Each includes anLRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present onthe DATA line into the serial shift register of the audio interface. Serial data is clocked into the TPA5051 on therising edge of BCLK. LRCLK is the serial audio left/right word clock, operated at the sampling frequency, fs. It isused to latch serial data into the internal registers of the serial audio interface. BCLK can be operated at 32 to64 times the sampling frequency for right-justified, left-justified, and I
2
S formats. Generally, both LRCLK andBCLK should be synchronous to the system clock. However, the TPA5051 does not have a system clock, so theonly synchonization necessary is between BCLK and LRCLK.
The TPA5051 supports industry-standard audio data formats, including right-justified, I
2
S, and left-justified. Thedata formats are shown in Figure 4 . Data formats are selected using the I
2
C interface and register map (seeTable 1 ).
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LRCK
(2)I2SDataFormat;L-Channel=LOW,R-Channel=HIGH
MSB LSB
1/fS
(= 32fS,48fS, or64fS)
18-BitRight-Justified,BCK=48f Sor64fS
1/fS
(1) Right-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW
(3)Left-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW
MSB LSB
20-Bit Right-Justified,BCK=48f Sor64fS
MSB LSB
24-BitRight-Justified,BCK=48f Sor64fS
1/fS
(=32fS,48fS, or64fS)
(=32fS,48fS, or64fS)
MSB LSB
16-BitRight-Justified,BCK=32f S
16-BitRight-Justified,BCK=48f Sor64fS
MSB LSB
L-Channel R-Channel
BCK
DATA 14 15 16 1 2 3 14 15 16
14 15 16 1 2 3 14 15 16
16 17 18
DATA
DATA
DATA
DATA
1 2 3 16 17 18
18 19 20 1 2 3 18 19 20
22 23 24 1 2 3
MSB LSB
MSB LSB
MSB LSB
MSB LSB
1 2 3 14 15 16
1 2 3 14 15 16
1 2 3 16 17 18
1 2 3 18 19 20
22 23 24
MSB LSB
1 2 3 22 23 24
L-Channel R-ChannelLRCK
BCK
DATA 1 2 3 1 2
MSB
N–2 N
N–1
LSB
1 2 3
MSB
N–2 N
N–1
LSB
L-Channel R-Channel
LRCK
BCK
DATA 1 2 3 N–2 N
N–1 1 2 3 N–2 N
N–1 1 2
MSB LSB LSBMSB
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
Figure 4. Audio Data Formats
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GENERAL I
2
C OPERATION
Register(N)
8-BitDatafor 8-BitDatafor
Register(N+1)
SINGLE-AND MULTIPLE-BYTE TRANSFERS
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
The I
2
C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in asystem. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus isacknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the masterdevice driving a start condition on the bus and ends with the master device driving a stop condition on the bus.The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions.A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bittransitions must occur within the low time of the clock period. These conditions are shown in Figure 5 . Themaster generates the 7-bit slave address and the read/write (R/W) bit to open communication with anotherdevice and then wait for an acknowledge condition. The TPA5051 holds SDA low during acknowledge clockperiod to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence.Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices sharethe same signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. Whenthe bus level is 5 V, pull-up resistors between 1 k Ωand 2 k Ωin value must be used. For a bus level of 3.3 V,higher resistor values, such as 10 k Ω, may be used.
Figure 5. Typical I
2
C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When thelast word transfers, the master generates a stop condition to release the bus. A generic data transfer sequenceis shown in Figure 5 .
The 7-bit address for the TPA5051 is selectable using the 3 address pins (ADD0, ADD1, ADD2). Table 1 liststhe 8 possible slave addresses.
Table 1. I
2
C Slave Address
SELECTABLE ADDRESS BITSFIXED ADDRESS
(4 MSB bits)
ADD2 ADD1 ADD0
1101 0 0 01101 0 0 11101 0 1 01101 0 1 11101 1 0 01101 1 0 11101 1 1 01101 1 1 1
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA5051 responds with data, a byte at a time, starting at the registerassigned, as long as the master device continues to respond with acknowledges.
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SINGLE-BYTE WRITE
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register DataByte
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
Register
SINGLE-BYTE READ
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
The TPA5051 supports sequential I
2
C addressing. For write transactions, if a register is issued followed by datafor that register and all the remaining registers that follow, a sequential I
2
C write transaction has taken place. ForI
2
C sequential write transactions, the register issued then serves as the starting point, and the amount of datasubsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
As shown is Figure 6 , a single-byte data write transfer begins with the master device transmitting a startcondition followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction ofthe data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I
2
Cdevice address and the read/write bit, the TPA5051 responds with an acknowledge bit. Next, the mastertransmits the register byte corresponding to the TPA5051 internal memory address being accessed. Afterreceiving the register byte, the TPA5051 again responds with an acknowledge bit. Next, the master devicetransmits the data byte to be written to the memory address being accessed. After receiving the data byte, theTPA5051 again responds with an acknowledge bit. Finally, the master device transmits a stop condition tocomplete the single-byte data write transfer.
Figure 6. Single-Byte Write Transfer
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytesare transmitted by the master device to the TPA5051 as shown in Figure 7 . After receiving each data byte, theTPA5051 responds with an acknowledge bit.
Figure 7. Multiple-Byte Write Transfer
As shown in Figure 8 , a single-byte data read transfer begins with the master device transmitting a startcondition followed by the I
2
C device address and the read/write bit. For the data read transfer, both a writefollowed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memoryaddress to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA5051 address and the read/write bit, the TPA5051 responds with an acknowledge bit.The master then sends the internal memory address byte, after which the TPA5051 issues an acknowledge bit.The master device transmits another start condition followed by the TPA5051 address and the read/write bitagain. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA5051 transmits the databyte from the memory address being read. After receiving the data byte, the master device transmits anot-acknowledge followed by a stop condition to complete the single-byte data read transfer.
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A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register DataByte
D7 D6 D1 D0 ACK
I2CDeviceAddressand
Read/WriteBit
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
MULTIPLE-BYTE READ
A6 A0 ACK
Acknowledge
I2CDeviceAddressand
Read/WriteBit
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition Not
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
TPA5051 Operation
VDD
DATA1
LRCLK1
BCLK1
GND
DATA_OUT1
SDA
SCL
ADD0
ADD1
ADD2
GND
3.3V
0.1 Fm
Digital Audio1
WordClock1
BitClock1
Delayed Audio1
I CClock
2
I CData
2
I C Address
Select
2
Digital Audio2
WordClock2
BitClock2
DATA2
LRCLK2
BCLK2
DATA_OUT2 Delayed Audio2
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
Figure 8. Single-Byte Read Transfer
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytesare transmitted by the TPA5051 to the master device as shown in Figure 9 . With the exception of the last databyte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 9. Multiple-Byte Read Transfer
The following sections describe the registers configurable via I
2
C commands for the TPA5051.
Only a single decoupling capacitor (0.1 µF–1 µF) is required across VDD and GND. The ADDx terminals can bedirectly connected to VDD or GND. Table 1 describes the I
2
C addresses selectable via the ADDx terminals. Aschematic implementation of the TPA5051 is shown in Figure 10 .
Figure 10. TPA5051 Schematic
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SERIAL CONTROL INTERFACE REGISTER SUMMARY
CONTROL REGISTER (0x01, 0x09)
AUDIO DELAY REGISTERS (0x02–0x05, 0x0A–0x0D)
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
Table 2. Serial Control Register Summary
REGISTER REGISTER NAME NO. OF CONTENTS INITIALIZATIONBYTES VALUE
0x01
(1)
Control Register 1 Description shown in subsequent section 000x02
(1)
Right Delay Upper (5 bits) 1 Description shown in subsequent section 000x03
(1)
Right Delay Lower (8 bits) 1 Description shown in subsequent section 000x04
(1)
Left Delay Upper (5 bits) 1 Description shown in subsequent section 000x05
(1)
Left Delay Lower (8 bits) 1 Description shown in subsequent section 000x06
(1)
Frame Delay 1 Description shown in subsequent section 000x07
(1)
RJ Packet Length 1 Description shown in subsequent section 000x08
(1)
Complete Update 1 Description shown in subsequent section 000x09
(2)
Control Register 1 Description shown in subsequent section 000x0A
(2)
Right Delay Upper (5 bits) 1 Description shown in subsequent section 000x0B
(2)
Right Delay Lower (8 bits) 1 Description shown in subsequent section 000x0C
(2)
Left Delay Upper (5 bits) 1 Description shown in subsequent section 000x0D
(2)
Left Delay Lower (8 bits) 1 Description shown in subsequent section 000x0E
(2)
Frame Delay 1 Description shown in subsequent section 000x0F
(2)
RJ Packet Length 1 Description shown in subsequent section 000x10
(2)
Complete Update 1 Description shown in subsequent section 00
(1) I
2
C registers for serial data channel 1(2) I
2
C registers for serial data channel 2
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I
2
S,Right-Justified, or Left-Justified).
Table 3. Control Registers (0x01, 0x09)
(1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 X X X X – – Left and Right channel are active.
0 1 X X X X – – Left channel is MUTED.1 0 X X X X – – Right channel is MUTED.1 1 X X X X – – Left and Right channel are MUTED.– – X X X X 0 0 I
2
S data format
– – X X X X 0 1 Right-justified data format (see PACKET LENGTH register 0x07)– – X X X X 1 0 Left-justified data format– – X X X X 1 1 Bypass mode – data is passed straight through without delay.
(1) Default values are in bold.
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper andlower registers as specified in Table 1 . A multiple byte transfer should be performed starting with the controlregister and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.The decimal value of D0–D13 equals the number of samples to delay. The maximum number of delayedsamples per channel is 4095 for the TPA5051. This equates to 85.3 ms ([4095 ×(1/Fs)] at 48 kHz) of delay perchannel.
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FRAME DELAY REGISTERS (0x06, 0x0E)
RJ PACKET LENGTH REGISTERS (0x07, 0x0F)
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
Table 4. Audio Delay Registers (0x02–0x05, 0x0A–0x0D)
(1)
D13 D12 D11–D2 D1 D0 FUNCTION
0 0 0 0 0 Left and Right audio is passed to output with no delay.
0 0 0 0 1 Left and Right audio is delayed by 1 sample (1/Fs = delay time)1 1 1 1 1 Left and Right audio is delayed by 4095 samples (4095/Fs = delay time)
(1) Default values are in bold.
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1,the audio delay registers (0x01–0x04) are bypassed and the Frame Delay Register is used to set the delaybased on the frame rate (D6), audio sample rate (D5–D3), and number of frames to delay (D2–D0).
The total audio delay time is calculated by the following formula:Audio Delay (in samples) = int [# Delay Frames ×(1/Frame Rate) ×Audio Sample Rate]
If the result of the formula above is greater than the maximum number of delay samples (4095 for TPA5051),then the value is limited to this maximum before passing to the delay block.
Table 5. Frame Delay Registers (0x06, 0x0E)
(1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 Settings in this register are masked and audio delay is determined bysettings in the right/left audio delay registers.
1 Right/left audio delay registers are masked and delay is determined by settings inthis register.
0 Frame rate = 50 Hz
1 Frame rate = 59.94 Hz
0 0 0 Audio sample rate = 32 kHz
0 0 1 Audio sample rate = 44.1 kHz0 1 0 Audio sample rate = 48 kHz0 1 1 Audio sample rate = 88.2 kHz1 0 0 Audio sample rate = 96 kHz1 0 1 Audio sample rate = 176.4 kHz1 1 0 Audio sample rate = 192 kHz1 1 1 Audio sample rate = 192 kHz
0 0 0 Delay frames = 1
0 0 1 Delay frames = 21 1 1 Delay frames = 8
(1) Default values are in bold.
This register is only used in right justified mode. The decimal value of bits [5:0] represents the width of theuseable data in a right justified audio stream. The number of BCLK transitions between LRCLK transitions mustbe greater than or equal to the packet length selected in this register. The maximum packet length value is 24bits. Any setting greater whose numerical value is greater than 24 bits is limited to the maximum 24 bits.
Table 6. RJ Package Length (0x07, 0x0F)
(1)
D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 Packet length = 0 bits
0 0 0 0 0 1 Packet length = 1 bits0 1 1 X X X Packet length = 24 bits
(1) Default values are in bold.
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COMPLETE UPDATE REGISTER (0x08, 0x10)
APPLICATION EXAMPLES
Connecting Two Devices in Series to Increase the Delay
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
2kW2kW
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
DATA_OUT1
DATA_OUT2
DATA_OUT1
DATA_OUT2
VDD
GND
0.1 Fm
VDD
GND
0.1 Fm
ADD2
ADD1
ADD0
SCLK
SDA
ADD2
ADD1
ADD0
SDA
SCL SCLK
Audio
Processor
SDA
SCL SCL
Audio
Amplifier
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
Since the audio delay values are divided among several registers, it is likely that multiple writes would benecessary to configure the device. This may cause interruptions in the audio stream and unwanted pops andclicks might occur as register data is passed to delay functional block.
To avoid this from happening, the Complete Update register is used to transfer the user settings from theregister file to the delay functional block when a 1 is written to the LSB. For example, if the right delay is set to35 samples, and the left delay is set to 300 samples, the device holds the right channel in MUTE until 35samples of audio data have passed, and holds the left channel in MUTE until 300 samples of audio data havepassed.
The Complete Update register must also be used when either the stream type is changed or the RJ packetlength is changed. If a complete update command is not issued, the changes will not take effect.
Note that the individual channels can be muted using the upper bits of the Control Registers without writing tothe Complete Update registers.
Table 7. Complete Update Registers (0x08, 0x10)
(1)
D7–D1 D0 FUNCTION
X0 No data from the register settings is passed to the delay block.
X 1 Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block.
(1) Default values are in bold.
It is sometimes desirable to increase the delay time beyond which one device can provide. In such cases,several TPA5051 devices can be placed in series to increase the delay. A maximum of eight devices can beplaced in series. This is because each device has eight I
2
address settings. Under no circumstances should twoTPA5051 devices share the same I
2
S address. See Figure 11 .
Figure 11. Two Devices Connected in Series
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I
2
C Examples
Single Byte Write
D2Start ACK 01 ACK C0 ACK Stop
TPA5051 Addressand
Write
Register Address Data
Multiple Byte Write
D2Start ACK
01 00 04
ACK
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA1
Data
(RightDelayUpperBits
)DATA1
ACK ACK 00 ACK
Data
(ControlRegister
)DATA1
Data
(RightDelayLowerBits
)DATA1
08 ACK
00 00 00
ACK
Data
(LeftDelayUpperBits
)DATA1
Data
(RJPacket=0Bits
)DATA1
ACK ACK 01 ACK
Data
(FrameDelay
)DATA1
Data
(CompleteUpdate
)DATA1
Data
(LeftDelayLowerBits
)DATA1
Stop
10 ACK
00 00 00
ACK
Data
(ControlRegister
)DATA2
Data
(LeftDelayUpperBits
)DATA2
ACK ACK 00 ACK
Data
(RightDelayLowerBits
)DATA2
Data
(LeftDelayLowerBits
)DATA2
Data
(RightDelayUpperBits
)DATA2
91 ACK
10 01 ACK
Data
(FrameDelay
)DATA2
ACK
Data
(CompleteUpdate
)DATA2
Data
(RJPacket=16Bits
)DATA2
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
The following are some examples of I
2
C commands used to read or write to the TPA5051. For all conditions,assume the address of the TPA5051 is set to 001.
In this example, the TPA5051 is set to mute both left and right channels of DATA1, and to operate in I
2
S mode.
NOTE:
Because no complete update command was issued in this example, the stream typechange will not take effect until a 1is written to the Complete Update register.
In this example, the TPA5051 is set to make both the left and right channels of both DATA1 and DATA2 active.DATA1 is set to operate in I
2
S mode, delay the right channel by 1024 samples, and delay the left channel by2048 samples. DATA2 is set to operate in the Right-Justified mode with a packet length of 16 bits. It is to delaythe audio signal by 40 ms using the Frame Delay function. Assume the audio sample rate (fs) = 48 kHz, and theFrame rate = 50 Hz. This is a sequential write, so all registers must have data written to them.
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Combination of Single Byte Writes
D2Start ACK 01 ACK 00 ACK Stop
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA1
Data
(ControlRegister
)DATA1
D2Start ACK 09 ACK C0 ACK
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA2
Data
(ControlRegister
)DATA2
Stop
Single Byte Read
D2
Start ACK 01 ACK Start D3 XX
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA1
Stop
ACK
DataRead
(ControlRegister
)DATA1
No
ACK
TPA5051 Addressand
Read
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
In this example, DATA1 set to operate in the I
2
S mode, and DATA2 is set to mute.
Note that in every circumstance where a delay or stream type is written into the memory of the TPA5051, a 1must be written to the Complete Update registers for the change to take effect. In this example, the stream typechange made to DATA1 would not take effect. This does not apply to muting, which occurs in the Controlregisters.
In this example, one byte of data is read from the Control Register (0x01). After the data (represented xx) by isread by the master device, the master device issues a Not Acknowledge, before stopping the communication.
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Multiple Byte Read
D2Start ACK
01
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA1
ACK ACK XX ACK
DataRead
(ControlRegister
)DATA2
DataRead
(ControlRegister
)DATA1
XX ACK
XX XX XX
ACK
DataRead
(RightDelayUpperBits
)DATA1
DataRead
(RJPacketLength
)DATA1
ACK ACK XX ACK
DataRead
(FrameDelay
)DATA1
DataRead
(CompleteUpdate
)DATA1
DataRead
(RightDelayLowerBits
)DATA1
Stop
XX ACK
XX XX XX
ACK
DataRead
(LeftDelayUpperBits
)DATA2
ACK ACK XX ACK
DataRead
(RightDelayLowerBits
)DATA2
DataRead
(LeftDelayLowerBits
)DATA2
DataRead
(RightDelayUpperBits
)DATA2
XX ACK
XX XX NO ACK
DataRead
(FrameDelay
)DATA2
ACK
Start D3
TPA5051 Addressand
Read
DataRead
(LeftDelayUpperBits
)DATA1
DataRead
(LeftDelayLowerBits
)DATA1
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
Often, when it is necessary to read what is contained in one register, it is necessary to determine whatinformation is contained in all registers. In such a case, a sequential read should be used. In situations wheredata must be read from a register at the beginning (0x01), and a register towards the end (0x0E), a sequentialread is likely to be faster to implement than multiple single byte reads.
In this example, a sequential read is initiated with the Control Register (0x01), and ends with the Frame DelayRegister (0x0E).
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DEVICE CURRENT CONSUMPTION
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
32 52 72 92 112 132 152 172 192
fs-SamplingFrequency-kHz
I-SupplyCurrent-mA
DD
V =3.6V
DD
V =3.3V
DD
V =3V
DD
BCLK=64fs
Data=24bit
SUPPLY CURRENT
vs
SAMPLINGFREQUENCY
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
The TPA5051 draws different amounts of supply current depending upon the conditions under which it isoperated. As V
DD
increases, so too does I
DD
. Likewise, as V
DD
decreases, I
DD
decreases. The same is true ofthe sampling frequency, fs. An increase in fs causes an increase in I
DD
.Figure 12 illustrates the relationshipbetween operating condition and typical supply current.
Figure 12. Typical Supply Current
16
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPA5051RSAR ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5051RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5051RSAT ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5051RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA5051RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPA5051RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA5051RSAR QFN RSA 16 3000 367.0 367.0 35.0
TPA5051RSAT QFN RSA 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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