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Z8 Encore! XP® F64XX Series with Date Codes 0344 to 0519

The errata listed in Table 1 are found in Zilog’s Z8 Encore! XP® F64XX Series devices with date codes

0344 to 0519, where the date code is YYWW (year and week of assembly). Date codes 0442 to 0519 are

mixed; the errata will apply to some units, but not others. These errata are NOT APPLICABLE to date

codes 0520 and later. When reviewing the following errata, it is recommended that you also download the

most recent version of the Product Specification.

Table 1. Z8 Encore! XP F64XX Series Errata Date Code 0344 to 0519

No. Summary Description

1Read protec t (RP)

option bit may be

bypassed.

The RP option bit does not prevent Flash access when bypassing the Flash

controller. For more information, refer to Third Party Flash Programming Sup-

port for Z8 Encore!® MCU Application Note (AN0117).

User code cannot be read through the on-chip debugger when read protect is

enabled. User code can only be read out when bypassing the Flash controller.

Workaround

None

2START, STOP and

NAK bits in the I2C

control register can

be cleared by soft-

ware writing a 0 to

these bits .

The START, STOP, and NAK bits in the I2C control register can be cleared by

software writing a 0 to these bits. The Product Specification states that they

cannot be cleared by writing a 0.

Workaround

None

3Device may not com-

plete Stop Mode

Recovery initiated by

a general-purpo se

input/output (GPIO)

pin transition.

When Stop Mode Recovery is initiated by a GPIO pin transition, multiple pin

transitions within 200 μs (approximate) of each other may cau se the de vice to

only partially wake up from STOP mode. Therefore, the device idles in a state

between STOP mode and normal operation. The crystal oscillator is oscillat-

ing, but code does not execute.

When stuck in this idle state, assertion of the external RESET pi n does not ini -

tiate a system reset.

Workaround

The workarounds are listed below:

•Add external filtering to the Stop Mode Recovery pin input signal to pre-

vent multiple transitions in less than 200 μs.

•Enable the Watchdog Timer (WDT) in STOP mode to allow a WDT to

complete the Stop Mode Recovery in the event the device does not suc-

cessfully complete the Stop Mode Recovery initiated by the GPIO pin tran-

sition.

Product Update

Errata for Z8 Encore! XP®

F64XX Series

UP006010-0508

Errata for Z8 Encore! XP® F64XX Series

UP006010-0508 Pag e 2 of 5

Z8 Encore! XP® F64XX Series with Date Codes Prior to 0344

The errata listed in Table 2 are found in the production Z8 Encore! XP® F64XX Series devices with date

codes prior to 0344, where the date code is YYWW (year and week of assembly). When reviewing the fol-

lowing errata, it is recommended that you also download the most recent version of the Product Specifica-

tion.

Table 2. Z8 Encore! XP F64XX Series Errata Date Coded Prior to 0334

No. Summary Description

1When the CPU exit s

from HALT mode, it

fails to reset the

master Interrupt

Request Enable

(IRQE) bit.

When the CPU exits from HALT mode, it fails to reset the master Interrupt

Request Enable (IRQE) bit (bit 7 of the Interrupt Contr ol Reg ister).

WDT interrupt s cause the program counter (PC) and Flags to be pushed twice

on the stack. The first push is the PC and Flags from where the interrupt

occurred. The second push is the starting address and Flags of the Interrupt

service routine (ISR).

This problem also affects exits from HALT mode caused by other interrupt

sources if more than one interr upt is pending. If only a single interrupt is pend-

ing then, the routine is executed normally except that interrupts are not dis-

abled

Workaround

To mimic standard interrupt operation, the ISR should execute a disable inter-

rupts (D I) instruction to reset the master Interrupt Request enable ( IRQE) bit to

Further, on WDT int er ru pts befor e exiting, the IS R sho u ld ad d th re e to the

stack pointer (SP). On normal interrupts, the ISR should check the program

counter on the stack. If the PC on the stack contains the starting address of

the ISR, then the ISR sho uld add thr ee to the stack pointer. This problem only

affects exits from HALT mode.

2System reset

latency may exceed

specification limits.

When exiting STOP mode and after a Power-On Reset (POR)/Voltage Brown-

out (VBO) reset, the system reset Latency is 514 WDT cycles plus 16 system

clock cycles rather than the 66 WDT cycles plus 16 system clock cycles as

specified.

Workaround

None. This error is unlikely to affect system operation.

3UART NEWFRM sta-

tus bit does not func-

tion.

The NEWFRM status bit (bit 2 of the UART Status 1 register) does not indicate

the start of a new frame.

Workaround

None

Errata for Z8 Encore! XP® F64XX Series

UP006010-0508 Pag e 3 of 5

4UART address com-

pare fu nction does

not work.

Setting bit 7 (MPMD[1]) of the UART control 1 register to 1 does not produce

the desired effect of enabling the UART address compare and associated

interrupt functionality.

Workaround

Leave MPMD[1] in its reset state of 0.

5UART ba ud rate

generator cannot be

used as simple

timer.

Setting BRGCTL (bit 2 of the UART Control 1 register) to 1 when the UART

receiver is disabled does not enable UART baud rate generator interrupt.

Thus, the UART baud rate generator cannot be used as a simple timer.

Workaround

Use one of the four standard timers or the baud rate generators in the SPI or

I2C blocks to perform the desired timing operations.

6Unlocking the Flash

controller allows pro-

gram and erase

operations on all

Flash pages.

During the Flash controller unlock se qu enc e, the specification indicate s that a

second write to the Flash Page Select register is required (step 5 of the

sequence) to unlock the Flash controller for the selected Flash page. The

Flash controller unlocks for all Flash pages once the step 1 to step 4 of the

unlock sequence are complete.

Workaround

None

7Setting bits in the

Flash sector pr ot ect

not lock sectors.

Writing bits in the Flash sector protect register to 1 fails to prevent program

and erase operations on the selected Flash memory sector.

Workaround

None

8Watchdog Timer

cannot be disabled

in STOP mode.

The Watchdog Timer and its associated internal RC oscillator cannot be dis-

abled in STOP mode .

Workaround

None

9Watchdog Timer

oscillator frequency

is out of specifica-

tion.

The typical Watchdog Timer internal oscillator frequency is 50 kHz rather than

the currently specified 10 kHz. This frequency can result in WDT time-out val-

ues that are less than expected.

Workaround

Increase the WDT reload value by a factor of 5 to compensate for the fre-

quency error.

10 Operating currents. Operating currents in the various mode ( NORM A L, HALT, and STOP) may be

higher than typical values.

Workaround

None

Table 2. Z8 Encore! XP F64XX Series Errata Date Coded Prior to 0334 (Continued)

No. Summary Description

Errata for Z8 Encore! XP® F64XX Series

UP006010-0508 Pag e 4 of 5

11 RESET pin is not fil-

tered. The RESET pin does not pr operly fil ter th e input signal. Th e device may enter

Reset when the RESET pin is asserted for less tha n the specified four system

clock cycles (from NORMAL mode).

Workaround

Add external filtering to the printed-circui t board.

12 Timers cannot be

cascaded. Setting the CSC bit (bit 4) of the Timer Control 0 Registers does not cascade

the timers as indicated in the specification.

Workaround

Timers can be cascaded using the Timer-Out and Timer-In functions through

the general-purpose I/O pins.

13 ADC generates

extra interrupts. The ADC continues to generate interrupts in CONTINUOUS mode after the

first interrupt be fore the results of the next conversion is complete.

Workaround

Do not use CONTINUOUS mode. Use SINGLE-SHOT mode instead.

Table 2. Z8 Encore! XP F64XX Series Errata Date Coded Prior to 0334 (Continued)

No. Summary Description

Errata for Z8 Encore! XP® F64XX Series

UP006010-0508 Pag e 5 of 5

DO NOT USE IN LIFE SUPPORT

LIFE SUPPORT POLICY

ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICA L COMPONENTS IN LIFE

SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF

THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)

support or sustain life and whose failure to perform when properly used in accordance with instructions for

use provided in the labeling can be reasonably expected to result in a significant injury to the user. A

critical component is any component in a life support device or system whose failure to perform can be

reasonably expected to cause the failure of the life support device or system or to affect its safety or

effectiveness.

Document Disclaimer

applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,

INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY

OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.

ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY

INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR

TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this

document has be en verified according to the general principles of electrical and mechanical engineering.

Z8, Z8 Encore!, and Z8 Encore! XP are registered trademarks of Zilog, Inc. All other product or service

names are the proper ty of thei r resp ec tiv e ow ners .

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