LM48310
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SNAS430D –NOVEMBER 2007–REVISED MAY 2013
LM48310 Ultra-Low EMI, Filterless, 2.6W, Mono, Class D
Audio Power Amplifier with E
2
S
Check for Samples: LM48310
1FEATURES DESCRIPTION
The LM48310 is a single supply, high efficiency,
2• Passes FCC Class B Radiated Emissions with mono, 2.6W, filterless switching audio amplifier. The
20 inches of cable LM48310 features TI’s Enhanced Emissions
• E2S System Reduces EMI while Preserving Suppression (E2S) system, that features a unique
Audio Quality and Efficiency patent-pending ultra low EMI, spread spectrum, PWM
architecture, that significantly reduces RF emissions
• Output Short Circuit Protection with Auto- while preserving audio quality and efficiency. The E2S
Recovery system improves battery life, reduces external
• Stereo Class D Operation component count, board area consumption, system
• No Output Filter Required cost, and simplifying design.
• Internally Configured Gain (12dB) The LM48310 is designed to meet the demands of
• Synchronizable Oscillator for Multi-Channel portable multimedia devices. Operating from a single
Operation 5V supply, the device is capable of delivering 2.6W of
continuous output power to a 4Ωload with less than
• Low Power Shutdown Mode 10% THD+N. Flexible power supply requirements
• Minimum External Components allow operation from 2.4V to 5.5V. The LM48310
• "Click and Pop" Suppression offers two logic selectable modulation schemes, fixed
frequency mode, and an EMI suppressing spread
• Micro-Power Shutdown spectrum mode. The E2S system includes an
• Available in Space-Saving WSON Package advanced, patent-pending edge rate control (ERC)
architecture that further reduce emissions by
APPLICATIONS minimizing the high frequency component of the
device output, while maintaining high quality audio
• Mobile Phones reproduction (THD+N = 0.03%) and high efficiency (η
• PDAs = 88%). The LM48310 also features a SYNC_IN input
• Laptops and SYNC_OUT, which allows multiple devices to
operate with the same switching frequency,
KEY SPECIFICATIONS eliminating beat frequencies and any other
interference caused by clock intermodulation.
• Efficiency at 3.6V, 400mW into 8Ω85% (typ) The LM48310 features high efficiency compared to
• Efficiency at 5V, 1W into 8Ω88% (typ) conventional Class AB amplifiers, and other low EMI
• Quiescent Power Supply Current at 5V 3.2mA Class D amplifiers. When driving and 8Ωspeaker
• Power Output at VDD = 5V, RL= 4Ω, THD+N ≤from a 5V supply, the device operates with 88%
10% 2.6W (typ) efficiency at PO= 1W. The gain of the LM48310 is
internally set to 12dB, further reducing external
• Power Output at VDD = 5V, RL= 8Ω, THD+N ≤component count. A low power shutdown mode
10% 1.6W (typ) reduces supply current consumption to 0.01μA.
• Shutdown current0.01μA (typ) Advanced output short circuit protection with auto-
recovery prevents the device from being damaged
during fault conditions. Superior click and pop
suppression eliminates audible transients on power-
up/down and during shutdown.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
H-
BRIDGE
OSCILLATOR
VDD PVDD
IN+
IN-
SD
GND
OUTA
OUTB
+2.4V to +5.5V
CSCS
CIN
CIN
MODULATOR
SYNC_IN SYNC_OUT
10.0
60.0
20.0
30.0
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50.0
100.0 300.0 500.0 700.0 900.0
30.0 200.0 400.0 600.0 800.0 1000.0
FREQUENCY (MHz)
AMPLITUDE (dBPV/m)
LM48310
SNAS430D –NOVEMBER 2007–REVISED MAY 2013
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EMI Graph 20in of Speaker Cable
Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
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2
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5SYNC_OUT
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OUTB
OUTA
PVDD
VDD
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SYNC_IN
LM48310
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SNAS430D –NOVEMBER 2007–REVISED MAY 2013
Connection Diagram
Figure 2. WSON Package - Top View
See Package Number DSC0010
PIN DESCRIPTIONS
Pin Name Description
1 IN+ Non-Inverting Input
2 IN- Inverting Input
3 VDD Power Supply
4 SD Active Low Shutdown Input. Connect to VDD for normal operation.
Mode Select and External Oscillator Input.
SYNC_IN = VDD: Spread spectrum mode with fS= 300kHz ± 30%
5 SYNC_IN SYNC_IN = GND: Fixed frequency mode with fS= 300kHz
SYNC_IN = Clocked: fS= external clock frequency
6 SYNC_OUT Clock Output
7 OUTB Inverting Output
8 GND Ground
9 PVDD H-Bridge Power Supply
10 OUTA Non-Inverting Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
Supply Voltage 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation(4) Internally Limited
ESD Rating(5) 2000V
ESD Rating(6) 200V
Junction Temperature 150°C
Thermal Resistance θJC 8.2°C/W
θJA 49.2°C/W
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditionsindicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX- TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
(5) Human body model, applicable std. JESD22-A114C.
(6) Machine model, applicable std. JESD22-A115-A.
OPERATING RATINGS(1)(2)
Temperature Range TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C
Supply Voltage 2.4V ≤VDD ≤5.5V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditionsindicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
ELECTRICAL CHARACTERISTICS VDD = PVDD = 5V(1)(2)
The following specifications apply for AV= 12dB, (RL= 8Ω, SYNC_IN = VDD (Spread Spectrum mode), f = 1kHz, unless
otherwise specified. Limits apply for TA= 25°C. LM48310 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(2)
VOS Differential Output Offset Voltage VIN = 0 1 3 mV (max)
VIN = 0, RL=∞2.7 3.9 mA (max)
VDD = 3.6V
IDD Quiescent Power Supply Current VIN = 0, RL=∞3.2 4.4 mA (max)
VDD = 5V
VIN = 0, VDD = 3.6V 2.7 mA
IDD Quiescent Power Supply Current VIN = 0, VDD = 5V 3.2 mA
ISD Shutdown Current VSD = GND 0.01 1.0 μA
VIH Logic Input High Voltage SD input, VDD = 3.6V 1.4 V (min)
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) RLis a resistive load in series with two inductors to simulate an actual speaker load. For RL= 8Ω, the load is 15µH + 8Ω, +15µH. For RL
= 4Ω, the load is 15µH + 4Ω+ 15µH.
(3) Typical values represent most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
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ELECTRICAL CHARACTERISTICS VDD = PVDD = 5V(1)(2) (continued)
The following specifications apply for AV= 12dB, (RL= 8Ω, SYNC_IN = VDD (Spread Spectrum mode), f = 1kHz, unless
otherwise specified. Limits apply for TA= 25°C. LM48310 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(2)
VIL Logic Input Low Voltage SD input, VDD = 3.6V 0.4 V (max)
TWU Wake Up Time 7.5 ms
SYNC_IN = VDD (Spread Spectrum) 300±30 kHz
SYNC_IN = GND (Fixed Frequency) 300 kHz
SYNC_IN = External Clock
fSW Switching Frequency 200 kHz
Minimum Frequency
SYNC_IN = External Clock 1000 kHz
Maximum Frequency 11 dB (min)
AVGain 12 13 dB (max)
RIN Input Resistance 20 17 kΩ(min)
RL= 4Ω, THD = 10%
f = 1kHz, 22kHz BW
VDD = 5V 2.6 W
VDD = 3.6V 1.3 W
VDD = 2.5V 555 mW
RL= 8Ω, THD = 10% (max)
f = 1kHz, 22kHz BW
VDD = 5V 1.6 W
VDD = 3.6V 800 mW
VDD = 2.5V 354 mW
POOutput Power RL= 4Ω, THD = 1% (max)
f = 1kHz, 22kHz BW
VDD = 5V 2.1 W
VDD = 3.6V 1 W
VDD = 2.5V 446 mW
RL= 8Ω, THD = 1% (max)
f = 1kHz, 22kHz BW
VDD = 5V 1.3 1.1 W (min)
VDD = 3.6V 640 mW
VDD = 2.5V 286 mW
PO= 200mW, RL= 8Ω, f = 1kHz 0.03 % (max)
THD+N Total Harmonic Distortion + Noise PO= 100mW, RL= 8Ω, f = 1kHz 0.03 %
VRIPPLE = 200mVP-P Sine,
fRIPPLE = 217Hz, Inputs AC GND, 82 dB
CIN = 1μF, Input referred
Power Supply Rejection Ratio
PSRR (Input Referred) VRIPPLE = 200mVP-P Sine,
fRIPPLE = 1kHz, Inputs AC GND, 80 dB
CIN = 1μF, Input referred
VRIPPLE = 1VP-P
CMRR Common Mode Rejection Ratio 70 dB
fRIPPLE = 217Hz
VDD = 5V, POUT = 1W 88 %
RL= 8Ω, f = 1kHz
ηEfficiency VDD = 3.6V, POUT = 400mW 85 %
RL= 8Ω, f = 1kHz
VDD = 5V, PO= 1W, 97 dB
Fixed Frequency Mode
SNR Signal to Noise Ratio VDD = 5V, PO= 1W, 97 dB
Spread Spectrum Mode
Input referred,
Fixed Frequency Mode, 14 μV
A-weighted Filter
εOS Output Noise Input referred,
Spread Spectrum Mode, 28 μV
Unweighted
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LM48310
SNAS430D –NOVEMBER 2007–REVISED MAY 2013
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Frequency THD+N vs Frequency
VDD = 2.5V, POUT = 300mW, RL= 4ΩVDD = 3.6V, POUT = 700mW, RL= 4Ω
Figure 3. Figure 4.
THD+N vs Frequency THD+N vs Frequency
VDD = 5.0V, POUT = 1.2W, RL= 4ΩVDD = 2.5V, POUT = 150mW, RL= 8Ω
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.6V, POUT = 400mW, RL= 8ΩVDD = 5V, POUT = 650mW, RL= 8Ω
Figure 7. Figure 8.
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50
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200
0 250 500 750 1000 1250 1500
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
VDD = 5V
VDD = 3.6V
VDD = 2.5V
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0 500 1000 1500 2000 2500
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
VDD = 5V
VDD = 3.6V
VDD = 2.5V
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VDD = 5V
VDD = 3.6V
VDD = 2.5V
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VDD = 5V
VDD = 3.6V
VDD = 2.5V
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VDD = 5V
VDD = 3.6V
VDD = 2.5V
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OUTPUT POWER (W)
THD+N (%)
VDD = 5V
VDD = 3.6V
VDD = 2.5V
LM48310
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SNAS430D –NOVEMBER 2007–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power THD+N vs Output Power
f = 1kHz, RL= 4Ωf = 1kHz, RL= 8Ω
Figure 9. Figure 10.
Efficiency vs Output Power Efficiency vs Output Power
f = 1kHz, RL= 4Ωf = 1kHz, RL= 8Ω
Figure 11. Figure 12.
Power Dissipation vs Output Power Power Dissipation vs Output Power
f = 1kHz, RL= 4Ωf = 1kHz, RL= 8Ω
Figure 13. Figure 14.
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SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
THD+N = 10%
THD+N = 1%
0
0.5
1
1.5
2
2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
THD+N = 10%
THD+N = 1%
LM48310
SNAS430D –NOVEMBER 2007–REVISED MAY 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Power vs Supply Voltage Output Power vs Supply Voltage
f = 1kHz, RL= 4Ωf = 1kHz, RL= 8Ω
Figure 15. Figure 16.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.6V, VRIPPLE = 200mVP-P, RL= 8ΩVDD = 5.0V, VRIPPLE = 200mVP-P, RL= 8Ω
Figure 17. Figure 18.
CMRR vs Frequency CMRR vs Frequency
VDD = 3.6V, VRIPPLE = 1VP-P, RL= 8ΩVDD = 5.0V, VRIPPLE = 1VP-P, RL= 8Ω
Figure 19. Figure 20.
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SUPPLY CURRENT (PA)
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LM48310
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SNAS430D –NOVEMBER 2007–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Fixed Frequency Output Spectrum vs Frequency Spread Spectrum Output Spectrum vs Frequency
VDD = 5.0V, VIN = 1VRMS, RL= 8ΩVDD = 5.0V, VIN = 1VRMS, RL= 8Ω
Figure 21. Figure 22.
Wideband Fixed Frequency Output Spectrum Wideband Spread Spectrum Output Spectrum
vs Frequency vs Frequency
VDD = 5.0V, RL= 8ΩVDD = 5.0V, RL= 8Ω
Figure 23. Figure 24.
Supply Current vs Supply Voltage Shutdown Supply Current vs Supply Voltage
No Load No Load
Figure 25. Figure 26.
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APPLICATION INFORMATION
GENERAL AMPLIFIER FUNCTION
The LM48310 mono Class D audio power amplifier features a filterless modulation scheme that reduces external
component count, conserving board space and reducing system cost. With no signal applied, the outputs (VOUTA
and VOUTB) switch between VDD and GND with a 50% duty cycle, in phase, causing the two outputs to cancel.
This cancellation results in no net voltage across the speaker, thus there is no current to the load in the idle
state.
With the input signal applied, the duty cycle (pulse width) of the LM48310 outputs changes. For increasing output
voltage, the duty cycle of VOUTAincreases, while the duty cycle of VOUTB decreases. For decreasing output
voltages, the converse occurs. The difference between the two pulse widths yields the differential output voltage.
ENHANCED EMISSIONS SUPPRESSION SYSTEM (E2S)
The LM48310 features ’s patent-pending E2S system that reduces EMI, while maintaining high quality audio
reproduction and efficiency. The E2S system features a synchronizable oscillator with selectable spread
spectrum, and advanced edge rate control (ERC). The LM48310 ERC greatly reduces the high frequency
components of the output square waves by controlling the output rise and fall times, slowing the transitions to
reduce RF emissions, while maximizing THD+N and efficiency performance. The overall result of the E2S system
is a filterless Class D amplifier that passes FCC Class B radiated emissions standards with 20in of twisted pair
cable, with excellent 0.03% THD+N and high 88% efficiency.
FIXED FREQUENCY MODE (SYNC_IN = GND)
The LM48310 features two modulations schemes, a fixed frequency mode and a spread spectrum mode. Select
the fixed frequency mode by setting SYNC_IN = GND. In fixed frequency mode, the amplifier output switch at a
constant 300kHz. In fixed frequency mode, the output spectrum consists of the fundamental and its associated
harmonics (see TYPICAL PERFORMANCE CHARACTERISTICS).
SPREAD SPECTRUM MODE (SYNC_IN = VDD)
The logic selectable spread spectrum mode eliminates the need for output filters, ferrite beads or chokes. In
spread spectrum mode, the switching frequency varies randomly by 30% about a 300kHz center frequency,
reducing the wideband spectral contend, improving EMI emissions radiated by the speaker and associated
cables and traces. Where a fixed frequency class D exhibits large amounts of spectral energy at multiples of the
switching frequency, the spread spectrum architecture of the LM48310 spreads that energy over a larger
bandwidth (See TYPICAL PERFORMANCE CHARACTERISTICS). The cycle-to-cycle variation of the switching
period does not affect the audio reproduction, efficiency, or PSRR. Set SYNC_IN = VDD for spread spectrum
mode.
EXTERNAL CLOCK MODE (SYNC_IN = CLOCK)
Connecting a clock signal to SYNC_IN synchronizes the LM48310 oscillator to an external clock, moving the
output spectral components out of a sensitive frequency band, and minimizing audible beat frequencies when
multiple LM48310s are used in a single system. The LM48310 accepts an external clock frequency between
200kHz and 1MHz. The LM48310 can be synchronized to a spread spectrum clock, allowing multiple LM48310s
to be synchronized in spread spectrum mode (see TYPICAL PERFORMANCE CHARACTERISTICS).
SYNC_OUT
SYNC_OUT is a clock output for synchronizing external devices. The SYNC_OUT signal is identical in frequency
and duty cycle of the amplifier’s switching frequency. When the LM48310 is in fixed frequency mode,
SYNC_OUT is a fixed, 300kHz clock. When the LM48310 is in spread spectrum mode, SYNC_OUT is an
identical spread spectrum clock. When the LM48310 is driven by an external clock, SYNC_OUT is identical to
the external clock. If unused, leave SYNC_OUT floating.
Multiple LM48310s can be synchronized to a single clock. In Figure 27, device U1 is the master, providing a
spread spectrum clock to the slave device (U2). This configuration synchronizes the switching frequencies of the
two devices, eliminating any audible beat frequencies. Because SYNC_OUT has no audio content, there is
minimal THD+N degredation or crosstalk between the devices, Figure 28 -Figure 30.
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SLAVE
VDD PVDD
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OUTA
SYNC
_OUT
OUTB
VDD
1 PF
VDD PVDD
IN+
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OUTA
OUTB
1 PF
LM48310
LM48310
U1
U2
RIGHT CHANNEL
DIFFERENTIAL
AUDIO INPUT
LEFT CHANNEL
DIFFERENTIAL
AUDIO INPUT
LM48310
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Figure 27. Cascaded LM48310
Figure 28. THD+N vs Output Power Figure 29. THD+N vs Frequency
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Figure 30. Crosstalk vs Frequency
DIFFERENTIAL AMPLIFIER EXPLANATION
As logic supplies continue to shrink, system designers are increasingly turning to differential analog signal
handling to preserve signal to noise ratios with restricted voltage signs. The LM48310 features a fully differential
speaker amplifier. A differential amplifier amplifies the difference between the two input signals. Traditional audio
power amplifiers have typically offered only single-ended inputs resulting in a 6dB reduction of SNR relative to
differential inputs. The LM48310 also offers the possibility of DC input coupling which eliminates the input
coupling capacitors. A major benefit of the fully differential amplifier is the improved common mode rejection ratio
(CMRR) over single ended input amplifiers. The increased CMRR of the differential amplifier reduces sensitivity
to ground offset related noise injection, especially important in noisy systems.
POWER DISSIPATION AND EFFICIENCY
The major benefit of a Class D amplifier is increased efficiency versus a Class AB. The efficiency of the
LM48310 is attributed to the region of operation of the transistors in the output stage. The Class D output stage
acts as current steering switches, consuming negligible amounts of power compared to their Class AB
counterparts. Most of the power loss associated with the output stage is due to the IR loss of the MOSFET on-
resistance, along with switching losses due to gate charge.
SHUTDOWN FUNCTION
The LM48310 features a low current shutdown mode. Set SD = GND to disable the amplifier and reduce supply
current to 0.01µA.
Switch SD between GND and VDD for minimum current consumption is shutdown. The LM48310 may be disabled
with shutdown voltages in between GND and VDD, the idle current will be greater than the typical 0.1µA value.
The LM48310 shutdown input has and internal pulldown resistor. The purpose of this resistor is to eliminate any
unwanted state changes when SD is floating. To minimize shutdown current, SD should be driven to GND or left
floating. If SD is not driven to GND or floating, an increase in shutdown supply current will be noticed.
AUDIO AMPLIFIER POWER SUPPLY BYPASSING/FILTERING
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass
capacitors as close to the device as possible. Typical applications employ a voltage regulator with 10µF and
0.1µF bypass capacitors that increase supply stability. These capacitors do not eliminate the need for bypassing
of the LM48310 supply pins. A 1µF capacitor is recommended.
12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM48310
IN+
IN-
CIN
CIN
RINEXT
RINEXT
RIN
RIN
RF
RF
LM48310
www.ti.com
SNAS430D –NOVEMBER 2007–REVISED MAY 2013
AUDIO AMPLIFIER INPUT CAPACITOR SELECTION
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM48310. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high pass filter is found using Equation 1 below.
f = 1 / 2πRINCIN
Where
• RIN is the value of the input resistor given in the Electrical Characteristics table (1)
The input capacitors can also be used to remove low frequency content from the audio signal. Small speakers
cannot reproduce, and may even be damaged by low frequencies. High pass filtering the audio signal helps
protect the speakers. When the LM48310 is using a single-ended source, power supply noise on the ground is
seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a
GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors
with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR.
AUDIO AMPLIFIER GAIN
The gain of the LM48310 is internally set to 12dB. The gain can be reduced by adding additional input resistance
Figure 31. In this configuration, the gain of the device is given by:
AV= 2 x [RF/ (RINEXT + RIN)]
Where
• RFis 40kΩ
• RIN is 20kΩ
• RINEXT is the value of the additional external resistor (2)
Figure 31. Reduced Gain Configuration
SINGLE-ENDED AUDIO AMPLIFIER CONFIGURATION
The LM48310 is compatible with single-ended sources. When configured for single-ended inputs, input
capacitors must be used to block and DC component at the input of the device. Figure 32 shows the typical
single-ended applications circuit.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM48310
VDD PVDD
IN-
IN+
OUTA
OUTB
VDD
1 PF
LM48310
SINGLE-ENDED
AUDIO INPUT
LM48310
SNAS430D –NOVEMBER 2007–REVISED MAY 2013
www.ti.com
Figure 32. Single-Ended Input Configuration
PCB LAYOUT GUIDELINES
As output power increases, interconnect resistance (PCB traces and wires) between the amplifier, load and
power supply create a voltage drop. The voltage loss due to the traces between the LM48310 and the load
results in lower output power and decreased efficiency. Higher trace resistance between the supply and the
LM48310 has the same effect as a poorly regulated supply, increasing ripple on the supply line, and reducing
peak output power. The effects of residual trace resistance increases as output current increases due to higher
output power, decreased load impedance or both. To maintain the highest output voltage swing and
corresponding peak output power, the PCB traces that connect the output pins to the load and the supply pins to
the power supply should be as wide as possible to minimize trace resistance.
The use of power and ground planes will give the best THD+N performance. In addition to reducing trace
resistance, the use of power planes creates parasitic capacitors that help to filter the power supply line.
The inductive nature of the transducer load can also result in overshoot on one of both edges, clamped by the
parasitic diodes to GND and VDD in each case. From an EMI standpoint, this is an aggressive waveform that can
radiate or conduct to other components in the system and cause interference. In is essential to keep the power
and output traces short and well shielded if possible. Use of ground planes beads and micros-strip layout
techniques are all useful in preventing unwanted interference.
As the distance from the LM48310 and the speaker increases, the amount of EMI radiation increases due to the
output wires or traces acting as antennas become more efficient with length. Ferrite chip inductors places close
to the LM48310 outputs may be needed to reduce EMI radiation.
Designator Quantity Description
C1 1 10μF ±10% 16V 500ΩTantalum Capacitor (B Case) AVX
TPSB106K016R0500
C2, C3 2 1μF ±10% 16V X7R Ceramic Capacitor (603) Panasonic
ECJ-1VB1C105K
C4, C5 2 1μF ±10% 16V X7R Ceramic Capacitor (1206) Panasonic
ECJ-3YB1C105K
C6 1 Not Installed Ceramic Capacitor (603)
R1 1 0Ω±1% resistor (603)
JP1 — JP2 2 3 Pin Headers
LM48310SDL 1 LM48310SD (10-pin WSON)
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM48310
SYNC_OUTSYNC_IN
LM48310SD
OUTB
SYNC_OUT
R1
0
6
C6
OPEN
GND
7
OUTA
10
U1
IN-
2OUTBIN-
OUTA
1 PF
C5
IN+
1IN+
1 PF
C4
GND
8GND
5
1
3
2
VDD
JU2
GND
1
3
2
VDD
JU1
GND
SD
4
SYNC_IN
VDD
3VDD 9
PVDD
+C2
1 PF
C1
10 PF
PVDD
PGND
C3
1 PF
PVDD
LM48310
www.ti.com
SNAS430D –NOVEMBER 2007–REVISED MAY 2013
LM48310 Demo Board Schematic
Figure 33. LM48310 DEMO BOARD SCHEMATIC
Demo Boards
Figure 34. Top Silkscreen Figure 35. Top Layer
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM48310
LM48310
www.ti.com
SNAS430D –NOVEMBER 2007–REVISED MAY 2013
REVISION HISTORY
Rev Date Description
1.0 11/13/07 Initial release.
1.01 02/26/08 Fixed few typos (Pin Description table).
1.02 03/04/08 Text edits under SHUTDOWN FUNCTION (Application Information section).
1.03 06/24/09 Text edits.
Changes from Revision C (May 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 16
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM48310
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM48310SD/NOPB ACTIVE WSON DSC 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 GI8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM48310SD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM48310SD/NOPB WSON DSC 10 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
MECHANICAL DATA
DSC0010A
www.ti.com
SDA10A (Rev A)
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