SX-A Family FPGAs
10 v3.0
Boundary Scan Testing (BST)
All SX-A devices are IEEE 1149.1 compliant. SX-A devices
offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing
capabilities. These functions are controlled through the
special test pins in conjunction with the program fuse. The
functionality of each pin is described in Table 3. In the
dedicated test mode, TCK, TDI and TDO are dedicated pins
and cannot be used as regular I/Os. In flexible mode, TMS
should be set HIGH through a pull-up resistor of 10kΩ. TMS
can be pulled LOW to initiate the test sequence.
Configuring Diagnostic Pins
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the “Variation” dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel's Designer software.
TRST pin
When the “Reserve JTAG Reset” box is checked (default
setting in Designer software), the TRST pin will become a
Boundary Scan Reset pin. In this mode, the TRST pin will
function as an asynchronous, active-low input to initialize or
reset the BST circuit. An internal pull-up resistor will be
automatically enabled on the TRST pin.
The TRST pin will function as a user I/O when “Reserve
JTAG Reset” box is not checked. The internal pull-up
resistor will be disabled in this mode.
Dedicated Test mode
When the “Reserve JTAG” box is checked, the SX-A is placed
in Dedicated Test mode, which configures the TDI, TCK, and
TDO pins for BST or in-circuit verification with Silicon
Explorer II. An internal pull-up resistor is automatically
enabled on both the TMS and TDI pins. In Dedicated test
mode, TCK, TDI, and TDO are dedicated test pins and
become unavailable for pin assignment in the Pin Editor.
The TMS pin will function as specified in the IEEE 1149.1
(JTAG) Specification.
Flexible mode
When the “Reserve JTAG” box is not selected (default
setting in Designer software), the SX-A is placed in Flexible
mode, which allows the TDI, TCK, and TDO pins to function
as user I/Os or BST pins. In this mode the internal pull-up
resistors on the TMS and TDI pins are disabled. An external
10kΩ pull-up resistor to VCCI is required on the TMS pin.
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
machine reaches the “logic reset” state. At this point the
BST pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set to logical HIGH.
The Program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
Development Tool Support
The SX-A devices are fully supported by Actel’s line of FPGA
development tools, including the Actel Designer Series suite
and Libero, the FPGA design tool suite. Designer Series,
Actel’s suite of FPGA development tools for PCs and
Workstations, includes the ACTgen Macro Builder, timing
driven place-and-route, timing analysis tools, and fuse file
generation. Libero is a design management environment
that integrates the needed design tools, streamlines the
design flow, manages all design and log files, and passes
necessary design data between tools. Libero includes,
Synplify, ViewDraw, Actel’s Designer Series, ModelSim HDL
Simulator, WaveFormer Lite, and Actel Silicon Explorer.
In addition, the SX-A devices contain internal probe
circuitry that provides built-in access to the output of every
C-cell, R-cell, and routed clock in the design, enabling
100-percent real-time observation and analysis of a device's
internal logic nodes without design iteration. The probe
circuitry is accessed by Silicon Explorer II, an easy-to-use
integrated verification and logic analysis tool that can
sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
SX-A Probe Circuit Control Pins
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 10 on page 11
illustrates the interconnection between Silicon Explorer II
and the FPGA to perform in-circuit verification. The TRST
pin is equipped with an internal pull-up resistor. To remove
the boundary scan state machine from the reset state during
probing, it is recommended that the TRST pin be left
floating.
Table 3 •Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode) Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated BST pins T CK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor
for TMS Use a pull-up resistor of
10kΩ on TMS