SSM3J130TU
2014-03-01
1
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM3J130TU
○ Power Management Switch Applications
• 1.5 V drive
• Low ON-resistance:RDS(ON) = 63.2 mΩ (max) (@VGS = -1.5 V)
RDS(ON) = 41.1 mΩ (max) (@VGS = -1.8 V)
RDS(ON) = 31.0 mΩ (max) (@VGS = -2.5 V)
RDS(ON) = 25.8 mΩ (max) (@VGS = -4.5 V)
Absolute Maximum Ratings (Ta = 25°C)
Characteristic Symbol Rating Unit
Drain-Source voltage VDSS -20 V
Gate-Source voltage VGSS ± 8 V
DC ID -4.4
Drain current Pulse IDP -8.8 A
PD (Note 1) 800
Power dissipation PD (Note 2) 500
mW
Channel temperature Tch 150 °C
Storage temperature range Tstg -55 to 150 °C
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual
reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: Mounted on a ceramic board.
(25.4 mm × 25.4 mm × 0.8 mm, Cu Pad: 645 mm2)
Note 2: Mounted on an FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
Marking Equivalent Circuit
(top view)
Unit: mm
JEDEC ―
JEITA ―
TOSHIBA 2-2U1A
Weight: 6.6 mg (typ.)
1: Gate
2: Source
3: Drain
-0.05
1.7±0.1
2.1±0.1
0.65±0.05
1
2
2.0±0.1
3
0.7±0.05
+0.1
0.3
0.166±0.05
UFM
JJC
1 2
3
1 2
3
Start of commercial production
2009-01
SSM3J130TU
2014-03-01
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Electrical Characteristics (Ta = 25°C)
Characteristic Symbol Test Conditions Min Typ. Max Unit
V (BR) DSS ID = -1 mA, VGS = 0 V -20 ⎯ ⎯
Drain-Source breakdown voltage
V (BR) DSX ID = -1 mA, VGS = 5 V (Note 4) -15 ⎯ ⎯
V
Drain cut-off current IDSS V
DS = -20 V, VGS = 0 V ⎯ ⎯ -1 μA
Gate leakage current IGSS V
GS = ±8 V, VDS = 0 V ⎯ ⎯ ±1 μA
Gate threshold voltage Vth V
DS = -3 V, ID = -1 mA -0.3 ⎯ -1.0 V
Forward transfer admittance ⏐Yfs⏐ V
DS = -3 V, ID = -2.0 A (Note 3) 8.8 17.5 ⎯ S
ID = -4.0 A, VGS = -4.5 V (Note 3) ⎯ 20.9 25.8
ID = -4.0 A, VGS = -2.5 V (Note 3) ⎯ 24.2 31.0
ID = -2.5 A, VGS = -1.8 V (Note 3) ⎯ 28.8 41.1
Drain–source ON-resistance RDS (ON)
ID = -1.5 A, VGS = -1.5 V (Note 3) ⎯ 32.4 63.2
mΩ
Input capacitance Ciss ⎯ 1800 ⎯
Output capacitance Coss ⎯ 205 ⎯
Reverse transfer capacitance Crss
VDS = -10 V, VGS = 0 V
f = 1 MHz ⎯ 190 ⎯
pF
Turn-on time ton ⎯ 25 ⎯
Switching time Turn-off time toff
VDD = -10 V, ID = -1.5 A
VGS = 0 to -2.5 V, RG = 4.7 Ω ⎯ 133 ⎯ ns
Total Gate Charge Qg ⎯ 24.8 ⎯
Gate-Source Charge Qgs ⎯ 18.0 ⎯
Gate-Drain Charge Qgd
VDS = -10 V, IDS = - 4.4 A,
VGS = - 4.5 V ⎯ 6.8 ⎯
nC
Drain-Source forward voltage VDSF I
D = 4.4 A, VGS = 0 V (Note 3) ⎯ 0.83 1.2 V
Note3: Pulse test
Note4: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the
drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit (b) VIN
Usage Considerations
Let Vth be the voltage applied between gate and source that causes the drain current (ID) to below −1 mA for the
SSM3J130TU. Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower than
Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on).
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
(c) VOUT
VDD = -10 V
RG = 4.7 Ω
Duty ≤ 1%
VIN: tr, tf < 5 ns
Common Source
Ta = 25°C
IN
0
-2.5V
10 μs VDD
OUT
RG
RL
ton
10%
90%
-2.5 V
0 V
90%
10%
toff
tr tf
VDS
(
ON
)
VDD
SSM3J130TU
2014-03-01
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-8.0
RDS (ON) – ID
Drain current ID (A)
Drain–source ON-resistance
RDS (ON) (mΩ)
0 -2.0 -4.0
0
-6.0 -10
100
50
VGS = -4.5 V
-1.5 V
-2.5 V
-1.8V
Common Source
Ta = 25° C
Pulse test
Ambient temperature Ta (°C)
RDS (ON) – Ta
Drain–source ON-resistance
RDS (ON) (mΩ)
0
−50 0 50 150 100
100
50
Common Source
Pulse test
ID = -4.0 A / VGS = -4.5 V
-1.5 A / -1.5 V
-4.0 A / -2.5 V
-2.5 A / -1.8V
Ambient temperature Ta (°C)
Vth – Ta
Gate threshold voltage Vth (V)
-1.0
0
−50 0 150
-0.5
50 100
Common Source
VDS = -3 V
ID = -1 mA
Drain–source ON-resistance
RDS (ON) (mΩ)
0 -2 -4 -6
Gate–source voltage VGS (V)
0
RDS (ON) – VGS
-8
50
-25 °C
25 °C
100
ID =-4.0A
Common Source
Ta = 25°C
Pulse test
Ta = 100 °C
Drain–source voltage VDS (V)
ID – VDS
Drain current ID (A)
0
-4.0
0 -0.2 -0.4 -0.6 -1
-2.0
-0.8
-6.0
-8.0
-8V
Common Source
Ta = 25 °C
Pulse test
-1.5 V
-1.8 V
VGS = -1.2 V
-2.5V
-10
-4.5V
Gate–source voltage VGS (V)
ID – VGS
Drain current ID (A)
-10
0
-0.1
-1
-0.001
-0.01
-0.0001
-1.5
-1.0
Common Source
VDS = -3 V
Pulse test
-25 °C
Ta = 100 °C
25 °C
-0.5
SSM3J130TU
2014-03-01
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Drain current ID (A)
Forward transfer admittance
⎪
Yfs
⎪
(S)
|Yfs| – ID
0.1
-10
1
10
-0.1 -1
3
0.3
-0.01
100
30
Common Source
VDS = -3 V
Ta = 25°C
Pulse test
Drain reverse current IDR (A)
Drain–source voltage VDS (V)
IDR – VDS
10
0
0.1
1
0.001
0.01
0.2 0.6
0.4 1.0 0.8 1.2
-25 °C
Ta =100 °C
25 °C
Common Source
VGS = 0 V
Pulse test
G
D
S
IDR
Drain current ID (A)
Switching time t (ns)
t – ID
1
-0.001
1000
-0.1
10000
-1 -10
100
tf
Common Source
VDD = -10 V
VGS = 0 to -2.5 V
Ta = 25 ° C
RG = 4.7Ω
10
-0.01
toff
tr
ton
Drain–source voltage VDS (V)
C – VDS
Capacitance C (pF)
10
-0.1 -1 -10 -100
1000
10000
3000
5000
300
500
100
50
30
Common Source
Ta = 25°C
f = 1 MHz
VGS = 0 V
Ciss
Crss
Coss
Total Gate Charge Qg (nC)
Dynamic Input Characteristic
Gate–source voltage VGS (V)
0 0 20 40
-4
-8
50
-6
-2
10 30
VDD = - 16 V
VDD = - 10 V
Common Source
ID = -4.4 A
Ta = 25°C
SSM3J130TU
2014-03-01
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Ambient temperature Ta (°C)
PD – Ta
Power dissipation PD (mW)
800
0
200
120 100 140
400
600
160
1000
80 60 40 20 0 -20 -40
a
b
a: Mounted on ceramic board
(25.4mm × 25.4mm × 0.8mm , Cu Pad : 645 mm2)
b: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm , Cu Pad : 645 mm2)
Transient thermal impedance Rth (°C/W)
Pulse Width tw (s)
Rth – tw
0.001 0.01 0.1 6001 10 100
1
100
600
10
b
c
a
Single pulse
a: Mounted on ceramic board
(25.4mm × 25.4mm × 0.8mm , Cu Pad : 645 mm2)
b: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm , Cu Pad : 645 mm2)
c: Mounted on FR4 Board
(
25.4mm × 25.4mm ×1.6mm , Cu Pad : 0.36 mm2×3
)
SSM3J130TU
2014-03-01
6
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