Enpirion(R) Power Datasheet ES1021QI Power Sequencing Controller ES1021QI Datasheet The Altera Enpirion ES1021QI is an integrated 4-channel controlled-on/controlled-off power-supply sequencer with supply monitoring, fault protection and a "sequence completed" signal (RESET). ES1021QI uses a patented, micropower 7x charge pump to drive four external lowcost NFET switch gates above the supply rail by 5.3V. These ICs can be biased from 5V down to 1.5V by any supply. ES1021QI has two groups of two channels, each with its independent I/O. It is ideal for voltage sequencing into redundant capability loads. All four inputs must be satisfied before turn-on, but a single group fault is ignored by the other group. Features * Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four Power Supplies (0.7V to 5V) * Operates From 1.5V to 5V Supply Voltage * Supplies VDD +5.3V of Charge Pumped Gate Drive * Adjustable Voltage Slew Rate for Each Rail * Multiple Sequencers Can be Daisy-Chained to Sequence an Infinite Number of Independent Supplies * Glitch Immunity * Undervoltage Lockout for Each Supply * Active Low ENABLE Input External resistors provide flexible voltage threshold programming of monitored rail voltages. Delay and sequencing are provided by external capacitors for ramp-up and ramp-down. * Dual Channel Groupings Additional I/O is provided for indicating and driving the RESET state in various configurations. Applications For volume applications, other programmable options and features are available. V1 V1OUT V2 V2OUT V3 V3OUT V4 V4OUT * QFN Package * Pb-free (RoHS-compliant) * Graphics Cards * FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing * Network Routers * Telecommunications Systems GATE A GATE B GATE C GATE D EN_1 5V/DIV EN_2 5V/DIV VDD UVLO_A ENABLE_1 UVLO_B ENABLE_2 UVLO_C UVLO_D RESET RESET_2 A_VOUT B_VOUT DLY_OFF_D DLY_ON_D DLY_OFF_C DLY_ON_C DLY_OFF_B DLY_ON_B DLY_OFF_A DLY_ON_A GROUND C_VOUT D_VOUT FIGURE 2. ES1021QI GROUP INDEPENDENT TURN-OFF AND DELAY ADJUSTABLE PRE-PROGRAMMED TURN-ON FIGURE 1. TYPICAL ES1021QI APPLICATION 101 Innovation Drive San Jose, CA 95134 www.altera.com July 2014 (c) 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Altera Corporation Subscribe 10128 July 9, 2014 Rev A Page 2 Ordering Information PART NUMBER (Notes 1, 2) ES1021QI PART MARKING PACKAGE (Pb-free) TEMP. RANGE (C) S1021 -40 to +85 24 Ld 4x4 QFN PKG. DWG. # L24.4x4 NOTES: 1. Add "T" suffix for Tape and Reel. Please refer to Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packingand-marking.html 2. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Enpirion Power Datasheet ES1021QI Power Sequencing Controller 10128 July 9, 2014 July 2014 Altera Corporation Rev A Page 3 Block Diagram VDD BIAS VDD+5V LOCK OUT Q-PUMP 1A 1A DLY_ONX 1.26V -1A 1A DLY_OFFX 10ms RISING DELAY 1.26V GATEX 30s FILTER UVLOX RESET LOGIC 0.633V RESET_2 150ms RISING DELAY ENABLE_1 ENABLE_2 FIGURE 3. ES1021QI BLOCK DIAGRAM July 2014 10128 Altera Corporation Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 9, 2014 Rev A Page 4 Pin Configurations ENABLE_1 22 NC NC 23 UVLO_A VDD 24 DLY_ON_A RESET ES1021QI (24 LD QFN) TOP VIEW 21 20 19 1 18 DLY_OFF_A GATE_A 2 17 UVLO_C DLY_OFF_C 3 16 DLY_ON_C EPAD (GND) 14 UVLO_D GATE_C 6 13 DLY_OFF_B 10 July 9, 2014 11 12 UVLO_B 9 ENABLE_2 8 GND 7 RESET_2 5 DLY_ON_B GATE_B GATE_D 4 Enpirion Power Datasheet ES1021QI Power Sequencing Controller 10128 15 DLY_ON_D DLY_OFF_D July 2014 Altera Corporation Rev A Page 5 Pin Descriptions PIN NAME PIN NUMBER VDD 23 DESCRIPTION Chip Bias. Bias IC from nominal 1.5V to 5V. GND 10 Bias Return. IC ground. ENABLE_1 1 ENABLE_2 11 Input to start on/off sequencing. Input to initiate start of programmed sequencing of supplies on or off. Enable functionality disabled for 10ms after UVLO is satisfied. ES1021QI has two ENABLE inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and ENABLE_2 is for (C, D). RESET 24 RESET_2 9 UVLO_A 20 UVLO_B 12 UVLO_C 17 UVLO_D 14 DLY_ON_A 21 DLY_ON_B 8 DLY_ON_C 16 DLY_ON_D 15 DLY_OFF_A 18 DLY_OFF_B 13 DLY_OFF_C 3 DLY_OFF_D 4 GATE_A 2 GATE_B 5 GATE_C 6 GATE_D 7 RESET Output. RESET provides low signal 150ms after all GATEs are fully enhanced. Delay is for stabilization of output voltages. RESET asserts low upon UVLO not being satisfied or ENABLE being deasserted. RESET outputs are open-drain, N-channel FET and are guaranteed to be in correct state for VDD down to 1V and are filtered to ignore fast transients on VDD and UVLO_X. RESET_2 only exists for (C, D) group I/O. Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout referenced to an internal 0.633V reference. Filtered to ignore short (<30s) transients below programmed UVLO level. Gate On Delay Timer Output. Allows programming of delay and sequence for VOUT turn-on using a capacitor to ground. Each capacitor charged with 1A 10ms after turn-on initiated by ENABLE/ENABLE. Internal current source provides delay to associated FET GATE turn-on. Gate Off Delay Timer Output. Allows programming of delay and sequence for VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each capacitor charged with 1A internal current source to an internal reference voltage, causing corresponding gate to be pulled down, thus turning off FET. FET Gate Drive Output. Drives external FETs with 1A current source to soft-start ramp into load. GND EPAD Ground. Die Substrate. Can be left floating. NC 19, 22 No Connect ES1021QI Feature Matrix PART NAME EN/EN CMOS/ TTL GATE DRIVE OR OPEN DRAIN OUTPUTS REQUIRED CONDITIONS FOR INITIAL START-UP EN CMOS Gate Drive 4 UVLO 2 EN ES1021QI July 2014 10128 NUMBER OF NUMBER OF CHANNELS THAT UVLO INPUTS TURN OFF WHEN ONE UVLO MONITORED BY FAULTS EACH RESET 2 UVLO Altera Corporation 2 Gates PRESET OR ADJUSTABLE SEQUENCE NUMBER OF UVLO AND PAIRS OF I/O Preset 2 Monitors with 2 I/O FEATURES Dual Redundant Operation Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 9, 2014 Rev A Page 6 Absolute Maximum Ratings (Note 5) Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V UVLO, ENABLE. . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V RESET, DLY_ON, DLYOFF . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Thermal Resistance (Typical) JA (C/W) JC (C/W) 24 Ld 4x4 QFN Package (Notes 3, 4) 46 8 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . +125C Maximum Storage Temperature Range . . . . . .-65C to +150C Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . +1.5V to +5.5V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 5. All voltages are relative to GND, unless otherwise specified. Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40C to +85C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +85C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT 619 633 647 mV UVLO Falling Undervoltage Lockout Threshold VUVLOvth TJ = +25C Undervoltage Lockout Threshold Tempco TCUVLOvth 40 V/C Undervoltage Lockout Hysteresis VUVLOhys 10 mV Undervoltage Lockout Threshold Range RUVLOvth Max VUVLOvth- Min VUVLOvth 7 mV Undervoltage Lockout Delay TUVLOdel ENABLE satisfied 10 ms VDD, UVLO, ENABLE glitch filter 30 s Transient Filter Duration tFIL DELAY ON/OFF Delay Charging Current Delay Charging Current Range Delay Charging Current Temperature Coefficient Delay Threshold Voltage Delay Threshold Voltage Temperature Coefficient DLY_ichg DLY_ichg_r VDLY = 0V 0.92 DLY_ichg(max) - DLY_ichg(min) 1 1.08 A 0.08 TC_DLY_ichg A 0.2 DLY_Vth 1.238 1.266 nA/C 1.294 V TC_DLY_Vth 0.2 mV/C ENABLE Threshold VENh 0.5 VDD V ENABLE Hysteresis VENh -VENl Measured at VDD = 1.5V 0.2 V ENABLE Lockout Delay tdelEN_LO UVLO satisfied 10 ms ENABLE Input Capacitance Cin_en 5 pF RESET Pull-up Voltage Vpu_rst VDD V ENABLE, RESET RESET Pull-Down Current RESET Delay after GATE High IRSTpd1 VDD = 1.5V, RST = 0.1V 5 mA IRSTpd3 VDD = 3.3V, RST = 0.1V 13 mA IRSTpd5 VDD = 5V, RST = 0.1V 17 mA TRSTdel GATE = VDD+5V 160 ms Enpirion Power Datasheet ES1021QI Power Sequencing Controller 10128 July 9, 2014 July 2014 Altera Corporation Rev A Page 7 Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40C to +85C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) PARAMETER RESET Output Low RESET Output Capacitance SYMBOL VRSTl TEST CONDITIONS MIN (Note 6) TYP Measured at VDD = 5V with 5k pull-up resistors MAX (Note 6) UNIT 0.1 V 10 COUT_RST pF GATE GATE Turn-On Current IGATEon GATE = 0V 0.8 1.1 1.4 A GATE Turn-Off Current IGATEoff_l GATE = VDD, Disabled -1.4 -1.05 -0.8 A 0.35 A GATE Current Range IGATE_range GATE Turn-On/Off Current Temperature Coefficient TC_IGATE GATE Pull-Down High Current IGATEoff_h GATE High Voltage GATE Low Voltage Within IC IGATE max-min 0.2 nA/C 88 mA VDD + 4.9V V VDD + 5.3V V GATE = VDD, UVLO = 0V VGATEh VDD < 2V, TJ = +25C VGATEh VDD > 2V VGATEl Gate Low Voltage, VDD = 1V IVDD_5V VDD + 5V 0 0.1 V VDD = 5V 0.20 0.5 mA IVDD_3.3V VDD = 3.3V 0.14 mA IVDD_1.5V VDD = 1.5V 0.10 mA BIAS IC Supply Current VDD Power-on Reset VDD_POR 1 V NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Descriptions and Operation The ES1021QI sequencer is a 4-channel voltage sequencing controller, and is designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD + 5.3V (VQP) in a user-programmed sequence. The ES1021QI is a 4-channel device that groups the four channels into two groups of two channels each. Each group of A, B and C, D, has its own ENABLE and RESET I/O pins. All four UVLO and both ENABLEs must be satisfied for sequencing to start. The A, B group turns on first, 10ms after the second ENABLE is pulled low, with A then B turning on, followed by C then D. Once the preceding GATE = VQP, the next DLY_ON pin starts to charge its capacitor; thus, all four GATEs turn on. Approximately 160ms after D GATE = VQP, the RESET output is released to go high. Once any UVLO is unsatisfied, only the related group's RESET and two GATEs are pulled low. The related EN input must be cycled for the faulted group to be turned on again. Normal shutdown is invoked by signaling both ENABLE inputs high, which causes the two related GATEs to shut down in reverse order from turn-on. DLY_X capacitors adjust the delay between GATES during turn-on and turn-off, but not the order. During bias up, the RESET output is guaranteed to be in the correct state, with VDD lower than 1V. ES1021QI requires that the related ENABLE be cycled for restart of its associated group GATEs. If no capacitors are connected between DLY_ON or DLY_OFF pins and ground, then all such related GATEs start to turn on immediately after the 10ms (TUVLOdel) ENABLE stabilization timeout has expired. The GATEs start to turn off immediately when ENABLE is asserted. July 2014 10128 Altera Corporation Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 9, 2014 Rev A Page 8 If some of the rails are sequenced together to reduce cost and eliminate the effect of capacitor variance on the timing, a common capacitor can be connected to two or more DLY_ON or DLY_OFF pins. In this case, multiply the capacitor value by the number of common DLY_X pins to obtain the desired timing. Table 1 shows the nominal time delay on the DLY_X pins for various capacitor values, from the start of charging to the 1.27V reference. This table does not include the 10ms of ENABLE lockout delay during a start-up sequence, but it does represent the time from the end of the ENABLE lockout delay to the start of GATE transition. There is no ENABLE lockout delay for a sequence-off, so this table illustrates the delay to GATE transition from a disable signal. TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE TIME(s) Open 0.00006 100pF 0.00013 1000pF 0.0013 0.01F 0.013 0.1F 0.13 1F 1.3 10F 13 NOTE: Nom. TDEL_SEQ = Capacitor (F)*1.3MW. Enpirion Power Datasheet ES1021QI Power Sequencing Controller 10128 July 9, 2014 July 2014 Altera Corporation Rev A Page 9 l Typical Performance Curves 1.04 634 633 1.03 VDD = 5V DLY CURRENT SOURCE (A) UV THRESHOLD (mV) 632 631 630 VDD = 1.5V 629 628 1.02 1.01 1.00 VDD = 1.5V 0.99 DLY_OFF/ON 627 0.98 626 -40 0.97 -40 VDD = +5V -20 0 20 40 60 80 100 -20 0 20 40 60 80 TEMPERATURE (C) TEMPERATURE (C) FIGURE 4. UVLO THRESHOLD VOLTAGE FIGURE 5. DLY CHARGE CURRENT Figure 6 demonstrates the independence of the ES1021QI, the redundant 2-rail sequencer. It shows that either one of the two groups can be turned off, and the ABCD order of restart with capacitor programmable delay, once both EN inputs are pulled low. Typical Performance Waveforms EN_1 5V/DIV EN_2 5V/DIV A_VOUT B_VOUT C_VOUT D_VOUT FIGURE 6. ES1021QI GROUP INDEPENDENT TURN-OFF AND DELAY ADJUSTABLE PRE-PROGRAMMED TURN-ON July 2014 10128 Altera Corporation Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 9, 2014 Rev A 100 Page 10 2.5V 3.3V 1.5V +5V C1 23 VDD DLY_ON_B DLY_ON_C 1 EN1 11 EN2 EN_1 EN_2 DLY_ON_D R1 7.68k R2 6.98k R4 4.99k DLY_ON_A R6 8.45k R5 4.99k DLY_OFF_D 14 UVLO_D DLY_OFF_C 17 UVLO_C DLY_OFF_B UVLO_A DLY_OFF_A R11 1.47k 22 21 0.068F 0.047F C8 13 0.01F 18 3 NC GATE_B GATE_C 5 6 25 EP RESET2 GND RESET1 0.01F C9 7 8 2 Q1 1 5 6 4 7 D2 DNP 19 C6 0.1F 2 GATE_D C7 4 ISL6123IR GATE_A NC C4 0.1F C5 0.01F UVLO_B 20 R3 3.01k C2 16 0.01F C3 15 S1 12 R12 2.26k 1F 8 9 24 Q1 7 8 3 R10 2 R9 DNP Q2 1 5 6 4 D1 750 10 R9 10 R10 10 R13 10 R14 FIGURE 7. ES1021QI SCHEMATIC Enpirion Power Datasheet ES1021QI Power Sequencing Controller 10128 July 9, 2014 Q2 3 RST2 RST July 2014 Altera Corporation Rev A 10 Page 11 Application Considerations Timing Error Sources In any system there are variance contributors. For ES1021QI, timing errors are mainly contributed by three sources. Capacitor Timing Mismatch Error Obviously, the absolute capacitor value is an error source; thus, lower-percentage tolerance capacitors help to reduce this error source. Figure 8 illustrates a difference of 0.57ms between two DLY_X outputs ramping to DLY_X threshold voltage. These 5% capacitors were from a common source. In applications where two or more GATEs or LOGIC outputs must have concurrent transitions, it is recommended that a common GATE drive be used to eliminate this timing error. FIGURE 8. CAPACITOR TIMING MISMATCH July 2014 10128 Altera Corporation Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 9, 2014 Rev A Page 12 DLY_X Threshold Voltage and Charging Current Mismatch The two other error sources come from the IC itself and are found across the four DLY_X outputs. These errors are the DLY_X threshold voltage (DLY_Vth) variance when the GATE_X charging and discharging current latches are set, and the DLY_X charging current (DLY_ichg) variances to determine the time to next sequencing event. Both of these parameters are bounded by specification. Figure 9 shows that, with a common capacitor, the typical error contributed by these factors is insignificant, since both DLY_X traces overlay each other. FIGURE 9. DLY_VTH AND DLY_ICHG TIMING MISMATCH Enpirion Power Datasheet ES1021QI Power Sequencing Controller 10128 July 9, 2014 July 2014 Altera Corporation Rev A Page 13 Revision History The table lists the revision history for this document. DATE REVISION July, 2014 1.0 July 2014 10128 CHANGE Initial Release. Altera Corporation Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 9, 2014 Rev A Page 14 Package Outline Drawing L24.4x4 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 4X 2.5 4.00 A 20X 0.50 B 19 PIN 1 INDEX AREA PIN #1 CORNER (C 0 . 25) 24 1 18 4.00 2 . 10 0 . 15 13 0.15 (4X) 12 7 0.10 M C A B 24X 0 . 23 +- 00 .. 07 05 24X 0 . 4 0 . 1 TOP VIEW 4 BOTTOM VIEW SEE DETAIL "X" 0.10 C C 0 . 90 0 . 1 BASE PLANE ( 3 . 8 TYP ) SEATING PLANE 0.08 C SIDE VIEW ( 2 . 10 ) ( 20X 0 . 5 ) C 0 . 2 REF 5 ( 24X 0 . 25 ) 0 . 00 MIN. 0 . 05 MAX. ( 24X 0 . 6 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. Enpirion Power Datasheet ES1021QI Power Sequencing Controller 10128 July 9, 2014 The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. July 2014 Altera Corporation Rev A