LTC3110 2A Bidirectional Buck-Boost DC/DC Regulator and Charger/Balancer DESCRIPTION FEATURES n n n n n n n n n n n VCAP Operating Range: 0.1V to 5.5V VSYS Operating Range: 1.71V to 5.25V Automatic Switchover from Charge to Backup Mode Programmable 2% Accurate Charge Input Current Limit from 125mA to 2A 1% Backup Voltage Accuracy Automatic Backup Capacitor Balancing Fixed 1.2MHz Switching Frequency Burst Mode(R) Operation: 40A Quiescent Current Built-In Programmable Multipurpose Comparator with Open-Collector Output Open-Collector Outputs to Indicate Direction of Operation and End of Charge Thermally Enhanced TSSOP-24 and 4mm x 4mm QFN-24 Packages The LTC(R)3110 is a 2A bidirectional buck-boost DC/DC regulator with capacitor charger and balancer. Its wide 0.1V to 5.5V capacitor/battery voltage and 1.8V to 5.25V system backup voltage ranges make it well suited to a wide variety of backup applications using supercapacitors or batteries. A proprietary low noise switching algorithm optimizes efficiency with capacitor/battery voltages that are above, below or equal to the system output voltage. The LTC3110 can autonomously transition from charge to backup mode or switch modes based on an external command. Pin-selectable Burst Mode operation reduces standby current and improves light-load efficiency, which combined with a 1A shutdown current make the LTC3110 ideally suited for backup applications. Additional features include voltage supervisors for direction control and end of charge, and a general purpose comparator with open-collector output for interfacing with a C. The LTC3110 is available in thermally enhanced, low profile 24-lead TSSOP and 4mm x 4mm QFN packages. APPLICATIONS n n n n Supercapacitor Backup Converter and Charger Battery Backup Converter and Charger Servers, RAID Systems RF Systems with Battery/Capacitor Backup All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION ICHARGE FB MAIN STEP-DOWN DC/DC 0.1V UP TO 5.5V 10F 1960k 2.2H 1F 51.1 SW2 SVSYS VCAP SW1 FBVCAP 220nF VSYS VSYS 3.25V 2A 47F RSEN 1.50k CMPIN 0.1F VMID SYSTEM DC/DC REGULATORS 976k LTC3110 2.5V 1.8V 1.2V FB 221k 1000k MODE RUN SGND PGND DIR CHRG CAPOK CMPOUT C END OF CHRG CAPLOW 3110 TA01a Document Feedback For more information www.analog.com 12V BUS SUPERVISOR 1.0 90 0.8 85 0.6 80 0.4 75 0.2 70 1000k 1.2 VSYS = 3.25V ISYS = 0.5A 95 PROG 13.7k 523k 100 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 POWER LOSS (W) 10F Backup Mode Efficiency IBACKUP EFFICIENCY (%) 12V BUS 0 VCAP (V) 3110 TA01b Rev C 1 LTC3110 ABSOLUTE MAXIMUM RATINGS (Note 1) VCAP, VSYS, SVSYS, VMODE, VCMPIN, VDIR, VRUN, VCAPOK, VCMPOUT, VCHRG....... -0.3V to 6V RSEN DC Current ...................................................... 1.6A Operating Junction Temperature Range (Notes 2, 3)............................................. -40C to 150C Storage Temperature Range................... -65C to 150C Lead Soldering Temperature (Soldering, 10 sec) TSSOP............................................................... 300C Reflow Peak Body Temperature (30sec max) QFN.................................................................... 260C PIN CONFIGURATION TOP VIEW 6 25 PGND CMPIN 1 7 RUN 8 17 SW2 FB 9 16 SW2 PROG 10 15 VSYS CHRG 11 14 RSEN SVSYS 12 13 VSYS 18 SW1 FBVCAP 2 19 PGND DIR VCAP SGND VCAP 20 SW1 17 SW1 SGND 3 18 PGND DIR 4 FE PACKAGE 24-LEAD PLASTIC TSSOP TJMAX = 150C, JA = 33C/W, JC = 5C/W, 4 LAYER BOARD EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB 16 PGND 25 PGND 15 PGND RUN 5 14 SW2 FB 6 13 SW2 7 8 9 10 11 12 VSYS 5 VMID FBVCAP 24 23 22 21 20 19 RSEN 21 SW1 CAPOK 4 VSYS 22 VCAP CMPIN CMPOUT 23 VCAP 3 CHRG 2 MODE SVSYS CMPOUT TOP VIEW MODE 24 VMID PROG CAPOK 1 UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 150C, JA = 37C/W, JC = 4.5C/W, 4 LAYER BOARD EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3110EFE#PBF LTC3110EFE#TRPBF LTC3110FE 24-Lead Plastic TSSOP -40C to 125C LTC3110IFE#PBF LTC3110IFE#TRPBF LTC3110FE 24-Lead Plastic TSSOP -40C to 125C LTC3110HFE#PBF LTC3110HFE#TRPBF LTC3110FE 24-Lead Plastic TSSOP -40C to 150C LTC3110EUF#PBF LTC3110EUF#TRPBF 3110 24-Lead (4mm x 4mm) Plastic QFN -40C to 125C LTC3110IUF#PBF LTC3110IUF#TRPBF 3110 24-Lead (4mm x 4mm) Plastic QFN -40C to 125C LTC3110HUF#PBF LTC3110HUF#TRPBF 3110 24-Lead (4mm x 4mm) Plastic QFN -40C to 150C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 Rev C For more information www.analog.com LTC3110 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VCAP = 3.3V, VSYS = 3.3V, VDIR = VSGND, VMODE = VRUN = VSYS = SVSYS unless otherwise noted. PARAMETER CONDITIONS VCAP No-Load Operating Range in Backup Operation VSYS 1.8V VCAP Start-Up VSYS Operating Range in Charge Operation Undervoltage Lockout Threshold VSYS Ramping Down, VCAP = 0V VSYS Ramping Up, VCAP = 0V l VCAP Ramping Down, VSYS = 0V, VRUN = VCAP VCAP Ramping Up, VSYS = 0V, VRUN = VCAP l 0C < TJ < 85C (Note 5) -40C < TJ < 150C l FB Feedback Voltage MIN TYP 0.1 VSYS < Undervoltage Lockout Threshold l 1.8 VDIR = VSYS l 1.8 5.5 FBVCAP End-of-Charge Threshold Rising DIR = VSYS l FBVCAP End-of-Charge Threshold Falling DIR = VSYS l FBVCAP Input Current VFBVCAP = 1.1V FBVCAP Overcharge Threshold Rising V V V 1.71 V V 1.71 V V 0.6 0.6 0.608 0.611 V V 0.1 50 nA 1.095 1.117 1.55 FB Feedback Pin Input Current UNITS 5.25 1.55 0.592 0.589 MAX V 1.040 1.061 0.1 50 nA 1.125 1.150 1.175 V FBVCAP Overcharge Hysteresis V 35 mV VMODE = 0V 40 A Quiescent Current, End of Charge (IVCAP + IVSYS + ISVSYS) VDIR = VSYS 40 A Quiescent Current, Burst Mode Operation (IVCAP + IVSYS + ISVSYS) Quiescent Current, Shutdown (IVCAP) VRUN = 0V, VSYS = SVSYS = 0V Peak Current Limit in Backup Operation (Note 4) 0.05 1 A 5 6 7 A DC Current Limit in Backup Operation (Note 4) 3.5 4.5 Peak Current Limit in Charge Operation (Note 4) 5 6 7 A Reverse Current Limit in Backup Operation (Note 4) 1 1.2 2 A Switch Leakage Switch B, C: VCAP = VSW1 = 5.5V, VSYS = VSW2 = 5.25V, 0.1 A Switch A, D: VCAP = 5.5V, VSYS = 5.25V VSW1 = VSW2 = 0V 0.1 A Switch A (Note 6) Switch B (Note 6) Switch C (Note 6) Switch D Including Sense Resistor (Note 6) 64 49 49 86 m m m m Switch On-Resistance Oscillator Frequency Soft Start-Up Time in Backup Mode Maximum Duty Cycle in Boost Mode l VCAP = 0.2V VSYS = 0.2V From VRUN rising to VFB = 90% l VCAP = 0.2V Minimum Duty Cycle in Buck Mode MODE Input Logic Threshold l 900 1200 300 300 1500 kHz kHz kHz 0.8 1.3 1.8 ms 91 93 98 96 % % 0 % 0.3 V V l Enable Burst Mode Operation Enable PWM Mode Operation A 1 MODE Input Pull-Down Resistor 6 M DIR Threshold Rising l 1.073 1.095 1.117 V DIR Threshold Falling l 1.024 1.045 1.066 V DIR Hysteresis l 30 DIR Input Current VDIR = 1.1V 50 70 mV 0.1 50 nA Rev C For more information www.analog.com 3 LTC3110 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VCAP = 3.3V, VSYS = 3.3V, VDIR = VSGND, VMODE = VRUN = VSYS = SVSYS unless otherwise noted. PARAMETER CONDITIONS CMPIN Threshold Rising CMPIN Threshold Falling CMPIN Input Current l MIN TYP MAX UNITS 0.638 0.65 0.662 V 0.575 0.59 0.605 V 0.1 50 nA VCMPIN = 5.5V PROG Voltage VFBVCAP = 1V, DIR = VSYS 0.6 V PROG Current Gain DIR = VSYS 200 A/A IVSYS Input Current Limit RPROG = 24.3k (Notes 7, 8), DIR = VSYS RPROG = 24.3k (Notes 7, 8, 9), DIR = VSYS, TJ = -40C to 125C RPROG = 12.1k (Notes 7, 8), DIR = VSYS RPROG = 12.1k (Notes 7, 8, 9), DIR = VSYS, TJ = -40C to 125C RPROG = 6.04k (Notes 7, 8), DIR = VSYS RPROG = 6.04k (Notes 7, 8, 9), DIR = VSYS, TJ = -40C to 125C RPROG = 3.01k (Notes 7, 8), DIR = VSYS RPROG = 3.01k (Notes 7, 8, 9), DIR = VSYS, TJ = -40C to 125C RPROG = 1.5k (Notes 7, 8), DIR = VSYS RPROG = 1.5k (Notes 7, 8, 9), DIR = VSYS, TJ = -40C to 125C VMID to VCAP Voltage Ratio VMID = Open Load, VCAP = 5V VMID Balancing Current VCAP = 5V, VMID = 5V VCAP = 5V, VMID = 0V l l 119 115 123 123 128 135 mA mA 241 234 248 248 255 270 mA mA 487 473 497 497 507 525 mA mA 977 948 997 997 1017 1046 mA mA 1960 1900 2000 2000 2040 2100 mA mA 0.492 0.5 0.508 150 300 -300 -150 mA mA VMID Current in Shutdown VRUN = 0V 0.1 1 A VMID Suspend Charging Threshold VMID Rising, VCAP = 5V VMID Falling, VCAP = 5V 2.6 2.4 2.62 V V CHRG, CAPOK, CMPOUT Open-Drain Output Voltage I = 10mA 0.1 0.3 V l RUN Input Logic Threshold l RUN Pull-Down Resistor 0.3 1 6 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3110 is tested under pulsed load conditions such that TJ ~ TA. The LTC3110E is guaranteed to meet performance specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3110I is guaranteed to meet specifications over the -40C to 125C operating junction temperature range. The LTC3110H is guaranteed to meet specifications over the full -40C to 150C operating junction temperature range. High temperatures degrade operating lifetime; operating life time is derated for junction temperatures greater than 125C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in C) is calculated from the ambient temperature (TA, in C) and power dissipation (PD, in watts) according to the formula: TJ = TA + (PD * JA), 2.38 V M Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: Current measurements are performed when the LTC3110 is not switching. The current limit values measured in operation will be somewhat higher due to the propagation delay of the comparators. Note 5: Guaranteed by design characterization and correlation with statistical process controls. Note 6: Guaranteed by design, correlation and bench measurements. Note 7: Current measurements are made when the output is not switching. Note 8: Accuracy of this specification is directly related to the accuracy of the resistor used to program the parameter. Note 9: The Input Current Limit is reduced at junction temperatures above 125C. See Thermal Foldback of Charge Current in the Operation section, and the graph VPROG Programming Voltage vs Temperature in the Typical Performance Characteristics section. where JA (in C/W) is the package thermal impedance. 4 Rev C For more information www.analog.com LTC3110 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs VCAP Voltage Burst Mode Efficiency VSYS = 3.25V PWM MODE 95 EFFICIENCY (%) 80 75 ISYS = 0.2A ISYS = 0.5A ISYS = 1A ISYS = 2A 70 65 0.5 1.5 2.5 3.5 VCAP (V) 4.5 80 75 70 0.001 0.01 ISYS (A) IVSYS (mA) IVSYS (A) 3 2 2 1 3 VCAP (V) 400 125 350 115 300 105 250 200 100 0 5 5.5 4 0 2 1 3 VCAP (V) 180 170 VCAP < ~75% * VSYS 80 4 60 TJ = 85C TJ = 25C 55 0 0.5 1 1.5 2 2.5 3 VCAP (V) 3.5 4 4.5 5 VCAP > ~75% * VSYS TJ = 155C TJ = 130C TJ = 85C TJ = 25C TJ = 0C TJ = -45C 95 75 45 1.5 2 2.5 3 3.5 4 4.5 5 150 140 130 120 110 100 3110 G06 105 90 80 75 TJ = 25C 70 TJ = 0C 60 3.5 4 4.5 5 5.5 VSYS (V) 3110 G07 3110 G08 TJ = 85C 85 60 1.5 3 TJ = 155C TJ = 125C 95 65 2.5 VSYS < ~75% * VCAP 100 70 2 5.5 RDS(ON) of SWD Static Including Sense Resistor 90 TJ = 0C TJ = -45C 0 5.5 4.5 VCAP (V) 80 50 45 RDS(ON) (m) RDS(ON) (m) 75 TJ = 125C 3.5 VCAP (V) 55 5 5.5 VSYS > ~75% * VCAP TJ = 155C TJ = 130C TJ = 85C TJ = 25C TJ = 0C TJ = -45C 160 65 2.5 85 RDS(ON) of SWD Dynamic Including Sense Resistor TJ = 155C 1.5 3110 G05 RDS(ON) of SWA Static 70 0.5 65 U_VSYS = 1.8V U_VSYS = 3.3V U_VSYS = 5.25V 50 1.0 RDS(ON) of SWA Dynamic 135 3110 G04 85 70 450 150 U_VSYS = 1.8V U_VSYS = 3.3V U_VSYS = 5.25V 1.5 VSYS = 3.3V RPROG = 3.01k 3110 G03 RDS(ON) (m) PULSED LOAD T = 1s 40% DUTY CYCLE 0 80 Maximum Load Current in Burst Mode Operation 4 0 2.0 3110 G02 Maximum Load Current in PWM Mode 1 90 50 0.5 0.1 3110 G01 5 2.5 60 VCAP = 5V, VSYS = 3.3V VCAP = 2.5V, VSYS = 1.8V 5.5 100 TJ = -45C 1.5 2 2.5 3 3.5 VSYS (V) 4 4.5 3110 G09 Rev C For more information www.analog.com 5 POWER LOSS (W) 85 EFFICIENCY (%) 85 90 EFFICIENCY (%) Charge Efficiency 90 RDS(ON) (m) 100 TA = 25C unless otherwise noted LTC3110 TYPICAL PERFORMANCE CHARACTERISTICS TJ = 155C TJ = 125C TJ = 85C TJ = 25C TJ = 0C TJ = -40C 2.5 3.5 4 4.5 VCAP (V) 3 5 5.5 6 Switch Leakage vs Temperature TJ = 155C TJ = 125C TJ = 85C TJ = 25C TJ = 0C TJ = -40C 2 2.5 3 3.5 4 4.5 VSYS (V) 0.5 0 1 2 3 VCAP (V) 4 VFB CHANGE FROM 25C (%) VFB CHANGE FROM VCAP = 2.4V (%) PWM MODE Burst Mode OPERATION -1.0 5 5.5 0.5 Burst Mode OPERATION 0 PWM MODE -0.5 600 VSYS = 3.3V VSYS = 1.8V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCAP (V) 30 55 80 105 130 155 3110 G12 VSYS Load Regulation 1.0 -5 75 35 115 0.5 PWM MODE 0 Burst Mode OPERATION -0.5 -1.0 155 0 0.5 1.0 2.5 1.5 2.0 ILOAD (A) 3.0 3110 G15 Switching Frequency vs Temperature Switching Frequency vs VSYS 1.0 1200 CHANGE FROM 25C (%) SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) 800 1000 800 600 400 200 FREQUENCY FOLDBACK AT LOW VSYS VCAP = 3.3V VCAP = 1.8V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VSYS (V) 3110 G16 6 5 3110 G14 1400 1000 200 1.0 TJ (C) Switching Frequency vs VCAP FREQUENCY FOLDBACK AT LOW VCAP 1.5 0 -45 -20 6 ILOAD = 1mA -1.0 -45 5 1200 400 2.0 TJ (C) 3110 G13 1400 2.5 Feedback Voltage vs Temperature 1.0 ILOAD = 1mA 0 3.0 3110 G11 Feedback Voltage vs VCAP 0.5 SWITCH B, C SWITCH A, D 3.5 0.5 3110 G10 1.0 4.0 VOLTAGE CHANGE (%) 2 RDS(ON) (m) RDS(ON) (m) RDS(ON) of SWC 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 1.5 SWITCH LEAKAGE (A) RDS(ON) of SWB 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 1.5 TA = 25C unless otherwise noted 3110 G17 0.5 0 -0.5 -1.0 -45 5 55 105 155 TJ (C) 3110 G18 Rev C For more information www.analog.com LTC3110 TYPICAL PERFORMANCE CHARACTERISTICS VPROG Programming Voltage vs Temperature VPROG Programming Voltage vs Temperature VPROG Programming Voltage vs VFBVCAP 1.0 0.7 0.7 0.8 0.5 THERMAL CHARGE CURRENT FOLDBACK 0.4 0.3 0.2 0.1 0.6 0.6 0.5 0.4 0.2 VPROG (V) VPROG CHANGE FROM 25C (%) 0.6 VPROG (V) TA = 25C unless otherwise noted 0 -0.2 -0.4 5 30 55 80 TJ (C) 0.1 -1.0 -45 105 130 155 5 -20 55 30 TJ (C) 80 105 VPROG Programming Voltage vs VCAP 0.2 0.1 0 0.4 0.3 0.2 0.1 0 0 1 2 3 VCAP (V) 4 1.2 -0.5 5 0 -0.5 1.7 2.6 -1.0 -45 5.3 4.4 3.5 -5 75 35 VSYS (V) FBVCAP Comparator Thresholds vs Temperature 115 155 TJ (C) 3110 G24 3110 G23 IVSYS Input Current Limit vs RPROG DIR Thresholds vs Temperature 1.0 1.4 FALLING RISING 3110 G22 1.0 2000 0.8 1750 0.4 0.2 0 -0.2 -0.4 -0.6 FALLING RISING -1.0 -45 -25 -5 15 35 55 75 95 115 135 155 TJ (C) 0.5 1500 1250 IVSYS (mA) 0.6 CHANGE FROM 25C (%) VFBVCAP CHANGE FROM 25C (%) 0.6 0.8 1.0 VFBVCAP (V) -0.4 -0.4 -0.8 0.4 0.5 -0.3 -0.3 0.2 1.0 RPROG = 6.04k -0.2 -0.2 0 CMPIN Threshold Voltage vs Temperature -0.1 -0.1 END OF CHARGE 3110 G21 CHAGNE FROM 25C (%) CHANGE IN VPROG FROM VSYS = 3.3V (%) CHANGE IN VPROG FROM VCAP = 1.8V (%) 0.5 0.3 -0.5 130 VPROG Programming Voltage vs VSYS RPROG = 6.04k 0.4 0 3110 G20 3110 G19 0.5 0.3 0.2 -0.6 -0.8 0 -45 -20 CHARGE CURRENT FOLDBACK AT END OF CHARGE 0.4 0 1000 -0.5 -1.0 -45 750 500 FALLING RISING -5 35 75 115 155 TJ (C) 3110 G25 3110 G26 250 0 0 2 4 6 8 10 12 14 16 18 20 22 24 RPROG (k) 3110 G27 Rev C For more information www.analog.com 7 LTC3110 TYPICAL PERFORMANCE CHARACTERISTICS PROG Current Gain vs Temperature IVSYS Input Current vs VCAP RPROG = 3.01k RPROG = 6.04k 0.50 RPROG = 12.4k 0 1.0 2.0 3.0 VCAP (V) 4.0 0.5 0 -0.5 -1.0 -2.0 -45 5.0 -15 15 45 3 2 1 RPROG = 6.04k RPROG = 3.01k RPROG = 1.50k -1.5 75 105 0 135 1 0 2 TJ (C) 3 VCAP (V) 4 5 3110 G29 3110 G28 VMID Load Regulation 3001 G30 VMID Buffer Current vs VCAP 1.0 VMID vs Temperature 1.0 400 VCAP = 2.5V NO LOAD 300 VMID = VCAP 200 VCAP = 5V 0 VOLTAGE CHANGE (%) 0.5 IVMID (mA) VOLTAGE CHANGE (%) RPROG = 1.50k RPROG = 3.01k RPROG = 6.04k RPROG = 12.4k 4 1.0 CURRENT (A) IVSYS (A) 1.50 1 IVCAP Charge Current vs VCAP 1.5 RPROG = 1.50k 2.00 0 5 2.0 CHANGE FROM 25C (%) 2.50 TA = 25C unless otherwise noted 100 0 -100 -0.5 -200 VMID = PGND 0.5 VCAP = 5.5V 0 VCAP = 2.6V -0.5 -300 -1.0 -0.3 -0.2 -0.1 0 0.1 IMID (A) 0.2 0.3 -400 0 1 2 3 4 5 -1.0 -45 -5 155 3110 G33 Backup Soft-Start Backup Time RUN 5V/DIV VSYS 2V/DIV VSYS 1V/DIV 0.50 115 TJ (C) 3110 G32 Input Current Limit Aging 1.00 75 35 VCAP (V) 3110 G31 CHANGE FROM T = 0 YEAR (%) 6 ILOAD = 2A 1A 0.5A 0.25A 0V 0V 0 -0.50 -1.00 ACCELERATED LOAD LIFE TEST DATA SCALED TO TJ = 105C, IVSYS = 2A CONDITIONS 0 5 10 15 20 TIME (YEAR) 25 VCAP 2V/DIV IL 0.2A/DIV 0A 0V 200s/DIV 3110 G35 C1 = C2 = 2.4F 2s/DIV 3110 G45 30 3110 G34 8 Rev C For more information www.analog.com LTC3110 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C unless otherwise noted Charge Sleep to Backup Transient in Autonomous Application Load Step 0A to 2A BACKUP VSYS 1V/DIV VSYS 200mV/DIV ILOAD 1A/DIV CHRGB 5V/DIV 0V VSYS 1V/DIV CHRGB 5V/DIV 0V IL 1A/DIV 0A IL 1A/DIV 3110 G37 200s/DIV Burst Mode Operation 3110 G38 PWM Mode Operation in VCAP Overvoltage Failure Condition SW1 1V/DIV SW1 5V/DIV IL 0.2A/DIV 0A IL 0.5A/DIV SW2 5V/DIV IL 100mA/DIV 0A SW2 1V/DIV 0A 10ms/DIV 3110 G40 500ns/DIV 3110 G41 FBVCAP = 1.2V VDIR = 0V Charge Balancer Operation C1 < C2 VCAP VMID 2V/DIV 0V 3110 G42 500ns/DIV ISYS = 100mA Charge Balancer Operation C1 > C2 3110 G39 200s/DIV PWM Mode Operation VSYS 50mV/DIV CHARGING 0A 0A 100s/DIV Backup to Charge Transient in Autonomous Application Single Capacitor Backup VCAP VMID 2V/DIV ILOAD = 300mA C1 = 1.2F VSYS 1V/DIV 0V 0V 0A 0A VCAP 1V/DIV ISYS 1A/DIV ISYS 1A/DIV 1s/DIV 3110 G43 0V 1s/DIV 3110 G44 500ms/DIV 3110 G36 Rev C For more information www.analog.com 9 LTC3110 PIN FUNCTIONS (FE/UFD) CAPOK (Pin 1/Pin 22): VCAP Voltage OK Indicator Output. The open-drain output is pulled low if the FBVCAP voltage is lower than the FBVCAP falling threshold. The output is released if FBVCAP is higher than the rising threshold. CMPOUT (Pin 2/Pin 23): General Purpose Comparator Output. The open-drain output is pulled low while the CMPIN pin voltage is above the comparator rising threshold. The output is released when CMPIN is below the falling threshold. MODE (Pin 3/Pin 24): Burst/PWM Mode Selection Input. Driving MODE to a logic 1 state programs fixed frequency, low noise PWM operation. Driving MODE low programs Burst Mode operation. Note that the MODE pin has no effect when operating in charger mode. CMPIN (Pin 4/Pin 1): General Purpose Comparator Positive Input with Hysteresis. The voltage at CMPIN is compared to an internal reference voltage. The pin can be driven digitally or configured as voltage supervisor with the help of an external resistor divider. If driven from a resistor divider or from a source with >200 impedance, connect a 0.1F capacitor between CMPIN and GND for best performance. The CMPIN rising threshold is 0.65V and the falling threshold is 0.59V. FBVCAP (Pin 5/Pin 2): VCAP End-Of-Charge Voltage Programming Feedback Divider Input with Hysteresis. The end-of-charge threshold can be adjusted from 1.1V to 5.5V. The FBVCAP rising threshold is 1.095V and falling threshold is 1.061V. SGND (Pin 6/Pin 3): Signal Ground Connection. A ground plane is highly recommended. Sensitive analog 10 components terminated at ground should connect to the SGND pin with a Kelvin connection, separated from the high current path in PGND. DIR (Pin 7/Pin 4): Charge/Backup Mode Selector Input with Hysteresis. A voltage on DIR above the rising threshold enables the LTC3110 charger mode. A voltage below the falling threshold enables the backup mode. The pin can be driven digitally, e.g., from a C. With the help of an external resistor divider the pin can be configured as voltage supervisor input monitoring any system voltage. The DIR rising threshold is 1.095V and the falling threshold is 1.045V. RUN (Pin 8/Pin 5): Logic-Controlled Shutdown Input. RUN 1.0V: Normal Operation RUN 0.3V: Shutdown FB (Pin 9/Pin 6): VSYS Backup Voltage Feedback Pin. Connect resistor divider tap here. The VSYS voltage can be adjusted from 1.8V to 5.25V. The feedback reference voltage is 0.6V. PROG (Pin 10/Pin 7): Charger Input Current (IVSYS) Programming Resistor. A resistor from PROG to SGND programs the average current flowing in VSYS when operating in charging mode. R PROG = 3k *A I VSYS for 1.5k < R PROG < 24.3k RPROG can be increased to 48.7k if the charge current foldback is avoided with FBVCAP held down < 1V or grounded. Rev C For more information www.analog.com LTC3110 PIN FUNCTIONS (FE/UFD) CHRG (Pin 11/Pin 8): Charge/Backup Mode Indicator Output. The open-drain output is pulled low while the regulator is in charge mode. The open-drain output is released while the regulator is in backup mode. SVSYS (Pin 12/Pin 9): Signal Supply Voltage Input for Buck/Boost Controller Circuitry. Pin must be shorted to VSYS or supplied from VSYS through a RC filter. See the Applications Information section for details. VSYS (Pins 13, 15/Pins 10, 12): Bidirectional Power Supply Pin for System Backup Output Voltage and Charge Current Input Voltage. A bypass capacitor must be connected between VSYS and PGND. Refer to the Typical Applications schematics and the Applications Information section for capacitor selection details. RSEN (Pin 14/Pin 11): Current Sense Resistor Tap at Junction of Internal Sense Resistor and Switch D. Pin RSEN is internally shorted to pin VSYS via low impedance. DC current in RSEN must be limited to 1.6A. SW2 (Pins 16, 17/Pin 13, 14): Switch Pin Connected to Internal Switches C and D of the Buck-Boost Regulator. Connect one side of the buck-boost inductor to SW2. Provide a short wide PCB trace from the inductor to SW2 to minimize voltage transients and noise. PGND (Pins 18, 19, Exposed Pad Pin 25/Pins 15, 16, Exposed Pad Pin 25): Power Ground Connection. Terminate all high current ground paths to PGND. The exposed pad must be soldered to the PCB ground for rated thermal performance. SW1 (Pins 20, 21/Pins 17, 18): Switch Pin Connected to Internal Switches A and B of the Buck-Boost Regulator. Connect one side of the buck-boost inductor to SW1. Provide a short wide PCB trace from the inductor to SW1 to minimize voltage transients and noise. VCAP (Pins 22, 23/Pins 19, 20): Bidirectional Power Pin for Connection to Supercap Backup Capacitor(s) or Backup Battery(ies). When in charge mode a current flows out of pin VCAP to charge the storage elements connected between VCAP and PGND. When in backup mode the current is flowing into pin VCAP and the stored energy is used to backup the load on VSYS. VMID (Pin 24/Pin 21): Active Voltage Balancing Power Output. This pin should be tied to the junction of two series supercapacitors. If the output is not used, a compensation capacitor of 1nF must be connected between pins VMID and PGND. Rev C For more information www.analog.com 11 LTC3110 BLOCK DIAGRAM CCAP 1F VOLTAGE BALANCING VMID VCAP SW1 A BUF D C2 10F B + - R1 END OF CHARGE SVSYS OVERCHARGE THRESHOLD CAPOK + - BUCK-BOOST CONTROL CHARGER + - ENABLE CMPIN CCMPIN 0.1F VTH(CMP) + - UNDERVOLTAGE LOCKOUT CMPOUT CAPLOW EN RRUN HIGH = ENABLE LOW = SHUTDOWN + - VREF(PROG) + - RUN DIR VSYS VTH(DIR) CHRG HIGH = CHARGING LOW = BACKUP RCHRG CHARGING/BACKUP EN COMP BACKUP R4 RPROG COMP VCAP + - VSYS LOCKOUT THRESHOLD + - + - RCAPLOW PROG OSC RMODE MODE R3 VSYS 1.8V TO 5.25V 2A VSYS CHARGER INPUT CURRENT SENSE ENABLE VSYS CSYS 47F VTH(CHRG) RUN HIGH = FORCED PWM LOW = Burst Mode OPERATION VSYS FBVCAP END OF CHARGE THRESHOLD RCAPOK C + - R2 VSYS RSEN SW2 + - C1 10F RSVSYS 51.1 CSVSYS RSEN 220nF L1 1.5H VCAP 0.1V TO 5.5V FB R6 VREF(FB) TEMP SHUTDOWN VREF AND BIAS VREFOK R5 EN SGND PGND 3110 BD 12 Rev C For more information www.analog.com LTC3110 OPERATION INTRODUCTION Charging The LTC3110 is a monolithic buck-boost DC/DC regulator/ charger combination with pin-selectable operation modes to utilize a single LTC3110 device for charging (VDIR = high) as well as for system backup (VDIR = low). During charging a limit for the average current drawn from the system power source can be accurately programmed with an external resistor. An integrated, active, voltage balancing buffer at pin VMID prevents capacitor overvoltage conditions caused from capacitor mismatch while charging a stack of supercapacitors. When powered from the system voltage, VSYS, the buckboost regulator is usually set to operate in charge mode (VDIR = high), that is, a voltage source connected to VSYS is the power input into the LTC3110 and the converter charges a backup storage element connected between the VCAP and PGND pins. When operating in charge mode, the LTC3110's average current limit circuitry is active. With a resistor between the PROG and SGND pins, the maximum average current drawn from VSYS can be programmed to accurately limit the current demand. The buck-boost regulator utilizes a proprietary switching algorithm which allows the system voltage, VSYS, to be regulated above, below, or equal to the voltage on the storage element, VCAP, without discontinuity in inductor current or large voltage ripple in the backup voltage VSYS. With the DIR pin direction control circuitry, the LTC3110 can instantly reverse the inductor current and change between charging and backup operation modes, reacting quickly on a power failure condition by providing the backup voltage to the system (see Figure 1). VCAP VMID 2V/DIV 0A ISYS 1A/DIV 1SECOND/DIV 3110 F02 Figure 2. Charge Foldback and Charge Termination Active Charge Balancer VSYS 1V/DIV CHRG 5V/DIV IL 1A/DIV 0A 200s/DIV 3110 F01 Figure 1. Transition from Charge- into Backup Operation The LTC3110 has been optimized to reduce quiescent current in shutdown and standby for applications that are sensitive to quiescent current drawn from the system voltage, VSYS, or the storage element, VCAP. In charge operation the standby current is only 40A. In backup/ Burst Mode operation, the no-load standby current is only 40A. In shutdown the total supply current is reduced to less than 1A. While charging, the integrated linear charge balancing buffer regulates the mid-voltage, VMID, of a stack of capacitors to half of VCAP thus equalizing out voltage mismatches of top and bottom capacitor, see Figure 3. If the capacitor mismatch is exceeding the current capabilities of the charge balancer, charging is suspended until VMID comes back to half of VCAP (see charging waveforms in the Typical Performance Characteristics section). Note, the suspend charge function is only active for VCAP > 2.2V = VTH(CHRG) with hysteresis. For VCAP < 2V the charger operation is always continuous. Rev C For more information www.analog.com 13 LTC3110 OPERATION LTC3110 C1 VMID VOLTAGE BALANCING current that can be delivered by the converter, reduces VSYS voltage ripple, and yields a low noise fixed-frequency switching spectrum. A proprietary switching algorithm provides seamless transitions between operating modes and eliminates discontinuities in the average inductor current, inductor current ripple, and loop transfer function throughout all regions of operation. These advantages result in increased efficiency, improved loop stability, and lower VSYS voltage ripple in comparison to the traditional 4-switch buck-boost converter. VCAP R BUF C2 R + - + - WINDOW COMPARATOR 1 = ALLOW CHARGING 0 = SUSPEND CHARGING 3110 F03 Figure 3. Active Charge Balancer Charge Termination The final charge voltage at pin VCAP is programmed with a resistor divider at FBVCAP, see Figure 10 in the Application Information Section. If FBVCAP exceeds typically 95% of its end of charge threshold, the PROG reference voltage and with it the charge current level begins to fold back (see Figure 2). Before charge termination the charge current is eventually folded back to a level of typically 30% of the programmed value (see charging waveforms in the Typical Performance Characteristic section). When the programmed voltage level is reached, the controller will terminate charging and switch off into a low quiescent current state wherein the charge balancer at the VMID pin is disabled and the CAPOK pin is released. The low current state is maintained until the voltage on VCAP decays and the FBVCAP falling threshold is crossed. After this, controller and charge balancer will resume operation with the CAPOK pin pulled low until the regulation voltage is reached again. Note the IC cannot prevent outside sources leaking current into the capacitors from overvoltaging them. Figure 4 shows the topology of the LTC3110 power stage which is comprised of two P-channel MOSFET switches and two N-channel MOSFET switches and their associated gate drivers. In response to the error amplifier output, an internal pulse-width modulator generates the appropriate switch duty cycles to maintain regulation of the VSYS voltage. When the VCAP voltage is significantly greater than the VSYS voltage, the buck-boost converter operates in buck mode. Switch D turns on continuously and switch C remains off. Switches A and B are pulse-width modulated to produce the required duty cycle to support the VSYS regulation voltage. As the VCAP voltage decreases, switch A remains on for a larger portion of the switching cycle. When the duty cycle reaches approximately 90%, the switch pair AC begins turning on for a small fraction of the switching period. As the VSYS voltage decreases further, the AC switch pair remains on for longer durations and the duration of the BD phase decreases proportionally. At this point, switch A remains on continuously while switch pair CD is pulse-width modulated to obtain the desired VSYS voltage. At this point, the converter is operating solely in boost mode. L VCAP Backup Operation in Fixed Frequency PWM Mode With the MODE pin held high while VDIR = low, the LTC3110 operates in a fixed-frequency pulse-width modulation (PWM) mode using a voltage mode control loop. This mode of operation maximizes the VSYS backup 14 SW2 SW1 A VSYS D B C LTC3110 3110 F04 Figure 4. Buck-Boost Switch Topology Rev C For more information www.analog.com LTC3110 OPERATION Backup in Burst Mode Operation Reverse Current Limit (Backup Mode) When MODE is held low while VDIR = low, the buck-boost converter operates in Burst Mode operation using a variable frequency switching algorithm that minimizes the no-load input quiescent current and improves efficiency at light load by reducing the amount of switching to the minimum level required to support the load. The VSYS current capability in Burst Mode operation is substantially lower than in PWM mode and is intended to support light stand-by loads. Curves showing the maximum Burst Mode load current as a function of the VCAP and VSYS voltage can be found in the Typical Performance Characteristics section of this data sheet. If the converter load in Burst Mode operation exceeds the maximum Burst Mode current capability, VSYS will lose regulation. Each Burst Mode cycle is initiated when switches A and C turn on producing a linearly increasing current through the inductor. When the inductor current reaches the Burst Mode peak current limit, switches A and C are turned off and switches B and D are turned on, discharging the energy stored in the inductor into the VSYS capacitor and load. Once the inductor current reaches zero, all switches are turned off and the cycle is complete. Current pulses generated in this manner are repeated as often as necessary to maintain regulation of the VSYS voltage. In PWM mode operation the LTC3110 has the ability to actively conduct current away from VSYS if it is necessary to maintain regulation. If VSYS is held above the regulation voltage, it could result in large reverse currents. This situation can occur if VSYS of the LTC3110 is held up by another supply. To prevent damage to the part in this condition, the LTC3110 has a reverse current comparator that monitors the current entering power switch D from the load. If this current exceeds 1.2A (typical), switch D is turned off for the remainder of the switching cycle. For a no-load current application, the inductor current ripple must be lower than double the minimum reverse current limit (1A * 2 = 2A maximum inductor current ripple). See the Inductor Selection section for information about how to calculate the inductor current ripple. VCAP Peak and DC-Current Limits (Backup Mode) The LTC3110 has two current limit circuits that are designed to limit the peak inductor current to ensure that the switch currents remain within the capabilities of the IC during output short-circuit or overload conditions. First current limit: In PWM mode the VCAP DC current limit operates by injecting a current into the feedback pin (FB). For this current limit feature being most effective, the Thevenin resistance (RBOT//RTOP) from FB to ground should exceed 100k. On a hard VSYS short, with Burst Mode operation or PWM mode selected, it is possible for the inductor current to increase substantially beyond the DC current limit threshold. In this case the peak current, second current limit, turns off the power switch until the start of the next switching cycle. Preventing VCAP Overcharge Failure Due to Reverse DC Current (Backup Mode) If during PWM backup operation (MODE = high and DIR = low), an external power supply or any second DC/ DC regulator wrongly drives VSYS higher than the programmed back-up voltage level, the LTC3110 will reverse its VSYS current and simultaneously create reverse current flow charging VCAP. If the wrong VSYS voltage level is kept for a longer period of time, FBVAP may exceed the overcharge threshold and the LTC3110 stops reverse charging. Charging through reverse DC current while VDIR is low is not indicated at pin CHRG, which remains high impedance. The overcharge condition is generally prevented in the application by setting the LTC3110 into charge operation, if VSYS is driven from an external source. If the external source is supervised from the DIR comparator, the CHRG output can drive the gate of a PMOS and isolate the external source in backup operation, see applications with PFET on pages 29, 30, 31. If VSYS is supervised from the DIR comparator, the external source must be capable to deliver more than the maximum reverse current limit of the LTC3110 in backup direction, see autonomous application on page 36. Only if the external supply is strong enough, charge operation can be initiated reliably. Rev C For more information www.analog.com 15 LTC3110 OPERATION FBVCAP Failure Condition RSEN Current Sense Resistor Tap External component failures, e. g., open or shorted resistors or leakage currents at pin FBVCAP, can cause VCAP to charge up to a higher, undefined voltage. If VCAP exceeds typically 5.95V, the LTC3110 suspends charging which protects the LTC3110 from substantially exceeding the absolute maximum ratings if FBVCAP is shorted to ground. RSEN connects to the junction of FET D and the integrated sense resistor. Note supercapacitors and batteries often have a lower maximum voltage rating than 5.95V. In these cases the general purpose comparator can be configured to detect the overvoltage at VCAP (see the figure General Purpose Comparator as redundant VCAP supervisor in the Application Information section). Soft-Start (Backup Mode) To minimize VCAP current transients on power-up, the LTC3110 incorporates an internal soft-start circuit. The soft-start is implemented by a linearly increasing ramp of the error amplifier reference voltage during the softstart duration. During the soft-start period the regulator is always operating in PWM operation independent of the MODE pin setting. In case the VSYS voltage at start-up is already pre-charged above 80% of the target value, the soft-start is skipped and the LTC3110 immediately enters the mode of operation that has been set with the MODE pin. The soft-start period is reset by thermal shutdown and from undervoltage lockout events. Error Amplifier and Internal Compensation of VSYS Backup Voltage Regulation The buck-boost converter utilizes a voltage mode error amplifier with an internal compensation network. Error Amplifier and Internal Compensation of VSYS Average Current Limit Regulation The buck-boost converter in charge mode (DIR = high) utilizes an error amplifier with an internal compensation network to regulate the average current flowing into the VSYS pin. The current limit is programmable with RPROG. 16 The RSEN pin can be left unconnected, otherwise a load current, IRSEN, will simultaneously decrease the average charge current flowing out of the VCAP pin. Note: A fast voltage step at VSYS in the presence of a large RSEN capacitor causes a large inrush current through the internal RSEN resistor, e. g., closure of a mechanical power connection supplying VSYS. In these cases, the value of the capacitor between RSEN and ground is limited to a maximum of 10F. VCAPOK End-Of-Charge Indicator and FBVCAP Comparator The LTC3110 includes an open-drain comparator output pin, VCAPOK, which is used to indicate the charging state of the energy storage element. The comparator input, FBVCAP, is typically connected with a resistor divider from VCAP to ground in order to program the final charge voltage. When FBVCAP exceeds the rising threshold, the comparator output, VCAPOK, is high impedance. When FBVCAP drops below the falling threshold, VCAPOK is pulled to ground. While RUN = high, CAPOK continues to pull down with reduced strength until both VCAP and VSYS are below the threshold of the internal pull-down transistor, maximum 1.4V. The comparator operates in both charge and backup mode and is unconditionally released if the LTC3110 is shut down with RUN = low. CHRG Operation Mode Indicator and DIR Comparator The LTC3110 includes an open-drain DIR comparator output pin, CHRG, which is typically used to indicate the operation mode of the chip: charge or backup. With the help of a pull-up resistor the output can be used to interface with a microcontroller, or connect to the gate of a p-channel MOSFET used as an input isolation switch (see USB application in the Typical Application section). The DIR comparator has hysteresis and the CHRG pin is pulled low while VDIR is greater than the comparator rising threshold and CHRG is released while VDIR is lower than its falling threshold. Rev C For more information www.analog.com LTC3110 OPERATION CMPIN CMPOUT LTC3110 is equipped with a thermal regulator. If the die temperature exceeds 130C (typical) the average VSYS current limit is lowered to help reduce the amount of power being dissipated in the package. The current limit is reduced to approximately 15% of the programmed limit just before thermal shutdown. The current limit will return to its full value when the die temperature drops below 130C, typically. LTC3110 VTH(CMP) + - EN 3110 F08 Figure 5. General Purpose Comparator The CHRG pin is unconditionally released if the LTC3110 is shut down with RUN = low or in undervoltage condition. Note that the DIR pin can be driven above VCAP or VSYS, as long as the voltage is limited to less than the absolute maximum rating. General Purpose Comparator The LTC3110 includes a voltage comparator with its input accessible at the CMPIN pin and with a fixed internal reference voltage. The comparator can be used to monitor VCAP, VSYS or any auxiliary supply voltage. The open-drain output, CMPOUT, can interface to a microcontroller with the help of a pullup resistor. The comparator is typically used to supervise VCAP and to set a threshold for the lowest VCAP voltage tolerated in backup mode before the system needs to reduce power consumption. The CMPOUT pin is unconditionally released if the LTC3110 is shut down with RUN = low or in undervoltage condition (see also the Applications Information section). Shutdown Shutdown of the LTC3110 is accomplished by pulling the RUN pin below 0.3V and IC operation is enabled by pulling the RUN pin above 1.0V. The RUN pin has an internal pulldown resistor. Note that RUN can be driven above VCAP or VSYS, as long as the voltage is limited to less than the absolute maximum rating. Thermal Foldback of Charge Current To help preventing the LTC3110 from going into thermal shutdown when charging very large capacitors, the Undervoltage Lockout If either voltages at VCAP and VSYS drop below the undervoltage lockout falling threshold, the LTC3110 will stop operation and the SW1, SW2, VMID, CMPOUT, CHRG and PROG pins will be high impedance. CAPOK will continue to pull down with reduced strength until both VCAP and VSYS are below the threshold of the internal pull-down transistor, maximum 1.4V. The LTC3110 will resume operation when at least one pin, VCAP or VSYS, rises above the undervoltage lockout rising threshold. THERMAL CONSIDERATIONS The power switches in the LTC3110 are designed to operate continuously with currents up to the internal current limit thresholds. However, when operating at high current levels there may be significant heat generated within the IC. As a result, careful consideration must be given to the thermal environment of the IC in order to optimize efficiency and ensure that the LTC3110 is able to provide its full-rated output current. Specifically, the exposed pad of both the QFN and TSSOP packages shall be soldered to the PC board and the PC board should be designed to maximize the conduction of heat out of the IC package. If the die temperature exceeds approximately 165C, the IC will enter overtemperature shutdown, all switching will be inhibited and the charge balancer disabled. Note: Open-drain output pins CAPOK, CMPOUT and CHRG may still pull down while in thermal shutdown. The part will remain disabled until the die cools by approximately 10C. The soft-start circuit is reinitialized in overtemperature shutdown to provide a smooth recovery when the fault condition is removed. Rev C For more information www.analog.com 17 LTC3110 APPLICATIONS INFORMATION The standard LTC3110 application circuit is shown as the Typical Application on the front page of this data sheet. The appropriate selection of external components is dependent upon the required performance of the IC in each particular application given considerations and trade-offs such as PCB area, cost, VSYS and VCAP voltage, allowable ripple voltage, efficiency and thermal considerations. This section of the data sheet provides some basic guidelines and considerations to aid in the selection of external components and the design of the application circuit. Inductor Selection The choice of inductor used in LTC3110 application circuits influences the maximum deliverable backup and charge current, the magnitude of the inductor current ripple, and the power conversion efficiency. The inductor must have low DC series resistance or current capability and efficiency will be compromised. Larger inductance values reduce inductor current ripple and will therefore generally yield greater backup current capability. For a fixed DC resistance, a larger value of inductance will yield higher efficiency by reducing the peak current to be closer to the average backup current and therefore minimize resistive losses due to high RMS currents. However, a larger inductor within any given inductor family will generally have a greater series resistance, thereby counteracting this efficiency advantage. An inductor used in LTC3110 applications should have a saturation current rating that is greater than the worst-case average inductor current plus half the ripple current. The peak-to-peak inductor current ripple for each operational mode can be calculated from the following formula: IL(P-P)(BUCK) = VSYS VCAP - VSYS 1.2MHz *L VCAP IL(P-P)(BOOST) = VCAP VSYS - VCAP 1.2MHz *L VSYS L is the inductance in H. In addition to its influence on power conversion efficiency, the inductor DC resistance can also impact the maximum output capability of the buck-boost converter particularly 18 at low VCAP voltages. In buck mode, the output current of the buck-boost converter is limited only by the inductor current reaching the current limit threshold. However, in boost mode, especially at large step-up ratios, the VSYS backup current capability can also be limited by the total resistive losses in the power stage. These include switch resistances, inductor resistance and PCB trace resistance. Use of an inductor with high DC resistance can degrade the VSYS backup current capability from that shown in the Typical Performance Characteristics section of this data sheet. As a guideline, in most applications the inductor DC resistance should be significantly smaller than the typical power switch resistance of 60m. The minimum inductor value must guarantee that the worst-case average VCAP current plus half the ripple current doesn't reach the VCAP current limit threshold. For the fixed switching frequency of 1.2MHz the recommended typical inductor value is 1.5H. Different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. Shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. The choice of inductor style depends upon the price, sizing, and EMI requirements of a particular application. Table 1 provides a small sampling of inductors that are well suited to many LTC3110 applications. Table 1. Recommended Inductors VENDOR Coilcraft www.coilcraft.com Wurth Elektronik www.we-online.com Coiltronics www. cooperindustries.com Vishay www.vishay.com Sumida www.sumida.com Murata www.murata.com Taiyo Yuden www.t-yuden.com TDK www.component.tdk.com PART/STYLE XAL50xx Series (XAL5030-222ME_) XAL60xx Series (XAL6030-222ME_) EPL7040 Series (EPL7040-222ME_) WE-HCI Series (744310150, 744314200) WE-LHMI Series (74437346018, 74437349022) DR73 Series (DR73-2R2-R) DRQ74 Series (DR74-2R2-R) IHLP-2525 Series (IHLP-2525AH-01, IHLP-2525CZ-01) IHLP-2020 Series (IHLP-2020CZ-A1) CDEP6D31ME Series (CDEP6D31MENP-2R2MC) LQH66S Series (LQH66SN1R5M03) NR6012T2R5NE NR8040T2R0N CLF Series Rev C For more information www.analog.com LTC3110 APPLICATIONS INFORMATION VSYS Capacitor Selection A low ESR capacitor should be utilized at the VSYS pin in order to minimize VSYS backup voltage ripple. Multilayer ceramic capacitors are an excellent option as they have low ESR and are available in small footprints. The capacitor value should be chosen large enough to reduce the VSYS voltage ripple to acceptable levels. Neglecting the capacitor ESR and ESL, the peak-to-peak VSYS voltage ripple can be calculated by the following formulas, where CVSYS is the VSYS capacitance and ILOAD is the VSYS load current. VP-P(BUCK) = VSYS 2 8 * (1.2MHz ) *L *C VSYS VP-P(BOOST) = VCAP - VSYS V CAP VSYS - VCAP ILOAD 1.2MHz *C VSYS VSYS Given the VSYS current is discontinuous in boost mode, the ripple in this mode will generally be much larger than the magnitude of the ripple in buck mode. In addition to VSYS voltage ripple generated across the VSYS capacitance, there is also VSYS voltage ripple produced across the internal resistance of the VSYS capacitor. The ESRgenerated VSYS voltage ripple is proportional to the series resistance of the VSYS capacitor. Supercapacitor Selection and Additional Bypass The LTC3110 is stable with a total CVCAP capacitance value greater than 2mF, or 4mF for each stacked capacitor. Supercapacitors are much larger physically than ceramic or tantalum capacitors, and therefore usually cannot be placed close to the charger. To minimize layout contribution to capacitor ESR, the trace width connecting the capacitors to each other and the IC should be as large as possible. The VMID pin trace is not as critical, as it only carries 300mA of average current. It is recommended that a local decoupling capacitor be placed from VCAP to ground, and the capacitor should be placed as close to the IC as possible. Multilayer ceramic capacitors are an excellent choice for voltage decoupling as they have extremely low ESR and are available in small footprints. While a 10F decoupling capacitor is sufficient for most applications, larger values may be used without limitation. To minimize voltage ripple and ensure proper operation of the IC, a low ESR bypass capacitor with a value of 100nF and a second low ESR bypass capacitor of 10F should be located as close to the VCAP pin as possible. The traces connecting this capacitor to VCAP and the ground plane should be made as short as possible. If using a single VSYS capacitor where balancing is not required, a capacitor of at least 1nF must be connected between VMID and PGND. Recommended VCAP and VSYS Bypass Capacitors The choice of capacitor technology is primarily dictated by a trade-off between cost, size and leakage current. Ceramic capacitors are often utilized in switching converter applications due to their small size, low ESR and low leakage currents. However, many ceramic capacitors designed for power applications experience significant loss in capacitance from their rated value with increased DC bias voltages. For example, it is not uncommon for a small surface mount ceramic capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. As a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a higher voltage rating than required in order to actually realize the intended capacitance at the full operating voltage. To ensure that the intended capacitance is realized in the application circuit, be sure to consult the capacitor vendor's curve of capacitance versus DC bias voltage. The capacitors listed in Table 3 provide a sampling of small surface mount ceramic capacitors that are well suited to LTC3110 application circuits. All listed capacitors are either X5R or X7R dielectric in order to ensure that capacitance loss over temperature is minimized. Maximum Capacitor Voltage and Balancing The service lifetime of a supercapacitor is determined by its rated voltage, rated temperature, rated lifetime, actual operating voltage, and operating temperature. To extend the life of a supercapacitor the operating voltage and temperature should be reduced from the maximum ratings. The websites for Illinois Capacitor1 and Maxwell2 provide the means to determine their capacitor lifetime. 1http://www.illinoiscapacitor.com/tech-center/life-calculators.aspx 2http://www.maxwell.com/products/ultracapacitors/docs/ APPLICATIONNOTE1012839_1.PDF Rev C For more information www.analog.com 19 LTC3110 APPLICATIONS INFORMATION Using the suggested derated voltage for each capacitor will improve lifetime. The LTC3110 will keep each capacitor voltage at VCAP/2 once VCAP is higher than typically 2.2V. To prevent an overvoltage on one of the supercapacitors during charging, the VMID voltage is continuously driven from the voltage balancing buffer output with typically 300mA of current capability. The LTC3110 has minimal current draw from VCAP at end of charge. Care should be taken to limit sources of current that may pull VCAP above its programmed regulation value, as there is no way for the LTC3110 to maintain regulation. VSYS Voltage Programming VCAP Voltage Programming The VCAP voltage is set via an external resistor divider connected to the FBVCAP pin as shown in Figure 7. The resistor divider values determine the maximum VCAP voltage according to the following formula: R VCAP = 1.095V * 1+ TOP RBOT Care should be taken to limit sources of current that may pull VCAP above its programmed maximum value, as there is no way for the LTC3110 to maintain VCAP regulation in charger mode (see also Figure 15, Overvoltage Error Signal Provided to the C). The VSYS voltage is set via an external resistor divider connected to the FB pin as shown in Figure 6. C1 The resistor divider values determine the VSYS backup voltage according to the following formula: R VSYS = 0.6V * 1+ TOP RBOT VSYS RBOT 3110 F10 Figure 7. VCAP Voltage Programming VMID Charge Balancer Output This pin should be tied to the junction of two series supercapacitors. A push/pull buffer output forces the VMID pin to half of the voltage of the VCAP pin. Generally capacitors with equal value of at least 1nF should be connected from VCAP to VMID and from VMID to PGND if the output is unused, e.g., for applications with a single supercapacitor or batteries. 1F C1 VCAP LTC3110 VMID C2 3110 F11 Figure 8. VMID Charge Balancer Output RTOP LTC3110 LTC3110 FBVCAP SGND C2 (1) The buck-boost converter utilizes voltage mode control and in addition to setting the VSYS voltage, the value of RTOP plays an integral role in the dynamics of the feedback loop. In general, a larger value for RTOP will increase stability and reduce the speed of the transient response. A smaller value of RTOP will reduce stability but increase the speed of the transient response. A good starting point is to choose RTOP = 1M and then calculate the required value of RBOT to set the desired VSYS voltage according to Equation 1. If a large VSYS capacitor is used, the bandwidth of the converter is reduced. In such cases RTOP can be reduced to improve the transient response. If a large inductor or small VSYS capacitor is utilized the loop will be less stable and the phase margin can be improved by increasing the value of RTOP. VCAP 1F RTOP FB SGND RBOT 3110 F09 Figure 6. Setting the VSYS Backup Voltage 20 For more information www.analog.com Rev C LTC3110 APPLICATIONS INFORMATION SINGLE CAPACITOR OR BATTERY 1F R TOP VTH(DIR _RISING) = 1.095V * 1+ RBOT +RMID VCAP 1nF LTC3110 VMID 1nF 3110 F12 Figure 9. Charge Balancer Unused with Single Capacitor DIR Backup Supervisor Threshold Voltage Programming The backup supervisor threshold voltage is set via an external resistor divider connected to the DIR pin as shown in Figure 10. The resistor divider values determine the DIR supervisor threshold voltage according to the following formula: R VTH(DIR _RISING) = 1.095V * 1+ TOP RBOT R VTH(DIR _FALLING) = 1.045V * 1+ TOP RBOT R TOP VTH(DIR _FALLING) = 1.045V * 1+ RBOT +RMID R +R VSYS = 0.6V * 1+ TOP MID RBOT Note the direction supervisor threshold VTH(DIR_RISING) must be higher and have enough voltage difference to the backup voltage VSYS to accommodate for the resistor tolerances, ripple voltage and voltage dipping from load current steps. If necessary an RC filter in front of the DIR pin may reduce the reaction speed of the supervisor, see Figure 12. Pay attention to the requirement, if the DIR input supervises VSYS as in Figure 11 or in the autonomous applications on page 36, the external VSYS supply must be capable to deliver more than the maximum reverse current limit of 2A of the LTC3110, in order to reliably change into charge operation. BACKUP VOLTAGE SUPERVISED VOLTAGE LTC3110 RTOP VSYS DIR SGND RTOP DIR RMID LTC3110 RBOT FB PGND 3110 F13 SGND RBOT 3110 F14 Figure 10. Setting the DIR Back-Up Supervisor Threshold Voltage Figure 11. Voltage with Reduced Tolerances Programming Backup Voltage and DIR Threshold Voltage with Improved Accuracy In applications with the DIR pin voltage and the FB pin voltage divided down from the same VSYS voltage, a single resistor divider string is reducing the effect of resistor tolerances and saves one resistor component: SUPERVISED VOLTAGE RTOP DIR LTC3110 PGND CDIR SGND RBOT 3110 F15 Figure 12. Filtering DIR voltage Rev C For more information www.analog.com 21 LTC3110 APPLICATIONS INFORMATION IVSYS Average Current Limit Programming for Charger Operation (DIR = High) The VSYS average current limit is set via an external resistor connected between the PROG pin and signal ground, SGND, as shown in Figure 13. The resistor value determines the average current into VSYS according to the following formula: IVSYS = 3k RPROG For applications with a wide temperature range, the thermal coefficient of resistor RPROG must be taken into account. If RPROG is > 12.4k, additional RFLT and CFLT are required for filtering. If CMPIN is driven from a resistor divider or from any output with >200 impedance, connect a 0.1F capacitor between CMPIN and GND for best performance, see Figure 14. General Purpose Comparator Configuration as Redundant VCAP Supervisor for Overvoltage Failure Detection Component failures interrupting the VCAP voltage feedback (FBVCAP) can potentially cause an over voltage condition at VCAP during charging. The general purpose comparator can be configured as the supervisor providing an overvoltage error signal to the microcontroller (see Figure 15). C1 RTOP C2 CCMPIN 0.1F RBOT PROG LTC3110 RPROG LTC3110 CMPIN CMPOUT 10k C ERR RUN CFLT 10nF (OPT) 3110 F18 RFLT 6.04k (OPT) SGND VDD VCAP Figure 15. Overvoltage Error Signal Provided to the C 3110 F16 Figure 13. Setting the VSYS Average Current Limit CMPIN Configuration as General Purpose Voltage Supervisor with Hysteresis The resistor divider values, see Figure 14, determine rising and falling threshold VTH according to the following formula: SVSYS Filtering In many noise critical applications it is useful to filter the signal supply pin, SVSYS, with a small RC filter on the PCB, see Figure 16. Note, if the filter is added any further loads connected to the SVSYS pin must be checked if they are small with respect to the resistor impedance and not creating undesired voltage drops at SVSYS. R VTH(RISING) = 0.65V * 1+ TOP R CSYS BOT VSYS R VTH(FALLING) = 0.59V * 1+ TOP RBOT OUT 3110 F19 CCMPIN 0.1F CMPIN Figure 16. SVSYS Filtering LTC3110 RUN, DIR, MODE, CMPIN Inputs Digitally Controlled CMPOUT 3110 F17 Figure 14. General Purpose Voltage Supervisor 22 CSVSYS 220nF SGND RTOP RBOT SVSYS LTC3110 VTH VDD RSVSYS 51.1 The RUN, DIR, MODE and CMPIN comparator inputs can be driven digitally from an external microcontroller. Rev C For more information www.analog.com LTC3110 APPLICATIONS INFORMATION VDD RUN DIR LTC3110 MODE CHRG LTC3110 CAPOK C C CMPOUT CMPIN SGND SGND 3110 F21 3110 F20 Figure 17. Inputs RUN, DIR, MODE, CMPIN Driven from a Microcontroller Open-Collector Outputs CHRG, CAPOK and CMPOUT open-collector outputs can be connected together with other external signals in wired OR configuration and pull-up resistors for level shifting when interfacing into C Inputs. Figure 18. Outputs CHRG, CAPOK, CMPOUT Interfacing to C The open-collector outputs can also be used to drive small loads up to 20mA, e.g., miniature lamps or LEDs. Table 2. Recommended Supercapacitors and Ultracapacitors VALUE (F) ESR (m) VOLTAGE (V) TEMPERATURE RANGE (C) Murata Electronics DMF3R5R5L334M3DTA0 DMF3Z5R5H474M3DTA0 0.33 0.47 60 40 4.2 (5.5 Peak) 4.2 (5.5 Peak) -30 to 70 -30 to 70 14.0 x 21.0 x 2.5 14.0 x 21.0 x 3.2 Tecate TPL-10/10X30F TPL-25/16X26F TPL-100/22X45F TPLE-25/16X26F TPLE-100/22X45F TPLS-400/35X60F 10 25 100 25 100 400 85 42 15 42 15 12 2.7 2.7 2.7 2.3 2.3 2.7 -40 to 65 -40 to 65 -40 to 65 -40 to 85 -40 to 85 -40 to 65 10.0 x 10.0 x 30.0 16.0 x 16.0 x 26.0 22.0 x 22.0 x 45.0 16.0 x 16.0 x 26.0 22.0 x 22.0 x 45.0 35.0 x 35.0 x 60.0 AVX BZ015A503Z_B BZ015A104Z_B 0.05 0.1 160 80 5.5 5.5 -20 to 70 -20 to 70 28.0 x 17.0 x 4.1 28.0 x 17.0 x 6.7 CAP-XX HS206F HS230 0.6 1.2 70 50 5.5 5.5 -40 to 85 -40 to 85 39.0 x 17.0 x 2.5 39.0 x 17.0 x 3.8 Cooper Bussmann A1635-2R5475-R M1325-2R5905-R HB1625-2R5256-R HV1860-2R7107-R 4.7 9 25 100 25 20 36 10 2.5 2.5 2.5 2.7 -25 to 70 -40 to 60 -25 to 70 -40 to 65 16.0 x 16.0 x 35.0 13.0 x 13.0 x 26.0 16.0 x 16.0 x 25.0 18.0 x 18.0 x 60.0 Illinois Capacitor 506DER2R5SLZ 357DER2R5SEZ 50 100 30 12 2.5 2.5 -40 to 70 -40 to 70 18.0 x 18.0 x 60.0 35.0 x 35.0 x 60.0 Maxwell BCAP0005 BCAP0100T01 5 100 170 15 2.7 2.7 -40 to 65 -40 to 65 10.0 x 10.0 x 20.0 22.0 x 22.0 x 45.0 Taiyo Yuden PAS2026FR2R5504 PAS0815LS2R5105 LIC2540R3R8207 0.5 1 200 55 70 50 2.5 2.5 2.2 to 3.8 -25 to 60 -25 to 70 -25 to 70 26.0 x 20.0 x 0.9 8.0 x 8.0 x 15.0 25.0 x 25.0 x 40.0 VENDOR SIZE (mm) W x L x H Rev C For more information www.analog.com 23 LTC3110 APPLICATIONS INFORMATION PCB Layout Considerations Table 3. Representative Bypass and VSYS Capacitors PART NUMBER VALUE (F) VOLTAGE (V) FOOTPRINT AVX 12066D106K 12066D226K 12066D476K 10 22 47 6.3 6.3 6.3 0603 0805 0805 Kemet C0603C106M9PACTU C0805C226M9PACTU C0805C476M9PACTU 10 22 47 6.3 6.3 6.3 0603 0805 0805 Murata GRM188D70J106MA73 GRM219B30J226ME47 GRM21BB30J476ME15 10 22 47 6.3 6.3 6.3 0603 0805 0805 TDK C1608X7S0J106M080AC C2012X5R0J226M085AB C2012X5R0J476M125AC 10 22 47 6.3 6.3 6.3 0603 0805 0805 Taiyo Yuden JMK107BJ106MA JMK212ABJ226MD JMK212BBJ476MG 10 22 47 6.3 6.3 6.3 0603 0805 0805 The LTC3110 switches large currents at high frequencies. Special care should be given to the PCB layout to ensure stable, noise-free operation. Figures 19 and 20 depict the recommended PCB layout to be utilized for the LTC3110, if a 2-layer PCB is being used. A 4-layer PCB layout is recommended for thermal and noise reasons. A few key guidelines follow: 1. All circulating high current paths should be kept as short as possible. This can be accomplished keeping the routes to the components in Figures 19 and 20 as short and as wide as possible. Capacitor ground connections should be connect by vias down to the ground plane in the shortest route possible. The bypass capacitors CSYS and CCAP should be placed as close to the IC as possible and should have the shortest possible path to ground. 2. The components shown and their connections should all be placed over a complete ground plane. 3. Use of vias in the die attach pad will enhance the thermal environment of the charger, especially if the vias extend to a ground plane region on the exposed bottom surface of the PCB. 4. Keep the connections to the FB, PROG, DIR, CMPIN and FBVCAP pins as short as possible and away from the switch pin connections. 24 Rev C For more information www.analog.com LTC3110 APPLICATIONS INFORMATION BOTTOM COPPER LAYER C2 TOP LAYER CCAP C1 1 24 2 23 3 22 4 21 LTC3110 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CSYS L1 COMPONENT NAMES: SEE TYPICAL APPLICATION ON PAGE 27 VIA TO GROUND PLANE 3110 F22 Figure 19. PCB Component Placement of the TSSOP Package Rev C For more information www.analog.com 25 LTC3110 APPLICATIONS INFORMATION BOTTOM COPPER LAYER COMPONENT NAMES: SEE TYPICAL APPLICATION ON PAGE 27 C2 TOP LAYER CCAP 1 19 20 21 22 23 24 C1 18 LTC3110 14 6 13 L1 12 5 11 15 10 16 4 7 3 7 17 7 2 CSYS VIA TO GROUND PLANE 3110 F23 Figure 20. PCB Component Placement of the QFN Package 26 Rev C For more information www.analog.com LTC3110 TYPICAL APPLICATIONS 3.3V/2A Output from Stack of Supercapacitors Backup/Recharge Application with Active Voltage Balancing MAIN STEP-DOWN DC/DC FB 12V BUS CSVSYS 220nF L1 1.5H C1 10F R1 1910k C2 10F R3 1910k CCAP 1F SW2 SVSYS FBVCAP R2 523k VSYS CMPIN VMID VSYS 3.25V 2A CSYS 47F RSEN PROG CCMPIN 0.1F R4 523k VCAP SW1 RSVSYS 51.1 12V BUS SUPERVISOR R5 976k LTC3110 MODE RPROG 6.04k FB R6 221k 1000k DIR DIR CHRG CAPOK CMPOUT RUN SGND 1000k C CAPOK CAPLOW AT VCAP = 2.8V PGND 3110 TA02 1.8V/300mA Output from Single Capacitor Discharged from 2.5V to 1V and with Reserve Available Down to 0.3V MAIN STEP-DOWN DC/DC FB 12V BUS VSYS = 1.9V CHARGING CSVSYS 220nF L1 1.5H C1 10F R1 2000k R3 1300k R4 1870k CCAP 1F VCAP SW1 SW2 SVSYS FBVCAP R2 1580k VSYS RSEN PROG CCMPIN 0.1F CMPIN CMID1 1nF CMID2 1nF VMID VSYS 1.83V BACKUP 300mA CSYS 47F LTC3110 MODE SGND 12V BUS SUPERVISOR R5 976k FB DIR CHRG CAPOK CMPOUT RUN RPROG 6.04k PGND R6 475k 1000k 1000k DIR C CAPOK CAPLOW 3110 TA03 Rev C For more information www.analog.com 27 LTC3110 TYPICAL APPLICATIONS 500mA USB Charge/Backup Application with Variable Charging Power, PCHRG, Depending on System Load USB PUSB UP TO 5V * 500mA M1 IRLML6402 R7 7.50k R8 2.49k 5V CSVSYS 220nF ROFF 3.3k L1 1.5H PCHRG = PUSB - PSYS C1 10F R1 1910k C2 10F R3 1910k CCAP 1F R4 1270k SW2 SVSYS VCAP SW1 FBVCAP R2 511k RSVSYS 51.1 VSYS CSYS 330F RSEN PROG FB VMID RPROG 6.04k R5 976k R6 133k DIR CHRG CAPOK CMPOUT RUN SGND CFB 10pF 1000k C USB DATA END OF CHRG CAPLOW 3110 TA04 PGND USB Connect Transition USB Disconnect Transition CHARGING CHARGING BACKUP 1V/DIV VSYS CHRG 5V/DIV CHRG 5V/DIV VSYS DISCONNECT VUSB VUSB ILI 2A/DIV ILI 2A/DIV 100s/DIV 28 1000k CDIR 1nF MODE BACKUP 1.2V, 1A CMPIN CCMPIN 0.1F LTC3110 1V/DIV PSYS 5V, 0.1A 2.5V, 0.1A 1.8V, 0.2A SYSTEM DC/DC REGULATORS 3110 TA04b 100s/DIV 3110 TA04c Rev C For more information www.analog.com LTC3110 TYPICAL APPLICATIONS Autonomous Backup and Recharge Application with Input Isolation Switch CSVSYS 220nF L1 2.2H C1 100F R1 1910k C2 100F R3 1910k R4 681k CCAP 1F VCAP SW1 SW2 SVSYS FBVCAP R2 536k RSVSYS 51.1 BACK-UP 3.2V VSYS CMPIN FB VMID LTC3110 DIR MODE SGND CMAIN 47F 12V BUS FB MAIN STEP-DOWN DC/DC 1.5A RPROG 3.01k R5 931k R6 215k 3.6V/3.21V 2.5V 1.8V SYSTEM DC/DC REGULATORS 1.2V R7 9.31k R8 4.53k 1000k 1000k 3110 TA08 CHRG CAPOK CAPLOW PGND CHARGE SLEEP 0V IL 1A/DIV 0A CHRGB 2V/DIV 0V ROFF 3.3k CHRG CAPOK CMPOUT RUN 1V/DIV CSYS 150F RSEN PROG CCMPIN 0.1F M1 IRLML6402 VMAIN CHARGING 3.6V 4% BACKUP VSYS VMAIN 500s/DIV 3110 TA06b Rev C For more information www.analog.com 29 LTC3110 TYPICAL APPLICATIONS Lead Acid Battery Backup/Recharge Application 12V 3.3V LDO OR BUCK REGULATOR M1 IRLML6402 3.6V 47F R7 9.31k R8 4.53k 3.21V/ 3.6V L1 1.5H ROFF 10k + BATT 4V 2.5Ah R1 976k R3 1910k R4 604k CMID1 1nF CMID2 1nF CCAP 1F SW2 SVSYS VCAP SW1 FBVCAP R2 316k VSYS 1.2V RSEN PROG CCMPIN 0.1F CSYS 150F 2.5V 1.8V SYSTEM DC/DC REGULATORS RPROG 6.04k CMPIN LTC3110 FB VMID R5 976k R6 226k 1000k 1000k DIR MODE CHRG CAPOK CMPOUT RUN SGND END OF CHRG BATTLOW PGND 3110 TA05 30 Rev C For more information www.analog.com LTC3110 TYPICAL APPLICATIONS NiMH Battery Backup/Recharge Application CSVSYS 220nF L1 1.5H NiMH 1.2V 3700mAh x3 + CCAP 1F VCAP SW1 SW2 SVSYS FBVCAP VSYS PROG CCMPIN 0.1F CMPIN CMID1 1nF CMID2 1nF VMID VSYS 3.25V 2A CSYS 47F RSEN R3 1910k R4 604k RSVSYS 51.1 LTC3110 MODE RPROG 12.4k RFAST 8.06k FB R6 221k DIR CHRG CAPOK CMPOUT RUN SGND VSYS SUPERVISOR R5 976k PGND 1000k DIR VCC BATTLOW FASTCHRG C RUN FBVCAP ADIN RTEMP 3110 TA06 NOTE ON DIGITAL CONTROL SIGNALS IN NiMH BACKUP/RECHARGE APPLICATION: CHARGING IS INITIATED BY PULLING DIR = HIGH AND FBVCAP = LOW. CHARGING IS TERMINATED BY PULLING DIR = HIGH AND FBVCAP = HIGH (FBVCAP MUST BE 1.2V). SYSTEM BACK-UP IS INITIATED BY FORCING FBVCAP = LOW, WAITING 5s, THEN FORCING DIR = LOW. GENERAL SAFETY NOTE: CHARGING MUST BE TERMINATED IF THE BATTERY VOLTAGE OR CHARGE TIME HAVE REACHED THEIR MAXIMUM VALUES OR IF THE BATTERY TEMPERATURE IS ABOVE OR BELOW THE SAVE OPERATING REGION OF THE BATTERY, SEE DATA SHEET OF THE BATTERY. THE THERMISTOR, USED FOR MEASURING THE TEMPERATURE, MUST HAVE GOOD THERMAL CONNECTION TO THE BATTERY PACK. Rev C For more information www.analog.com 31 LTC3110 TYPICAL APPLICATIONS R11 348 ISOLAR + D1 SOLAR CELL - 24h/7d Active Solar Powered Sensor/Transmitter Supply Q1 PBSS302 VSOLAR PRIMARY BATTERY LITH 3V, 1Ah OPTIONAL D1 SCHOTTKY OPTIONAL C1 100F MODULE 6V, 150mA ~12 CELLS CSVSYS 220nF L1 2.2H R1 1910k C2 100F CCAP 47F FBVCAP R2 511k SUPERCAPS SW2 SVSYS VCAP SW1 VSYS PROG CCMPIN 0.1F LTC3110 FB S1 S2 PFO GND RUN RST SGND PGND DAY 1 DAY 2 DAY 3 DAY 4 ISOLAR 20mA/DIV VCAP 2V/DIV VSYS 2V/DIV MODE = LOW ISYS = 0.5mA 8h/DIV CHRG CAPOK CMPOUT M2 2N7002 32 VSOLAR 5V/DIV 0V ISOLAR 100mA/DIV 0A VSYS AC COUPLED 100mV/DIV IVCAP 1A/DIV 0A 3110 TA09b R9 1000k 3110 TA09 Charging States PRE CHARGING CHARGING VCAP = 4V 5ms/DIV CHARGING WITH SOLAR CURRENT AND 24/7 BACKUP: IF DAYLIGHT IS PRESENT, THE SUPERCAPACITORS ARE CHARGED UP WITH THE OUTPUT CURRENT OF THE SOLAR CELLS. WHEN DAYLIGHT IS NOT PRESENT, THE SUPERCAPS PARTIALLY DISCHARGE AND PROVIDE THE BACKUP POWER TO MAINTAIN VSYS. HIGH BACKUP POWER MODE (NO WAVEFORM): IF MODE = HIGH AND WITH THE SUPERCAPACITORS CHARGED, THE APPLICATION CAN PROVIDE THE VSYS BACKUP VOLTAGE WITH LOW RIPPLE AND FULL OUTPUT CURRENT CAPABILITIES. MODE = HIGH STOPS FURTHER CHARGING. CHARGING STATES: IF MODE = LOW: THE VSYS VOLTAGE IS FED WITH CURRENT FROM THE SOLAR MODULE OR IS REGULATED FROM THE LTC3110 IN BURST MODE IF SUNLIGHT IS MISSING. IF SUNLIGHT IS PRESENT, VSYS IS REGULATED WITH A TWO POINT VOLTAGE REGULATION DEFINED BY DIR RISING AND DIR FALLING THRESHOLDS. THE APPLICATION HAS THREE STATES OF OPERATION: 1. CSYS PRE-CHARGING STATE: THE SOLAR PANEL OUTPUT CURRENT PRE-CHARGES THE CAPACITOR CSYS UNTIL THE DIR VOLTAGE RISES ABOVE THE DIR RISING THRESHOLD AND THE SUPERCAPACITOR CHARGING STATE IS ENTERED. 2. SUPERCAPACITOR CHARGING STATE: THE LTC3110 CHARGES THE SUPERCAPACITORS BY DRAWING CURRENT FROM CAPACITOR CSYS UNTIL THE VSYS VOLTAGE FALLS BELOW THE DIR FALLING THRESHOLD AND THE VSYS PRE-CHARGING STATE IS RE-ENTERED. THE LTC3110 TOGGLES BETWEEN THE PRE-CHARGING STATE AND THE CHARGING STATE UNTIL FBVCAP IS ABOVE THE FBVCAP RISING THRESHOLD AND THE CHARGE SLEEP STATE IS ENTERED. SENSOR R8 422k M1 2N7002 Charging with Solar Current and 24/7 Backup DISPLAY R10 1000k R7 953k MODE LTC2935-2 TRANSMITTER GSM R6 221k DIR VCC 2A PULSE HIGH BACKUP END OF POWER CHARGE CAPLOW MODE R5 976k CMPIN CSYS3 4700F <30m MICRO CONTROLLER RPROG 3.01k VMID S0 CSYS2 4700F <30m CSYS1 47F RSEN R3 1910k R4 523k 3.25V LOW RIPPLE HIGH BACKUP POWER MODE, MODE = HIGH 3.42V/3.58V SOLAR CHARGING, MODE = LOW ISYS VSYS = RSVSYS 51.1 3110 TA09C 3. CHARGE SLEEP STATE (NO WAVEFORM): VCAP IS FULLY CHARGED AND FBVCAP IS ABOVE THE FBVCAP FALLING THRESHOLD WHILE THE VSYS VOLTAGE IS REGULATED WITH LTC3110's BURST MODE BACKUP OPERATION. IN THE CHARGE SLEEP STATE, THE SOLAR MODULE IS ISOLATED FROM VSYS. STARTUP WITH DISCHARGED SUPERCAPS: THE VSYS VOLTAGE IS MONITORED WITH THE LTC2935-2 SUPERVISOR ENABLING THE LTC3110 ONLY AT A VOLTAGE ABOVE 2.7V. IF POWERED FROM HIGH IMPEDANCE SOURCES (E. G. SOLAR CELLS). VSYS MUST BE INITIALLY HIGH ENOUGH TO SKIP THE SOFT START FUNCTION OF THE LTC3110, SEE SOFT START (BACKUP MODE) IN THE OPERATION SECTION. NOTES: THE REQUIRED PANEL SIZE AND THE NUMBER OF SOLAR CELLS IN SERIES OR IN PARALLEL STRONGLY DEPENDS ON THE LOCAL SUNLIGHT CONDITIONS. VSOLAR MUST BE ONE VBE HIGHER THAN VSYS (3.58V + 0.7V = 4.3V) IN THE LOWEST LIGHT CONDITION TO DELIVER SOLAR CURRENT. TO PREVENT OVERVOLTAGING OF VSYS, THE IVSYS AVERAGE CURRENT LIMIT MUST BE AT LEAST FOUR TIMES LARGER THAN THE MAXIMUM SOLAR CURRENT (IVSYS_PROG > 4 x ISOLAR_MAX). ALTERNATIVELY, OUTPUT CHRG CAN BE ADDITIONALLY CONNECTED TO THE BASE OF Q1 TO ISOLATE THE SOLAR PANEL DURING CHARGING. THE ABSOLUTE MAXIMUM OF VSOLAR IS DEFINED FROM THE VCEO VALUE OF Q1 (E.G. 20V) WHICH ALLOWS THE CONNECTION OF MODULES WITH OPEN CIRCUIT VOLTAGES OF VOC > 5.25V. OPTIONALLY A PRIMARY BATTERY CAN BE ADDED AS RESERVE TO COVER POOR LIGHT CONDITIONS. EXAMPLE SOLAR MODULE MANUFACTURERS: SHARP, PANASONIC, POWERFILM Rev C For more information www.analog.com LTC3110 PACKAGE DESCRIPTION FE Package 24-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1771 Rev B) Exposed Pad Variation AA 7.70 - 7.90* (.303 - .311) 3.25 (.128) 3.25 (.128) 24 23 22 21 20 19 18 17 16 15 14 13 6.60 0.10 2.74 (.108) 4.50 0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 0.05 1.05 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.25 REF 0 - 8 0.65 (.0256) BSC 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE24 (AA) TSSOP REV B 0910 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE Rev C For more information www.analog.com 33 LTC3110 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm x 4mm) (Reference LTC DWG # 05-08-1697 Rev B) 0.70 0.05 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (4 SIDES) BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 0.75 0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER 23 24 PIN 1 TOP MARK (NOTE 6) 0.40 0.10 1 2 2.45 0.10 (4-SIDES) (UF24) QFN 0105 REV B 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 34 Rev C For more information www.analog.com LTC3110 REVISION HISTORY REV DATE DESCRIPTION A 03/16 Add H-grade option. Clarified conditions and Note 9 for Input Current Limit. PAGE NUMBER 2, 4 4 Changed axis labels VMID Buffer Current, Backup Time, Charge Balancer curves. 8, 9 Enhanced 1.8V/300mA output circuit. 27 B 11/16 Changed reference page number in Preventing VCAP Overcharge Failure section 15 C 8/18 Changed capacitor value 19 Rev C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 35 LTC3110 TYPICAL APPLICATION Autonomous Backup and Recharge Application (3.6V Nominal, 3.2V Backup Voltage) 12V BUS FB MAIN STEP-DOWN DC/DC 2A + ISYS = MINIMUM REQUIREMENT CSVSYS 220nF L1 2.2H C1 10F R1 1910k C2 10F R3 1910k R4 715k CCAP 1F SW2 SVSYS VCAP SW1 FBVCAP R2 681k 3.6V 4%, 2A NOMINAL FROM MAIN DC/DC 3.21V, 1.5A BACKUP RSVSYS 51.1 CMPIN VMID LTC3110 MODE RPROG 6.04k R5 1020k 2.5V 1.8V SYSTEM DC/DC REGULATORS 1.2V R6 200k FB R7 280k 1000k 1000k 1000k DIR CHRG CAPOK CMPOUT RUN NOTE: THE DRIVING CAPABILITY OF THE MAIN DC/DC SHOULD EXCEED THE MAXIMUM REVERSE CURRENT LIMIT OF THE LTC3110 PLUS ISYS,THE LOAD CURRENT DEMANDED FROM THE SYSTEM DC/DC REGULATORS CONNECTED AT VSYS. 3.6V/3.21V RSEN PROG CCMPIN 0.1F CSYS 47F VSYS CHRG CAPOK CAPLOW 3110 TA07 SGND PGND RELATED PARTS PART NUMBER LTC4040 DESCRIPTION 2.5A Battery Backup Power Manager LTC3226 2-Cell Supercapacitor Charger with Backup PowerPathTM Controller LTC3625/LTC3625-1 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing LTC3128 LTC3350 3A Monolithic Buck-Boost Supercapacitor Charger and Balancer with Accurate Input Current Limit High Current Supercapacitor Backup Controller and System Monitor COMMENTS Step-Up Backup Supply and Step-Down Battery Charger, 6.5A Switches for 2.5A, Automatic Seamless Switchover to Backup Mode Backup from 3.2V Battery 1x/2x Multimode Charge Pump Supercapacitor Charger with Automatic Cell Balancing. Internal 2A LDO Backup Supply (CPO to VOUT). Automatic Main/Backup Switchover, 3mm x 3mm QFN-16 Package High Efficiency Step-Up/Step-Down Charging of Two Series Supercapacitors, Automatic Cell Balancing. Programmable Charging Current Up to 500mA (Single Inductor), 1A (Dual Inductor), 3mm x 4mm DFN-12 Package 2% Accurate Average Input Current Limit Programmable to 3A, Active Charge Balancing, Charges 1 or 2 Capacitors, VIN: 1.73V to 5.5V, VOUT: 1.8V to 5.5V Synchronous Step-Down CC/CV Charging up to Four Series Supercapacitors VIN: 4.5V to 35V, 14-Bit ADC for Monitoring System Voltages/Currents, Capacitance and ESR, Internal Active Balancers, 38-Lead 5mm x 7mm QFN Package LTC4425 Linear SuperCap Charger with CurrentConstant-Current/Constant-Voltage Linear Charger for 2-cell Series Supercapacitor Limited Ideal Diode and V/I Monitor Stack, 2A Charge Current, Auto Cell Balancing, 20A Quiescent Current LTC3127 1A Buck-Boost DC/DC Converter with Programmable (0.2A to 1A) 4% Accurate Average Input Current Limit, Programmable Input Current Limit 1.8V to 5.5V (Input) and 1.8V to 5.25V (Output) Voltage Range LTC3125 1.2A IOUT, 1.6MHz, Synchronous Boost DC/DC 94% Efficiency, VIN: 1.8V to 5.5V, VOUT(MAX) = 5.25V, IQ = 15A, Converter With Adjustable Input Current Limit ISD < 1A, 2mm x 3mm DFN-8 Package 95% Efficiency, VIN: 2.4V to 5.5V, VOUT : 2.4V to 5.25V, IQ = 50A, LTC3441/LTC3441-2/ 1.2A IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter ISD < 1A, 3mm x 4mm DFN-12 Package LTC3441-3 LTC3113 3A Low Noise Buck-Boost DC/DC Converter 96% Efficiency, VIN: 1.8V to 5.5V, VOUT : 1.8V to 5.5V, IQ = 40A, ISD < 1A, 4mm x 5mm DFN-16 and 20-Lead TSSOP Packages LTC3355 20V 1A Buck DC/DC with Integrated SCAP VIN Voltage Range: 3V to 20V, VOUT Voltage Range: 2.7V to 5V, 1A Current Mode Buck Main Regulator, 5A Boost Backup Regulator Powered from Single Charger and Backup Regulator Supercapacitor Down to 0.5V, Overvoltage Protection LTC3643 2A Bidirectional Power Backup Supply Bidirectional Synchronous Boost Capacitor Charger/Buck Regulator for System Backup, Wide VIN Voltage Range: 3V to 17V, Up to 40V Capacitor Voltage, 2A Maximum CAP Charge Current, Low Profile 24-Lead 3mm x 5mm QFN Package 36 Rev C D17165-0-7/18(C) www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2015-2018