6−104
Description
The HCPL-260L/060L/263L/063L
are optically coupled gates that
combine a GaAsP light emitting
diode and an integrated high gain
photo detector. An enable input
allows the detector to be strobed.
The output of the detector IC is an
open collector Schottky-clamped
transistor. The internal shield
provides a guaranteed common
mode transient immunity
specification of 15 kV/ µs.
Agilent HCPL-260L/ 060L/263L/063L
High Speed LVTTL Compatible
3.3 Volt Optocouplers
Data Sheet
Features
• Low power consumption
• 15 kV/µs minimum Common Mode
Rejection (CMR) at V
CM
= 50 V
• High speed: 15 MBd typical
• LVTTL/LVCMOS compatible
• Low input current capability:
5 mA
• Guaranteed AC and DC performance
over temperature: –40˚C to +85˚C
• Available in 8-pin DIP, SOIC-8
• Strobable output (single channel
products only)
• Safety approvals; UL, CSA, VDE
(pending)
Applications
• Isolated line receiver
• Computer-peripheral interfaces
• Microprocessor system interfaces
• Digital isolation for A/D, D/A
conversion
• Switching power supply
• Instrument input/output isolation
• Ground loop elimination
• Pulse transformer replacement
• Field buses
Functional Diagram
This unique design provides
maximum AC and DC circuit
isolation while achieving
LVTTL/LVCMOS compatibility.
The optocoupler AC and DC
operational parameters are
guaranteed from –40˚C to +85˚C
allowing trouble-free system
performance.
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.
1
2
3
4
8
7
6
5
CATHODE
ANODE
GND
V
V
CC
O
1
2
3
4
8
7
6
5
ANODE
2
CATHODE
2
CATHODE
1
ANODE
1
GND
V
V
CC
O2
V
E
V
O1
HCPL-260L/060L HCPL-263L/063L
NC
NC
LED
ON
OFF
ON
OFF
ON
OFF
ENABLE
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
TRUTH TABLE
(POSITIVE LOGIC)
SHIELD SHIELD
6−104
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These optocouplers are suitable
for high speed logic interfacing,
input/output buffering, as line
receivers in environments that
conventional line receivers
cannot tolerate and are
recommended for use in
extremely high ground or induced
noise environments.
These optocouplers are available
in an 8-pin DIP and industry
standard SO-8 package. The part
numbers are as follows:
8-pin DIP SO-8 Package
HCPL-260L HCPL-060L
HCPL-263L HCPL-063L
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-260L #XXX
060 = VDE 0884 VIORM = 630 Vpeak Option
500 = Tape and Reel Packaging Option
Option data sheets available. Contact Agilent sales representative or
authorized distributor for information.
Schematic
SHIELD
8
6
5
2+
3
V
F
USE OF A 0.1 F BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
–
I
F
I
CC
V
CC
V
O
GND
I
O
V
E
I
E
7
HCPL-260L/060L
SHIELD
8
7
+
2
V
F1
–
I
F1
I
CC
V
CC
V
O1
I
O1
1
SHIELD
6
5
–
4
V
F2
+
I
F2
V
O2
GND
I
O2
3
HCPL-263L/063L
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Package Outline Drawings
8-Pin DIP Package
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5° TYP. 0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
OPTION CODE*
UL
RECOGNITION
UR
TYPE NUMBER
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
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Small Outline SO-8 Package
Solder Reflow Temperature Profile
(Surface Mount Option Parts)
Regulatory Information
The HCPL-260L/060L/263L/063L
are pending by the following
organizations:
UL
Approval (pending) under UL
1577, Component Recognition
Program, File E55361.
CSA
Approval (pending) under CSA
Component Acceptance Notice
#5, File CA 88324.
VDE
Approval (pending) according to
VDE 0884/06.92.
XXX
YWW
8765
432
5.994 ± 0.203
(0.236 ± 0.008)
3.937 ± 0.127
(0.155 ± 0.005)
0.406 ± 0.076
(0.016 ± 0.003) 1.270
(0.050)BSG
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005) 1.524
(0.060)
45° X 0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
0.305
(0.012)MIN.
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
0.203 ± 0.102
(0.008 ± 0.004)
7°
PIN ONE
0 ~ 7°
*
*
240
∆T = 115°C, 0.3°C/SEC
0
∆T = 100°C, 1.5°C/SEC
∆T = 145°C, 1°C/SEC
TIME – MINUTES
TEMPERATURE – °C
220
200
180
160
140
120
100
80
60
40
20
0
260
123456789101112
NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS HIGHLY RECOMMENDED.
1
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Insulation and Safety Related Specifications
8-Pin DIP
(300 Mil) SO-8
Parameter Symbol Value Value Units Conditions
Minimum External Air L (101) 7.1 4.9 mm Measured from input terminals to output
Gap (External Clearance) terminals, shortest distance through air.
Minimum External Tracking L (102) 7.4 4.8 mm Measured from input terminals to output
(External Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic 0.08 0.08 mm Through insulation distance, conductor to
Gap (Internal Clearance) conductor, usually the direct distance
between the photoemitter and photodetector
inside the optocoupler cavity.
Minimum Internal Tracking NA NA mm Measured from input terminals to output
(Internal Creepage) terminals, along internal cavity.
Tracking Resistance CTI 200 200 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
VDE 0884 Insulation Related Characteristics
Description Symbol Characteristic Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms I-IV
for rated mains voltage ≤ 450 V rms I-III
Climatic Classification 55/85/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage V
IORM
630 V
peak
Input to Output Test Voltage, Method b*
V
IORM
x 1.875 = V
PR
, 100% Production Test with t
m
= 1 sec, V
PR
1181 V
peak
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
IORM
x 1.5 = V
PR
, Type and Sample Test, V
PR
945 V
peak
t
m
= 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage* V
IOTM
6000 V
peak
(Transient Overvoltage, t
ini
= 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature T
S
175 ˚C
Input Current I
S,INPUT
230 mA
Output Power P
S,OUTPUT
600 mW
Insulation Resistance at T
S
, V
IO
= 500 V R
S
≥ 10
9
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Ω
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Absolute Maximum Ratings (No Derating Required up to 85˚C)
Parameter Symbol Package** Min. Max. Units Note
Storage Temperature T
S
–55 125 ˚C
Operating Temperature†T
A
–40 85 ˚C
Average Forward Input Current I
F
Single 8-Pin DIP 20 mA 2
Single SO-8
Dual 8-Pin DIP 15 1, 3
Dual SO-8
Reverse Input Voltage V
R
8-Pin DIP, SO-8 5 V 1
3
Input Power Dissipation P
I
40 mW
Supply Voltage (1 Minute Maximum) V
CC
7V
Enable Input Voltage (Not to Exceed V
E
Single 8-Pin DIP V
CC
+ 0.5 V
V
CC
by more than 500 mV) Single SO-8
Enable Input Current I
E
5mA
Output Collector Current I
O
50 mA 1
Output Collector Voltage V
O
7V1
Output Collector Power Dissipation P
O
Single 8-Pin DIP 85 mW
Single SO-8
Dual 8-Pin DIP 60 1, 4
Dual SO-8
Lead Solder Temperature T
LS
8-Pin DIP 260˚C for 10 sec., 1.6 mm below
(Through Hole Parts Only) seating plane
260˚C for 10 sec., up to seating
plane
Solder Reflow Temperature Profile SO-8 See Package Outline Drawings
(Surface Mount Parts Only) section
**Ratings apply to all devices except otherwise noted in the Package column.
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Input Current, Low Level I
FL
* 0 250 µA
Input Current, High Level
[1]
I
FH
** 5 15 mA
Power Supply Voltage V
CC
2.7 3.3 V
Low Level Enable Voltage V
EL
0 0.8 V
High Level Enable Voltage V
EH
2.0 V
CC
V
Operating Temperature T
A
–40 85 ˚C
Fan Out (at R
L
= 1 kΩ
Ω
)
[1]
N 5 TTL Loads
Output Pull-up Resistor R
L
330 4 k
*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used
for best performance and to permit at least a 20% LED degradation guardband.
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Electrical Specifications
Over Recommended Temperature (TA = –40˚C to +85˚C) unless otherwise specified. All Typicals at VCC = 3.3 V,
TA = 25˚C. All enable test conditions apply to single channel products only. See Note 5.
Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note
High Level Output Current IOH* 4.5 50 µAV
CC = 3.3 V, VE = 2.0 V, 1 1, 15
VO = 3.3 V, IF = 250 µA
Input Threshold Current ITH 3.0 5.0 mA VCC = 3.3 V, VE = 2.0 V, 2 15
VO = 0.6 V,
IOL (Sinking) = 13 mA
Low Level Output Voltage VOL* 0.35 0.6 V VCC = 3.3 V, VE = 2.0 V, 3 15
IF = 5 mA,
IOL (Sinking) = 13 mA
High Level Supply Current ICCH 4.7 7.0 mA VE = 0.5 V VCC = 3.3 V
IF = 0 mA
Low Level Supply Current ICCL 7.0 10.0 mA VE = 0.5 V VCC = 3.3 V
IF = 10 mA
High Level Enable Current IEH –0.5 –1.2 mA VCC = 3.3 V, VE = 2.0 V
Low Level Enable Current IEL*–0.5 –1.2 mA VCC = 3.3 V, VE = 0.5 V
High Level Enable Voltage VEH 2.0 V 15
Low Level Enable Voltage VEL 0.8 V
Input Forward Voltage VF1.4 1.5 1.75* V TA = 25˚CI
F = 10 mA 5 1
Input Reverse Breakdown BVR*5 V I
R = 10 µA
Voltage
Input Diode Temperature ∆VF/–1.6 mV˚CI
F = 10 mA 1
Coefficient ∆TA
–1.9
Input Capacitance C 60 pF f = 1 MHz, VF = 0 V 1
*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.
1
IN
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Switching Specifications
Over Recommended Temperature (T
A
= –40˚C to +85˚C), V
CC
= 3.3 V, I
F
= 7.5 mA unless otherwise specified. All Typicals
at T
A
= 25˚C, V
CC
= 3.3 V.
Parameter Sym. Package** Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay t
PLH
90 ns T
A
= 25˚CR
L
= 350 Ω6, 7, 8 1, 6, 15
Time to High Output C
L
= 15 pF
Level
Propagation Delay t
PHL
75 ns 1, 7, 15
Time to Low Output
Level
Pulse Width |t
PHL
– t
PLH
| 8-Pin DIP 25 ns 8 9, 15
Distortion SO-8
Propagation Delay t
PSK
40 ns 8, 9, 15
Skew
Output Rise Time t
r
45 ns 1, 15
(10-90%)
Output Fall Time t
f
20 ns 1, 15
(90-10%)
Propagation Delay t
ELH
45 ns R
L
= 350 Ω,910
Time of Enable from C
L
= 15 pF,
V
EH
tp V
EL
V
EL
= 0 V, V
EH
= 3 V
Propagation Delay t
EHL
30 ns 11
Time of Enable from
V
EL
to V
EH
*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
Parameter Sym. Device Min. Typ. Units Test Conditions Fig. Note
Logic High |CM
H
| HCPL-263L 15,000 25,000 V/µs|V
CM
| = 10 V V
CC
= 3.3 V, I
F
= 0 mA, 11 12, 14, 15
Common HCPL-063L V
O(MIN)
= 2 V,
Mode R
L
= 350 Ω, T
A
= 25˚C
Transient HCPL-260L 15,000 25,000 |V
CM
| = 50 V
Immunity HCPL-060L
Logic Low |CM
L
| HCPL-263L 15,000 25,000 V/µs|V
CM
| = 10 V V
CC
= 3.3 V, I
F
= 7.5 mA, 11 13, 14, 15
Common HCPL-063L V
O(MAX)
= 0.8 V,
Mode R
L
= 350 Ω, T
A
= 25˚C
Transient HCPL-260L 15,00 25,000 | = 50 V
Immunity HCPL-060L |V
CM
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Package Characteristics
All Typicals at T
A
= 25˚C.
Parameter Sym. Package Min. Typ. Max Units Test Conditions Fig. Note
Input-Output I
I-O
* Single 8-Pin DIP 1 µA 45% RH, t = 5 s, 16, 17
Insulation Single SO-8 V
I-O
= 3 kV DC, T
A
= 25˚C
Input-Output V
ISO
8-Pin DIP, SO-8 2500 V rms RH ≤ 50%, t = 1 min, 16, 17
Momentary T
A
= 25˚C
Withstand
Voltage**
Input-Output R
I-O
8-Pin, SO-8 10
12
ΩV
I-O
=500 V dc 1, 16, 19
Resistance
Input-Output C
I-O
8-Pin DIP, SO-8 0.6 pF f = 1 MHz, T
A
= 25˚C 1, 16, 19
Capacitance
Input-Input I
I-I
Dual Channel 0.005 µA RH ≤ 45%, t = 5 s, 20
Insulation V
I-I
= 500 V
Leakage
Current
Resistance R
I-I
Dual Channel 10
11
Ω20
(Input-Input)
Capacitance C
I-I
Dual 8-Pin Dip 0.03 pG f = 1 MHz 20
(Input-Input) Dual SO-8 0.25
*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level
safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
of the output pulse.
7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
of the output pulse.
8. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test
conditions.
9. See test circuit for measurement details.
10. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The tELH enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. CMH is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
(i.e., Vo > 2.0 V).
13. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., Vo < 0.8 V).
14. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM (p-p).
15. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved
CMR performance. For single channel products only. See application information provided.
16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
VDE 0884 Insulation Characteristics Table, if applicable.
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
VDE 0884 Insulation Characteristics Table, if applicable.
19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
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Figure 1. Typical high level output current vs.
temperature.
Figure 2. Typical input threshold current vs.
temperature.
Figure 3. Typical low level output voltage vs.
temperature.
Figure 5. Typical input diode forward
characteristic.
Figure 4. Typical low level output current vs.
temperature.
Figure 6. Test circuit for t
PHL
and t
PLH
.
I
OH
– HIGH LEVEL OUTPUT CURRENT – µA
-60
0
T
A
– TEMPERATURE – °C
100
10
15
-20
5
20
V
CC
= 3.3 V
V
O
= 3.3 V
V
E
= 2.0 V*
I
F
= 250 µA
60
-40 0 40 80
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
OUTPUT V
O
MONITORING
NODE
3.3 V
7
5
6
8
2
3
4
1
PULSE GEN.
Z = 50 Ω
t = t = 5 ns
O
f
I
F
R
L
R
M
V
CC
0.1 F
BYPASS
*C
L
GND
INPUT
MONITORING
NODE
r
SINGLE CHANNEL
OUTPUT V
O
MONITORING
NODE
3.3 V
7
5
6
8
2
3
4
1
PULSE GEN.
Z
O
= 50 Ω
t
f
= t
r
= 5 ns
I
F
R
L
R
M
V
CC
0.1 F
BYPASS
C
L
*
GND
INPUT
MONITORING
NODE
DUAL CHANNEL
*C
L
IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
1.5 V
t
PHL
t
PLH
I
F
INPUT
V
O
OUTPUT
I
F
= 7.50 mA
I
F
= 3.75 mA
I
F
– FORWARD CURRENT – mA
1.1
0.001
V
F
– FORWARD VOLTAGE – V
1.0
1000
1.3
0.01
1.51.2 1.4
0.1
T
A
= 25 °C
10
100
8-PIN DIP, SO-8
I
F
+
–
V
F
1.6
0.8
0.4
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
0.2
80400-40
0
V
OL
– LOW LEVEL OUTPUT VOLTAGE – V
I
O
= 13 mA
0.1
0.5
0.7
8-PIN DIP, SO-8
V
CC
= 3.3 V
V
E
= 2.0 V*
I
F
= 5.0 mA
0.3
0.6
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
V
CC
= 3.3 V
V
E
= 2.0 V*
V
OL
= 0.6 V
70
60
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
50
80400-40
20
I
OL
– LOW LEVEL OUTPUT CURRENT – mA
40
I
F
= 5.0 mA
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
V
CC
= 3.3 V
V
O
= 0.6 V
12
6
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
4
80400-40
0
I
TH
– INPUT THRESHOLD CURRENT – mA
R
L
= 350 Ω
2
8
10
R
L
= 1 KΩ
R
L
= 4 KΩ
8-PIN DIP, SO-8
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Figure 7. Typical propagation delay vs.
temperature.
Figure 9. Test circuit for tEHL and tELH.
Figure 10. Test circuit for common mode transient immunity and typical waveforms.
V
CC
= 3.3 V
I
F
= 7.5 mA
150
120
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
90
80400-40
0
t
P
– PROPAGATION DELAY – ns
60
30
t
PHL
, R
L
= 350 Ω
t
PLH
, R
L
= 350 Ω
Figure 8. Typical pulse width distortion vs.
temperature.
V
CC
= 3.3 V
I
F
= 7.5 mA
50
40
-20 20 60 100
T
A
– TEMPERATURE – °C
30
80400-40
PWD – PULSE WIDTH DISTORTION – ns
20
R
L
= 350 Ω
10
-60
0
OUTPUT V
O
MONITORING
NODE 1.5 V
t
EHL
t
ELH
V
E
INPUT
V
O
OUTPUT
3.0 V
1.5 V
+3.3 V
7
5
6
8
2
3
4
1
PULSE GEN.
Z
O
= 50 Ω
t
f
= t
r
= 5 ns
I
F
R
L
V
CC
0.1 F
BYPASS
*C
L
*C
L
IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
GND
7.5 mA
INPUT V
E
MONITORING NODE
+3.3 V
7
5
6
8
2
3
4
1VCC
0.1 F
BYPASS
GND
OUTPUT VO
MONITORING
NODE
PULSE
GENERATOR
ZO = 50 Ω
+
IF
B
A
VFF
VCM
–
RL
SINGLE CHANNEL
+3.3 V
7
5
6
8
2
3
4
1VCC
0.1 F
BYPASS
GND
OUTPUT VO
MONITORING
NODE
PULSE
GENERATOR
ZO = 50 Ω
+
IF
B
A
VFF
VCM
–
RL
DUAL CHANNEL
VO0.5 V
VO (MIN.)
3.3 V
0 V SWITCH AT A: IF = 0 mA
SWITCH AT B: IF = 7.5 mA
VCM
CMH
CML
VO (MAX.)
VCM (PEAK)
VO
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6−115
Figure 11. Recommended printed circuit board layout.
Figure 12. Recommended LVTTL interface circuit.
GND BUS (BACK)
V
CC
BUS (FRONT)
ENABLE
0.1 F
10 mm MAX.
(SEE NOTE 5)
OUTPUT
NC
NC
SINGLE CHANNEL
DEVICE ILLUSTRATED.
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
V
CC1
3.3 V
GND 1
D1*
I
F
V
F
SHIELD
SINGLE CHANNEL DEVICE
8
6
5
R
L
0.1 F
BYPASS
2
3
+
–
3.3 V
GND 2
V
CC2
2
220 Ω
1
7
V
E
V
CC1
3.3 V
GND 1
D1*
SHIELD
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
8
7
5
R
L
0.1 F
BYPASS
1
2
+
–
3.3 V
GND 2
V
CC2
2
220 Ω
1
I
F
V
F
6章104-117(PDF用) 01.5.24, 4:24 PMPage 115 AdobePageMaker6.0J/PPC
6−116
Figure 13. Recommended drive circuit for High-CMR.
0.01 F
350 Ω
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
VO
VCC+
8
7
6
1
3
SHIELD 5
2
4
HCPL-260L
GND
GND2
220 Ω
VCC
220 Ω
*
*
*
HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).
GND1
Application Information
Common-Mode Rejection for
HCPL-260L Families:
Figure 13 shows the recom-
mended drive circuit for optimal
common-mode rejection
performance. Two main points to
note are:
1. The enable pin is tied to VCC
rather than floating (this
applies to single-channel parts
only).
2. Two LED-current setting
resistors are used instead of
one. This is to balance ILED
variation during common-
mode transients.
If the enable pin is left floating, it
is possible for common-mode
transients to couple to the enable
pin, resulting in common-mode
failure. This failure mechanism
only occurs when the LED is on
and the output is in the Low
State. It is identified as occurring
when the transient output voltage
rises above 0.8 V. Therefore, the
enable pin should be connected
to either VCC or logic-level high
for best common-mode
performance with the output low
(CMRL). This failure mechanism
is only present in single-channel
parts which have the enable
function.
Also, common-mode transients
can capacitively couple from the
LED anode (or cathode) to the
output-side ground causing
current to be shunted away from
the LED (which can be bad if the
LED is on) or conversely cause
current to be injected into the
LED (bad if the LED is meant to
be off). Figure 14 shows the
parasitic capacitances which
exists between LED
anode/cathode and output ground
(CLA and CLC). Also shown in
Figure 14 on the input side is an
AC-equivalent circuit.
Figure 14. AC equivalent circuit.
350 Ω
1/2 R
LED
V
CC
+
15 pF
+
V
CM
8
7
6
1
3
SHIELD 5
2
4
C
LA
V
O
GND
0.01 F
1/2 R
LED
C
LC
I
LN
I
LP
–
For transients occurring when the
LED is on, common-mode rejec-
tion (CMRL, since the output is in
the “low” state) depends upon the
amount of LED current drive (IF).
For conditions where IF is close
to the switching threshold (ITH),
CMRL also depends on the extent
which ILP and ILN balance each
other. In other words, any
condition where common-mode
transients cause a momentary
decrease in IF will cause
common-mode failure for
transients which are fast enough.
Likewise for common-mode
transients which occur when the
LED is off (i.e. CMR H, since the
output is “high”), if an imbalance
between ILP and ILN results in a
transient IF equal to or greater
than the switching threshold of
the optocoupler, the transient
“signal” may cause the output to
spike below 2 V (which consti-
tutes a CMRH failure).
By using the recommended
circuit in Figure 13, good CMR
can be achieved. The balanced
ILED-setting resistors help equalize
ILP and ILN to reduce the amount
by which ILED is modulated from
transient coupling through CLA
and CLC
.
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6−117
CMR with Other Drive
Circuits
CMR performance with drive
circuits other than that shown in
Figure 13 may be enhanced by
following these guidelines:
1. Use of drive circuits where
current is shunted from the
LED in the LED off” state (as
shown in Figures 15 and 16).
This is beneficial for good
CMRH.
2. Use of I FH > 3.5 mA. This is
good for high CMRL.
Figure 15 shows a circuit which
can be used with any totem-pole-
output TTL/LSTTL/HCMOS logic
gate. The buffer PNP transistor
allows the circuit to be used with
logic devices which have low
current-sinking capability. It also
helps maintain the driving-gate
power-supply current at a
constant level to minimize ground
shifting for other devices
connected to the input-supply
ground.
When using an open-collector
TTL or open-drain CMOS logic
gate, the circuit in Figure 16 may
be used. When using a CMOS
gate to drive the optocoupler, the
circuit shown in Figure 17 may
be used. The diode in parallel
with the RLED speeds the turn-off
of the optocoupler LED.
Figure 15. TTL interface circuit.
Figure 16. TTL open-collector/open drain gate drive circuit.
Figure 17. CMOS gate drive circuit.
420 Ω
(MAX)
1
3
2
4
2N3906
(ANY PNP)
V
CC
74L504
(ANY
TTL/CMOS
GATE)
HCPL-260L
LED
R
1
3
2
4
V
CC
74HC00
(OR ANY
OPEN-COLLECTOR/
OPEN-DRAIN
LOGIC GATE)
HCPL-260L
LED
220 Ω
1
3
2
4
V
CC
74HC04
(OR ANY
TOTEM-POLE
OUTPUT LOGIC
GATE)
HCPL-260L
1N4148
LED
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
5980-2523EN (11/00)
”
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