Touch Screen Controller
Data Sheet
AD7877
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
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FEATURES
4-wire touch screen interface
LCD noise reduction feature (STOPACQ pin)
Automatic conversion sequencer and timer
User-programmable conversion parameters
On-chip temperature sensor: −40°C to +85°C
On-chip 2.5 V reference
On-chip 8-bit DAC
3 auxiliary analog inputs
1 dedicated and 3 optional GPIOs
2 direct battery measurement channels (0.5 V to 5 V)
3 interrupt outputs
Touch-pressure measurement
Wake up on touch function
Specified throughput rate of 125 kSPS
Single supply, VCC of 2.7 V to 5.25 V
Separate VDRIVE level for serial interface
Shutdown mode: 1 µA maximum
32-lead, LFCSP, 5 mm × 5 mm package
25-ball,WLCSP, 2.5 mm × 2.8 mm package
Qualified for automotive applications
APPLICATIONS
Personal digital assistants
Smart hand-held devices
Touch screen monitors
Point-of-sale terminals
Medical devices
Cell phones
Pagers
FUNCTIONAL BLOCK DIAGRAM
19
DIN
26
DCLK
27
DOUT
28
V
DRIVE
18
CS
23
DAV
CONTROL LOGICAND SERIAL PO RT
DAC
REGISTER
CONTROL
REGISTERS
GPIO
REGISTERS
ALERT STATUS/
MASK REGISTER
LIMIT
REGISTERS
LIMIT
COMPARATOR
RESULTS
REGISTERS
SEQUENCER
8-BIT
DAC
29
ARNG
30
AOUT
4
AUX3/GPIO3
5
AUX2/GPIO2
6
AUX1/GPIO1
31
V
REF
PEN I NTERRUPT
AND WAKE-UP
ON TOUCH
17
PENIRQ
ALERT
LOGIC
22
ALERT
STOP
ACQ
LOGIC
20
STOPACQ
14
AGND
15
DGND
21
GPIO4
2.5V
REF BUF
TO
GPIO1-3
ADC DATA
12-BIT SUCCESS IVE
APPROXIMATION ADC
WI TH TRACK-AND- HOLD
CLOCK
9 TO 1
INPUT
MUX
TEMPERATURE
SENSOR
2
BAT2 BATTERY
MONITOR
3
BAT1 BATTERY
MONITOR
11
Y–
13
Y+
10
X–
12
X+
7
V
CC
REF–
IN
REF+
DUAL 3-1
MUX
X– Y– GND X+ Y+ V
REF
AD7877
03796-001
Figure 1.
GENERAL DESCRIPTION
The AD7877 is a 12-bit, successive approximation ADC with a
synchronous serial interface and low on resistance switches for
driving touch screens. The AD7877 operates from a single 2.7 V
to 5.25 V power supply (functional operation to 2.2 V), and
features throughput rates of 125 kSPS. The AD7877 features
direct battery measurement on two inputs, temperature and
touch-pressure measurement.
The AD7877 also has an on-board reference of 2.5 V. When not
in use, it can be shut down to conserve power. An external
reference can also be applied and varied from 1 V to +VCC, with
an analog input range of 0 V to VREF. The device includes a
shutdown mode that reduces its current consumption to less
than 1 µA.
To reduce the effects of noise from LCDs, the acquisition phase
of the on-board ADC is controlled via the STOPACQ pin. User-
programmable conversion controls include variable acquisition
time and first conversion delay. Up to 16 averages can be taken
per conversion. There is also an on-board DAC for LCD back-
light or contrast control. The AD7877 runs in either slave or
master mode using a conversion sequencer and timer. It is ideal
for battery-powered systems such as personal digital assistants
with resistive touch screens and other portable equipment.
The part is available in a 32-lead lead frame chip scale package
(LFCSP), and a 25-ball wafer level chip scale package (WLCSP).
AD7877 Data Sheet
Rev. D | Page 2 of 44
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Timing Diagrams .......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 13
Circuit Information ........................................................................ 14
Touch Screen Principles ............................................................ 14
Measuring Touch Screen Inputs ............................................... 15
Touch-Pressure Measurement .................................................. 16
STOPACQ Pin ............................................................................ 16
Temperature Measurement ....................................................... 17
Battery Measurement ................................................................. 18
Auxiliary Inputs .......................................................................... 19
Limit Comparison ...................................................................... 19
Control Registers ............................................................................ 20
Control Register 1 ...................................................................... 20
Control Register 2 ...................................................................... 21
Sequencer Registers ................................................................... 22
Interrupts ..................................................................................... 24
Syncronizing the AD7877 to the Host CPU ........................... 25
8-Bit DAC ........................................................................................ 26
Serial Interface ................................................................................ 28
Writing Data ............................................................................... 28
Write Timing ............................................................................... 29
Reading Data ............................................................................... 29
VDRIVE Pin ..................................................................................... 29
General-Purpose I/O Pins ............................................................. 30
GPIO Configuration .................................................................. 30
Grounding and Layout .................................................................. 32
PCB Design Guidelines for Chip Scale Packages ................... 32
Register Maps .................................................................................. 33
Detailed Register Descriptions ..................................................... 35
GPIO Registers ........................................................................... 42
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
Automotive Products ................................................................. 44
REVISION HISTORY
12/11—Rev. C to Rev. D
Change to Features Section ............................................................. 1
Updated Outline Dimensions ....................................................... 44
Changes to Ordering Guide .......................................................... 44
Added Automotive Products Section .......................................... 44
9/09—Rev. B to Rev. C
Changes to Offset Error and Gain Error Parameters .................. 3
Added VBAT to GND Parameter ...................................................... 6
Changes to Pin 23 Description ....................................................... 7
Changes to Power Management (Control Register 2,
Bits[7:6]) Section ............................................................................ 22
Changes to Bit 7 Description (Tabl e 17) ...................................... 36
Updated Outline Dimensions ....................................................... 44
Changes Ordering Guide ............................................................... 44
6/06—Rev. A to Rev. B
Added Wafer Level Chip Scale Package ........................... Universal
Changes to Tabl e 3 ............................................................................ 6
Changes to Figure 21 ...................................................................... 11
Change to Figure 25 ....................................................................... 12
Changes to Figure 38 and Figure 39............................................. 23
Change to Figure 40 ....................................................................... 24
Changes to Data Available Output (DAV) Section .................... 24
Updated Outline Dimensions ....................................................... 42
Changes to Ordering Guide .......................................................... 42
11/04—Rev. 0 to Rev. A
Changes to Absolute Maximum Ratings ....................................... 6
Changes to Figure 4 ........................................................................... 7
Changes to Table 4 ............................................................................. 7
Changes to Grounding and Layout section ................................ 32
Changes to Figure 42 ...................................................................... 32
Changes to Ordering Guide .......................................................... 43
7/04—Revision 0: Initial Version
Data Sheet AD7877
Rev. D | Page 3 of 44
SPECIFICATIONS
VCC = 2.7 V to 3.6 V, VREF = 2.5 V internal or external, fDCLK = 2 MHz, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DC ACCURACY
Resolution 12 Bits
No Missing Codes 11 12 Bits
Integral Nonlinearity (INL)1 ±2 LSB LSB size = 610 µV
Differential Nonlinearity (DNL)1 Minimum LSB size = 610 µV
Negative DNL −0.99 LSB
Positive DNL +2 LSB
Offset Error1 ±5 LSB Specified for 11bits
Gain Error1 ±3 LSB Specified for 11 bits; external reference
Noise 70 µV rms
Power Supply Rejection 70 dB
Internal Clock Frequency 2 MHz
SWITCH DRIVERS
On Resistance1
Y+, X+ 14 Ω
Y−, X− 14 Ω
ANALOG INPUTS
Input Voltage Ranges 0 VREF V
DC Leakage Current ±0.1 µA
Input Capacitance 30 pF
Accuracy 0.3 % All channels, internal VREF
REFERENCE INPUT/OUTPUT
Internal Reference Voltage 2.44 2.55 V
Internal Reference Tempco ±50 ppm/°C
VREF Input Voltage Range 1 VCC V
DC Leakage Current ±1 µA
V
REF
Input Impedance
1
GΩ
CS = GND or VCC; typically 25 Ω when the on-board
reference is enabled
TEMPERATURE MEASUREMENT
Temperature Range −40 +85 °C
Resolution
Differential Method2 1.6 °C
Single Conversion Method3 0.3 °C
Accuracy
Differential Method2
±4
°C
0°C to 70°C
Single Conversion Method3 ±2 °C Calibrated at 25°C
BATTERY MONITOR
Input Voltage Range
0.5
5
V
@ V
REF
= 2.5 V
Input Impedance 14 kΩ Sampling, 1 GΩ when the battery monitor is off
Accuracy 1 3.2 % External/internal reference, see Figure 26
AD7877 Data Sheet
Rev. D | Page 4 of 44
Parameter Min Typ Max Unit Test Conditions/Comments
DAC
Resolution 8 Bits
Integral Nonlinearity ±1 Bits
Differential Nonlinearity ±1 Guaranteed monotonic by design
Voltage Mode
Output Voltage Range 0 − VCC/2 V DAC register Bit 2 = 0, Bit 0 = 0
0 − VCC V DAC register Bit 2 = 0, Bit 0 = 1
Slew Rate −0.4, +0.5 V/µs
Output Settling Time 12 15 µs 0 to 3/4 scale, RLOAD = 10 kΩ, CLOAD = 50 pF
Capacitive Load Stability 50 100 pF RLOAD = 10 kΩ
Output Impedance
75
kΩ
Power-down mode
Short-Circuit Current 21 mA
Current Mode
Output Current Range 0 1000 µA DAC register, Bit 2 = 1; full-scale current is set by RRNG
Output Impedance Open Power-down mode
LOGIC INPUTS
Input High Voltage, VINH 0.7 VDRIVE V
Input Low Voltage, VINL 0.3
VDRIVE
V
Input Current, IIN ±1 µA Typically 10 nA, VIN = 0 V or VCC
Input Capacitance, CIN4 10 pF
LOGIC OUTPUTS
Output High Voltage, VOH VDRIVE − 0.2 V ISOURCE = 250 µA, VCC/VDRIVE = 2.7 V to 5.25 V
Output Low Voltage, VOL 0.4 V ISINK = 250 µA
Floating-State Leakage Current ±10 µA
Floating-State Output Capacitance
4
10 pF
Output Coding
Straight (natural) binary
CONVERSION RATE
Conversion Time 8 µs CS high to DAV low
Throughput Rate 125 kSPS
POWER REQUIREMENTS
VCC (Specified Performance) 2.7 3.6 V Functional from 2.2 V to 5.25 V
VDRIVE 1.65 VCC V
ICC Digital inputs = 0 V or VCC
Converting Mode 240 380 µA ADC on, internal reference off, VCC = 3.6 V
650 900 µA ADC on, internal reference on, VCC = 3.6 V
900 µA ADC on, internal reference on, DAC on
Static
150
µA
ADC on, but not converting, internal reference off,
VCC = 3.6 V
Shutdown Mode 1 µA
1 See the Terminology section.
2 Difference between Temp0 and Temp1 measurement. No calibration necessary.
3 Temperature drift is −2.1 mV/°C.
4 Sample tested @ 25°C to ensure compliance.
Data Sheet AD7877
Rev. D | Page 5 of 44
TIMING SPECIFICATIONS
TA = TMIN to TMAX, unless otherwise noted, VCC = 2.7 V to 5.25 V, VREF = 2.5 V. Sample tested at 25°C to ensure compliance. All input
signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
Table 2.
Parameter Limit at TMIN, TMAX
Unit Description
fDCLK1 10 kHz min
20 MHz max
t1
16 ns min CS falling edge to first DCLK rising edge
t2
20 ns min DCLK high pulse width
t
3
20
ns min
DCLK low pulse width
t4
12 ns min DIN setup time
t5
12 ns min DIN hold time
t62
16 ns max CS falling edge to DOUT, three-state disabled
t72
16 ns max DCLK falling edge to DOUT valid
t83
16 ns max CS rising edge to DOUT high impedance
t
9
0
ns min
CS rising edge to DCLK ignored
1 Mark/space ratio for the DCLK input is 40/60 to 60/40.
2 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V.
3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
TIMING DIAGRAMS
03796-004
DCLK
t1t2t3
t5
t4
t6t7
t9
t8
DIN MSB LSB
MSB LSB
DOUT
1 2 3 15 16
CS
Figure 2. Detailed Timing Diagram
03796-003
200µA IOL
200µA IOH
1.6V
TO OUTPUT
PIN CL
50pF
Figure 3. Load Circuit for Digital Output Timing Specifications
AD7877 Data Sheet
Rev. D | Page 6 of 44
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Output Voltage to GND −0.3 V to VCC + 0.3 V
VREF to GND −0.3 V to VCC + 0.3 V
VBAT to GND −0.3 V to VCC +5 V
Input Current to Any Pin Except Supplies1 10 mA
ESD Rating (IEC 1000-4-2, Air Discharge)
Tablet Pins (X+, X−, Y+, Y−) 4 kV
Other Pins 2 kV
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature
150°C
LFCSP Package
Power Dissipation 450 mW
θJA Thermal Impedance 135.7°C/W
IR Reflow Peak Temperature 220°C
Pb-Free Parts Only 260°C (±0.5°C)
Lead Temperature (Soldering 10 sec) 300°C
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet AD7877
Rev. D | Page 7 of 44
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03796-002
NC
1
BAT2
2
BAT1
3
AUX3/GPIO3
4
AUX2/GPIO2
5
AUX1/GPIO1
6
V
CC 7
NC
8
NC
24
DAV
23
ALERT
22
GPIO4
21
STOPACQ
20
DIN
19
CS
18
PENIRQ
17
NC
V
REF
AOUT
ARNG
V
DRIVE
DOUT
DCLK
NC
32 31 30 29 28 27 26 25
NC
X–
Y–
X+
Y+
AGND
DGND
NC
910 11 12 13 14 15 16
NOTES
1. NC = NO CO NNE CT
2. THE EX P OSE D P AD IS NO T CO NNE CTED I NTERNALLY . F OR
INCRE AS E D RE LIABIL ITY OF THE SOL DE R JOINTS AND
MAXIMUM THERMAL CAPABILITY, I T I S RECOMMENDED
THAT THE P AD BE S OL DE RE D TO GRO UND P LANE.
AD7877
TOP VI EW
(No t t o Scal e)
Figure 4. LFCSP Pin Configuration
AD7877 WLCSP
TOP VI EW
Not t o Scal e
03796-051
DCLK
ALERT
STOP
ACQ
CS
DGND
DOUT
GPIO4
DIN
PENIRQ
Y+
VDRIVE
DAV
AUX2/
GPI02
AGND
X+
ARNG
VREF
BAT1
VCC
Y–
AOUT
BAT2
AUX3/
GPI03
AUX1/
GPI01
X–
PIN 1
Figure 5. WLCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8, 9, 16,
24, 25, 32
NC No Connect.
2 BAT2 Battery Monitor Input. ADC Input Channel 7.
3 BAT1 Battery Monitor Input. ADC Input Channel 6.
4 AUX3/GPIO3 Auxiliary Analog Input. ADC Input Channel 5. Can be reconfigured as GPIO pin.
5 AUX2/GPIO2 Auxiliary Analog Input. ADC Input Channel 4. Can be reconfigured as GPIO pin.
6 AUX1/GPIO1 Auxiliary Analog Input. ADC Input Channel 3. Can be reconfigured as GPIO pin.
7 VCC Power Supply Input. The VCC range for the AD7877 is from 2.2 V to 5.25 V.
10 X− Touch Screen Position Input.
11 Y− Touch Screen Position Input. ADC Input Channel 2.
12
X+
Touch Screen Position Input. ADC Input Channel 0.
13 Y+ Touch Screen Position Input. ADC Input Channel 1.
14 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7877. All analog input signals and any
external reference signal should be referred to this voltage.
15 DGND Digital Ground. Ground reference for all digital circuitry on the AD7877. Refer all digital input signals to this
voltage.
17 PENIRQ Pen Interrupt. Digital active low output (has a 50 kΩ internal pull-up resistor).
18 CS Chip Select Input. Active low logic input. This input provides the dual function of initiating conversions on the
AD7877 and enabling the serial input/output register.
19 DIN SPI® Serial Data Input. Data to be written to the AD7877 registers are provided on this input and clocked into
the register on the rising edge of DCLK.
20
STOPACQ
Stop Acquisition Pin. A signal applied to this pin can be monitored by the AD7877, so that acquisition of new
data by the ADC is halted while the signal is active. Used to reduce the effect of noise from an LCD screen on
the touch screen measurements.
21 GPIO4 Dedicated General-Purpose Logic Input/Output Pin.
22 ALERT Digital Active Low Output. Interrupt output that goes low if a GPIO data bit is set, or if the AUX1, TEMP1, BAT1,
or BAT2 measurements are out of range.
23
DAV Data Available Output. Active low logic output. Asserts low when new data is available in the AD7877 results
registers.
26 DCLK External Clock Input. Logic input. DCLK provides the serial clock for accessing data from the part.
27 DOUT Serial Data Output. Logic output. The conversion result from the AD7877 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the DCLK input. This output is high impedance
when CS is high.
AD7877 Data Sheet
Rev. D | Page 8 of 44
Pin No. Mnemonic Description
28 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage for the serial
interface of the AD7877.
29 ARNG When the DAC is in current output mode, a resistor from ARNG to GND sets the output range.
30 AOUT Analog Output Voltage or Current from DAC.
31 VREF Reference Output for the AD7877. The internal 2.5 V reference is available on this pin for use external to the
device. The reference output must be buffered before it is applied elsewhere in a system. To reduce system
noise effects, it is strongly recommended to place a capacitor of 100 nF between the VREF pin and GND.
Alternatively, an external reference can be applied to this input. The voltage range for the external reference is
1.0 V to VCC. For the specified performance, it is 2.5 V on the AD7877.
Data Sheet AD7877
Rev. D | Page 9 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 125 kHz, fDCLK = 16 × fSAMPLE = 2 MHz, unless otherwise noted.
800
700
600
500
–50 –30 –10 0 30 50 70 90
03796-030
TEMPERATURE (°C)
CURRENT (µA)
ADC AND REF
ADC, REF, AND DAC
Figure 6. Supply Current vs. Temperature
1000
400
500
600
700
800
900
2.0 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0
03796-031
V
CC
(V)
CURRENT (µA)
ADC AND REF
ADC, REF, AND DAC
Figure 7. Supply Current vs. VCC
0.6
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–50 –30 –10 10 30 50 70 90
03796-039
TEMPERATURE (°C)
DELTA FROM 25°C (LSB)
Figure 8. Change in ADC Gain vs. Temperature
200
80
100
120
140
160
180
–50 –30 –10 10 30 50 70 90
03796-032
TEMPERATURE (°C)
CURRENT (nA)
Figure 9. Full Power-Down IDD vs. Temperature
0.6
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–50 –30 –10 10 30 50 70 90
03796-040
TEMPERATURE (°C)
DELTA FROM 25°C (LSB)
Figure 10. Change in ADC Offset vs. Temperature
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 500 1000 1500 2000 2500 3000 3500 4000
03796-044
CODE
INL (LSB)
Figure 11. ACD INL Plot
AD7877 Data Sheet
Rev. D | Page 10 of 44
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 500 1000 1500 2000 2500 3000 3500 4000
03796-045
CODE
DNL (LSB)
Figure 12. ADC DNL Plot
22
8
10
12
14
16
18
20
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
03796-048
V
CC
(V)
R
ON
(Ω)
Y+ TO V
CC
Y– TO GND
X+ TO V
CC
X– TO GND
Figure 13. Switch On Resistance vs. VCC
(X+, Y+: VCC to Pin; X−, Y−: Pin to GND)
22
8
10
12
14
16
18
20
–40 –20 020 40 60 80
03796-049
TEMPERATURE (°C)
R
ON
(Ω)
Y+ TO V
CC
Y– TO GND
X+ TO V
CC
X– TO GND
Figure 14. Switch On Resistance vs. Temperature
(X+, Y+: VCC to Pin; X−, Y−: Pin to GND)
16
14
12
10
8
6
4
2
0
–50 9070503010–10–30
03796-046
TEMPERATURE (°C)
REFERENCE CURRENT (µA)
Figure 15. External Reference Current vs. Temperature
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
2.475
–50 –30 –10 10 30 50 70 90
03796-033
TEMPERATURE (°C)
V
REF
(V)
Figure 16. Internal VREF vs. Temperature
2.508
2.496
2.498
2.500
2.502
2.504
2.506
2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0
03796-034
V
CC
(V)
V
REF
(V)
Figure 17. Internal VREF vs. VCC
Data Sheet AD7877
Rev. D | Page 11 of 44
3145
3135
3125
3115
3105
3095
3085
3075
3065
3055
3045
–50 –30 –10 10 30 50 70 90
03796-041
TEMPERATURE (°C)
ADC CODE (Decimal)
Figure 18. ADC Code vs. Temperature (2.7 V Supply)
1183
1176
1177
1178
1179
1180
1181
1182
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
03796-042
V
CC
(V)
TEMP1 CODE
Figure 19. Temp1 vs. VCC
982
975
976
977
978
979
980
981
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
03796-043
V
CC
(V)
TEMP0 CODE
Figure 20. Temp0 vs. VCC
03796-047
INTERNAL VREF (V)
TURN-ON TIME (µs)
0
2.5
6
20 40 60 80 100 120–20 0
NO CAP
0.711µs SETTLING TIME
100nF CAP
54.64µs SETTLING TIME
Figure 21. Internal VREF vs. Turn-On Time
10
–150
–130
–110
–90
–70
–50
–30
–10
0 10k 20k 30k
SNR 70.25dB
THD 78.11dB
40k
03796-035
FREQUENCY
INPUT TONE AMPLITUDE (dB)
Figure 22. Typical FFT Plot for the Auxiliary Channels of the AD7877
at 90 kHz Sample Rate and 10 kHz Input Frequency
3.50
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
012345678910
03796-036
SOURCE/SINK CURRENT (mA)
DAC O/P LEVEL (V)
DAC O/P SOURCE ABILITY
DAC O/P SINK ABILITY
Figure 23. DAC Source and Sink Current Capability
AD7877 Data Sheet
Rev. D | Page 12 of 44
03796-037
CH1 200mV CH2 100mV M2.00µs CH1 780mV
1
∆
: 144mV
@: 1.296V
V
DD
= 3V
TEMPERATURE = 25°C
Figure 24. DAC Output Settling Time (Zero Scale to Half Scale)
600
500
400
300
200
100
0025 50 75 100 125 150 175 200 225 250
03796-038
INP UT CODE ( Decimal )
DAC SI NK CURRE NT (µ A)
DAC SI NK CURRE NT
NOTE: M AX IMUM DAC S INK CURRENT IS
SET ACCORDING TO THE EQUATION:
I
MAX
= V
CC
/(R
RNG
× 6)
Figure 25. DAC Sink Current vs. Input Code with RRNG = 1 kΩ
–2 –1 0 1 2
03796-050
ERROR (%)
Figure 26. Typical Accuracy for Battery Channel (25°C)
Data Sheet AD7877
Rev. D | Page 13 of 44
TERMINOLOGY
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale at 1 LSB below the first code
transition, and full scale at 1 LSB above the last code transition.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00…000) to
(00…001) from the ideal (AGND + 1 LSB).
Gain Error
The deviation of the last code transition (111…110) to
(111…111) from the ideal (VREF − 1 LSB) after the offset
error has been adjusted out.
On Resistance
A measure of the ohmic resistance between the drain and the
source of the switch drivers.
AD7877 Data Sheet
Rev. D | Page 14 of 44
CIRCUIT INFORMATION
The AD7877 is a complete, 12-bit data acquisition system for
digitizing positional inputs from a touch screen in PDAs and
other devices. In addition, it can monitor two battery voltages,
ambient temperature, and three auxiliary analog voltages, with
high and low limit comparisons on three of the inputs, and has
up to four general-purpose logic I/O pins.
The core of the AD7877 is a high speed, low power, 12-bit
analog-to-digital converter (ADC) with input multiplexer,
on-chip track-and-hold, and on-chip clock. The results of
conversions are stored in 11 results registers, and the results
from one auxiliary input and two battery inputs can be com-
pared with high and low limits stored in limit registers to generate
an out-of-limit ALERT. The AD7877 also contains low resistance
analog switches to switch the X and Y excitation voltages to the
touch screen, a STOPACQ pin to control the ADC acquisition
period, 2.5 V reference, on-chip temperature sensor, and 8-bit
DAC to control LCD contrast. The high speed SPI serial bus
provides control of, and communication with, the device.
Operating from a single supply from 2.2 V to 5 V, the AD7877
offers throughput rates of up to 125 kHz. The device is available
in a 5 mm × 5 mm, 32-lead, lead frame chip scale package
(LFCSP), and in a 2.5 mm × 2.8 mm, wafer level chip scale
package (WLCSP), with a 5 × 5 ball grid array.
The data acquisition system of the AD7877 has a number of
advanced features:
• Input channel sequenced automatically or selected by
the host.
• STOPACQ feature to reduce noise from LCD.
• Averaging of from 1 to 16 conversions for noise reduction.
• Programmable acquisition time.
• Power management.
• Programmable ADC power-up delay before first
conversion.
• Choice of internal or external reference.
• Conversion at preprogrammed intervals.
TOUCH SCREEN PRINCIPLES
A 4-wire touch screen consists of two flexible, transparent,
resistive-coated layers that are normally separated by a small air
gap. The X layer has conductive electrodes running down the
left and right edges, allowing the application of an excitation
voltage across the X layer from left to right.
03796-005
X+
X–
Y–
Y+
CONDUCTIVE ELECTRODE
ON BOTTOM SIDE
PLASTIC FILM WITH
TRANSPARENT, RESISTIVE
COATING ON BOTTOM SIDE
PLASTIC FILM WITH
TRANSPARENT, RESISTIVE
COATING ON TOP SIDE
LCD SCREEN
CONDUCTIVE ELECTRODE
ON TOP SIDE
Figure 27. Basic Construction of a Touch Screen
The Y layer has conductive electrodes running along the top
and bottom edges, allowing the application of an excitation
voltage down the Y layer from top to bottom.
Provided that the layers are of uniform resistivity, the voltage at
any point between the two electrodes is proportional to the
horizontal position for the X layer and the vertical position for
the Y layer.
When the screen is touched, the two layers make contact. If
only the X layer is excited, the voltage at the point of contact,
and therefore the horizontal position, can be sensed at one of
the Y layer electrodes. Similarly, if only the Y layer is excited,
the voltage, and therefore the vertical position, can be sensed at
one of the X layer electrodes. By switching alternately between
X and Y excitation and measuring the voltages, the X and
Y coordinates of the contact point can be found.
In addition to measuring the X and Y coordinates, it is also
possible to estimate the touch pressure by measuring the
contact resistance between the X and Y layers. The AD7877 is
designed to facilitate this measurement.
Figure 28 shows an equivalent circuit of the analog input
structure of the AD7877, showing the touch screen switches,
the main analog multiplexer, the ADC with analog and
differential reference inputs, and the dual 3-to-1 multiplexer
that selects the reference source for the ADC.
Data Sheet AD7877
Rev. D | Page 15 of 44
AUX3/GPIO4
BAT1
BAT2
AUX2/GPIO3
AUX1/GPIO2
12-BIT SUCCESSIVE
APPROXIMATION ADC
WITH TRACK-AND-HOLD
9 TO 1
I/P
MUX
TEMPERATURE
SENSOR
Y–
Y+
X–
X+
V
CC
REF–
IN+
REF
INT/EXT
REF+
DUAL 3-1
MUX
X– Y– GND X+ Y+ V
REF
03796-006
Figure 28. Analog Input Structure
The AD7877 can be set up to automatically convert either
specific input channels or a sequence of channels. The results of
the ADC conversions are stored in the results registers. See the
Serial Interface section for details.
When measuring the ancillary analog inputs (AUX1 to AUX3,
BAT1 and BAT2), the ADC uses the internal reference, or an
external reference applied to the VREF pin, and the measurement
is referred to GND.
MEASURING TOUCH SCREEN INPUTS
When measuring the touch screen inputs, it is possible to
measure using the internal (or external) reference, or to use the
touch screen excitation voltage as the reference and perform a
ratiometric, differential measurement. The differential method
is the default and is selected by clearing the SER/DFR bit
(Bit 11) in Control Register 1. The single-ended method is
selected by setting this bit.
Single-Ended Method
Figure 29 illustrates the single-ended method for the Y position.
For the X position, the excitation voltage is applied to X+ and
X− and the voltage measured at Y+.
03796-007
ADC
REF+
INPUT
(VIA MUX)
X+
REF–
TOUCH
SCREEN
Y+
Y–
GND
V
REF
V
CC
Figure 29. Single-Ended Conversion of Touch Screen Inputs
The voltage seen at the input to the ADC in Figure 29 is
YTOTAL
Y
CC
IN
R
R
VV −
×=
(1)
The advantage of the single-ended method is that the touch
screen excitation voltage can be switched off once the signal is
acquired. Because a screen can draw over 1 mA, this is a
significant consideration for a battery-powered system.
The disadvantages of the single-ended method are as follows:
• It can be used only if VCC is close to VREF. If VCC is greater
than VREF, some positions on the screen are outside the
range of the ADC. If VCC is less than VREF, the full range of
the ADC is not used.
• The ratio of VCC to VREF must be known. If VREF and/or VCC
vary relative to one another, this can introduce errors.
• Voltage drops across the switches can introduce errors.
Touch screens can have a total end-to-end resistance
ranging from 200 Ω to 900 Ω. Taking the lowest screen
resistance of 200 Ω and a typical switch resistance of 14 Ω
can reduce the apparent excitation voltage to 200/228 ×
100 = 87% of its actual value. In addition, the voltage drop
across the low-side switch adds to the ADC input voltage.
This introduces an offset into the input voltage, thus, it can
never reach zero.
The single-ended method is adequate for applications that use a
fairly blunt and imprecise instrument for an input device, such
as a finger.
Ratiometric Method
The ratiometric method illustrated in Figure 30 shows the
negative input of the ADC reference tied to Y− and the positive
input connected to Y+. Thus, the screen excitation voltage
provides the reference for the ADC. The input of the ADC is
connected to X+ to determine the Y position.
03796-008
ADC
REF+
INPUT
(VIA MUX)
REF–
VCC
X+
TOUCH
SCREEN
Y+
Y–
GND
Figure 30. Ratiometric Conversion of Touch Screen Inputs
AD7877 Data Sheet
Rev. D | Page 16 of 44
For greater accuracy, the ratiometric method has two significant
advantages:
• The reference to the ADC is provided from the actual
voltage across the screen; therefore, when the voltage drops
across the switches, it has no effect.
• Because the measurement is ratiometric, it does not matter
if the voltage across the screen varies in the long term.
However, it must not change after the signal has been
acquired.
The disadvantage of the ratiometric method is that the screen
must be powered up at all times because it provides the
reference voltage for the ADC.
TOUCH-PRESSURE MEASUREMENT
The pressure applied to the touch screen via a pen or finger can
also be measured with the AD7877 using some simple calcula-
tions. The contact resistance between the X and Y plates is
measured providing a good indication of the size of the
depressed area and, therefore, the applied pressure. The area of
the spot that is touched is proportional to the size of the object
touching it. The size of this resistance (RTOUCH) can be calculated
using two different methods.
First Method
The first method requires the user to know the total resistance
of the X-plate tablet (RX). Three touch screen conversions are
required:
• Measurement of the X position, XPOSITION (Y+ input).
• Measurement of the Y− input with the excitation voltage
applied to Y+ and X− (Z1 measurement).
• Measurement of the X+ input with the excitation voltage
applied to Y+ and X− (Z2 measurement).
These three measurements are illustrated in Figure 31.
The AD7877 has two special ADC channel settings that
configure the X and Y switches for Z1 and Z2 measurement and
store the results in the Z1 and Z2 results registers. The Z1
measurement is ADC Channel 1010b, and the result is stored in
the register with Read Address 11010b. The Z2 measurement is
ADC Channel 0010b, and the result is stored in the register with
Read Address 10010b.
The touch resistance can then be calculated using the following
equation:
RTOUCH = (RXPlate) × (XPOSITION /4096 × [Z2/Z1) − 1] (2)
03796-009
Y–
Y+
X–
X+
TOUCH
RESISTANCE
MEASURE
Z1 POSITION
X–
X+
Y–
Y+
TOUCH
RESISTANCE
MEASURE
X POSITION
Y–
Y+
X–
X+
TOUCH
RESISTANCE
MEASURE
Z2 POSITION
Figure 31. Three Measurements Required for Touch Pressure
Second Method
The second method requires the user to know the resistance of
the X-plate and Y-plate tablets. Three touch screen conversions
are required, a measurement of the X position (XPOSITION),
Y position (YPOSITION), and Z1 position.
The following equation also calculates the touch resistance:
RTOUCH = RXPlate × (XPOSITION /4096) × [(4096/Z1) − 1]
− RYPlate × [1 − (YPOSITION/4096)] (3)
STOPACQ PIN
As previously explained in the Touch Screen Principles section,
touch screens are composed of two resistive layers, normally
placed over an LCD screen. Because these layers are in close
proximity to the LCD screen, noise can be coupled from the
screen onto these resistive layers, causing errors in the touch
screen positional measurements.
For example, a jitter might be noticeable in the cursor on-screen.
In most LCD touch screen systems, a signal, such as an LCD
invert signal or other control signal, is present, and noise is
usually coupled onto the touch screen during the active period
of this signal (see Figure 32).
03796-010
LCD SIGNAL
TOUCH SCREEN
SIGNAL NOISY
PERIOD NOISY
PERIOD
Figure 32. Effect of LCD Noise on Touch Screen Measurements
Data Sheet AD7877
Rev. D | Page 17 of 44
It is only during the sample or acquisition phase of the ADC
operation of the AD7877 that noise from the LCD screen has an
effect on the ADC measurements. During the hold or
conversion phase, the noise has no effect, because the voltage at
the input of the ADC has already been acquired. Therefore, to
minimize the effect of noise on the touch screen measurements,
the ADC acquisition phase should be halted.
The LCD control signal should be applied to the STOPACQ pin.
To ensure that acquisition never occurs during the noisy period
when the LCD signal is active, the AD7877 monitors this signal.
No acquisitions take place when the control signal is active. Any
acquisition that is in progress when the signal becomes active is
aborted and restarts when the signal becomes inactive again.
To accommodate signals of different polarities on the
STOPACQ pin, a user-programmable register bit is used to
indicate whether the signal is active high or low. The POL bit
is Bit 3 in Control Register 2, Address 0x02. Setting POL to 1
indicates that the signal on STOPACQ is active high; setting
POL to 0 indicates that it is active low. POL defaults to 0 on
power-up. To disable monitoring of STOPACQ, the pin should
be tied low if POL = 1, or tied high if POL = 0. Under no
circumstances should the pin be left floating.
The signal on STOPACQ has no effect while the ADC is in
conversion mode, or during the first conversion delay time.
(See the Control Registers section for details on the first
conversion delay.)
When enabled, the STOPACQ monitoring function is imple-
mented on all input channels to the ADC: AUX1, AUX2, BAT1,
BAT2, TEMP1, and TEMP2, as well as on the touch screen
input channels.
TEMPERATURE MEASUREMENT
Two temperature measurement options are available on the
AD7877: the single conversion method and the differential
conversion method. The single conversion method requires
only a single measurement on ADC Channel 1000b. Whereas
differential conversion requires two measurements, one on
ADC Channel 1000b and a second on ADC Channel 1001b.
The results are stored in the results registers with Address 11000b
(TEMP1) and Address 11001b (TEMP2). The AD7877 does not
provide an explicit output of the temperature reading; the
system must perform some external calculations. Both methods
are based on an on-chip diode measurement.
Single Conversion Method
The single conversion method makes use of the fact that the
temperature coefficient of a silicon diode is approximately
−2.1 mV/°C. However, this small change is superimposed on
the diode forward voltage, which can have a wide tolerance. It
is, therefore, necessary to calibrate by measuring the diode
voltage at a known temperature to provide a baseline from
which the change in forward voltage with temperature can be
measured. This method provides a resolution of approximately
0.3°C and a predicted accuracy of ±2.5°C.
The temperature limit comparison is performed on the result in
the TEMP1 results register, which is simply the measurement of
the diode forward voltage. The values programmed into the high
and low limits should be referenced to the calibrated diode for-
ward voltage to make accurate limit comparisons. An example
is shown in the Limit Comparison section.
Differential Conversion Method
The differential conversion method is a 2-point measurement.
The first measurement is performed with a fixed bias current
into a diode (when the TEMP1 channel is selected), and the
second measurement is performed with a fixed multiple of the
bias current into the same diode (when the TEMP2 channel is
selected). The voltage difference in the diode readings is pro-
portional to absolute temperature and is given by the following
formula:
∆VBE = (kT/q) × (ln N) (4)
where:
VBE represents the diode voltage.
N is the bias current multiple (typical value for AD7877 = 120).
k is Boltzmann’s constant.
q is the electron charge.
This method provides a resolution of approximately 1.6°C, and
a guaranteed accuracy of ±4°C without calibration. Determina-
tion of the N value on a part-by-part basis improves accuracy.
Assuming a current multiple of 120, which is a typical value
for the AD7877, taking Boltzmann’s constant, k = 1.38054 ×
10−23 electrons V/°K, the electron charge q = 1.602189 × 10−19,
then T, the ambient temperature in Kelvin, would be calculated
as follows:
∆VBE = (kT/q) × (ln N)
T°k = (∆VBE × q)/(k × ln N)
= (∆VBE × 1.602189 × 10−19)/(1.38054 × 10−23 × 4.65)
T°C = 2.49 × 120 × ∆VBE − 273
∆VBE is calculated from the difference in readings from the first
conversion to the second conversion. The user must perform
the calculations to get ∆VBE, and then calculate the temperature
value in degrees. Figure 33 shows a block diagram of the
temperature measurement circuit.
03796-011
TEMP1 TEMP2
MUX ADC
I
V
BE
I20 × I
Figure 33. Block Diagram of Temperature Measurement Circuit
AD7877 Data Sheet
Rev. D | Page 18 of 44
Temperature Calculations
If an explicit temperature reading in °C is required, then this is
calculated as follows for the single measurement method:
1. Calculate the scale factor of the ADC in degrees per LSB:
Degrees per LSB = ADC LSB size/−2.1 mV =
(VREF/4096)/−2.1 mV
2. Save the ADC output, DCAL, at the calibration
temperature, TCAL.
3. Take ADC reading, DAMB, at the temperature to be
measured, TAMB.
4. Calculate the difference in degrees between TCAL and TAMB
using
∆T = (DAMB − DCAL) × degrees per LSB
5. Add ∆T to TCAL
Example:
The internal 2.5 V reference is used.
1. Degrees per LSB = (2.5/4096)/−2.1 × 10−3 = −0.291
2. The ADC output is 983 decimal at 25°C, equivalent to a
diode forward voltage of 0.6 V.
3. The ADC output at TAMB is 880.
4. ∆T = (880 − 983) × −0.291 = 30°
5. TAMB = 25 + 30 = 55°C
To calculate the temperature explicitly using the differential
method:
1. Calculate the LSB size of the ADC in V:
LSB = VREF/4096
2. Subtract TEMP1 from TEMP2 and multiply by LSB size to
get ∆VBE.
3. Multiply by 2490 and subtract 273 to obtain the
temperature in °C.
Example:
The internal 2.5 V reference is used.
1. LSB size = 2.5 V/4096 = 6.1 × 10−4 V(610 µV)
2. TEMP1 = 880 and TEMP2 = 1103:
∆VBE = (1103 − 880) × 6.1× 10−4 = 0.136 V
3. T = 0.136 × 2490 − 273 = 65°C
BATTERY MEASUREMENT
The AD7877 can monitor battery voltages from 0.5 V to 5 V on
two inputs, BAT1 and BAT2. Figure 34 shows a block diagram
of a battery voltage monitored through the BAT1 pin. The
voltage to the VCC pin of the AD7877 is maintained at the
desired supply voltage via the dc/dc regulator while the input
to the regulator is monitored. This voltage on BAT1 is divided
down by 2 internally, so that a 5 V battery voltage is presented
to the ADC as 2.5 V. To conserve power, the divider circuit is on
only during the sampling of a voltage on BAT1. The BAT2 input
circuitry is identical.
The BAT1 input is ADC Channel 0110b and the result is stored
in Register 10110b. The BAT2 input is ADC Channel 0111b and
the result is stored in Register 10111b.
03796-012
ADC
0.25V–2.5V
SW
BAT1 V
CC
V
REF
5kΩ
5kΩ
DC-DC
CONVERTER
BATTERY
0.5V TO 5V
Figure 34. Block Diagram of Battery Measurement Circuit
Figure 34 shows the ADC using the internal reference of 2.5 V.
The maximum battery voltage that the AD7877 can measure
changes when a different reference voltage is used. The maxi-
mum voltage that is measurable is VREF × 2, because this voltage
gives a full-scale output from the ADC. If a smaller reference is
used, such as 2 V, then the maximum measurable battery voltage
is 4 V. If a larger reference is used, such as 3.5 V, then the maxi-
mum measurable battery voltage is 7 V. The internal reference is
particularly suited for use when measuring lithium-ion batteries,
wherein the minimum voltage is about 2.7 V and the maximum
voltage is about 4.2 V. A proper choice of external reference
ensures that other voltage ranges can be accommodated.
Data Sheet AD7877
Rev. D | Page 19 of 44
AUXILIARY INPUTS
The AD7877 has three auxiliary analog inputs, AUX1 to AUX3.
These channels have a full-scale input range from 0 V to VREF.
The ADC channel addresses for AUX1 to AUX3 are 0011b,
0100b, and 0101b, and the results are stored in Register 10011b,
Register 10100b, and Register 10101b. These pins can also be
reconfigured as general-purpose logic inputs/outputs, as
described in the GPIO Configuration section.
LIMIT COMPARISON
The AUX1 measurement, the two battery measurements, and
the TEMP1 measurement can all be compared with high and
low limits, and an out-of-limit result that generates an alarm
output at the ALERT pin. The limits are stored in registers with
addresses from 00100b to 01011b. After a measurement from
any one of the four channels is converted, it is compared with
the corresponding high and low limits. An out-of-limit result
sets one of the status bits in the alert status/enable register. For
details on these and other registers, see the Register Maps and
Detailed Register Descriptions sections. For details on writing
and reading data, see the Serial Interface section.
As described in the Single Conversion Method section, the
temperature comparison is made using the result of the TEMP1
measurement, that is, the diode forward voltage. Because the
temperature coefficient of the diode is known but the actual
forward voltage can have a wide tolerance, it is not possible
to program the high and low limit registers with predeter-
mined values.
Instead, it is necessary to calibrate the temperature measure-
ment, calculate the TEMP1 readings at the high and low limit
temperatures, and then program those values into the limit
registers, as follows:
1. Calculate
LSB per degree = −2.1 mV/(VREF/4096).
2. Save the calibration reading DCAL at the calibration
temperature, TCAL.
3. Subtract TCAL from limit temperatures THIGH and TLOW
to get the difference in degrees between the limit
temperatures and the calibration temperature.
4. Multiply this value by LSB per degree to obtain the
value in LSBs.
5. Add these values to the digital value at the calibration
temperature to get the digital high and low limit values.
Example:
The internal 2.5 V reference is used.
1. THIGH = +65°C and TLOW = −10°C.
2. LSB per degree = −2.1 × 10−3/(2.5/4096) = −3.44.
3. DCAL = 983 decimal at 25°C.
4. DHIGH = (65 − 25) × −3.44 + 983 = 845.
5. DLOW = (−10 − 25) × −3.44 + 983 = 1103.
AD7877 Data Sheet
Rev. D | Page 20 of 44
CONTROL REGISTERS
Control Register 1 contains the ADC channel address, the
SER/DFR bit (to choose single or differential methods of touch
screen measurement), the register read address, and the ADC
mode bits. Control Register 1 should always be the last register
to be programmed prior to starting conversions. Its power-on
default value is 0x00. To change any parameter after conversion
has begun, the part should first be put into Mode 00, the
changes made, and then Control Register 1 reprogrammed,
ensuring that it is always the last register to be programmed
before conversions begin.
03796-013
SER/
DFR
CHNL
ADD
3
CHNL
ADD
2
CHNL
ADD
1
CHNL
ADD
0
RD
ADD
4
RD
ADD
3
RD
ADD
2
RD
ADD
1
RD
ADD
0
ADC
MODE
1
ADC
MODE
0
11 0
Figure 35. Control Register 1
Control Register 2 sets the timer, reference, polarity, first
conversion delay, averaging, and acquisition time. Its power-on
default value is 0x00. See the Detailed Register Descriptions
section for more information on the control registers.
03796-014
AVG
1AVG
0ACQ
1ACQ
0PM
1PM
0FCD
1FCD
0POL REF TMR
1TMR
0
11 0
Figure 36. Control Register 2
CONTROL REGISTER 1
ADC Mode (Control Register 1, Bits[1:0])
These bits select the operating mode of the ADC. The AD7877
has three operating modes. These are selected by writing to the
mode bits in Control Register 1. If the mode bits are 00, no
conversion is performed.
Table 5. Control Registera 1 Mode Selection
MODE1 MODE0 Function
0 0 Do not convert (default)
0 1 Single-channel conversion, AD7877 in
slave mode
1 0 Sequence 0, AD7877 in slave mode
1 1 Sequence 1, AD7877 in master mode
If the mode bits are 01, a single conversion is performed on the
channel selected by writing to the channel bits of Control
Register 1 (Bit 7 to Bit 10). At the end of the conversion, if the
TMR bits in Control Register 2 are set to 00, the mode bits
revert to 00 and the ADC returns to no convert mode until a
new conversion is initiated by the host. Setting the TMR bits to
a value other than 00 causes the conversion to be repeated, as
described in the Timer (Control Register 2, Bits[1:0]) section.
The flowchart in Figure 38 shows how the AD7877 operates in
Mode 01.
The AD7877 can also be programmed to convert a sequence of
selected channels automatically. The two modes for this type of
conversion are slave mode and master mode.
For slave mode operation, the channels to be digitized are
selected by setting the corresponding bits in Sequencer
Register 0. Conversion is initiated by writing 10b to the mode
bits of Control Register 1. The ADC then digitizes the selected
channels and stores the results in the corresponding results
registers. At the end of the conversion, if the TMR bits in
Control Register 2 are set to 00, the mode bits revert to 00 and
the ADC returns to no convert mode until a new conversion is
initiated by the host. Setting the TMR bits to a code other than
00 causes the conversion sequence to be repeated. The
flowchart in Figure 39 shows how the AD7877 operates in
Mode 10.
For master mode operation, the channels to be digitized are
written to Sequencer Register 1. Master mode is then selected
by writing 11 to the mode bits in Control Register 1. In this
mode, the wake-up on touch feature is active, so conversion
does not begin immediately. The AD7877 waits until the screen
is touched before beginning the sequence of conversions. The
ADC then digitizes the selected channels, and the results are
written to the results registers. The AD7877 waits for the screen
to be touched again, or for a timer event if the screen remains
touched, before beginning another sequence of conversions.
The flowchart in Figure 40 shows how the AD7877 operates in
Mode 11.
ADC Channel (Control Register 1, Bits[10:7])
The ADC channel is selected by Bits [10:7] of Control Register 1
(CHADD3 to CHADD0). In addition, the SER/DFR bit, Bit 11,
selects between single-ended and differential conversion. A
complete list of channel addresses is given in Table 6.
For Mode 0 (single-channel) conversion, the channel is selected
by writing the appropriate CHADD3 to CHADD0 code to
Control Register 1.
For sequential channel conversion, channels to be converted are
selected by setting bits corresponding to the channel number in
Sequencer Register 1 for slave mode sequencing or Sequencer
Register 2 for master mode sequencing.
For both single-channel and sequential conversion, normal
(single-ended) conversion is selected by clearing the SER/DFR
bit in Control Register 1. Ratiometric (differential) conversion
is selected by setting the SER/DFR bit.
Data Sheet AD7877
Rev. D | Page 21 of 44
Table 6. Codes for Selecting Input Channel and Normal or Ratiometric Conversion
Channel SER/DFR CHADD(3:0) Analog Input X Switches Y Switches +REF −REF
0 0 0 0 0 0 X+ (Y position) Off On Y+ Y−
1 0 0 0 0 1 Y+ (X position) On Off X+ X−
2 0 0 0 1 0 Y− (Z2) X+ off, X− on Y+ on, Y− off Y+ X−
3 0 0 01 1 AUX1 Off Off VREF GND
4 0 0 1 00 AUX2 Off Off VREF GND
5 0 0 1 0 1 AUX3 Off Off VREF GND
6 0 0 1 1 0 BAT1 Off Off VREF GND
7 0 0 1 1 1 BAT2 Off Off VREF GND
8 0 1 0 0 0 TEMP1 Off Off VREF GND
9
0
1 0 0 1
TEMP2
Off
Off
V
REF
GND
10 0 1 0 1 0 X+ (Z1) X+ OFF, X− ON Y+ on Y− off Y+ X−
- 0 1 0 1 1 Invalid address
-
0
1 1 0 0
Invalid address
- 0 1 1 0 1 Invalid address
- 0 1 1 1 0 Invalid address
- 0 1 1 1 1 Invalid address
0 1 0 0 0 0 X+ (Y position) Off On VREF GND
1 1 0 0 0 1 Y+ (X position) On Off VREF GND
2 1 0 0 1 0 Y− (Z2) X+ off, X− on Y+ on, Y− off VREF GND
3 1 0 0 1 1 AUX1 Off Off VREF GND
4
1
0 1 0 0
AUX2
Off
Off
V
REF
GND
5 1 0 1 0 1 AUX3 Off Off VREF GND
6 1 0 1 1 0 BAT1 Off Off VREF GND
7 1 0 1 1 1 BAT2 Off Off VREF GND
8 1 1 0 0 0 TEMP1 Off Off VREF GND
9 1 1 0 0 1 TEMP2 Off Off VREF GND
10
1
1 0 1 0
X+ (Z1)
X+ off, X− on
Y+ on, Y− off
V
REF
GND
- 1 10 1 1 Invalid address
- 1 1 1 0 0 Invalid address
-
1
1 1 0 1
Invalid address
- 1 1 1 1 0 Invalid address
- 1 1 1 1 1 Invalid address
CONTROL REGISTER 2
Timer (Control Register 2, Bits[1:0])
The TMR bits in Control Register 2 enable the ADC to
repeatedly perform a conversion or conversion sequence either
once only or at intervals of 512 µs, 1.024 ms, or 8.19 ms. In slave
mode, the timer starts as soon as the conversion sequence is
finished. In master mode, the timer starts at the end of a
conversion sequence only if the screen remains touched. If the
touch is released at any stage, then the timer stops and, the next
time the screen is touched, a conversion sequence begins
immediately.
Table 7. Control Register 2 Timer Selection
TMR1 TMR0 Function
0 0 Convert only once (default)
0 1 Every 1024 clocks (512 µs)
1 0 Every 2048 clocks (1.024 ms)
1 1 Every 16,384 clocks (8.19 ms)
Int/Ext Reference (Control Register 2, Bit[2])
If the REF bit in Control Register 2 is 0 (default value), the
internal reference is selected. Buffer any connection made to
VREF while the internal reference is selected (for example, to
supply a reference to other circuits). An external power supply
should not be connected to this pin while REF is equal to 0,
because it might overdrive the internal reference. Because the
internal reference is 2.5 V, it operates only with supply voltages
down to 2.7 V. Below this value, use an external reference.
If the REF bit is 1, the VREF pin becomes an input and the
internal reference is powered down. This overrides any setting
of the PM bits with regard to the reference. An external
reference can then be applied to the REF pin.
AD7877 Data Sheet
Rev. D | Page 22 of 44
STOPACQ Polarity (Control Register 2, Bit[3])
This bit should be set according to the polarity of the signal
applied to the STOPACQ pin. If that signal is active high, that
is, no acquisitions should occur during the high period of the
signal, then the POL bit should be set to 1. If the signal is active
low, then the POL bit should be 0. The default value for POL is 0.
First Conversion Delay (Control Register 2, Bits[5:4])
The first conversion delay (FCD) bits in Control Register 2
program a delay of 500 ns (default), 128 µs, 1.024 ms, or 8.19 ms
before the first conversion, to allow the ADC time to power up.
This delay also occurs before conversion of the X and Y coordi-
nate channels, to allow extra time for screen settling, and after
the last conversion in a sequence, to precharge PENIRQ. If the
signal on the STOPACQ pin is being monitored and goes active
during the FCD, it is ignored until after the FCD period.
Table 8. First Conversion Delay Selection
FCD1 FCD Function
0 0 1 clock delay (500 ns)
0
1
256 clock delays (128 µs)
1 0 2048 clock delays (1.024 ms)
1 1 16,384 clock delays (8.19 ms)
Power Management (Control Register 2, Bits[7:6])
The power management (PM) bits in Control Register 2 allow
the power management features of the ADC to be programmed.
If the PM bits are 00, the ADC is powered down permanently.
This overrides any setting of the mode bits in Control Register 1.
If the PM bits are 01, the ADC and the reference both power
down when the ADC is not converting. If the PM bits are 10,
the ADC and reference are powered up continuously. If the PM
bits are 11, the ADC, but not the reference, powers down when
the ADC is not converting. If the AD7879 is in full power mode
(PM=10), the master sequencer should not be used. PM bits
must be set to 01 or 11 when using the master sequencer.
Table 9. Power Management Selection
PM1 PM0 Function
0 0 Power down continuously (default)
0 1 Power down ADC and reference when
ADC is not converting (powers up with
FCD at start of a conversion)
1
0
Powered up continuously
1 1 Power down ADC when ADC is not
converting (powers up with FCD at start
of conversion)
Acquisition Time (Control Register 2, Bits[9:8])
The ACQ bits in Control Register 2 allow the selection of
acquisition times for the ADC of 2 µs (default), 4 µs, 8 µs, or
16 µs. The user can program the ADC with an acquisition time
suitable for the type of signal being sampled. For example,
signals with large RC time constants can require longer
acquisition times.
Table 10. Acquisition Time Selection
ACQ1 ACQ0 Function
0 0 4 clock periods (2 µs)
0 1 8 clock periods (4 µs)
1 0 16 clock periods (8 µs)
1
1
32 clock periods (16 µs)
Averaging (Control Register 2, Bits[11:10])
Signals from touch screens can be extremely noisy. The AVG
bits in Control Register 2 allow multiple conversions to be
performed on each input channel and averaged to reduce noise.
A single conversion can be selected (no averaging), which is the
default, or 4, 8, or 16 conversions can be averaged. Only the
final averaged result is written into the results register.
Table 11. Averaging Selection
AVG1 AVG0 Function
0 0 ADC performs 1 average per channel
0 1 ADC performs 4 averages per channel
1 0 ADC performs 8 averages per channel
1 1 ADC performs 16 averages per channel
SEQUENCER REGISTERS
There are two sequencer registers on the AD7877. Sequencer
Register 0 controls the measurements performed during a slave
mode sequence. Sequencer Register 1 controls the measure-
ments performed during a master mode sequence.
To include a measurement in a slave mode or master mode
sequence, the relevant bit must be set in Sequencer Register 0 or
Sequencer Register 1. Setting Bit 11 includes a measurement on
ADC Channel 0 in the sequence, which is the Y positional
measurement. Setting Bit 10 includes a measurement on ADC
Channel 1 (X+ measurement), and so on, through Bit 1 for
Channel 10. Figure 37 illustrates the correspondence between
the bits in the sequencer registers and the various measure-
ments. Bit 0 in both sequencer registers is not used. See also the
Detailed Register Descriptions section.
03796-015
Y+ X+ Z2 AUX
1AUX
2AUX
3BAT
1BAT
2TEMP
1TEMP
2Z1 NOT
USED
11 0
Figure 37. Sequencer Register
Data Sheet AD7877
Rev. D | Page 23 of 44
03796-016
LI MI T CO MPARI SON
ST ART F CD TI M E R
UPDAT E ALERT
ENABLE/STATUS
REGISTER
CONVERT
SELECTED CHANNEL
IS FCD
FINISHED?
HOS T PROG RAM S
AD7877 I N M ODE 01
NO
YES
NO
YES
NO
YES
YES
NO
YES
NO
IS AVERAGI NG
FINISHED?
ONCE-ONLY
MODE?
WRITE RESUL T TO
REGISTERS
GO TO MODE 00
ALERT
SOURCE
ENABLED?
IS ACQUISITION
TIME FINISHED?
TIMER
FINISHED?
IS FCD
REQUIRED?
START ACQUISITION TIMER
ST ART T IMER
OUT-OF-LIMIT?
ASSE RT AL E RT
OUTPUT
1
YES
NO
NO YES
YES
NO
1
SEE SEQUENCER REGISTERS SE CTION.
IS STOPACQ
SIGNAL ACT IVE ?
NO
IS STOPACQ
SIGNAL ACT IVE ?
NO
YES
YES
Figure 38. Single Channel Operation
03796-017
YES
NO
ONCE-ONLY
MODE?
GO TO MODE 00
TIMER
FINISHED?
START TIMER
NO
YES
1
SEE SEQUENCER REG ISTERS SECTION.
LI M I T COMP ARISO N
START F CD TI MER
UPDATE ALERT
ENABLE/STATUS
REGISTER
CONVERT
SELE CT E D CHANN EL
IS FCD
FINISHED?
HOST PROGRAMS
AD7877 IN MO DE 10
NO
YES
NO
YES
NO
YES
YES
NO
IS AVERAGING
FINISHED?
WRITE RESULT TO
REGISTERS
ALERT
SOURCE
ENABLED?
IS ACQUISITION
TIME FINISHED?
IS FCD
REQUIRED?
START ACQUISITION TIMER
OUT-OF-LIMIT?
ASSERT ALERT
OUTPUT
1
YES
NO
YES
NO
VALID
SEQ UE NCE 0?
SELECT NEXT
CHANNEL
GO TO MODE 00
LAST CHANNE L
IN SEQUE NCE?
YES
NO
YES
IS S T OPACQ
SIG NAL ACTIVE?
NO
YES
IS STOPACQ
SIGNAL ACTIVE ?
YES
NO
NO
Figure 39. Slave Mode Sequencer Operation
AD7877 Data Sheet
Rev. D | Page 24 of 44
03796-018
YES
NO
ONCE-ONLY
MODE?
TIMER
FINISHED?
START TIMER
NO
YES
1
SEE SEQUENCER REGISTERS SECTION.
LIMIT COMPARISON
START FCD TIMER
UPDATE ALERT
ENABLE/STATUS
REGISTER
CONVERT
SEL E CTED CHAN NE L
IS FCD
FINISHED? NO
YES
NO
YES
NO
YES
YES
NO
IS AVERAGING
FINISHED?
WRITE RESULT TO
REGISTERS
ALERT
SOURCE
ENABLED?
IS ACQUI S ITION
TIME FINISHED?
IS FCD
REQUIRED?
START ACQUISITION TIMER
OUT-OF-LIMIT?
ASSE RT ALERT
OUTPUT
1
YES
NO
YES
NO
VALID
SEQUENCE 1?
SELECT NEXT
CHANNEL
GO TO MODE 00
LAST CHANNEL
IN SEQUENCE?
YES
IS
SCREEN
TOUCHED?
NO
YES
YES
NO
IS STOPACQ
SIGNAL ACT IVE?
IS STOPACQ
SIGNAL ACTI VE?
NO
YES
YES
NO
IS
SCREEN STILL
TOUCHED?
YES
IS
SCREEN STIL L
TOUCHED?
YES
NO
NO
NO
HOST PROGRAMS
AD7877 IN MODE 11
Figure 40. Master Mode Sequencer Operation
INTERRUPTS
Data Available Output (DAV)
The data available output (DAV) indicates that new ADC data
is available in the results registers. While the ADC is idle or is
converting, DAV is high. Once the ADC has finished converting
and new data has been written to the results registers, DAV goes
low. Taking DAV low to read the registers resets DAV to a high
condition. DAV is also reset, if a new conversion is started by
the AD7877 because the timer expired. The host should attempt
to read the results registers only when DAV is low.
03796-019
CS
DAV
AD7877
S
TATUS
IDLE SETUP
BY HOST ADC
CONVERTING NEW DATA
AVAILABLE HOST READS
RESULTS IDLE
t
CONV
Figure 41. Operation of DAV Output
DAV is useful as a host interrupt in master mode. In this mode,
the host can program the AD7877 to automatically perform a
sequence of conversions, and can be interrupted by DAV at the
end of each conversion sequence.
When the on-board timer is programmed to perform automatic
conversions, a limited time is available to the host to read the
results registers before another sequence of conversions begins.
The DAV signal is reset high when the timer expires, and the
host should not access the results registers while DAV is high.
Figure 42 shows the worst-case timings for reading the results
registers after DAV has gone low. The timer is set at a
minimum, and the conversion sequence includes all 11 possible
ADC channels. t1 is the time taken for acquisition and
conversion on one ADC channel. t2 shows the minimum timer
delay, that is, 1024 clock periods. t3 is the time taken to read all
11 result registers. If the host wants to read all 11 registers, then
it must do so before the timer expires. t4 is the maximum time
allowable between DAV going low and the host beginning to
read the results registers. If t4 is exceeded, then all registers
cannot be read before the start of a new conversion, and
incorrect data could be read by the host.
03796-020
DOUT
AD7877
S
TATUS CHANNEL 11
CONVERSION AND
ACQUISITION
TIMER INTERVAL CHNL
1
t
1
t
2
t
3
t
4
CS
DAV
Figure 42. Timing for Reads after DAV Goes Low
Data Sheet AD7877
Rev. D | Page 25 of 44
If fDCLK = 20 MHz (maximum), then tDCLK = 50 ns.
t2 = 512 µs with timer set to 1024 (TMR bits = 01b)
tWRITE = tREAD = 16 CLK period × tDCLK = 800 ns
t3 = maximum time taken to write read address and read
11 registers = 800 ns (write) + [800 ns (read) × 11] = 9.6 µs.
t4MAX = t2 − t3 = 512 µs − 9.6 µs = 502.4 µs
Pen Interrupt (PENIRQ)
The pen interrupt request output (PENIRQ) goes low whenever
the screen is touched. The pen interrupt equivalent output
circuitry is outlined in Figure 43. This is a digital logic output
with an internal pull-up resistor of 50 kΩ, which means it does
not need an external pull-up. The PENIRQ output idles high.
The PENIRQ circuitry is always enabled, except during
conversions.
03796-021
X+
TOUCH
SCREEN
Y+
50kΩ
Y–
X–
PENIRQ
ENABLE
PENIRQ
VCC VCC
Figure 43. PENIRQ Output Equivalent Circuit
When the screen is touched, PENIRQ goes low. This generates
an interrupt request to the host. When the screen touch ends,
and if the ADC is idle, PENIRQ immediately goes high. If the
ADC is converting, PENIRQ goes high once the ADC becomes
idle. The PENIRQ operation for these two conditions is shown
in Figure 44.
03796-022
SCREEN
PENIRQ
ADC
STATUS
TOUCHED NOT
TOUCHED
NOT
TOUCHED
NOT
TOUCHED
NOT
TOUCHED
ADC IDLE
SCREEN
PENIRQ
ADC
STATUS
TOUCHED
ADC IDLE ADC
CONVERTING ADC IDLE
RELEASE NOT
DETECTED
PENIRQ
DETECTS
RELEASE
PENIRQ
DETECTS
RELEASE
PENIRQ
DETECTS
TOUCH
PENIRQ
DETECTS
TOUCH
Figure 44. PENIRQ Operation for ADC Idle and ADC Converting
SYNCRONIZING THE AD7877 TO THE HOST CPU
The two suggested methods for synchronizing the AD7877
to its host CPU are slave mode, in which the mode bits can
be either 01b or 10b, and master mode, in which the mode
bits are 11b.
In slave mode, PENIRQ can be used as an interrupt to the host.
When PENIRQ goes low to indicate that the screen has been
touched, the host is awakened. The host can then program the
AD7877 to begin converting in either Mode 01b or Mode 10b,
and can read the result registers after the conversions are
completed.
In master mode, DAV can also be used as an interrupt to the
host. However, the host should first initialize the AD7877 in
Mode 11b. The host can then go into sleep mode to conserve
power. The wake-up on touch feature of the AD7877 is active in
this mode, therefore, when the screen is touched, the
programmed sequence of conversions begins automatically.
When the DAV signal asserts, the host reads the new data avail-
able in the AD7877 results registers and returns to sleep mode.
This method can significantly reduce the load on the host.
AD7877 Data Sheet
Rev. D | Page 26 of 44
8-BIT DAC
The AD7877 features an on-chip 8-bit DAC for LCD contrast
control. The DAC can be configured for voltage output by
clearing Bit 2 of the DAC register (Address 1110b), or for
current output by setting this bit.
The output voltage range can be set to 0 to VCC/2 by clearing
Bit 0 of the DAC register, or to 0 to VCC by setting this bit. In
current mode, the output range is selectable by an external
resistor, RRNG, connected between the ARNG pin and GND.
This sets the full-scale output current according to the following
equations:
IFS = VCC/(RRNG × 6)
therefore,
RRNG = VCC/(IFS × 6) (5)
In current mode, the DAC sinks current, that is, positive
current flows into ground. The maximum output current is
1000 µA. The DAC is updated by writing to Address 1110b of
the DAC register. The 8 MSBs of the data-word are used for
DAC data.
The most effective way to control LCD contrast with the DAC is
to use it to control the feedback loop of the dc-to-dc converter
that supplies the LCD bias voltage, as shown in Figure 45. The
bias voltage for graphic LCDs is typically in the range of 20 V to
25 V, and the dc-to-dc converter usually has a feedback loop
that attenuates the output voltage and compares it with an
internal reference voltage.
03796-023
DC-DC
CONVERTER
VFB VOUT
TO LCD
8-BIT
DAC
AD7877
ARNG
RRNG1
GND
NOTES:
1RRNG IS RE QUIRE D ONL Y IF DAC IS IN CURRENT M ODE.
2R1 IS REQUIRED ONLY IF DAC IS IN VOLTAGE MODE.
AOUT R12
IOUT R3
R2
COMP
VREF
Figure 45. Using the DAC to Adjust LCD Contrast
The circuit operates as follows. If the DAC is in current mode
when the DAC output is zero, it has no effect on the feedback
loop. Regardless of what the DAC does, the feedback loop
maintains the voltage across R4, VFB, equal to VREF, and the
output voltage, VOUT, is
VREF × (R2 + R3)/R3
As the DAC output is increased, it increases the feedback current,
so the voltage across R2 and, therefore, the output voltage also
increase. Note that the voltage across R3 does not change. This
is important for calculation of the adjustment range.
In current mode, it is quite easy to calculate the resistor values
to give the required adjustment range in VOUT using the
following steps:
1. Find the required maximum and minimum values of VOUT
from the LCD manufacturer’s data
2. Decide on the current around the feedback loop. For
reasonable accuracy of the output voltage, this current
should be at least 100 times the input bias current of the
dc-to-dc converter’s comparator
3. Calculate R3 using the following equation:
R3 = VFB/IFB = VREF/IFB
4. Calculate R2 for the minimum value of VOUT, when the
DAC has no effect
R2 = R3(VOUT(MIN) − VREF)/VREF
5. Because the voltage across R3 does not change, subtract
VREF from VOUTMAX and VOUTMIN to get the maximum and
minimum voltages across R2
6. Calculate the change in feedback current between
minimum and maximum output voltages
∆I = VR2(MAX)/R2 − VR2(MIN)/R2
This is the required full-scale current of the DAC.
7. Calculate RRNG from Equation 5
Example:
1. VCC = 5 V
VOUT(MIN) is 20 V and VOUT(MAX) is 25 V
VREF is 1.25 V
2. Allow 100 µA around the feedback loop.
3. R3 = 1.25 V/100 µA = 12.5 kΩ
Use the nearest preferred value of 12 kΩ and recalculate
the feedback current as
IFB = 1.25 V/12 kΩ = 104 µA
4. R2 = (20 V − 1.25 V)/104 µA = 180 kΩ
5. ∆I = 23.75 V/180 kΩ − 18.75 V/180 kΩ = 28 µA
6. RRNG = 5 V/(6 × 28 µA) = 30 kΩ
In voltage mode, the circuit operation depends on whether the
maximum output voltage of the DAC exceeds the dc to dc
converter VREF.
Data Sheet AD7877
Rev. D | Page 27 of 44
When the DAC output voltage is zero, it sinks the maximum
current through R1. The feedback current and, therefore, VOUT
are at their maximum. As the DAC output voltage increases, the
sink current and, thus, the feedback current decrease, and VOUT
falls. If the DAC output exceeds VREF, it starts to source current,
and VOUT has to further decrease to compensate. When the
DAC output is at full scale, VOUT is at its minimum.
Note that the effect of the DAC on VOUT is opposite in voltage
mode to that in current mode. In current mode, increasing
DAC code increases the sink current, so VOUT increases with
increasing DAC code. In voltage mode, increasing DAC code
increases the DAC output voltage, reducing the sink current.
Calculate the resistor values as follows:
1. Decide on the feedback current as before.
2. Calculate the parallel combination of R1 and R3 when the
DAC output is zero
RP = VREF/IFB
3. Calculate R2 as before, but use RP and VOUT(MAX)
R2 = RP(VOUT(MAX) − VREF)/VREF
4. Calculate the change in feedback current between
minimum and maximum output voltages as before using
∆I = VR2(MAX)/R2 − VR2(MIN)/R2
This is equal to the change in current through R1 between
zero output and full scale, which is also given by
∆I = current at zero − current at full scale
= V/R1 − (VREF − V)/R1
= V/R1
5. R1 = VFS/∆.
6. Calculate R3 from R1 and R using
R3 = (R1 × RP)/(R1 − RP)
Example:
1. VCC = 5 V and VFS = VCC. VOUT(MIN) is 20 V and VOUT(MAX) is
25 V. VREF is 1.25 V. Allow 100 µA around the feedback loop.
2. RP = 1.25 V/100 µA = 12.5 kΩ.
3. R2 = 12.5 kΩ × (25 Ω − 1.25 Ω)/1.25 Ω = 237 kΩ.
Use the nearest preferred value of 240 kΩ.
4. ∆I = 25 V/240 kΩ − 20 V/240 kΩ = 21 µA.
5. R1 = 5 V/21 µA = 238 kΩ.
Use the nearest preferred value of 250 kΩ.
6. R3 = (180 kΩ × 12.5 kΩ)/(180 kΩ − 12.5 kΩ) = 13.4 kΩ.
Use nearest preferred value of 13 kΩ.
The actual adjustment range using these values is 21 V to 26 V.
AD7877 Data Sheet
Rev. D | Page 28 of 44
SERIAL INTERFACE
The AD7877 is controlled via a 3-wire serial peripheral
interface (SPI). The SPI has a data input pin (DIN) for inputting
data to the device, a data output pin (DOUT) for reading data
back from the device, and a data clock pin (DCLK) for clocking
data into and out of the device. A chip-select pin (CS) enables
or disables the serial interface.
WRITING DATA
Data is written to the AD7877 in 16-bit words. The first four
bits of the word are the register address that directs the AD7877
to the register to write to. The next 12 bits are data. How the
AD7877 handles the data bits depends on the register address.
Register Address 0000b is a dummy address, which does
nothing. Register Addresses 0010b to Register Address 1110b
are 12-bit registers that perform various functions as described
in the register map.
Register Address 1111b is not a physical register, but enables an
extended writing mode that allows writing to the GPIO
configuration registers. When the register address is 1111b, the
next four bits of the data-word are the address of a GPIO
configuration register and the eight LSBs are the GPIO
configuration data. For details on the configuration of the GPIO
pins, see the General-Purpose I/O Pins section.
Register Address 0001b is a physical register, Control Register 1,
but this is a special register. It contains data for setting up the
ADC channel and operating mode, but Bit 20 to Bit 6 compose
the register address for reading. These define the register that is
read back during the next read operation. Control Register 1
should be the last register in the AD7877 to be programmed
before starting a conversion. The three types of data-words used
for writing are shown in Figure 46.
03796-024
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT DATA-WORD
WADD3 WADD2 WADD1 WADD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WRITING TO A REGISTER
12 BITS DATA4-BIT REGISTER WRITE ADDRESS
1111EADD3 EADD2 EADD1 EADD0 D7 D6 D5 D4 D3 D2 D1 D0
EXTENDED WRITE OPERATION TO GPIO REGISTERS
8 BITS GPIO DATA4-BIT EXTENDED ADDRESS
0000SER/DFR CHADD3 CHADD2 CHADD1 CHADD0 RADD4 RADD3 RADD2 RADD1 RADD0 MODE 1 MODE 0
WRITING TO CONTROL REGISTER 1 TO SET ADC CHANNEL, MODE, AND READ REGISTER ADDRESS
ADC CHANNEL ADDRESS 5-BIT READ REGISTER ADDRESS OPERATING
MODE
EXTENDED WRITE ADDRESS
CONTROL REGISTER 1 ADDRESS
NORMAL (SINGLE-ENDED)/
RATIOMETRIC (DIFFERENTIAL)
CONVERSION
Figure 46. Designation of Data-Word Bits in AD7877 Write Operations
03796-025
DCLK
DOUT
1
DIN
2
CS
NOTES:
1
DATA IS CLOCKED OUT ON THE FALLING EDGE OF DCLK.
2
INPUT DATA IS SAMPLED ON THE RISING EDGE OF DCLK.
3
FOR 8-BIT REGISTERS, 8 LEADING ZEROS PRECEDE 8 BITS OF DATA.
4
REGISTER READ ADDRESS INCREMENTS AUTOMATICALLY, PROVIDED THAT A NEW ADDRESS IS NOT WRITTEN TO CONTROL REGISTER 1.
HIGH-Z HIGH-Z
1 16 1 16
REGISTER n + 1 DATA
4
REGISTER n DATA
4
0000 + 12-BIT DATA
3
0000 + 12-BIT DATA
3
4-BIT ADDRESS + 12-BIT DATA
D15 D0
D15 D0 D15 D0
Figure 47. Overall Read/Write Timing
Data Sheet AD7877
Rev. D | Page 29 of 44
WRITE TIMING
No serial interface operations can take place when CS is high.
To write to the AD7877, CS must be taken low. To write to the
device, a burst of 16 clock pulses is input to DCLK while the write
data is input to DIN. Data is clocked in on the rising edge of
DCLK. If multiple write operations are to be performed, CS must
be taken high after the end of each write operation before another
write operation can be performed by taking CS low again.
READING DATA
Data is available on the DOUT pin following the falling edge of
CS, when the device is being clocked. The MSB is clocked out
on the falling edge of CS, with subsequent data bits clocked out
on the falling edge of DCLK.
After CS is taken low and the device is clocked, the AD7877
outputs data from the register whose read address is currently
stored in Control Register 1. Once this data has been output,
the address increments automatically. CS must be taken high
between reads. When CS is taken low again, reading continues
from the register whose read address is in Control Register 1,
provided that a write operation does not change the address. If
the register read address reaches 11111b, it is then reset to zero.
This feature allows all registers to be read out in sequence with-
out having to explicitly write all their addresses to the device.
Note that because data-words are 16 bits long, but the data
registers are only 12 bits long, or 8 bits in the case of GPIO
registers, the first four bits of a readback data-word are zeros, or
the first 8 bits in the case of a GPIO register.
VDRIVE PIN
The supply voltage to all pins associated with the serial interface
(DAV , DIN, DOUT, DCLK, CS, PENIRQ, and ALERT) is
separate from the main VCC supply and is connected to the
VDRIVE pin. This allows the AD7877 to be connected directly to
processors whose supply voltage is less than the minimum
operating voltage of the AD7877, in fact, as low as 1.7 V.
AD7877 Data Sheet
Rev. D | Page 30 of 44
GENERAL-PURPOSE I/O PINS
The AD7877 has one dedicated general-purpose logic input/
output pin (GPIO4), and any or all of the three auxiliary analog
inputs can also be reconfigured as GPIOs. Associated with the
GPIOs are two 8-bit control registers and one 8-bit data register
that are accessed using the extended write mode.
As described in the Reading Data section, GPIO registers are
written to using the extended writing mode. The first four bits
of the data-word must be 1111b to access the extended writing
map, and the next four bits are the GPIO register address. This
leaves 8 bits for the GPIO register data, because all GPIO
registers are 8 bits.
The GPIO control registers are located at the 0000b and 0001b
extended writing map addresses, and the GPIO data register is
at Address 0010b. GPIO registers are read in the same way as
other registers, by writing a 5-bit address to Control Register 1.
The GPIO registers are located at Read Addresses 11011b to
Read Address 11101b.
GPIO CONFIGURATION
Each GPIO pin is configured by four bits in one of the GPIO
control registers and has a data bit in the GPIO data register.
The GPIO configuration bits are described in the following
sections and in Table 12. Also see the Detailed Register
Descriptions section.
Enable (EN)
These bits enable or disable the GPIO pins. When EN = 0, the
corresponding GPIO pin is configured as the alternate function
(AUX input). The other GPIO configuration bits have no effect,
if the particular GPIO is not enabled. When EN = 1, the pin is
configured as a GPIO pin. GPIO4, which does not have an
alternate function, does not have an EN bit; it is always enabled.
Direction—DIR
These bits set the direction of the GPIO pins. When DIR = 0,
the pin is an output. Setting or clearing the relevant bit in the
GPIO data register outputs a value on the corresponding GPIO
pin. The output value depends on the POL bit.
When DIR = 1, the pin is an input. An input value on the
relevant GPIO pin sets or clears the corresponding bit in the
GPIO data register, depending on the POL bit. A GPIO data
register bit is read-only when DIR = 1 for that GPIO.
Polarity (POL)
When POL = 0, the GPIO pin is active low. When POL = 1, the
GPIO pin is active high. How this bit affects the GPIO opera-
tion also depends on the DIR bit.
If POL = 1 and DIR = 1, a 1 at the input pin sets the corre-
sponding GPIO data register bit to 1. A 0 at the input pin clears
the corresponding GPIO data bit to 0.
If POL = 1 and DIR = 0, a 1 in the GPIO data register bit puts a
1 on the corresponding GPIO output pin. A 0 in the GPIO data
register bit puts a 0 on the GPIO output pin.
If POL = 0 and DIR = 1, a 1 at the input pin sets the corre-
sponding GPIO data bit to 0. A 0 at the input pin clears the
corresponding GPIO data bit to 1.
If POL = 0 and DIR = 0, a 1 in the GPIO data register bit puts a
0 on the corresponding GPIO output pin. A 0 in the GPIO data
register bit puts a 1 on the GPIO output pin.
ALERT Enable (ALEN)
GPIOs can operate as interrupt sources to trigger the ALERT
output. This is controlled by the ALERT enable (ALEN) bits in
the GPIO configuration registers. When ALEN = 1, the corre-
sponding GPIO can trigger an ALERT. When ALEN = 0, the
corresponding GPIO cannot cause the ALERT output to assert.
ALERT is asserted low if any GPIO data register bit is set when
the GPIO is configured as an input. The GPIO data bit is set if a
1 appears on the GPIO input pin when POL = 1, or if a 0
appears on the GPIO input pin when POL = 0. ALERT is
triggered only when the GPIO is configured as an input, that is,
when DIR = 1. ALERT can never be triggered by a GPIO that is
configured as an output, that is, DIR = 0.
ALERT Output
The ALERT pin is an alarm or interrupt output that goes low if
any one of a number of interrupt sources is asserted. The results
of high and low limit comparisons on the AUX1, BAT1, BAT2,
and TEMP1 channels are interrupt sources. An out-of-limit
comparison sets a status bit in the alert status/mask register
(Address 00011b).There are separate status bits for both the
high and low limits on each channel to indicate which limit was
exceeded. The interrupt sources can be masked out by clearing
the corresponding enable bit in this register. There is one enable
bit per channel.
ALERT is also asserted if an input on a GPIO pin sets a bit in
the GPIO data register, as explained in the ALERT Enable
(ALEN) section. GPIO interrupts can be disabled by clearing
the corresponding ALEN bit in the GPIO control registers.
The interrupt source can be identified by reading the GPIO data
register and the alert status/enable register. ALERT remains
asserted until the source of the interrupt has been masked out
or removed.
Data Sheet AD7877
Rev. D | Page 31 of 44
If the ALERT source is a GPIO, then masking out the interrupt
by clearing the corresponding ALEN bit to 0 or removing the
source of the interrupt on the GPIO pin causes ALERT to go
high again.
If the ALERT source is an out-of-limit measurement, writing a
0 to the corresponding status bit in the alert status/enable
register causes ALERT to go high. However, the status bit is set
to 1 again on the next measurement cycle, if the measurement
remains out of limit. The ALERT source can also be masked by
clearing the relevant bit in the alert status/enable register to 0.
Table 12. GPIO Configuration
EN DIR POL ALEN Data Bit Pin Voltage ALERT
0 X X X X X X
1 0 0 0 0 11 1
1 0 0 0 1 01 1
1 0 0 1 0 11 1
1
0
0
1
1
0
1
1
1 0 1 0 0 01 1
1 0 1 0 1 11 1
1 0 1 1 0 01 1
1 0 1 1 1 11 1
1
1
0
0
12
0
1
1 1 0 0 02 1 1
1 1 0 1 12 0 0
1 1 0 1 02 1 1
1 1 1 0 02 0 1
1 1 1 0 12 1 1
1
1
1
1
0
2
0
1
1 1 1 1 12 1 0
1 A change in the data register causes a change in the output voltage on the pin.
2 A change in input voltage on the pin causes a change in the data register bit.
AD7877 Data Sheet
Rev. D | Page 32 of 44
GROUNDING AND LAYOUT
It is recommended that the ground pins, AGND and DGND, be
shorted together as close as possible to the device itself on the
user’s PCB.
For more information on grounding and layout considerations
for the AD7877, refer to the AN-577 Application Note, Layout
and Grounding Recommendations for Touch Screen Digitizers.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGES
The lands on the chip scale package (CP-32) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. To ensure that the solder joint size is
maximized, center the land on the pad.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, provide a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern to ensure that shorting is avoided.
Using thermal vias on the printed circuit board thermal pad
improves the thermal performance of the package. If vias are
used, incorporate them in the thermal pad at a 1.2 mm pitch
grid. Keep the via diameter between 0.3 mm and 0.33 mm. The
via barrel should be plated with 1 oz. copper to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
03796-026
HOST
NC = NO CONNECT
AD7877
24
NC
21
GPIO4
20
STOPACQ
19
DIN
17
PENIRQ
18
CS
22
ALERT
23
DAV
NC
1
BAT2
2
BAT1
3
AUX3/GPIO3
4
AUX2/GPIO2
5
AUX1/GPIO1
6
V
CC
7
NC
8
NC
32
V
REF
31
AOUT
30
ARNG
29
V
DRIVE
28
DOUT
27
DCLK
26
NC
25
NC
9
X–
10
Y–
11
X+
12
Y+
13
AGND
14
DGND
15
NC
16
INT1
SPI
INTERFACE
INT2
SCLK
MISO
MOSI
PENIRQ
CS
GPIO
HSYNC SIGNAL
FROM LCD
V
CC
R
RNG
0.1µF
DC-DC
CONVERTER
V
IN
OUT
FB
TO LCD
BACKLIGHT
TOUCH
SCREEN
0.1µF
1.0µF–10µF
(OPTIONAL)
VOLTAGE
REGULATOR
TEMPERATURE
MEASUREMENT
DIODE
MAIN
BATTERY
SECONDARY
BATTERY FROM AUDIO
REMOTE CONTROL
FROM
HOTSYNC INPUTS
Figure 48. Typical Application Circuit
Data Sheet AD7877
Rev. D | Page 33 of 44
REGISTER MAPS
Table 13. Write Register Map
Register Address
Binary
WADD3 WADD2 WADD1 WADD0 Hex Register Name
Description
0 0 0 0 0 None Unused; writing to this address has no effect
0 0 0 1 1 Control Register 1 Contains ADC channel address, register read address, and ADC
mode
0
0
1
0
2
Control Register 2
Contains ADC averaging, acquisition time, power management,
first conversion delay, STOPACQ polarity, and reference and timer
settings
0
0
1
1
3
Alert
status/enable
register
Contains status of high/low limit comparisons for TEMP1, BAT1,
BAT2, and AUX1, and enable bits to allow these channels to
become interrupt sources
0
1
0
0
4
AUX1 high limit
User-programmable AUX1 upper limit
0 1 0 1 5 AUX1 low limit User-programmable AUX1 lower limit
0 1 1 0 6 BAT1 high limit User-programmable BAT1 upper limit
0
1
1
1
7
BAT1 low limit
User-programmable BAT1 lower limit
1 0 0 0 8 BAT2 high limit User-programmable BAT2 upper limit
1 0 0 1 9 BAT2 low limit User-programmable BAT2 lower limit
1 0 1 0 A TEMP1 low limit User-programmable TEMP1 lower limit
1 0 1 1 B TEMP1 high limit User-programmable TEMP1 upper limit
1 1 0 0 C Sequencer
Register 0
Contains channel selection data for slave mode (software)
sequencing
1 1 0 1 D Sequencer
Register 1
Contains channel selection data for master mode (hardware)
sequencing
1 1 1 0 E DAC register Contains DAC data and setup information
1 1 1 1 F Extended write Not a physical register; enables writing to extended writing map
Table 14. Extended Writing Map
Register Address
Binary
EADD3
EADD2
EADD1
EADD0
Hex
Register Name
Description
0 0 0 0 0 GPIO Control
Register 1
Contains polarity, direction, enabling, and interrupt enabling
settings for GPIO1 and GPIO2
0 0 0 1 1 GPIO Control
Register 2
Contains polarity, direction, enabling, and interrupt enabling
settings for GPIO3 and GPIO4
0 0 1 0 2 GPIO data Contains GPIO1 to GPIO4 data
AD7877 Data Sheet
Rev. D | Page 34 of 44
Table 15. Read Register Map
Register Address
Binary
RADD4 RADD3 RADD2 RADD1 RADD0 Hex Register Name Description
0
0
0
0
0
00
None
Reads back all zeros
0 0 0 0 1 01 Control Register 1 See Table 13
0 0 0 1 0 02 Control Register 2 See Table 13
0 0 0 1 1 03 Alert status/enable
register
See Table 13
0 0 1 0 0 04 AUX1 high limit See Table 13
0 0 1 0 1 05 AUX1 low limit See Table 13
0 0 1 1 0 06 BAT1 high limit See Table 13
0
0
1
1
1
07
BAT1 low limit
See Table 13
0 1 0 0 0 08 BAT2 high limit See Table 13
0 1 0 0 1 09 BAT2 low limit See Table 13
0
1
0
1
0
0A
TEMP1 low limit
See Table 13
0 1 0 1 1 0B TEMP1 high limit See Table 13
0 1 1 0 0 0C Sequencer Register 0 See Table 13
0
1
1
0
1
0D
Sequencer Register 1
See Table 13
0 1 1 1 0 0E DAC register See Table 13
0 1 1 1 1 0F None Factory use only
1
0
0
0
0
10
X+
Measurement at X+ input for Y position
1 0 0 0 1 11 Y+ Measurement at Y+ input for X position
1 0 0 1 0 12 Y− (Z2) Measurement at Y− input for touch-pressure
calculation Z2
1 0 0 1 1 13 AUX1 Auxiliary Input 1 measurement
1 0 1 0 0 14 AUX2 Auxiliary Input 2 measurement
1 0 1 0 1 15 AUX3 Auxiliary Input 3 measurement
1 0 1 1 0 16 BAT1 Battery Input 1 measurement
1
0
1
1
1
17
BAT2
Battery Input 2 measurement
1 1 0 0 0 18 TEMP1 Single-ended temperature measurement
1 1 0 0 1 19 TEMP2 Differential temperature measurement
1
1
0
1
0
1A
X+ (Z1)
Measurement at X+ input for touch-pressure
calculation Z1
1 1 0 1 1 1B GPIO Control
Register 1
See Table 14
1 1 1 0 0 1C GPIO Control
Register 2
See Table 14
1 1 1 0 1 1D GPIO data See Table 14
1 1 1 1 0 1E None Factory use only
1
1
1
1
1
1F
None
Factory use only
Data Sheet AD7877
Rev. D | Page 35 of 44
DETAILED REGISTER DESCRIPTIONS
Register Name: Control Register 1
Write Address: 0001
Read Address: 00001
Default Value: 0x000
Type: Read/write
Table 16.
Bit Name Read/Write Description
0 MODE0 R/W LSB of ADC mode code
1
MODE1
R/W
MSB of ADC mode code
00 = no conversion
01 = single conversion
10 = conversion sequence (slave mode)
11 = conversion sequence (master mode)
2 RD0 R/W LSB of register read address; to read a register, its address must first be written to Control Register 1
3 RD1 R/W Bit 1 of register read address; to read a register, its address must first be written to Control Register 1
4 RD2 R/W Bit 2 of register read address; to read a register, its address must first be written to Control Register 1
5 RD3 R/W Bit 3 of register read address; to read a register, its address must first be written to Control Register 1
6 RD4 R/W MSB of register read address; to read a register, its address must first be written to Control Register 1
7 CHADD0 R/W LSB of ADC channel address
8 CHADD1 R/W Bit 1 of ADC channel address
9 CHADD2 R/W Bit 2 of ADC channel address
10 CHADD3 R/W MSB of ADC channel address
0000 = X+ input (Y position)
0001 = Y+ input (X position)
0010 = Y− (Z2) input (used for touch-pressure calculation)
0011 = Auxiliary Input 1 (AUX1)
0100 = Auxiliary Input 2 (AUX2)
0101 = Auxiliary Input 3 (AUX3)
0110 = Battery Monitor Input 1 (BAT1)
0111 = Battery Monitor Input 2 (BAT2)
1000 = Temperature Measurement 1 (used for single conversion)
1001 = Temperature Measurement 2 (used for differential measurement method)
1010 = X+ (Z1) input (used for touch-pressure calculation)
11 SER/DFR R/W Selects normal (single-ended) or ratiometric (differential) conversion
0 = ratiometric (differential)
1 = normal (single-ended)
AD7877 Data Sheet
Rev. D | Page 36 of 44
Register Name: Control Register 2
Write Address: 0010
Read Address: 00010
Default Value: 0x000
Type: Read/write
Table 17.
Bit Name Read/Write Description
0 TMR0 R/W LSB of conversion interval timer
1 TMR1 R/W MSB of conversion interval timer
00 = convert only once
01 = every 1024 clock periods (512 µs)
10 = every 2048 clock periods (1.024 ms)
11 = every 16,384 clock periods (8.19 ms)
2 REF R/W Selects internal or external reference
0 = internal reference
1 = external reference
3 POL R/W Indicates polarity of signal on STOPACQ pin
0 = active low
1 = active high
4 FCD0 R/W LSB of first conversion delay
5 FCD1 R/W MSB of first conversion delay
This delay occurs before the first conversion after powering up the ADC, before converting the X and Y
coordinate channels to allow settling, and after the last conversion to allow PENIRQ precharge
00 = 1 clock period delay (500 ns)
01 = 256 clock periods delay (128 µs)
10 = 2048 clock periods delay (1.024 ms)
11 = 16,384 clock periods delay (8.19 ms)
6 PM0 R/W LSB of ADC power management code
7 PM1 R/W MSB of ADC power management code
00 = ADC and reference powered down continuously
For the following codes, regardless of PM bits, the reference is always powered down if the REF bit is 1:
01 = ADC and reference powered down when not converting
10 = ADC and reference powered up continuously (master sequencer does not work if PM = 10)
11 = ADC powered down when not converting, reference powered up
8 ACQ0 R/W LSB of ADC acquisition time
9 ACQ1 R/W MSB of ADC acquisition time
00 = 4 clock periods (2 µs)
01 = 8 clock periods (4 µs)
10 = 16 clock periods (8 µs)
11 = 32 clock periods (16 µs)
10 AVG0 R/W LSB of ADC averaging code
11 AVG1 R/W MSB of ADC averaging code
00 = no averaging (1 conversion per channel)
01 = 4 measurements per channel averaged
10 = 8 measurements per channel averaged
11 = 16 measurements per channel averaged
Data Sheet AD7877
Rev. D | Page 37 of 44
Register Name: Alert Status/Enable Register
Write Address: 0011
Read Address: 00011
Default Value: 0x000
Type: Read/write
Table 18.
Bit Name Read/Write Description
0 AUX1LO R/W When this bit is 1, the AUX1 channel is below its low limit
1 BAT1LO R/W When this bit is 1, the BAT1 channel is below its low limit
2 BAT2LO R/W When this bit is 1, the BAT2 channel is below its low limit
3 TEMP1LO R/W When this bit is 1, the TEMP1 channel is above its low limit
4 AUX1HI R/W When this bit is 1, the AUX1 channel is above its high limit
5 BAT1HI R/W When this bit is 1, the BAT1 channel is above its high limit
6 BAT2HI R/W When this bit is 1, the BAT2 channel is above its high limit
7 TEMP1HI R/W When this bit is 1, the TEMP1 channel is below its high limit
8 AUX1EN R/W Setting this bit enables AUX1 as an interrupt source to the ALERT output
9 BAT1EN R/W Setting this bit enables BAT1 as an interrupt source to the ALERT output
10 BAT2EN R/W Setting this bit enables BAT2 as an interrupt source to the ALERT output
11 TEMP1EN R/W Setting this bit enables TEMP1 as an interrupt source to the ALERT output
Register Name: AUX1 High Limit
Write Address: 0100
Read Address: 00100
Default Value: 0x000
Type: Read/write
This register contains the 12-bit high limit for Auxiliary Input 1.
Register Name: AUX1 Low Limit
Write Address: 0101
Read Address: 00101
Default Value: 0x000
Type: Read/write
This register contains the 12-bit low limit for Auxiliary Input 1.
Register Name: BAT1 High Limit
Write Address: 0110
Read Address: 00110
Default Value: 0x000
Type: Read/write
This register contains the 12-bit high limit for Battery
Monitoring Input 1.
Register Name: BAT1 Low Limit
Write Address: 0111
Read Address: 00111
Default Value: 0x000
Type: Read/write
This register contains the 12-bit low limit for Battery
Monitoring Input 1.
Register Name: BAT2 High Limit
Write Address: 1000
Read Address: 01000
Default Value: 0x000
Type: Read/write
This register contains the 12-bit high limit for Battery
Monitoring Input 2.
AD7877 Data Sheet
Rev. D | Page 38 of 44
Register Name: BAT2 Low Limit
Write Address: 1001
Read Address: 01001
Default Value: 0x000
Type: Read/write
This register contains the 12-bit low limit for Battery
Monitoring Input 2.
Register Name: TEMP1 Low Limit
Write Address: 1010
Read Address: 01010
Default Value: 0x000
Type: Read/write
This register contains the 12-bit low limit for temperature
measurement.
Register Name: TEMP1 High Limit
Write Address: 1011
Read Address: 01011
Default Value: 0x000
Type: Read/write
This register contains the 12-bit high limit for temperature
measurement.
Data Sheet AD7877
Rev. D | Page 39 of 44
Register Name: Sequencer Register 0
Write Address: 1100
Read Address: 01100
Default Value: 0x000
Type: Read/write
Table 19.
Bit Name Read/Write Description
0 Not Used R/W This bit is not used
1 Z1_SS R/W Setting this bit includes the Z1 touch-pressure measurement (X+ input) in a slave mode sequence
2 TEMP2_SS R/W Setting this bit includes a temperature measurement using differential conversion in a slave mode
sequence
3
TEMP1_SS
R/W
Setting this bit includes a temperature measurement using single-ended conversion in a slave mode
sequence
4 BAT2_SS R/W Setting this bit includes measurement of Battery Monitor Input 2 in a slave mode sequence
5 BAT1_SS R/W Setting this bit includes measurement of Battery Monitor Input 1 in a slave mode sequence
6 AUX3_SS R/W Setting this bit includes measurement of Auxiliary Input 3 in a slave mode sequence
7 AUX2_SS R/W Setting this bit includes measurement of Auxiliary Input 2 in a slave mode sequence
8 AUX1_SS R/W Setting this bit includes measurement of Auxiliary Input 1 in a slave mode sequence
9 Z2_SS R/W Setting this bit includes the Z2 touch-pressure measurement (Y− input) in a slave mode sequence
10 XPOS_SS R/W Setting this bit includes measurement of the X position (Y+ input) in a slave mode sequence
11 YPOS_SS R/W Setting this bit includes measurement of the Y position (X+ input) in a slave mode sequence
Register Name: Sequencer Register 1
Write Address: 1101
Read Address: 01101
Default Value: 0x000
Type: Read/write
Table 20.
Bit Name Read/Write
Description
0 Not Used R/W This bit is not used
1 Z1_MS R/W Setting this bit includes the Z1 touch-pressure measurement (X+ input) in a master mode sequence
2
TEMP2_MS
R/W
Setting this bit includes a temperature measurement using differential conversion in a master mode
sequence
3 TEMP1_MS R/W Setting this bit includes a temperature measurement using single-ended conversion in a master mode
sequence
4 BAT2_MS R/W Setting this bit includes measurement of Battery Monitor Input 2 in a master mode sequence
5 BAT1_MS R/W Setting this bit includes measurement of Battery Monitor Input 1 in a master mode sequence
6
AUX3_MS
R/W
Setting this bit includes measurement of Auxiliary Input 3 in a master mode sequence
7 AUX2_MS R/W Setting this bit includes measurement of Auxiliary Input 2 in a master mode sequence
8 AUX1_MS R/W Setting this bit includes measurement of Auxiliary Input 1 in a master mode sequence
9 Z2_MS R/W Setting this bit includes the Z2 touch-pressure measurement (Y− input) in a master mode sequence
10 XPOS_MS R/W Setting this bit includes measurement of the X position (Y+ input) in a master mode sequence
11 YPOS_MS R/W Setting this bit includes measurement of the Y position (X+ input) in a master mode sequence
AD7877 Data Sheet
Rev. D | Page 40 of 44
Register Name: DAC Register
Write Address: 1110
Read Address: 01110
Default Value: 0x008
Type: Read/write
Table 21.
Bit Name Read/Write Description
0 RANGE R/W Output range of the DAC in voltage mode
0 = 0 to VCC/2
1 = 0 to VCC
1 Not Used R/W This bit is not used
2 V/I R/W Voltage output and current output
0 = voltage
1 = current
3 PD R/W DAC power-down
0 = DAC on
1 = DAC powered down
4 DAC0 LSB of DAC data
5 DAC1 Bit 1 of DAC data
6 DAC2 Bit 2 of DAC data
7 DAC3 Bit 3 of DAC data
8 DAC4 Bit 4 of DAC data
9 DAC5 Bit 5 of DAC data
10 DAC6 Bit 6 of DAC data
11 DAC7 MSB of DAC data
Register Name: Y Position
Write Address: N/A
Read Address: 10000
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
the X+ input with Y layer excited (Y position measurement).
Register Name: X Position
Write Address: N/A
Read Address: 10001
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
the Y+ input with X layer excited (X position measurement).
Register Name: Z2
Write Address: N/A
Read Address: 10010
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
the Y− input with excitation voltage applied to Y+ and X− (used
for touch-pressure calculation).
Register Name: AUX1
Write Address: N/A
Read Address: 10011
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
Auxiliary Input 1.
Data Sheet AD7877
Rev. D | Page 41 of 44
Register Name: AUX2
Write Address: N/A
Read Address: 10100
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
Auxiliary Input 2.
Register Name: AUX3
Write Address: N/A
Read Address: 10101
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
Auxiliary Input 3.
Register Name: BAT1
Write Address: N/A
Read Address: 10110
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
Battery Monitor Input 1.
Register Name: BAT2
Write Address: N/A
Read Address: 10111
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of the measurement at
Battery Monitor Input 2.
Register Name: TEMP1
Write Address: N/A
Read Address: 11000
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of a temperature
measurement using single-ended conversion.
Register Name: TEMP2
Write Address: N/A
Read Address: 11001
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of a temperature
measurement using a differential conversion.
Register Name: Z1
Write Address: N/A
Read Address: 11010
Default Value: 0x000
Type: Read only
This register contains the 12-bit result of a measurement at the
X+ input with excitation voltage applied to Y+ and X− (used for
touch-pressure calculation).
AD7877 Data Sheet
Rev. D | Page 42 of 44
GPIO REGISTERS
GPIO registers are written to using an extended 8-bit address.
The first four bits of the data-word are always 1111b to access
the extended writing map. The next four bits are the register
address. This leaves 8 bits for the GPIO data.
GPIO registers are read like all other registers, by writing a 5-bit
address to Control Register 1, then reading DOUT.
See the GPIO Configuration section for information on
configuring the GPIOs.
Register Name: GPIO Control Register 1
Write Address: [1111] 0000
Read Address: 11011
Default Value: 0x000
Type: Read/write
Table 22.
Bit Name Read/Write Description
0 GPIO2_ALEN R/W If this bit is 1, GPIO2 is an interrupt source for the ALERT output; clearing this bit masks out GPIO2
as an interrupt source for the ALERT output
1 GPIO2_DIR R/W This bit sets the direction of GPIO2
0 = output
1 = input
2 GPIO2_POL R/W This bit determines if GPIO2 is active high or low
0 = active low
1 = active high
3 GPIO2_EN R/W This bit selects the function of AUX2/GPIO2
0 = AUX2
1 = GPIO2
4 GPIO1_ALEN R/W If this bit is 1, GPIO1 is an interrupt source for the ALERT output; clearing this bit masks out GPIO1
as an interrupt source for the ALERT output
5 GPIO1_DIR R/W This bit sets the direction of GPIO1
0 = output
1 = input
6 GPIO1_POL R/W This bit determines if GPIO1 is active high or low
0 = active low
1 = active high
7 GPIO1_EN R/W This bit selects the function of AUX1/GPIO1
0 = AUX1
1 = GPIO1
Data Sheet AD7877
Rev. D | Page 43 of 44
Register Name: GPIO Control Register 2
Write Address: [1111] 0001
Read Address: 11100
Default Value: 0x000
Type: Read/write
Table 23.
Bit Name Read/Write Description
0 GPIO4_ALEN R/W If this bit is 1, GPIO4 is an interrupt source for the ALERT output; clearing this bit masks out GPIO3
as an interrupt source for the ALERT output
1 GPIO4_DIR R/W This bit sets the direction of GPIO4
0 = output
1 = input
2 GPIO4_POL R/W This bit determines if GPIO4 is active high or low
0 = active low
1 = active high
3 Not Used This bit is not used
4 GPIO3_ALEN R/W If this bit is 1, GPIO3 is an interrupt source for the ALERT output; clearing this bit masks out GPIO4
as an interrupt source for the ALERT output
5 GPIO3_DIR R/W This bit sets the direction of GPIO3
0 = output
1 = input
6 GPIO3_POL R/W This bit determines if GPIO3 is active high or low
0 = active low
1 = active high
7 GPIO3_EN R/W This bit selects the function of AUX3/GPIO3
0 = AUX3
1 = GPIO3
Register Name: GPIO Data Register
Write Address: [1111] 0010
Read Address: 11101
Default Value: 0x000
Type: Read/write
Table 24.
Bit Name Read/Write Description
0 Not used This bit is not used
1 Not used This bit is not used
2 Not used This bit is not used
3 Not used This bit is not used
4 GPIO4_DAT R/W GPIO4 data bit
5 GPIO3_DAT R/W GPIO3 data bit
6 GPIO2_DAT R/W GPIO2 data bit
7 GPIO1_DAT R/W GPIO1 data bit
AD7877 Data Sheet
Rev. D | Page 44 of 44
OUTLINE DIMENSIONS
3.25
3.10 SQ
2.95
FO R PROP ER CO NNECT I O N O F
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATION AND
FUNCTION DESCRIPTI ONS
SECTION O F THI S DATA SHE ET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
1
32
8
9
25
24
1716
COPLANARITY
0.08
3.50 REF
0.50
BSC
PIN 1
INDICATOR
PIN 1
INDICATOR
0.30
0.25
0.18 0. 2 0 REF
12° M AX 0.80 MAX
0.65 TYP
1.00
0.85
0.80 0.05 MA X
0.02 NOM
S
EATING
PLANE
0.50
0.40
0.30
5.00
BSC SQ
4.75
BSC SQ
0.60 M AX
0.60 M AX
0.25 M I N
05-25-2011-A
TOP VI EW
EXPOSED
PAD
BOT T OM VIEW
Figure 49. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
BALL 1
IDENTIFIER
SEATING
PLANE
0.50
BALL
PITCH
2.605
2.545
2.485
0.650
0.590
0.530
2.825
2.765
2.705
A
1
2345
B
C
D
E
BOTTOM VIEW
(BALL SI DE UP)
TOP VI EW
(BALL S IDE DOW N)
0.280
0.240
0.200
0.240
0.220
0.200
0.360
0.320
0.280
081607- A
Figure 50. 25-Ball Wafer Level Chip Scale Package [WLCSP]
2.5 mm × 2.8 mm Body
(CB-25-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
AD7877ACPZ-REEL −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD7877ACPZ-REEL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD7877ACPZ-500RL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD7877ACBZ-REEL −40°C to +85°C 25-Ball WLCSP CB-25-1
AD7877ACBZ-REEL7 −40°C to +85°C 25-Ball WLCSP CB-25-1
AD7877WACPZ-REEL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
EVAL-AD7877EBZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications
AUTOMOTIVE PRODUCTS
The AD7877WACPZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03796-0-12/11(D)
