KAF-50100 8176 (H) x 6132 (V) Full Frame CCD Image Sensor Description The KAF-50100 Image Sensor is a high performance, 50-megapixel CCD. Based on the TRUESENSE 6.0 micron Full Frame CCD Platform, the sensor features ultra-high resolution, broad dynamic range, and a four-output architecture. A lateral overflow drain suppresses image blooming, while an integrated Pulse Flush Gate clears residual charge on the sensor with a single electrical pulse. A Fast Dump Gate can be used to selectively remove a line of charge to facilitate partial image readout. The sensor also utilizes the TRUESENSE Transparent Gate Electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. The sensor shares a common pin-out and electrical configuration with the KAF-40000 Image Sensor, allowing a single camera design to support both members of this sensor family. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Figure 1. KAF-50100 Full Frame CCD Image Sensor Typical Value Architecture Full Frame CCD (Square Pixels) Total Number of Pixels 8304 (H) x 6220 (V) = 51.6 Mp Number of Effective Pixels 8208 (H) x 6164 (V) = 50.5 Mp Features Number of Active Pixels 8176 (H) x 6132 (V) = 50.1 Mp * TRUESENSE Transparent Gate Electrode Pixel Size 6.0 mm (H) x 6.0 mm (V) Active Image Size 49.1 mm (H) x 36.8 mm (V) 61.3 mm (Diagonal), 645 1.1x Optical Format Aspect Ratio 4:3 Horizontal Outputs 4 Saturation Signal 40.3 ke- Output Sensitivity 31 mV/e- Quantum Efficiency KAF-50100-CAA KAF-50100-AAA KAF-50100-ABA (with Lens) 22%, 22%, 16% (Peak R, G, B) 25% 62% Read Noise (f = 18 MHz) 12.5 e- Dark Signal (T = 60C) 42 pA/cm2 Dark Current Doubling Temperature 5.7C Dynamic Range (f = 18 MHz) 70.2 dB Estimated Linear Dynamic Range (f = 18 MHz) 69.3 dB Charge Transfer Efficiency Horizontal Vertical * * * * for High Sensitivity Ultra-High Resolution Board Dynamic Range Low Noise Architecture Large Active Imaging Area Applications * * * * Digitization Mapping/Aerial Photography Scientific ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. 0.999995 0.999999 Blooming Protection (4 ms Exposure Time) 800X Saturation Exposure Maximum Date Rate 18 MHz Package Ceramic PGA Cover Glass MAR Coated, 2 Sides or Clear Glass NOTE: All Parameters are specified at T = 40C unless otherwise noted. (c) Semiconductor Components Industries, LLC, 2015 December, 2015 - Rev. 4 1 Publication Order Number: KAF-50100/D KAF-50100 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description KAF-50100-ABA-JP-BA Monochrome, Microlens, Enhanced, ESD, Ceramic PGA, Taped-Clear Cover Glass, Standard Grade KAF-50100-ABA-JP-AE Monochrome, Microlens, Enhanced, ESD, Ceramic PGA, Taped-Clear Cover Glass, Engineering Grade KAF-50100-ABA-JR-BA (1) Monochrome, Microlens, Enhanced, ESD, Ceramic PGA, Taped-Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAF-50100-ABA-JR-AE (1) Monochrome, Microlens, Enhanced, ESD, Ceramic PGA, Taped-Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAF-50100-CAA-JD-AA Color (Bayer RGB), No Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAF-50100-CAA-JD-AE Color (Bayer RGB), No Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAF-50100-AAA-JD-BA Monochrome, No Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAF-50100-AAA-JD-AE Monochrome, No Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Engineering Grade Marking Code KAF-50100-ABA Serial Number KAF-50100-ABA Serial Number KAF-50100-CAA Serial Number KAF-50100-AAA Serial Number 1. Not recommended for new designs. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAF-50100 DEVICE DESCRIPTION Architecture 1 Test Row 26 16 V1 V1 4 KAF-50100 8176 (H) x 6132 (V) 6.0 x 6.0 mm Pixels 4 28 16 H1LR OG R 4 Blue + 12 Buffer Pixels 29 Dark Pixels RD L VOUT LB VDD LB PFG FDG LOD 4 (Last VCCD Phase = V2) H1L L OGL RG L VDD LA VOUT LA VSS L VSUB 16 28 4 1 Test Column PFG FDG LOD 1 Test Column V2 V2 1 10 4 1 4 28 16 4088 RD R RG R VDD RA 4088 VOUT RA 16 28 4 1 4 10 1 VSS R VSUB 1 10 4 1 4 28 16 4088 VOUT RB 16 28 4 1 4 10 1 4088 VDD RB H1B L H2 L H1A L H1A R H2R H1B R XG 4152 Pixels/Line/Output NOTE: Showing the filter pattern of the color version. Figure 2. Block Diagram Dark Reference Pixels Surrounding the periphery of the device is a border of light shielded pixels creating a dark region. Within this dark region are light shielded pixels that include 28 leading dark pixels on every line. There are also 29 full dark lines at the start and 26 full dark lines at the end of every frame. Under normal circumstances, these pixels do not respond to light and may be used as a dark reference. The filter description is for the color version only. No filter pattern is provided for the monochrome version. Dummy Pixels Within each horizontal shift register there are 20 leading pixels. These are designated as dummy pixels and should not be used to determine a dark reference level. Image Acquisition CTE Monitor Pixels Two CTE test columns, at the leading end of each output, and one CTE test row are included for manufacturing test purposes. The filter description is for the color version only. No filter pattern is provided for the monochrome version. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs (charge) within the device. These photon-induced electrons are collected locally by the formation of potential wells at each pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel's capacity is reached, excess electrons are discharged into the lateral overflow drain (LOD) to prevent crosstalk or `blooming'. During the integration period, the V1 and V2 register clocks are held at a constant (low) level. Active Buffer Pixels Forming the outer boundary of the effective active pixel region, there are 16 unshielded active buffer pixels between the photoactive area and the dark reference. These pixels are light sensitive but they are not tested for defects and non-uniformities. For the leading 16 active column pixels, the first 4 pixels are covered with blue pigment while the remaining are arranged in a Bayer pattern (R, GR, GB, B). www.onsemi.com 3 KAF-50100 Charge Transport separate FDG pin. Draining is accomplished by first clocking V2 high while V1 is held low. This forces all charge into the V2 phase of the pixel. While V2 is high, PFG (or FDG) may be clocked high to begin draining the signal from the pixel to the LOD. Charge transfer out of the pixel is fully completed only after V2 has been clocked low plus some characteristic time. The integrated charge from each pixel in the Vertical CCD (VCCD) is transported to the output using a two-step process. Each remaining line (row) of charge is first transported from the VCCD to a dual parallel split horizontal register (HCCD) using the V1 and V2 register clocks. The transfer to the HCCD occurs on the falling edge of V2 while H1A is held high. This line of charge may be readout immediately (dual split) or may be passed through a transfer gate (XG) into a second (B) HCCD register while the next line loads into the first (A) HCCD register (dual parallel split). Readout of each line in the HCCD is always split at the middle and, thus, either two or four outputs are used. Left (or right) outputs carry image content from pixels in the left (or right) columns of the VCCD. A separate connection to the last H1 phase (H1L) is provided to improve the transfer speed of charge to the output amplifier. On each falling edge of H1L, a new charge packet is sensed by the output amplifier. Left and right HCCDs are electrically isolated from each other except for the common transfer gate (XG). Horizontal Register Output Structure The output consists of a floating diffusion connected to a three-stage source follower. Charge presented to the floating diffusion (FD) is converted into a voltage and is current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the FD. Once the signal has been sampled by the system electronics, the reset gate (RG) is clocked to remove the signal and FD is reset to the potential applied by reset drain (RD). Increased signal at the floating diffusion reduces the voltage seen at the output pin. To activate the output structure, an off-chip current source must be added to the VOUT pin of the device. See Figure 4. Pulsed Flush Gate/Fast Dump Gate The Pulsed Flush Gate (PFG) feature is used to drain the charge of all pixels prior to exposure. The exception is pixels in the Fast Dump Gate (FDG) row that are drained using the H2 H1 H2 HCCD Charge Transfer HIL VDD OG RG RD Floating Diffusion VOUT VSUB VSS Source Follower #1 Source Follower #2 Source Follower #3 Figure 3. Output Architecture (Each Output) www.onsemi.com 4 KAF-50100 Output Load VDD = +15 V IOUT = |5 mA| 0.1 mF VOUT 2N3904 or Equivalent Buffered Video Output 140 W 1 kW NOTE: Component values may be revised based on operating conditions and other design considerations. Figure 4. Recommended Output Structure Load Diagram www.onsemi.com 5 KAF-50100 Physical Description Pin Description and Device Orientation DIRECTION OF TRANSFER DIRECTION OF TRANSFER To VOUTLA To VOUTRA To VOUTLB To VOUTRB PIN 1 Figure 5. Image Transfer Diagram VSUB FDG V1 V2 LOD 1 2 3 4 5 LOD PFG V1 V2 LOD V2 V1 FDG VSUB 14 15 16 17 18 PFG V2 V1 PFG LOD D D 13 6 C C PFG VSUB VSUB Top View VOUTLA VOUTLB OGL RGL H1LL H1BL XG VSUB VSUB NC H1BR H1LR RGR OGR VOUTRB VOUTRA B B 1 2 3 4 5 6 7 11 12 8 13 14 15 16 17 18 A A VSUB VDDLA VSSL RDL VDDLB H1AL H2L H2R H1AR VDDRB RDR VSSR VDDRA VSUB Notes: 1. Pins with the same name are nominally tied together on the circuit board and have the same operating conditions. In addition, pins labeled with left (`L') and (`R') designations may also be tied together except for VOUT pins. 2. To achieve optimal output signal matching, electrical layout of the PCB should be made as symmetrical as possible relative to the left and right sides of the sensor. Figure 6. Pinout Diagram www.onsemi.com 6 KAF-50100 Table 3. PIN DESCRIPTION Pin Name Substrate C1 LOD Lateral Overflow Drain Output Amplifier Supply, Left A C2 PFG Pulse Flush Gate Output Amplifier Return, Left C3 V1 Vertical Phase 1 Reset Drain, Left C4 V2 Vertical Phase 2 Output Amplifier Supply, Left B C5 PFG Pulse Flush Gate Horizontal Phase 1, A Left C6 VSUB Substrate Horizontal Phase 2, Left C13 VSUB Substrate Horizontal Phase 2, Right C14 PFG Pulse Flush Gate Horizontal Phase 1, A Right C15 V2 Vertical Phase 2 Output Amplifier Supply, Right B C16 V1 Vertical Phase 1 Reset Drain, Right C17 PFG Pulse Flush Gate Output Amplifier Return, Right C18 LOD Lateral Overflow Drain D1 VSUB D2 FDG Fast Dump Gate V1 Vertical Phase 1 Vertical Phase 2 Pin Name Description A1 VSUB A2 VDDLA A3 VSSL A4 RDL A5 VDDLB A6 H1AL A7 H2L A12 H2R A13 H1AR A14 VDDRB A12 RDR A16 VSSR A17 VDDRA Output Amplified Supply, Right A A18 VSUB Substrate Description Substrate B1 VOUTLA Video Output, Left A D3 B2 VOUTLB Video Output, Left B D4 V2 B3 OGL Output Gate, Left D5 LOD Lateral Overflow Drain B4 RGL Reset Gate, Left D14 LOD Lateral Overflow Drain B5 H1LL Horizontal Phase 1, Last Gate, Left D15 V2 Vertical Phase 2 B6 H1BL Horizontal Phase 1, B Left D16 V1 Vertical Phase 1 Fast Dump Gate B7 XG Horizontal Transfer Gate D17 FDG B8 VSUB Substrate D18 VSUB Substrate Substrate NOTE: The leads are on a 0.100 spacing. B11 VSUB B12 NC B13 H1BR Horizontal Phase 1, B Right B14 H1LR Horizontal Phase 1, Last Gate, Right B15 RGR Reset Gate, Right B16 OGR Output Gate, Right B17 VOUTRB Video Output, Right B B18 VOUTRA Video Output, Right A No Connection www.onsemi.com 7 KAF-50100 IMAGING PERFORMANCE Table 4. TYPICAL OPERATIONAL CONDITIONS Description Test Condition - Unless Otherwise Noted Units 1,001 1,754 ms Frame Time (tREADOUT + tINT) Integration Time (tINT) Notes Dual Parallel Split Dual Split Variable Horizontal Clock Frequency 18 MHz Temperature 25 C Operation Room Temperature Nominal Operating Levels Table 5. SPECIFICATIONS Symbol Min. Nom. Max. Units Notes Verification Plan15 Saturation Signal NSAT Ne-SAT Q/V 1,075 - - 1,250 40.3 31 - - - mV ke- mV/e- 1 Die Quantum Efficiency (Color) Red Green Blue QEMAX - - - 22 22 16 - - - Quantum Efficiency (Monochrome) @ 450 nm QEMAX - 25 - Photoresponse Non-Linearity PRNL - 5 10 % 2 Die Photoresponse Non-Uniformity PRNU - 8.5 25 % p-p 3 Die VDARK,READ - 18 30 mV/s 4 Die VDARK,INT - 3 10 mV/s 5 Die DSNU - 1 4 mV p-p 6, 16 Die Dark Signal Doubling Temperature DT - 5.7 - C 4 Design Read Noise NR - 12.5 - e- rms 7 Design Dynamic Range DR - 70.2 - dB 8 Design DRLIN (Est.) - 69.3 - dB RGHueUnif BGHueUnif - - 5 5 12 12 % Horizontal Charge Transfer Efficiency HCTE - 0.999995 - Vertical Charge Transfer Efficiency VCTE - 0.999999 - XAB - 800 DC Offset, Output Amplifier VODC - 7.5 Output Amplifier Bandwidth f-3dB - 220 Description Readout Dark Signal Integration Dark Signal Dark Signal Non-Uniformity Estimated Linear Dynamic Range Red-Green Hue Shift Blue-Green Hue Shift (Color Version) Blooming Protection www.onsemi.com 8 % QE Design % QE Design Design 9 Die 10 Design x Esat 11 Design - V 12 Die - MHz 13 Design Die KAF-50100 Table 5. SPECIFICATIONS (continued) Description Symbol Min. Nom. Max. Units Output Impedance, Amplifier ROUT - 145 - W Reset Feedthrough VRFT - 0.5 - V Notes Verification Plan15 Die 14 Design 1. Increasing output load currents to improve bandwidth will decrease these values. 2. Worst-case deviation (from 15 mV & 90% NSAT min) relative to a linear fit applied between 0 and 65% of VSAT. 3. Difference between the maximum and minimum average signal levels of 168 x 168 blocks within the sensor on a per color basis as a % of average signal level. 4. T = 60C. tINT = 0. Average non-illuminated signal with respect to over-clocked horizontal register signal. 5. T = 60C. Average non-illuminated signal with respect to over-clocked vertical register signal. 6. T = 60C. Absolute difference between the maximum and minimum average signal levels of 168 x 168 blocks within the sensor. 7. rms deviation of horizontal over-clocked pixels measured in the dark. 8. 20Log (Ne-SAT / NR) 9. Gradual variations in hue (red with respect to green pixels and blue with respect to green pixels) in regions of interest (168 x 168 blocks) within the sensor. The specification refers to the largest value of the response difference. 10. Measured per transfer above and below (~70% VSAT min) saturation exposure levels. Typically, no degradation in HCCD CTE is observed up to 18 MHz. 11. XAB is the number of times above the VSAT illumination level that the sensor will bloom by spot size doubling. The spot size is 10% of the imager height. XAB is measured at 4 ms. 12. Video level offset with respect to ground. 13. Last stage only. Assumes 5 pF off-chip load. 14. Amplitude of feed-through in VOUT during RG clocking. 15. A "die" parameter is measured on every sensor during production testing. A "design" parameter is quantified during design verification and not guaranteed by specification. 16. tINT = 1,000 ms www.onsemi.com 9 KAF-50100 TYPICAL PERFORMANCE CURVES KAF-50100 Spectral Response 25 Absolute Quantum Effeciency (%) R 20 G B 15 10 5 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1,000 1,050 1,100 Wavelength (nm) Figure 7. Spectral Response (KAF-50100-CAA Version) KAF-50100 Monochrome Quantum Efficiency 30 Absolute Quantum Effeciency (%) 25 20 15 10 5 0 350 400 450 500 550 600 650 700 750 800 850 900 950 Wavelength (nm) Figure 8. Spectral Response (KAF-50100-AAA Version) www.onsemi.com 10 1,000 1,050 1,100 KAF-50100 KAF-50100-ABA Monochrome with Lens QE 70 Absolute Quantum Effeciency (%) 60 50 40 30 20 10 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1,000 1,050 1,100 Wavelength (nm) Figure 9. Spectral Response (KAF-50100-ABA Version) KAF-50100 Quantum Efficiency GR - GB Difference 1.2 1.0 Absolute GR-GB QE Difference 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 350 400 450 500 550 600 650 700 750 800 850 900 950 1,000 1,050 1,100 Wavelength (nm) Figure 10. Typical GR - GB QE Difference (KAF-50100-CAA Version) www.onsemi.com 11 KAF-50100 KAF-50100 - Typical Angular Response 1 0.9 Normalized Response 0.8 0.7 0.6 0.5 0.4 Vertical 0.3 Horizontal 0.2 Cosine 0.1 0 -40 -20 0 20 40 Incident Light Angle (Deg) Figure 11. Typical Normalized Angle Response (KAF-50100-CAA Version) KAF-50100 Monochrome - Typical Angular Response 1 0.9 Normalized Response 0.8 0.7 0.6 0.5 0.4 Vertical 0.3 Horizontal 0.2 Cosine 0.1 0 -40 -30 -20 -10 0 10 20 30 Incident Light Angle (Deg) Figure 12. Typical Normalized Angle Response (KAF-50100-AAA Version) www.onsemi.com 12 40 KAF-50100 KAF-50100-ABA Monochrome with Lens 1.1 1 0.9 0.7 0.6 0.5 0.4 0.3 0.2 Horizontal 0.1 Vertical 0 -40 -30 -20 -10 0 10 20 30 Incident Light Angle (Deg) Figure 13. Typical Normalized Angle Response (KAF-50100-ABA Version) KAF-50100 Anti-Blooming Performance 6,000 5,000 4,000 XAB Normalized Response 0.8 3,000 2,000 1,000 0 0 5 10 15 20 Integration Time (ms) Figure 14. Typical Anti-Blooming Performance www.onsemi.com 13 25 40 KAF-50100 DEFECT DEFINITIONS Operating Conditions Bright defect tests performed at T = 25C, tINT = 250 ms and tREADOUT = 2,527 ms. Dark defect tests performed at T = 25C, tINT = 1,000 ms and tREADOUT = 2,527 ms. Table 6. SPECIFICATIONS Classification Points Clusters Columns Includes Dead Columns Standard Grade < 4,000 < 50 < 20 Yes A column that deviates by more that 1.5% above or below neighboring columns under illuminated conditions. Point Defects A pixel that deviates by more than 36 mV above neighboring pixels under non-illuminated conditions. A pixel that deviates by more than 7% above or 11% below neighboring pixels under illuminated conditions Column defects are separated by no less than 4 good columns. No multiple column defects (double or more) will be permitted. Cluster Defect A grouping of not more than 10 adjacent point defects. Column and cluster defects are separated by at least 4 good columns in the x direction. Cluster defects are separated by no less than 4 good pixels in any direction. Dead Column A column that deviates by more than 50% below neighboring columns under illuminated conditions. Column Defect A grouping of more than 10 point defects along a single column. Saturated Column A column that deviates by more than 120 mV above neighboring columns under non-illuminated conditions. No saturated columns are allowed. A column that deviates by more that 1.2 mV above neighboring columns under non-illuminated conditions. www.onsemi.com 14 KAF-50100 OPERATION Table 7. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Diode Pin Voltages VDIODE -0.5 20 V 1, 2 Gate Pin Voltages VGATE1 -14.3 14.5 V 1, 3 RG Pin Voltage VRG -0.5 14.5 V 1 Overlapping Gate Voltages V1-2 -14.3 14.5 V 4 Non-Overlapping Gate Voltages Vg-g -14.3 14.5 V 5 Output Bias Current IOUT - -30 mA 6 LOD Diode Voltage VLODT -0.5 13.5 V 1 TOP 0 60 C 7 Operating Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Referenced to pin VSUB. 2. Includes pins: RD, VDD, VSS, VOUT. 3. Includes pins: V1, V2, H1A, H1B, H1L, H2, OG, PFG, FDG, XG. 4. Voltage difference between overlapping gates. Includes: V1 to V2, H1/H1L to H2, H1L to OG, V1 to H2, PFG to V1/V2, FDG to V1/V2, XG to H1A/H1B/H2. 5. Voltage difference between non-overlapping gates. Includes: V1 to H1A/H1B/H1L, V2 to XG, H2 to PFG/FDG, PFG to FDG. 6. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and lower load capacitance at the expense of reduced gain (sensitivity). Operation at these values will reduce MTTF (Mean Time to Failure). 7. Noise performance will degrade at higher temperatures. Power-up Sequence The sequence chosen to perform an initial power-up is not critical for device reliability. A coordinated sequence may minimize noise and the following sequence is recommended: 1. Connect the ground pins (VSUB). 2. Supply the appropriate biases and clocks to the remaining pins. Table 8. DC BIAS OPERATING CONDITIONS Symbol Minimum Nominal Maximum Units Maximum DC Current (mA) Notes Reset Drain VRD 11.3 11.5 11.7 V IRD = 0.01 1 Output Amplifier Return VSS 0.5 0.7 1.0 V ISS = 3.0 1 Output Amplifier Supply VDD 14.5 15.0 15.5 V IOUT + ISS 1 Substrate VSUB - 0 - V 0.01 Output Gate VOG -2.2 -2.0 -1.8 V 0.01 1 Lateral Drain VLOD 9.8 10.0 10.2 V 0.01 1 Video Output Current IOUT - 5 10 mA Description 1. Subscripts (L, R, LA, LB, RA, RB, T, B) have not been included in the symbol list. 2. An output load sink must be applied to VOUT to activate output amplifier - see Figure 4. www.onsemi.com 15 2 KAF-50100 AC Operating Conditions Table 9. CLOCK LEVELS Pin Description for Clocked Signal Symbol Level Min. Nom. Max. Units Effective Capacitance (Note 1) Notes V1 (4 Pins Total) V1L Low -9.2 -9.0 -8.8 V 568 nF 2 V1H High 2.3 2.5 2.7 V 568 nF 2 V2L Low -9.2 -9.0 -8.8 V 645 nF 2 V2H High 3.3 3.5 3.7 V 645 nF 2 V2 (4 Pins Total) H1AL and H1AR H1BL and H1BR H1LL and H1LR H2L and H2R RGL and RGR PFG (2 Pins Total) FDG (2 Pins Total) XG H1L Low -4.2 -4.0 -3.8 V 491 pF 2 H1H High 1.8 2.0 2.2 V 491 pF 2 H1L Low -4.2 -4.0 -3.8 V 541 pF 2 H1H High 1.8 2.0 2.2 V 541 pF 2 H1LLOW Low -6.2 -6.0 -5.8 V 17 pF 2 H1LHIGH High 1.8 2.0 2.2 V 17 pF 2 H2L Low -4.2 -4.0 -3.8 V 1,025 pF 2 H2H High 1.8 2.0 2.2 V 1,025 pF 2 VRGL Low 0.8 1.0 1.2 V 15 pF 2 VRGH High 7.8 8.0 8.2 V 15 pF 2 PFGL Low -9.2 -9.0 -8.8 V 322 nF 2 PFGH High 4.8 5.0 5.2 V 322 nF 2 FDGL Low -9.2 -9.0 -8.8 V 120 pF 2 FDGH High 4.8 5.0 5.2 V 120 pF 2 XGL Low -4.7 -4.5 -4.3 V 265 pF 2 XGH High 2.8 3.0 3.2 V 265 pF 2 1. All pins shown are expected to draw less than 10 mA DC current. Capacitance values relative to SUB (substrate). 2. Pins with the same name are nominally tied together on the circuit board and have the same operating conditions. For pin description entries with more than one pin for this clocked signal, the capacitance value shown is for all pins in the row tied together. www.onsemi.com 16 KAF-50100 TIMING Table 10. REQUIREMENTS AND CHARACTERISTICS Description Symbol Min. Nom. Max. Units Notes H1, H2 Clock Frequency fH - - 18 MHz 1, 2 V1, V2 Clock Frequency fV - - 25 kHz 1, 2 V1-V2 Cross-over VVCR 0 1.0 2.7 V H1-H2 Cross-over VHCR -2.0 -1.0 0 V H1, H2 Setup Time tHS 5 - - ms V2-H1A Delay tD1 5 - - ms H1A-XG Delay tD2 30 - - ms XG-V2 Delay tD3 5 - - ms H1, H2 Rise, Fall Times tH1r, tH1f 5 - 10 % 5, 6 H1L Rise - H2 Fall Cross-over VH1LCR -2.0 -1.0 1.0 V 9 V1, V2 Rise, Fall Times tV1r, tV1f 5 - 10 % 5 RG Clock Pulse Width tRGw 5 - - ns 7 tRGr, tRGf 5 - 10 % 5 tVw 20 - - ms 2, 3, 4 2 RG Rise, Fall Times V1, V2 Clock Pulse Width Pixel Period (1 Count) te 55.56 - - ns H1L-VOUT Delay tHV - 10 - ns RG-VOUT Delay tRV - 5 - ns tREADOUT - DS tREADOUT - DPS 1.71 0.98 - - - - s 8 tF - DS tF - DPS 0.6 1.0 - - - - fps 8 tLINEDS - DS tLINEDP - DPS 275.7 315.7 - - - - ms 8 PFG Holdoff Time tPFG 180 - - ms FDG Holdoff Time tFDG 20 - - ms Readout Time Frame Rate Line Rate 1. 2. 3. 4. 5. 6. 7. 8. 9. 50% duty cycle values. CTE will degrade above the maximum frequency. Longer times will degrade noise performance. Measured where VCLOCK is at 0 V. Relative to the pulse width (based on 50% of high/low levels). The maximum specification or 10 ns whichever is greater based on the frequency of the horizontal clocks. RG should be clocked continuously. DS = Dual Split DPS = Dual Parallel Split. The charge capacity near the output could be degraded if the voltage at the clock crossover point is outside this range. www.onsemi.com 17 KAF-50100 Edge Alignment Horizontal Clock H1AL/H1AR/H1BL/H1BR H2L/H2R VHCR Vertical Clock V2 V1 VVCR Figure 15. Timing Edge Alignment www.onsemi.com 18 KAF-50100 Frame Timing Dual-Parallel Split timing reads pixels out of all four outputs with even lines reading out of VOUTLA and VOUTRA and odd lines reading out of VOUTLB and VOUTRB. Dual split timing reads the pixels out of VOUTLA and VOUTRA. H1B may be grounded in this operating mode. Frame Timing - Dual Split tINT V1 V2 tREADOUT Line 1 2 6219 3 6220 H1A/B/L H2 XG Frame Timing - Dual-Parallel Split tINT V1 V2 tREADOUT Line Pair 1 3 2 3109 3110 H1A XG H1B/L H2 Figure 16. Frame Timing Frame Timing Detail Vertical Clocks V1 V1HIGH 90% tV 10% tV1r V1LOW tV1f V2 90% V2HIGH tV 10% tV2r tV2f Figure 17. Frame Timing Detail www.onsemi.com 19 V2LOW KAF-50100 Line Timing (Each Output) H1A (tD2), and then passed through XG (tD3) and into H1B. During this time, the second, full resolution, row will load into H1A at the second falling edge of V2 following the characteristic delay tHD. XG is held low unless the Dual-Parallel Split timing is required. While operating in Dual-Parallel Split mode, full resolution rows are passed from V2 (tD1), through Line Timing - Dual Split t LINE tV tV t HS V1 V2 H1A/B/L 4152 Counts H2 XG Line Timing - Dual-Parallel Split t LINE tV tV tV t D3 t HS V1 V2 H1A XG t D1 H1B/L t D2 tV 4152 Counts H2 Figure 18. Line Timing www.onsemi.com 20 KAF-50100 Pixel Timing te H1A/B/L H2 RG VOUT Figure 19. Pixel Timing Pixel Timing Detail Reset Clock RGHIGH RGL/RGR 90% tRGw VRG 10% RGLOW tRGr tRGf Horizontal Clocks H1AHIGH/ H1BHIGH/ H2HIGH H1AR/H1BR/H2R/ H1AL/H1BL/H2L 90% 50% te / 2 10% tHr tHf H1LHIGH H1LR/H1LL H1ALOW/ H1BLOW/ H2LOW 90% 50% te / 2 10% tHr tHf Figure 20. Pixel Timing Detail www.onsemi.com 21 H1LLOW KAF-50100 MODE OF OPERATION Power-Up Flush Cycle Pulse Flush Gate Timing The PFG clock resets all pixels in the array (except the FDG row). Charge transfer out of the pixel is fully completed only after V2 has been clocked low as shown. Frame Timing - Pulse Flush Operation tINT tFLUSH tREADOUT V1 V2 tV PFG tPFG Figure 21. Pulse Flush Gate Timing time period (tFDG). The position of the FDG row is illustrated in Figures 23-25, including the timing required for a simple 1 line dump operation. Pixels colored in yellow represent dumped pixels. Fast Dump Gate (FDG) Timing The FDG clock only resets pixels that happen to be in the FDG row. Charge transfer out of the pixel is fully completed only after V2 has been clocked low plus the characteristic Row# 4 3 2 Fast Dump Gate Row 1 Bottom LOD Contact Row HCCD Register A HCCD Register B Figure 22. Fast Line Dump Layout Line Timing - Fast Dump Gate tFDG V1 V2 FDG H1 4152 Counts H2 t0 t1 t2 t3 t4 t5 Figure 23. One Line Dump Timing Example www.onsemi.com 22 KAF-50100 Line Timing - Fast Dump Gate (3 Line Dump) tV tV tFDG V1 V2 FDG H1 4152 Counts H2 Figure 24. Line Dump Timing Example t0 4 VCCD 4 3 FDG LOD 2 1 V2 V1 V2 V1 V2 V1 V2 V1 V2 t1 GR4 B4 GR4 B4 R3 GB3 R3 GB3 GR2 B2 GR2 B2 R1 GB1 R1 GB1 GR4 B4 GR4 B4 R3 GB3 R3 GB3 GR2 R1 B2 GB1 t3 t2 GR2 R1 GR4 B4 GR4 B4 R3 GB3 R3 GB3 GR4 B4 GR4 B4 R3 GB3 R3 GB3 B2 t5 t4 GR4 B4 GR4 B4 R3 GB3 R3 GB3 R1 GB1 R1 GB1 GB1 R1 GB1 R1 B4 GR4 B4 R3 GB3 R3 GB3 R1 GB1 R1 GB1 GB1 R1 V1 V2 HCCD A GB1 R1 GB1 XG HCCD B NOTE: Areas highlighted in yellow represent pixels drained of charge. Figure 25. One Line Dump Pixel Illustration using Color Filter Designation www.onsemi.com 23 GR4 KAF-50100 MECHANICAL DRAWINGS Completed Assembly Notes: 1. Device marking for the monochrome no-lens version is "KAF-50100-AAA". 2. Device marking for the monochrome version with lens is "KAF-50100-ABA". Figure 26. Completed Assembly Drawing Cover Glass Specification - MAR 1. Substrate material Schott D263T eco or equivalent. 2. 10 mm max. scratch/dig specification on the glass. No defect in the glass that exceeds 10 mm in any X-Y dimension. 3. Multilayer anti-reflective coating. Table 11. COVER GLASS SPECIFICATION - MAR Wavelength Total Reflectance 420-450 2% 450-630 1% 630-680 2% Cover Glass Specification - CLEAR 1. Substrate material Schott D263T eco or equivalent. 2. 10 mm max. scratch/dig specification on the glass. No defect in the glass that exceeds 10 mm in any X-Y dimension. www.onsemi.com 24 KAF-50100 Table 12. COVER GLASS SPECIFICATION - CLEAR Wavelength Total Reflectance 420-450 10% 450-630 10% 630-680 10% REFERENCES For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 25 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAF-50100/D