Order Number: 290645, Revision: 022
January 2005
Intel® Advanced+ Boot Block Flash
Memory (C3)
28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16)
Datasheet
Product Features
The Intel® Advanced+ Book Block Flash Memory (C3) device, manufactured on Intel’s latest
0.13 µm and 0.18 µm technologies, represents a feature-rich solution for low-power
applications. The C3 device incorporates low-voltage capability (3 V read, program, and erase)
with high-speed, low-power operation. Flexible block locking allows any block to be
independently locked or unlocked. Add to this the Intel® Flash Data Integrator (Intel® FDI)
software and you have a cost-effective, flexible, monolithic code plus data storage solution.
Intel® Advanced+ Boot Block Flash Memory (C3) products are available in 48-lead TSOP, 48-
ball CSP, and 64-ball Easy BGA packages. Additional information on this product family can be
obtained from the Intel® Flash website: http://www.intel.com/design/flash.
■Flexible SmartVoltage Technology
—2.7 V– 3.6 V read/program/erase
—12 V for fast production programming
■1.65 V to 2.5 V or 2.7 V to 3.6 V I/O
Option
—Reduc es overa ll system power
■High Performance
—2.7 V– 3.6 V: 70 ns max access time
■Optimized Architecture for Code Plus
Data Storage
—Eight 4 Kword blocks, top or bottom
parameter boot
—Up to 127 x 32 Kword blocks
—Fast program suspend capability
—Fast erase suspend capability
■Flexible Block Locking
—Lock/unlock any block
—Full protection on power-up
—Write Protect(WP#) pin for hardware
block protection
■Low Power Consumption
—9 mA typical read
—7 uA typical standby with Automatic
Power Savings feature
■Extended Temperature Operation
—-40 °C to +85 °C
■128-bit Protection Register
—64 bit unique device identifier
—64 bit user programmable OTP cells
■Extended Cycling Capability
—Minimum 100,000 block erase cycles
■Software
—Intel® Flash Data Integrator
—Supports top or bottom boot storage,
streaming data (for example, voice)
—Intel Basic Command Set
—Common Flash Interface
■Standard Surface Mount Packaging
—48-Ball µBGA*/VFBGA
—64-Ball Easy BGA packages
—48-TSOP package
■ETOX™ VIII (0.13 µm) Flash
Technology
—8, 16, 32 Mbit
■ETOX™ VII (0.18 µm) Flash Technology
—16, 32, 64 Mbit
■ETOX™ VI (0.25 µm) Flash Technology
—8, 16 and 32 Mbit
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
2 Order Number: 290645, Revision: 022
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Copyright © 2005, Intel Corporation. All Rights Reserved.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 3
Contents
1.0 Introduction....................................................................................................................................7
1.1 Nomenclature .......................................................................................................................7
1.2 Conventions..........................................................................................................................7
2.0 Functional Overview .....................................................................................................................8
2.1 Product Overview .................................................................................................................8
2.2 Block Diagram ......................................................................................................................9
2.3 Memory Map.........................................................................................................................9
3.0 Package Information ...................................................................................................................12
3.1 mBGA* and VF BGA Package............................................................................................12
3.2 TSOP Package.............. .......... ................................ ........... ................................ ................13
3.3 Easy BGA Package............................................................................................................14
4.0 Ballout and Signal Descriptions ................................................................................................15
4.1 48-Lead TSOP Package.....................................................................................................15
4.2 64-Ball Easy BGA Package................................................................................................18
4.3 Signal Descriptions.............................................................................................................18
5.0 Maximum Ratings and Operating Conditions...........................................................................20
5.1 Absolute Maximum Ratings................................................................................................20
5.2 Operating Conditions..........................................................................................................20
6.0 Electrical Specifications.............................................................................................................22
6.1 Current Characteristics.......................................................................................................22
6.2 DC Voltage Characteristics.................................................................................................24
7.0 AC Characteristics ......................................................................................................................25
7.1 AC Read Characteristics ......... ................................ ................................ ........... ................25
7.2 AC Write Characteristic s................................ ................................ ................................ .....29
7.3 Erase and Program Timings...............................................................................................33
7.4 AC I/O Test Conditions.......................................................................................................33
7.5 Device Capacitance............................................................................................................34
8.0 Power and Reset Specifications ................................................................................................35
8.1 Active Power (Program/Erase/Read)....................... ........... ................................ ........... .....35
8.2 Automatic Power Savings (APS) ........................................................................................35
8.3 Standby Power ...................................................................................................................35
8.4 Deep Power-Down Mode....................................................................................................35
8.5 Power and Reset Considerations .......................................................................................36
8.5.1 Power-Up/Down Characteristics............................................................................36
8.5.2 RP# Connected to System Reset..........................................................................36
8.5.3 VCC, VPP and RP# Transitions ............................................................................36
8.5.4 Reset Specifications..............................................................................................37
8.6 Power Supply Decoupling...................................................................................................37
9.0 Device Operations.......................................................................................................................39
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
4 Order Number: 290645, Revision: 022
9.1 Bus Operations...... ........... .......... ................................ ........... ................................ .............39
9.1.1 Read......................................................................................................................39
9.1.2 Write ......................................................................................................................39
9.1.3 Output Disable.......................................................................................................39
9.1.4 Standby..................................................................................................................40
9.1.5 Reset .....................................................................................................................40
10.0 Modes of Operation.....................................................................................................................41
10.1 Read Mode............ ........... .......... ........... ................................ ................................ ...... .......41
10.1.1 Read Array................................ ........... .......... ........... ................................ .............41
10.1.2 Read Identifier .......................... ........... .......... ................................ ........... .............41
10.1.3 CFI Query..............................................................................................................42
10.1.4 Read Status Register........................... ................................ ................................ ..42
10.1.4.1 Clear Status Register.............................................................................43
10.2 Program Mode.................. .......... ........... ................................ ........... ..................................43
10.2.1 12-Volt Production Programming...........................................................................43
10.2.2 Suspending and Resuming Program.....................................................................44
10.3 Erase Mode ........................................................................................................................44
10.3.1 Suspending and Resuming Erase.........................................................................45
11.0 Security Modes............................................................................................................................49
11.1 Flexible Block Locking........................................................................................................49
11.1.1 Locking Operation................................ .......... ........... ........... ................................ ..50
11.1.1.1 Locked State..........................................................................................50
11.1.1.2 Unlocked State.......................................................................................50
11.1.1.3 Lock-Down State....................................................................................50
11.2 Reading Block-Lock Status.................................................................................................50
11.3 Locking Operations during Erase Suspend........................................................................51
11.4 Status Register Error Checking..........................................................................................51
11.5 128-Bit Protection Register.................................................................................................51
11.5.1 Reading the Protection Register............................................................................52
11.5.2 Programming the Protection Register....................................................................52
11.5.3 Locking the Protection Register.............................................................................52
11.6 VPP Program and Erase Voltages......................................................................................52
11.6.1 Program Protection.............................. .......... ........... ................................ .............53
Appendix A Write State Machine States.............................................................................................54
Appendix B Flow Charts......................................................................................................................56
Appendix C Common Fla sh Interface.................................................................................................62
Appendix D Additional Information ....................................................................................................70
Appendix E Ordering Information.......................................................................................................71
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 5
Revision History
Date of
Revision Version Description
05/12/98 -001 Original version
07/21/98 -002
48- Lead TSOP package diagram change
µBGA package diagrams change
32- M bit ordering inform ation change (Section 6)
CFI Query Structure Output Table Change (Table C2)
CFI Pr imary-Vendor Specific Extended Query Table Change for Optional Features and
Command Support change (Table C8)
Protection Register Address Change
IPPD test cond itions clarification (Section 4.3)
µBGA package top side mark information clarification (Section 6)
10/03/98 -003
Byte-Wide Pr otection Register Address change
VIH Specification change (Section 4.3)
VIL Maximum Specification change (Section 4.3)
ICCS test conditions clarific ation (Section 4.3)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from 3 Volt Adv anced Boot Block, 8-, 16-, 32-Mbit Flash Memor y
Family.
12/04/98 -004 Added tBHWH/tBHEH and tQVBL (Section 4.6)
Programming the Protection Register clarification (Section 3.4.2)
12/31/98 -005 Removed all references to x8 configurations
02/24/99 -006 Removed reference to 40-Lead TSOP from front page
06/10/99 -007
Add ed Easy BGA package (S ection 1.2)
Rem ov e d 1.8 V I/O refe r e n ce s
Locking Operations Flowchart changed (Appendix B)
Add ed tWHGL (Section 4.6)
CFI Primary Vendor -Specific Extended Query changed (Appen dix C)
03/20/00 -008 Max ICCD changed to 25 µA
Table 10, added note indicatin g VCCMax = 3.3 V for 32-Mbit device
04/24/00 -009 Added specifications for 0.18 micron produ ct offerings throughout document Adde d 64-
Mbit density
10/12/00 -010
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
Changed VccMax=3.3V refere nce to indicate that the affected product is the 0.25µm
32M b it de v ic e .
Minor text edits throughout document.
7/20/01 -011
Add ed 1.8v I/ O op eration documentation where applica ble
Added TSOP PCN ‘Pin-1’ indicator information
Changed references i n 8 x 8 BGA pinout diagra m s from ‘GND’ to ‘Vssq’
Added ‘Vssq’ to Pin Descriptions Inform ation
Rem ov ed 0.4 µm r ef er e n c es in D C ch aracte r i st ic s table
Corr ected 64Mb package Ordering Information from 48 -uBGA to 48-VFBGA
Corr ected ‘bottom’ para meter block sizes to on 8Mb device to 8 x 4KWo rds
Minor text edi ts throughout document
10/02/01 -012 Added specifications for 0.13 micron product offer ings throughout documen t
2/05/02 -013 Corrected Iccw / Ippw / Icces /Ippes values.
Added mechanicals for 16Mb and 64Mb
Minor text edits throughout document.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
6 Order Number: 290645, Revision: 022
4/05/02 -014
Updated 64Mb product offerings.
Updated 16Mb product offerings.
Revised and corrected DC Characteristics Table.
Adde d mech anic als for Easy BGA.
Minor text edits throughout document.
3/06/03 -016 Complete technical update.
10/01/03 -017 Corrected inf ormati on in the Device Geom etry Details table, address 0x34.
5/20/04 -018 Updated the layou t of the datasheet.
9/1/04 -019 Fixed typo for Standby power on cover page.
9/14/04 -020 Added lead-free line items to Tabl e 37 “Prod uc t In fo rm ation O rd er i ng Ma tri x ” on pag e 72.
9/27/04 -021 Added specification for 8Mb 0.13 micron device.
Added 0.13 micron to Table 37 “Product Information Ordering Matrix” on page 72.
1/26/05 -022 Conver ted datasheet to new te mplate. Deleted Description in Table 4. Deleted No te in
Figure 5.
Date of
Revision Version Description
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 7
1.0 Introduction
This datasheet contains the specifications for the Intel® Advanced+ Boot Block Flash Memory
(C3) device family, hereafter called the C3 flash memory device. These flash memories add
features such as instant block locking and protection registers that can be used to enhance the
security of systems.
1.1 Nomenclature
0x Hexadecimal prefix
0b Binary prefix
Byte 8 bits
Word 16 bits
KW or Kword 1024 words
Mword 1,048,576 words
Kb 1024 bits
KB 1024 bytes
Mb 1,048,576 bits
MB 1,048,576 bytes
APS Automatic Power Savings
CSP Chip Scale Package
CUI Command User Interface
OTP One Time Programmable
PR Protection Register
PRD Protection Register Data
PLR Protection Lock Register
RFU Reserved for Future Use
SR Status Register
SRD Status Register Data
WSM Write State Machine
1.2 Conventions
The terms pin and signal are often used interchangeably to refer to the external signal connections
on the package; for chip scale package (CSP) the term ball is used.
Group Membership Brackets: Square brackets will be used to designate group membership or to
define a group of signals with similar function (i.e. A[21:1], SR[4:1])
Set: When referring to registers, the term set means the bit is a logical 1.
Clear: When referring to registers, the term clear means the bit is a logical 0.
Block: A group of bits (or words) that erase simultaneously with one block erase instruction.
Main Block: A block that contains 32 Kwords.
Pa ra me te r Bl o ck: A block that contains 4 Kwords.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
8 Order Number: 290645, Revision: 022
2.0 Functional Overview
This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device
features and architecture.
2.1 Product Overview
The C3 flash memory device provides high-performance asynchronous reads in package-
compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally
sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at
either the top or bottom of the device’ s memory map. The rest of the memory array is grouped into
32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase
and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC and VPP can be tied
together for a simple, ultra-low-power design. In addition to I/O voltage flexibility, the dedicated
VPP input provides complete data protection when VPP ≤ VPPLK.
The Intel® Advanced+ Boot Block Flash Memory (C3) device features a 128-bit protection
register enabling security techniques and data protection schemes through a combination of
factory-programmed and user-programmable OTP data registers. Zero-latency locking/unlocking
on any memory block provides instant and complete protection for critical system code and data.
Additional block lock-down capability provides hardware protection where software commands
alone cannot change the block’s protection status.
A com mand Us er Int erfa ce (CU I) serv es as the inte rfac e betw een th e sys tem pro cess or and inter nal
operation of the device. A valid command sequence issued to the CUI initiates device automation.
An internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS), standby
mode, and deep power-down mode. The device automatically enters APS mode following read
cycle completion. Standby mode begins when the system deselects the flash memory by
deasserting Chip Enable, CE#. The deep power-down mode begins when Reset Deep Power-
Down, RP# is asserted, which deselects the memory and places the outputs in a high-impedance
state, producing ultra-low power savings. Combined, these three power-savings features
significantly enhanced power consumption flexibility.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 9
2.2 Block Diagram
2.3 Memory Map
The Intel® Advanced+ Boot Block Flash Memory (C3) device is asymmetrically blocked, which
enables system code and data integration within a single flash device. The bulk of the array is
divided into 32 Kword main blocks that can store code or data, and 4 Kword boot blocks to
facilitate storage of boot code or for frequently changing small parameters. See Table 1, “Top Boot
Memory Map” on page 10 and Table 2, “Bottom Boot Memory Map” on page 11 for details.
Figure 1. C3 Flash Memory Device Block Diagram
Output
M ultiplexer
4-KWord
Parameter Blo c k
32-KWord
Main Block
32-KWord
Main Block
4-KWord
Parameter Blo c k
Y-Gating/Sensing Write Stat e
Machine Program/Erase
Volt age Swit ch
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Power
Reduction
Control
Input Buffer
Output Buffer
GND
V
CC
V
PP
CE#
WE#
OE#
RP#
Command
User
Interface
Input Buffer
DQ
0
-DQ
15
V
CCQ
WP#
A[MAX:MIN]
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
10 Order Number: 290645, Revision: 022
Table 1. Top Boot Memory Map
Size
(KW) Blk 8-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 16-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 32-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 64-Mbit Memory
Addressing (Hex)
422 7F000-
7FFFF 4 38 FF000-FFFFF 470 1FF000-
1FFFFF 4 134 3FF000-3FFFFF
421 7E000-
7EFFF 4 37 FE000-FEFFF 469 1FE000-
1FEFFF 4 133 3FE000-3FEFFF
420 7D000-
7DFFF 4 36 FD000-FDFFF 4681FD000-
1FDFFF 4 132 3FD000-3FDFFF
419 7C000-
7CFFF 4 35 FC000-FCFFF 4671FC000-
1FCFFF 4 131 3FC000-3FCFFF
418 7B000-
7BFFF 4 34 FB000-FBFFF 466 1FB000-
1FBFFF 4 130 3FB000-3FBFFF
417 7A000-
7AFFF 4 33 FA000-FAFFF 465 1FA000-
1FAFFF 4 129 3FA000-3FAFFF
4 16 79000-79FFF 4 32 F9000-F9FFF 464 1F9000-
1F9FFF 4 128 3F9000-3F9FFF
4 15 78000-78FFF 4 31 F8000-F8FFF 463 1F8000-
1F8FFF 4 127 3F8000-3F8FFF
32 14 70000-77FFF 32 30 F0000-F7FFF 32 62 1F0000-
1F7FFF 32 126 3F0000-3F7FFF
32 13 68000-6FFFF 32 29 E8000-EFFFF 32 61 1E8000-
1EFFFF 32 125 3E8000-3EFFFF
32 12 60000-67FFF 32 28 E0000-E7FFF 32 60 1E0000-
1E7FFF 32 124 3E0000-3E7FFF
32 11 58000-5FFFF 32 27 D8000-DFFFF 32 59 1D8000-
1DFFFF 32 123 3D8000-3DFFFF
... ... ... ... ... ... ... ... ... ... ... ...
32 2 10000-17FFF 32 2 10000-17FFF 32 2 10000-17FFF 32 2 10000-17FFF
32 1 8000-0FFFF 32 1 08000-0FFFF 32 1 08000-0FFFF 32 1 08000-0FFFF
32 0 0000-07FFF 32 0 00000-07FFF 32 0 00000-07FFF 32 0 00000-07FFF
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 11
Table 2. Bottom Boot Memory Map
Size
(KW) Blk 8-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 16-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 32-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 64-Mbit Memory
Addressing (Hex)
32 22 78000-7FFFF 32 38 F8000-FFFFF 32 70 1F8000-1FFFFF 32 134 3F8000-3FFFFF
32 21 70000-77FFF 32 37 F0000-F7FFF 32 69 1F0000-1F7FFF 32 133 3F0000-3F7FFF
32 20 68000-6FFFF 32 36 E8000-EFFFF 32 68 1E8000-1EFFFF 32 132 3E8000-3EFFFF
32 19 60000-67FFF 32 35 E0000-E7FFF 32 67 1E0000-1E7FFF 32 131 3E0000-3E7FFF
... ... ... ... ... ... ... ... ... .... ...
32 10 18000-1FFFF 32 10 18000-1FFFF 32 10 18000-1FFFF 32 10 18000-1FFFF
32 9 10000-17FFF 32 9 10000-17FFF 32 9 10000-17FFF 32 9 10000-17FFF
32 8 08000-0FFFF 32 8 08000-0FFFF 32 8 08000-0FFFF 32 8 08000-0FFFF
4 7 07000-07FFF 4 7 07000-07FFF 4 7 07000-07FFF 4 7 07000-07FFF
4 6 06000-06FFF 4 6 06000-06FFF 4 6 06000-06FFF 4 6 06000-06FFF
4 5 05000-05FFF 4 5 05000-05FFF 4 5 05000-05FFF 4 5 05000-05FFF
4 4 04000-04FFF 4 4 04000-04FFF 4 4 04000-04FFF 4 4 04000-04FFF
4 3 03000-03FFF 4 3 03000-03FFF 4 3 03000-03FFF 4 3 03000-03FFF
4 2 02000-02FFF 4 2 02000-02FFF 4 2 02000-02FFF 4 2 02000-02FFF
4 1 01000-01FFF 4 1 01000-01FFF 4 1 01000-01FFF 4 1 01000-01FFF
4 0 00000-00FFF 4 0 00000-00FFF 4 0 00000-00FFF 4 0 00000-00FFF
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
12 Order Number: 290645, Revision: 022
3.0 Package Informat ion
3.1 µBGA* and VF BGA Package
Figure 2. µBGA* and VF BGA Package Drawing and Dimensions
Bottom View -Bump side up
e
b
S1
Ball A1
Corner
Top View - Bump Side down
Ball A1
Corner
E
D
Side View
A
A2
A
1
Seating
Y
A
B
C
D
E
F
S2
Plan
123
4
5678
A
B
C
D
E
F
123
4
5678
Note: Drawing not to scale
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
Package Height A 1.000 0.0394
Ball Height A1 0.150 0.0059
Package Body Thickness A2 0.665 0.0262
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length 8M (.25) D 7.810 7.910 8.010
Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13) D 7.186 7.286 7.386 0.2829 0.2868 0.2908
Package Body Length 64M (.18) D 7.600 7.700 7.800 0.2992 0.3031 0.3071
Package Body Wi dth 8M (.25) E 6.400 6.500 6.600 0.2520 0.2559 0.2598
Package Body Wi dth 16M (.25/.18/.13) 32M (.18/.13) E 6.864 6.964 7.064 0.2702 0.2742 0.2781
Package Body Wi dth 32M (.25) E 10.750 10.850 10.860 0.4232 0.4272 0.4276
Package Body Wi dth 64M (.18) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.750 0.0295
Ball (Lead) Count 8M, 16M N 46 46
Ball (Lead) Count 32M N 47 47
Ball (Lead) Count 64M N 48 48
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along D 8M (.25) S1 1.230 1.330 1.430 0.0484 0.0524 0.0563
Corner to Ball A1 Distance Along D 16M (.25/.18/.13) 32M (.18/.13) S1 0.918 1.018 1.118 0.0361 0.0401 0.0440
Corner to Ball A1 Distance Along D 64M (.18) S1 1.125 1.225 1.325 0.0443 0.0482 0.0522
Corner to Ball A1 Distance Along E 8M (.25) S2 1.275 1.375 1.475 0.0502 0.0541 0.0581
Corner to Ball A1 Distance Along E 16M (.25/.18/.13) 32M (.18/.13) S2 1.507 1.607 1.707 0.0593 0.0633 0.0672
Corner to Ball A1 Distance Along E 32M (.25) S2 3.450 3.550 3.650 0.1358 0.1398 0.1437
Corner to Ball A1 Distance Along E 64M (.18) S2 2.525 2.625 2.725 0.0994 0.1033 0.1073
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 13
3.2 TSOP Package
Notes:
1. One dimple on packag e denotes P in 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pi n 1 will always be in the upper l eft corner of the package, in referenc e to the pr oduct mar k .
Figure 3. TSOP Package Drawing and Dimensions
Dimensions
A5568-02
A
0
L
Detail A
Y
D
C
Z
Pin 1
E
D
1
b
Detail B
S ee Det ail A
e
See Det ail B
A
1
A
2
Seating
Plane
S ee Not es 1, 2, 3 and 4
Family: Thin Small Out-Li n e Pa ckage
Symbol Millimeters Inches
Min Nom Max Notes Min Nom Max Notes
Pac k ag e H eig ht A 1. 200 0. 04 7
Standoff A1 0.050 0.002
Pack age Bo dy Thi ckn ess A2 0.950 1.0 00 1 . 0 50 0. 03 7 0.0 39 0 .041
Lead W idt h b 0.150 0.200 0.300 0. 006 0.008 0. 012
Lead T hic k ness c 0. 100 0. 150 0.200 0. 004 0.006 0.008
Pla stic Bod y Lengt h D1 1 8. 200 18. 400 18. 600 0. 717 0 . 724 0.732
Pack age Bo dy W i dth E 11.800 12.0 00 12 . 2 00 0.465 0 . 472 0. 48 0
Lead Pit ch e 0.500 0.0197
T er m i nal D i m e nsion D 19.80 0 20.0 00 20 . 2 00 0.780 0.787 0 .79 5
Lead T ip Length L 0. 500 0.600 0. 700 0. 020 0.024 0. 028
Lead C ount N 48 48
Lead T i p A ng le Ø 0° 3° 5° 0° 3° 5 °
Seat in g Plan e C oplan arit y Y 0 . 100 0. 004
Lead t o Pac k age Off s et Z 0.150 0.250 0.350 0. 006 0.010 0. 014
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
14 Order Number: 290645, Revision: 022
3.3 Easy BGA Package
Figure 4. Easy BGA Package Drawing and Dimension
Millimeters Inches
Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.200 0.0472
Ball Height A10.250 0.0098
Pac kage Body T hickness A20.780 0.0307
Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209
Pac kage Body Width D 9.900 10 .000 10.100 1 0.3898 0.3937 0.3976
Pac kage Body Length E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157
Pitch [e] 1.000 0.0394
Ball ( Lea d) Count N 64 64
Seating Plane Coplanarity Y 0.100 0.0039
Cor ner to Ball A1 Distance Along D S11.400 1.500 1.600 1 0.0551 0.0591 0.0630
Cor ner to Ball A1 Distance Along E S22.900 3.000 3.100 1 0.1142 0.1181 0.1220
Dimensions Table
Note: (1) Package dimensions are for reference only . These dimensions are estimates based
on di e size , and are sub
j
ect to chan
g
e.
E
Seating
Plane
S1
S2
e
Top View - Ball side down Bottom View - Ball Side Up
Y
A
A1
D
Ball A1
Corner
A2
Note: Drawing not to scale
A
B
C
D
E
F
G
H
8765432187654321
A
B
C
D
E
F
G
H
b
Ball A1
Corner
Side Vie w
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 15
4.0 Ballout and Signal Descriptions
The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball µBGA, and Easy BGA
packages. See Figure 5 on page 15, Figure 7 on page 17, and Figure 8 on page 18, respectively.
4.1 48-Lead TSOP Package
Figure 5. 48-Lead TSOP Package
Advanced+ Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
16
V
CCQ
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
21
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
21
22
23
24
OE#
GND
CE#
A
0
28
27
26
25
A
4
A
3
A
2
A
1
32 M
16 M
64 M
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
16 Order Number: 290645, Revision: 022
Figure 6. Mark for Pin-1 Indicator on 48-Lead 8-Mb, 16-M b and 32-Mb TS OP
Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel® Advanced and Advanced + Boot Block
48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the
white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in
package size, materials, functionality, customer handling, or manufacturability. Product will
continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes
shown in Table 3.
Table 3. 48-Lead TSOP
Extended 64 Mbit Exte nded 32 Mbit Extended 16 Mbit Extended
TE28F640C3TC80
TE28F640C3BC80 TE28F320C3TD70
TE28F320C3BD70 TE28F160C3TD70
TE28F160C3BD70 TE28F800C3TA90
TE28F800C3BA90
TE28F320C3TC70
TE28F320C3BC70 TE28F160C3TC80
TE28F160C3BC80 TE28F800C3TA110
TE28F800C3BA110
TE28F320C3TC90
TE28F320C3BC90 TE28F160C3TA90
TE28F160C3BA90
TE28F320C3TA100
TE28F320C3BA100 TE28F160C3TA110
TE28F160C3BA110
TE28F320C3T A110
TE28F320C3BA110
Current Mark:
New Mark:
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 17
Notes:
1. Shaded connections ind icate the up gr ade addr ess connections. Intel recomme nds to not use r outing in
this ar ea.
2. A19 denotes 16 Mb it ; A 20 denotes 32 M bit; A21 de not es 64 Mbit.
3. Unused address balls are no t po pulated.
Figure 7. 48-Ball µBGA* and 48-Ball VF BGA Chip Scale Package (Top View, Ball Down)1,2,3
13254768
A
B
C
D
E
F
A13
A14
A15
A16
VCCQ
A11
A10
A12
D14
D15
A8
WE#
A9
D5
D6
VPP
RP#
A21
D11
D12
WP#
A18
A20
D2
D3
A19
A17
A6
D8
D9
A7
A5
A3
CE#
D0
A4
A2
A1
A0
GND
GND D7 D13 D4 VCC D10 D1 OE#
16M
32M64M
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
18 Order Number: 290645, Revision: 022
4.2 64-Ball Easy BGA Package
Figure 8. 64-Ball Easy BGA Package1,2
Notes:
1.A19 denotes 16 M bit; A20 de not es 32 Mbit; A21 denotes 64 Mbit.
2. U n used addre ss ball s are no t po pulated .
4.3 Signal Descriptions
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
Top View
- Ball Side Bottom View - Ball Side
A
1 A
6 A
18 V
PP V
CC GND A10 A
15
A
2 A
17 A
19
(1) RP# DU A
20
(1) A11 A
14
A
3 A
7 WP# WE# DU A
21
(1) A12 A
13
A
4 A
5 DU
DQ
8 DQ
1 DQ
9 DQ
3 DQ
12 DQ
6 DU DU
CE# DQ
0 DQ
10 DQ
11 DQ
5 DQ14 DU DU
A
0 V
SSQ DQ
2 DQ
4 DQ
13 DQ15 VSSQ A
16
A
22
(2) OE# V
CCQ V
CC V
SSQ DQ
7 V
CCQ DU
DU DU DU A8 A9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
A
15 A
10 GND VCC V
PP A
18 A6A1
A
14 A
11 A
20(1) DU RP# A19
(1) A
17 A2
A
13 A
12 A
21(1) DU WE# WP# A7A3
A9A
8 DU
DU DU DQ
6DQ
12 DQ
3 DQ
9DQ1DQ8
DU DU DQ
14 DQ
5 DQ11 DQ
10 DQ
0 CE#
A
16 VSSQ D
15 D13 DQ
4 DQ
2V
SSQ A0
DU V
CCQ D
7 V
SSQ VCC V
CCQ OE# A22
(2)
DU DU DU A
5 A4
Table 4. Signal Descriptions
Symbol Type Description
A[MAX:0] Input
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
8 Mbi t: AMAX= A1 8
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
DQ[15:0] Input/
Output
DATA INP UTS/OUT PU T S: Inputs data and commands during a write cycle; outputs data during read
cycle s. Inp ut s comman ds t o the Comman d U ser Interface w hen CE# and WE# ar e active. Dat a is
inter nal ly latched. The dat a pi ns float to tri- st ate when t he chip is de-se lected or the outputs are
disabled.
CE# Input CHIP ENABLE: Acti ve-low inp ut. Activ ates the inter nal cont rol logic, inp ut buff ers, decoder s and sense
ampli fiers . CE# is activ e low. CE# high de-se lect s the memory dev ice and r educ es p ower c ons umpt ion
to sta ndby levels.
OE# Input OUTPUT ENABLE: Acti ve- low input. E nables the device’s outputs through the data buffers dur ing a
Read operation .
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 19
RP# Input
RESET/DEEP POWER-DOWN: Ac tive-low input .
When RP# is at logi c lo w, the de vice is in reset/ deep power -d own mode, which drive s th e outputs t o
High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
When RP# is at logic high, t he device is in standard operation. When RP# transitio ns from logi c- low to
logic-high, the devi ce r esets all blocks to locked and default s t o th e r ead array mode .
WE# Input WRITE ENABLE: Active-lo w input. W E# control s writes to t he device. Address an d data a re latch ed on
the rising edge o f t he WE # pulse.
WP# Input
WRITE PROTECT: Active-low input.
Whe n WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot
be unlocked through software.
Whe n WP# is logic high, the lock-d own mech anism is disabl ed and blo cks prev iousl y locked -dow n are
now locked and ca n be unlocked and locked thr ough software. After WP# go es lo w, any blo cks
previously ma rk ed lock-dow n r evert to the loc k- dow n state.
See Section 11.0, “Se cur it y Mo des” on page 49 for detai ls on block locki ng.
VPP Input/
Power
PROGRA M /ER ASE Power Supp ly : Operates as an input at logi c le vels to control complete device
protection. Supplies power for accelerate d Program and Erase operations in 12 V ± 5% range. Do not
leave this pin floating.
Lower VPP ≤ VPP LK to protect all conten t s against Program and Erase comman ds.
Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can
drop as low as 1.65 V to allow fo r resistor or diode drop from th e system supply.
Apply VPP to 12 V ± 5 % f or faster pr ogra m a nd er ase in a pr oduc tion en vironm ent . A pplyi ng 12 V ± 5%
to VPP can only be do ne f or a maxi mum of 1000 cycles on the main bl ocks and 2500 cy cles on the
boot blocks. V PP can be connected to 12 V for a to t al of 80 hou r s m aximum. See Section 11.6 for
details on VP P vol t age conf ig ur ations.
VCC Power DEVICE CORE Power Supply: Supplies power for device ope ra tions.
VCCQ Power OUTPU T Po wer Su pply: Output-d riven sourc e vol tage. This ball can be tied direct l y to VCC if
operat ing withi n VCC range.
GND Power Ground: For all internal circuitry. All ground inputs must be connected.
DU — Do Not Use: Do not us e th is ball. This bal l must not be connected to any po we r supplies, sig nal s or
other balls,; it must be left floating.
NC — No Connect
Table 4. Signal Descriptions
Symbol Type Description
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
20 Order Number: 290645, Revision: 022
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These ratings are stress ratings only. Operation beyond the “Operating Conditions” is not
recommended, and extended exposure beyond the “Operating Conditions” may affect device
reliability.
.
5.2 Operating Conditions
NOTICE: Specifications are subject to change without notice. V erify with your local Intel Sales office that you have the latest
datasheet before finalizing a design.
Parameter Maximum Rating Notes
Exten ded Operating Temperatur e
Duri ng Read –40 °C t o + 85 °C
Duri ng Block Erase and Program –40 °C t o +85 °C
Temperature und er Bias –40 °C t o +85 °C
Storage Tem peratur e –65 °C t o + 125 °C
Volt age On Any Pin (except VCC and VPP) with Respect to GND –0.5 V to +3.7 V 1
VPP Voltage (for Block Erase and Program) with Respect to G ND –0.5 V to +13.5 V 1,2,3
VCC and VCCQ Su pply Voltage with Respec t to GND –0. 2 V t o + 3 . 6 V
Output Short Circuit Curr ent 100 mA 4
Notes:
1.Minimu m DC volta ge i s –0.5 V on inpu t/ou tput pins. During transit ions , this le vel m ay
unde rshoot to –2.0 V fo r pe r iods <20 ns. Maximum DC voltage on input/o utput pins is VCC
+0.5 V which , du r in g transition s, may overshoot to VCC +2.0 V for periods <20 ns.
2.Maxim um D C voltage on VPP may overshoot to + 14. 0 V for pe ri ods <20 ns.
3.VPP Progr am vo lt age is n orm ally 1 .65 V–3. 6 V. Conne ctio n to a 11.4 V–12. 6 V supply can b e
done for a m aximum of 10 00 cycles on the m ain blocks and 2500 cycl es on the parameter
bloc ks dur ing pro gram/ era se. V PP m ay be connect ed to 12 V for a tot al of 80 hour s maximum .
4.Out put shor ted for no more than one second. No mor e than one o ut put shorted at a time.
Table 5. Te mperature and Voltage Operating Conditions
Symbol Parameter Notes Min Max Units
TAOperat in g Temp er ature –40 +85 °C
VCC1 VCC Supply Volt age 1, 2 2.7 3.6 Volts
VCC2 1, 2 3. 0 3.6
VCCQ1
I/O Supply Voltage
12.73.6
VoltsVCCQ2 1.65 2.5
VCCQ3 1.8 2.5
VPP1 Supply Voltage 1 1.65 3.6 Volts
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 21
VPP2 1, 3 11.4 12.6 Volts
Cycling Block Erase Cycling 3 100,000 Cycles
Notes:
1.VCC and VCCQ must share t he same supply when they ar e in the VCC1 r ange.
2.VCCM ax = 3.3 V for 0.25µm 32-Mb it devices.
3.Appl ying VPP = 11.4 V–12.6 V during a pro gram/er as e can only be done for a maxi mum of 100 0 cycles on
the main blocks and 25 00 cycles on the param et er blocks. VPP may be conne cted to 12 V for a tota l of
80 hours m axi m um.
Table 5. Temperature and Voltage Operating Conditions
Symbol Parameter Notes Min Max Units
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
22 Order Number: 290645, Revision: 022
6.0 Elec trical Specifications
6.1 Current Characteristics
Table 6. DC Current Characteristics (Sheet 1 of 2)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ Max Typ Max Typ Max
ILI Input Load Current 1,2 ± 1 ± 1 ± 1µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or G ND
ILO Out put Leakage
Current 1,2 ± 10 ± 10 ± 10 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or G ND
ICCS
VCC Standby Current
for 0.13 and 0.18
Micron Product 1 7 15 20 50 150 250 µA VCC = VCCMax
CE# = RP# = VCCQ
or during Progra m / Erase
Suspend
WP# = VCCQ or G ND
VCC Standby Current
for 0.25 M icron
Product 1 10 25 20 50 150 250 µA
ICCD
VCC Pow er - Down
Current for 0.13 and
0.18 Micron Product 1,2715720720µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or G ND
RP# = GN D ± 0.2 V
VCC Pow er - Down
Current for 0.25
Product 1,2725725725µA
ICCR
VCC Read Current for
0.13 and 0.18 Micron
Product 1,2,3 9 18 8 15 9 15 mA VCC = VCCMax
VCCQ = VCCQMax
OE# = VIH, C E# =VIL
f = 5 MHz, IOUT=0 mA
Inputs = VIL or VIH
VCC Read Current for
0.25 Micron Product 1,2,3 10 18 8 15 9 15 mA
IPPD VPP Deep Power-
Down Current 1 0.2 5 0.2 5 0.2 5 µA RP# = GND ± 0. 2 V
VPP ≤ VCC
ICCW VCC Program Current 1,4 18 55 18 55 18 55 mA VPP =VPP1,
Program in Progress
82210301030mA
VPP = VPP2 ( 12v)
Program in Progress
ICCE VCC Erase Current 1,4 16 45 21 45 21 45 mA VPP = VPP1,
Erase in Progr ess
81516451645mA
VPP = VPP2 (12v) ,
Erase in Progr ess
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 23
ICCES/
ICCWS
VCC Erase Suspend
Current for 0.13 and
0.18 Micr on Product 1,4,5
7 15 50 200 50 200 µA CE# = VIH, Erase Suspend in
Progress
VCC Erase Suspend
Current for 0.25
Micron Product 10 25 50 200 50 200 µA
IPPR VPP Read Curre nt 1,4 2±15 2 ±15 2 ±15 µA VPP ≤ VCC
50 200 50 200 50 200 µA VPP > VCC
IPPW VPP Program Current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP =VPP1,
Program in Progr ess
8228 22 8 22mA
VPP = VPP2 (12v)
Program in Progr ess
IPPE VPP Erase Curr ent 1,4 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP = VPP1,
Erase in Progress
82216451645mA
VPP = VPP2 (12v) ,
Erase in Progress
IPPES/
IPPWS VCC Erase Suspend
Current 1,4
0.2 5 0.2 5 0.2 5 µA VPP = VPP1,
Prog ram or Erase S uspend in
Progress
50 200 50 200 50 200 µA VPP = VPP2 (12v) ,
Prog ram or Erase S uspend in
Progress
Notes:
1.All cur r ents are in RMS unless otherwise noted. Typical valu es at nomina l VCC, TA= +25 °C.
2.The test condition s VCCMax, VCCQMax, V CCM i n, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed
at the top of each column. VCCMax = 3. 3 V f or 0.25µm 32-Mbit de vices.
3.Aut omat i c Pow er Savings (APS) reduces I CCR to ap pr oximately standby levels in static operation (CMOS input s).
4.Sampled, not 10 0% t est ed.
5.ICCES or ICCWS is specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES an d
ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR.
Table 6. DC Current Characteristics (Sheet 2 of 2)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ Max Typ Max Typ Max
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
24 Order Number: 290645, Revision: 022
6.2 DC Voltage Characteristics
Table 7. DC Voltage Characteristics
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Min Max Min Max Min Max
VIL Input Low
Voltage –0.4 VCC *
0.22 V –0.4 0.4 –0.4 0.4 V
VIH Input High
Voltage 2.0 VCCQ
+0.3V VCCQ –
0.4V VCCQ
+0.3V VCCQ –
0.4V VCCQ
+0.3V V
VOL Output Low
Voltage –0.1 0.1 -0.1 0.1 -0. 1 0.1 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High
Voltage VCCQ
–0.1V VCCQ –
0.1V VCCQ –
0.1V V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-
Out Voltage 1 1.0 1.0 1.0 V Complete Write
Protection
VPP1 VPP during
Program /
Erase
Operations
1 1.65 3.6 1.65 3.6 1.65 3.6 V
VPP2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 V
VLKO
VCC Prog/
Erase
Lock
Voltage 1.5 1.5 1.5 V
VLKO2
VCCQ Prog/
Erase
Lock
Voltage 1.2 1.2 1.2 V
Notes:
1. Erase an d Progr a m are inhibited when VPP < VPPLK and not guaran teed out si de the val id VPP ranges of VPP1 and VPP2.
2.Applying VPP = 1 1 .4 V–12.6 V during progr am/er ase can onl y be don e for a maximum of 1000 cycles on th e main bloc ks and
2500 cy cle s on the pa ra meter blocks . VPP may be co nnected to 12 V for a total of 80 hour s m axi m um.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 25
7.0 AC Characteristics
7.1 AC Read Characteristics
Table 8. Read Operations—8-Mbit Density
#SymParameter
Density 8 Mbit
Product 70 ns 90 ns 110 ns
VCC 2.7 V – 3.6 V 3.0 V – 3. 6 V 2 .7 V – 3. 6 V 3.0 V – 3.6 V 2.7 V – 3. 6 V
Note Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
R1 tAVAV Read Cycle Time 3,4 70 80 90 100 110
R2 tAVQV Address to
Output Delay 3,4 70 80 90 100 110
R3 tELQV CE# to Output
Delay 1,3,4 70 80 90 100 110
R4 tGLQV OE# to Out put
Delay 1,3,4 20 30 30 30 30
R5 tPHQV RP# t o O utput
Delay 3,4 150 150 150 150 150
R6 tELQX CE# to Output in
Low Z 2,3,40 0 0 0 0
R7 tGLQX OE# to Out put in
Low Z 2,3,40 0 0 0 0
R8 tEHQZ CE# t o O utput in
High Z 2,3,4 20 20 20 20 20
R9 tGHQZ OE# to Output in
High Z 2,3,4 20 20 20 20 20
R10 tOH
Output Hold from
Address, CE#, or
OE# Cha nge,
Whichever
Occurs First
2,3,40 0 0 0 0
Notes:
1.O E# may be delayed up to tELQV–tGLQV after the fa ll ing edge of CE # w it hout imp act on tELQV.
2.Sampled, but no t 10 0% tested.
3.See Figur e 9, “Read Operat ion W aveform” on page 28.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timi ng measurements and m aximum allowa ble input
slew rate.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
26 Order Number: 290645, Revision: 022
Table 9. Read Operations—16-Mbit Density
#SymParameter
Dens it y 16 Mb it
Notes
Product 70 ns 80 ns 90 ns 110 ns
VCC 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6V 2.7 V–3.6V
Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
R1 tAVAV Read Cycle Time 70 80 80 90 100 110 3,4
R2 tAVQV Address to Output
Delay 70 80 80 90 100 110 3,4
R3 tELQV CE# to Output Delay 70 80 80 90 100 110 1,3,4
R4 tGLQV OE# to Output Delay 20 20 30 30 30 30 1,3,4
R5 tPHQV RP# to Output Delay 150 150 150 150 150 150 3,4
R6 tELQX CE# to Output in Low Z 000000
2,3,4
R7 tGLQX OE# to Output in Low Z 000000
2,3,4
R8 tEHQZ CE# to Output in High
Z20 20 20 20 20 20 2,3,4
R9 tGHQZ OE# to Output in High
Z20 20 20 20 20 20 2,3,4
R10 tOH
Output Hold from
Address, CE#, or OE#
Change, Whichever
Occurs First 000000
2,3,4
Notes:
1.OE # m ay be delay ed up to tELQV–tGLQV aft er the falli ng edge of CE# wi thout impact on tELQV.
2.Sampled, but not 100% tested.
3.See Figure 9, “Read Operatio n Waveform” on page 28.
4. See Figur e 11, “AC Input/O utput Refer ence Wavefor m ” on page 33 for timing measurements and maximum allowable
inpu t slew rate.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 27
Table 10. Read Operations—32-Mbit Density
# Sym Parameter
Dens it y 3 2 Mbit
Notes
Product 70 ns 90 ns 100 ns 110 ns
VCC 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V 3.0 V–3.3 V 2. 7 V–3.3 V
Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
R1 tAVAV Read Cycle Time 70 90 90 100 100 110 3,4
R2 tAVQV Address to Output
Delay 70 90 90 100 100 110 3,4
R3 tELQV CE# to Output Delay 70 90 90 100 100 110 1,3,4
R4 tGLQV OE# to Output Delay 20 20 30 30 30 30 1,3,4
R5 tPHQV RP# to Output Delay 150 150 150 150 150 150 3,4
R6 tELQX CE# to Output in Low Z 000000
2,3,4
R7 tGLQX OE# to Output in Low Z 000000
2,3,4
R8 tEHQZ CE# to Output in High Z 20 20 20 20 20 20 2,3,4
R9 tGHQZ OE# to Output in High
Z20 20 20 20 20 20 2,3,4
R10 tOH
Output Hold from
Address, CE#, or OE#
Change, Whichever
Occurs First 000000
2,3,4
Notes:
1.O E# may be delayed up to tELQV–tGLQV after the fa ll ing edge of CE # w it hout imp act on tELQV.
2.Sampled, but no t 10 0% tested.
3.See Figur e 9, “Read Operat ion W aveform” on page 28.
4. See Figure 11, “ AC Input/O utput Ref er ence Wavefor m ” on page 33 for timing m easurem ents and ma ximum
allow able i nput slew ra te.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
28 Order Number: 290645, Revision: 022
Table 11 . Read Operations — 64-Mbit Density
#Sym Parameter
Density 64 Mbit
Unit
Product 70 ns 80 ns
VCC 2.7 V–3.6 V 2 .7 V–3.6 V
Note Min Max Min Max
R1 tAVAV Rea d C ycle Time 3,4 70 80 ns
R2 tAVQV Address to Output Delay 3,4 70 80 ns
R3 tELQV CE# to Output Delay 1,3,4 70 80 ns
R4 tGLQV OE# to Output Delay 1,3,4 20 20 ns
R5 tPHQV RP# to Output Delay 3,4 150 150 ns
R6 tELQX CE# to Output in Low Z 2,3,4 0 0 ns
R7 tGLQX OE# to Output in Low Z 2,3,4 0 0 ns
R8 tEHQZ CE# to Outp ut in H igh Z 2,3,4 20 20 ns
R9 tGHQZ OE# to Output in High Z 2,3,4 20 20 ns
R10 tOH Output Hold fr om Address , C E#, or OE#
Change, Whichever Occurs First 2,3,4 0 0 ns
Notes:
1.OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# with out impact on tELQV.
2.Sam pled, but not 100% tested.
3.See Figure 9, “Read Operation Waveform” on page 28.
4.See Fi gure 11, “A C Input /Outpu t Refere nce W a vefor m” on pa ge 33 for timi ng measu rem ent s an d maximum
allow able input sl ew r ate.
Figure 9. Read Operation Waveform
R5
R10
R7
R6
R9R4
R8R3
R1
R2 R1
A
ddress [A]
CE# [E]
OE# [G]
WE# [W]
Data [D/Q]
RST# [P]
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 29
7.2 AC Write Characteristics
Table 12. Write Operations—8- Mbit Density
#Sym Parameter
Density 8 Mbit
Product 70ns 90 ns 110 ns
VCC
3.0 V – 3. 6 V 80 100
2.7 V – 3. 6 V 70 90 110
Note Min
(ns) Min
(ns) Min
(ns) Min
(ns) Min
(ns)
W1 tPHWL /
tPHEL RP# High Rec overy to WE# (CE#) Going Low 4,5 150 150 150 150 150
W2 tELWL /
tWLEL CE# (WE#) Set up to WE# (CE#) Going Low 4,5 0 0 0 0 0
W3 tWLWH /
tELEH WE# (CE#) Pulse Width 4,5 45 50 60 70 70
W4 tDVWH /
tDVEH Data Setup to WE# (CE#) Going High 2,4,5 40 50 50 60 60
W5 tAVWH /
tAVEH Addre ss Se t up to WE # ( CE#) Goin g Hi g h 2, 4,5 50 50 60 70 70
W6 tWHEH /
tEHWH CE# (W E# ) Hol d Time f r om WE # ( C E# ) H igh 4 ,5 0 0 0 0 0
W7 tWHDX /
tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 0
W8 tWHAX /
tEHAX Address Ho ld Time from WE # ( CE#) Hig h 2,4,5 0 0 0 0 0
W9 tWHWL /
tEHEL WE# (CE#) Puls e Width High 2,4,5 25 30 30 30 30
W10 tVPWH /
tVPEH VPP Setup to WE# (CE #) G oing High 3,4,5 200 200 200 200 200
W11 tQVVL VPP Ho ld from Valid SRD 3,4 0 0 0 0 0
W12 tBHWH /
tBHEH WP# Setup to WE# (CE#) Going Hig h 3,4 0 0 0 0 0
W13 tQVBL WP# Hold from V a lid SRD 3,4 0 0 0 0 0
W14 tWHGL WE# High to OE# G oing Low 3, 4 30 30 30 30 30
Notes:
1.Write pulse width (tWP) is defined from C E# or WE# going low ( w hichever goes l ow last) to C E# or WE # going high (whichever
goes hig h fir st). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, write pulse width high (tWPH) is defi ned from CE # or
WE# going high (whichever goes high first) to CE# or WE# going low ( whichever goes low last). Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Ref er to Table 22, “C om m and Bus O per at ions” on page 46 for valid A IN or DIN.
3.Sampled, but no t 10 0% tested.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timi ng measurements and m aximum allowa ble input
slew rate.
5.See Figur e 10, “Write Operations Wavefo r m” on page 32.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
30 Order Number: 290645, Revision: 022
Table 13. Write Operations—16-Mbit Density
#SymParameter
Density 16 Mbit
Unit
Product 70 ns 80 ns 90 ns 110 ns
VCC
3.0 V – 3.6 V 80 100
2.7 V – 3.6 V 70 80 90 110
Note Min Min Min Min Min Min
W1 tPHWL /
tPHEL RP# High Recovery to WE# (CE#) Going
Low 4,5 150 150 150 150 150 150 ns
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 0 0 ns
W3 tWLWH /
tELEH WE# (CE#) Pulse Width 1,4,5 45 50 50 60 70 70 ns
W4 tDVWH /
tDVEH Data Setup to WE# (CE#) Going High 2,4,5 40 40 50 50 60 60 ns
W5 tAVWH /
tAVEH Address Setup to WE# (CE#) Going High 2,4,5 50 50 50 60 70 70 ns
W6 tWHEH /
tEHWH CE# (WE#) Hold Time from WE# (CE#)
High 4,5 0 0 0 0 0 0 ns
W7 tWHDX /
tEHDX D ata Hold Tim e from WE# ( C E#) High 2,4,5 0 0 0 0 0 0 ns
W8 tWHAX /
tEHAX Addres s Hold Time from WE# (CE# ) Hi gh 2,4,5 0 0 0 0 0 0 ns
W9 tWHWL /
tEHEL WE# (CE#) Pulse Wi dth High 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH /
tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP Hold from Valid SRD 3,4 0 0 0 0 0 0 ns
W12 tBHWH /
tBHEH WP# Set up t o WE# (CE#) Going High 3,4 0 0 0 0 0 0 ns
W13 tQVBL WP# Hold from Valid S R D 3,4 0 0 0 0 0 0 ns
W14 tWHGL WE# High to OE# Going Low 3,4 30 30 30 30 30 30 ns
Notes:
1.Write pulse width (tWP) is def ined from CE # or WE# g oing l ow (w hich eve r goe s low l ast) to CE# or WE# going high (whichever
goes high first). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similar ly, write pulse widt h high (tWPH) is defined from CE # or
WE# go in g high (whichever goe s hig h first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Refer to Table 22, “Command Bus Operations” on page 46 fo r vali d AIN or DIN.
3.Sampled, but not 100% tested.
4.See Figure 11, “AC Input /Ou tput Re ference Waveform” on pa ge 33 for tim ing mea surem ents and max imu m allow able i nput
slew rate.
5.See Figure 10, “Write Op er ations Wavef or m ” on page 32.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 31
Table 14. Write Operations—32-Mbit Density
#Sym Parameter
Density 32 Mbit
Unit
Product 70 ns 90 ns 100 ns 110 ns
VCC
3.0 V – 3.6 V690 100
2.7 V – 3.6 V 70 90 100 110
Note Min Min Min Min Min Min
W1 tPHWL /
tPHEL RP# High Recovery to WE# (CE#)
Going Low 4,5 150 150 150 150 150 150 ns
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#)
Going Low 4,5000000ns
W3 tWLWH
/
tELEH WE# (CE#) Pulse Width 1,4,5 45 60 60 70 70 70 ns
W4 tDVWH /
tDVEH Da t a Set up to WE # (CE# ) Go ing Hi gh 2,4, 5 40 40 50 60 60 60 ns
W5 tAVWH /
tAVEH Address Setup to WE# (CE#) Going
High 2,4,5 50 60 60 70 70 70 ns
W6 tWHEH /
tEHWH CE# (WE#) Hold Time from WE#
(CE#) High 4,5000000ns
W7 tWHDX /
tEHDX Data Hold T ime from WE# (CE#)
High 2,4,5 0 0 0 0 0 0 ns
W8 tWHAX /
tEHAX Address Hold T ime from WE# (CE#)
High 2,4,5 0 0 0 0 0 0 ns
W9 tWHWL /
tEHEL WE# (CE#) Pulse Width High 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH /
tVPEH VPP Setup to WE# (C E#) Going H igh 3,4,5 200 200 2 00 200 200 200 ns
W11 tQVVL VPP Hold from V a lid SRD 3,4 0 0 0 0 0 0 ns
W12 tBHWH /
tBHEH WP # S e t up to WE # ( C E # ) G oing
High 3,4000000ns
W13 tQVBL WP# Hold from Valid SRD 3,4 0 0 0 0 0 0 ns
W14 tWHGL WE# High to OE# Goin g Low 3,4 30 30 30 30 30 30 ns
Notes:
1.Write pulse width (tWP) is defined from C E# or WE# going low ( w hichever goes l ow last) to C E# or WE # going high (whichever
goes hig h fir st). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, write pulse width high (tWPH) is defi ned from CE # or
WE# going high (whichever goes high first) to CE# or WE# going low ( whichever goes low last). Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Ref er to Table 22, “C om m and Bus O per at ions” on page 46 for valid A IN or DIN.
3.Sampled, but no t 10 0% tested.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timi ng measurements and m aximum allowa ble input
slew rate.
5.See Figur e 10, “Write Operations Wavefo r m” on page 32.
6.VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
32 Order Number: 290645, Revision: 022
Table 15. Write Operations—64-Mbit Density
# Symbol Parameter
Density 64 Mbi t
UnitProduct 80 ns
VCC 2.7 V – 3.6 V Note Min
W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 ns
W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 ns
W3 tWLWH / tELEH WE# (CE#) Pulse Width 1,4,5 60 ns
W4 tDVWH / tDVEH Data Setup to WE# (CE#) Go ing High 2,4,5 40 n s
W5 tAVWH / tAVEH Address Se tu p to WE# (CE#) Going Hig h 2,4,5 60 ns
W6 tWHEH / tEHWH CE# (WE#) Hold Time f rom WE# (CE #) High 4,5 0 ns
W7 tWHDX / tEHDX Data Hold T ime from WE# ( C E#) High 2,4,5 0 ns
W8 tWHAX / tEHAX Address Hold Ti me from WE# (CE#) High 2,4,5 0 ns
W9 tWHWL / tEHEL WE# (CE#) Pulse Wi dth High 1,4,5 30 ns
W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 ns
W11 tQVVL VPP Hold from Valid SRD 3,4 0 ns
W12 tBHWH / tBHEH WP# Setup to WE# (CE #) G oi ng High 3,4 0 ns
W13 tQVBL WP# Hold from Valid SRD 3,4 0 ns
W14 tWHGL WE# High to OE# Going Low 3,4 30 ns
Notes:
1.W rite pulse w idth (tWP) is def ined fro m CE # or WE# go ing l ow (w hich ever goes l ow la st) t o CE# or WE# goi ng high (whic hever
goes high firs t). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, write pulse width high (tWPH) is defin ed from CE# or
WE# go in g high (whichever goe s hig h first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Refer to Table 22, “Command Bus Operations” on page 46 fo r vali d AIN or DIN.
3.Sampled, but not 100% tested.
4.See Figure 11, “AC Input /Ou tput Re ference Waveform” on pa ge 33 for tim ing mea surem ents and max imu m allow able i nput
slew rate.
5.See Figure 10, “Write Op er ations Wavef or m ” on page 32.
Figure 10. Write Operations Waveform
W10
W1
W7W4
W9W9
W3W3
W2
W6
W8W5
A
ddress [A]
CE # [E]
WE# [W]
OE# [G]
Data [D/Q]
RP # [P]
Vpp [V]
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 33
7.3 Erase and Program Timings
Table 16. Erase and Program Timings
7.4 AC I/O Test Conditions
Note: Input timin g begins, and output tim in g ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.
Worst-case speed con di ti ons are when VCC = VCCMin.
Symbol Parameter VPP 1.65 V–3.6 V 1 1.4 V–12.6 V Unit
Note Typ Max Typ Max
tBWPB 4-KW Parameter Block
W ord Program Time 1, 2, 3 0.10 0 .3 0 0.0 3 0.12 s
tBWMB 32-KW Main Block
W ord Program Time 1, 2, 3 0.8 2.4 0.24 1 s
tWHQV1 / tEHQV1
Word Program Time for 0.13
and 0. 18 Micron Pr oduct 1, 2, 3 12 200 8 185 µs
Word Program Time for 0.25
Micron Product 1, 2, 3 22 200 8 185 µs
tWHQV2 / tEHQV2 4-KW Parameter Block
Eras e Time 1, 2, 3 0.5 4 0.4 4 s
tWHQV3 / tEHQV3 32-KW Main Block
Eras e Time 1, 2, 3 1 5 0.6 5 s
tWHRH1 / tEHRH1 Program Suspend Latency 1,3 5 10 5 10 µs
tWHRH2 / tEHRH2 Erase Suspend Latency 1,3 5 20 5 20 µs
Notes:
1.Typical valu es m easured at TA= +25 °C and nominal voltages.
2.Excl udes externa l system-le vel over head.
3.Sampled, but no t 10 0% tested.
Figure 11. AC Input/Output Refere nce Wave form
V
CCQ
0V
V
CCQ
/2 V
CCQ
/2
Test Points
Input Outpu
t
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
34 Order Number: 290645, Revision: 022
Note: See Table 17 f or com ponent valu es.
7.5 Device Capacitance
TA = 25 °C, f = 1 MHz
Figure 12. Tr an s ient Equivalent Te sting Load Circuit
Device
Under Test
V
CCQ
C
L
R
2
R
1
Ou
t
Table 17. Test Configuration Component Values for Worst-Case Speed Conditions
Test Configuration CL (pF) R1 (kΩ)R
2 (kΩ)
VCCQMin Standard Test 50 25 25
Note: CL includes jig capacitance.
Table 18. Device Capacitance
Symbol Parameter§Typ Max Unit Condition
CIN Inpu t C apacitance 6 8 pF VIN = 0.0 V
COUT Output Capacitance 8 12 pF VOUT = 0.0 V
§Sampl ed, not 100% test ed.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 35
8.0 Power and Reset Specifications
Intel® flash devices have a tiered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby
mode, where current consumption is even lower. If RP# is deasserted, the flash enter deep power-
down mode for ultra-low current consumption. The combination of these features can minimize
memory power consumption, and therefore, overall system power consumption.
8.1 Active Power (Program/Erase/Read)
W ith CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer
to the DC Characteristic tables for ICC current values. Active power is the largest contributor to
overall system power consumption. Minimizing the active current could have a profound effect on
system power consumption, especially for battery-operated devices.
8.2 Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address li nes are idle, APS circuitry places the device in a mode where
typical cu rrent is comparable to ICCS. The flash stays in this static state with outputs valid until a
new location is read.
8.3 Standby Power
When CE# is at a logic-high level (VIH), the flash memory is in standby mode, which disables
much of the device’ s circuitry and substantially reduces power consumption. Outputs are placed in
a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-
high level during Erase or Program operations, the device will continue to perform the operation
and consume corresponding active power until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time and quantify
the respective power consumption in each mode for their specific application. This approach will
provide a more accurate measure of application-spe c if i c po we r and energy requi r em e nt s.
8.4 Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL. During read modes, RP# going low de-
selects the memory and places the outputs in a high-impedance state. Recovery from deep power-
down requires a minimum time of tPHQV for read operations, and tPHWL/tPHEL for write operations.
During program or erase modes, RP# transitioning low aborts the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low-power savings mode (RP# transitioning to VIL or turning off power
to the device clears the Status Register).
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
36 Order Number: 290645, Revision: 022
8.5 Power and Reset Considerations
8.5.1 Power-Up/Down Characteristics
To prevent any condition that may result in a spurious write or erase operation, Intel recommends
to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-down together.
Intel also recommends that you power-up VPP with or after VCC has reached VCCmin.
Conversely, VPP must powerdown with or slightly before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain VCCmin before
applying VCCQ and VPP. Device inputs must not be driven before supply voltage reaches
VCCmin.
Power supply transitions must only occur when RP# is low.
8.5.2 RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system reads from the flash memory when it comes out of reset. If a CPU reset occurs without a
flash memory reset, proper CPU initialization will not occur because the flash memory may be
providing status information instead of array data. Intel recommends connecting RP# to the system
CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Be cause
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the device in reset during power-up/down, invalid bus conditions during power-up can
be masked, providing yet another level of memory protection.
8.5.3 VCC, VPP and RP# Transitions
The CUI la tches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage), is read-array mode.
After any program or Block-Erase operation is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read-array mode by the Read Array command if access to the
flash-memor y array is desired.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 37
8.5.4 Reset Specifications
8.6 Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System
designers should consider the following three supply current issues:
•Standby current levels (ICCS)
•Read current levels (ICCR)
•Transient peaks produced by falling and rising edges of CE#.
Table 19. Reset Specifications
Symbol Parameter VCC 2.7 V – 3.6 V Unit Notes
Min Max
tPLPH RP# Low to Reset during Read
(If RP# is tied to VCC, this specificat ion is n ot
applicable) 100 ns 1, 2
tPLRH1 RP# Lo w t o R eset during Block Erase 22 µs 3
tPLRH2 RP# Lo w t o R eset during Progr am 12 µs 3
Notes:
1.If tPLPH is < 100 ns th e device may stil l reset but this is not guara nt eed.
2.If RP# is asserte d while a Bl ock Era se or Word Program ope r ation is not exe cutin g, the reset
will complete within 100 ns.
3.Sampled, but no t 10 0% tested.
Figure 13. Reset Operations Waveforms
IH
V
IL
V
RP # (P )
PLPH
t
IH
V
IL
V
R P # (P )
PLPH
t
(A) Reset during Read Mode
Abort
Complete
PHQV
t
PHWL
t
PHEL
t
PHQV
t
PHWL
t
PHEL
t
(B ) R eset during Program or Block Erase, <
PLPH
t
PLRH
t
PLRH
t
IH
V
IL
V
R P # (P )
PLPH
t
Abort
Complete
PHQV
t
PHWL
t
PHEL
t
PLRH
t
Deep
Power-
Down
(C) R e s e t P ro g ra m o r Blo c k E ra s e , >
PLPH
t
PLRH
t
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
38 Order Number: 290645, Revision: 022
T ransient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-
line control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND,
and between its VPP and VSS. These high-frequency, inherently low-inductance capacitors should
be placed as close as possible to the package leads.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 39
9.0 Device Ope rati ons
The Intel® Advanced+ Boot Block Flash Memory (C3) device uses a CUI and automated
algorithms to simplify Program and Erase operations. The CUI allows for 100% CMOS-level
control inputs and fixed power supplies during erasure and programming.
The internal WSM completely automates Program and Erase operations while the CUI signals the
start of an operation and the Status Register reports device status. The CUI handles the WE#
interface to the data and address latches as well as system status requests during WSM operation.
9.1 Bus Operations
The Intel® Advanced+ Boot Block Flash Memory (C3) device performs read, program, and erase
operations in-system through the local CPU or microcontroller. Four control pins (CE#, OE#,
WE#, and RP#) manage the data flow in and out of the flash device. Table 20 on page 39
summarizes these bus operations.
9.1.1 Read
When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted.
CE# is the device selection control; when active low, it enables the flash memory device. OE# is
the data output control; when low, data is output on DQ[15:0]. See Figure 9, “Read Operation
Waveform” on page 28.
9.1.2 Write
A write cycle occurs when both CE# and WE# are low; RP# and OE# are high. Commands are
issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory
location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever
occurs first. See Figure 10, “Write Operations Waveform” on page 32.
9.1.3 Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. DQ[1 5:0] are placed in a
high-impedance state.
Table 20. B us Operations
Mode RP# CE# OE# WE# DQ[15:0]
Read VIH VIL VIL VIH DOUT
Write VIH VIL VIH VIL DIN
Output Disable VIH VIL VIH VIH High-Z
Standby VIH VIH X X High-Z
Reset VIL X X X High-Z
Note: X = Don’t Care (VIL or VIH)
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9.1.4 Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during a Program or Erase operation, the device continues to consume active power
until the Program or Erase operation is complete.
9.1.5 Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-
impedance state, and turns of f all internal circuits. After return from reset, a time tPHQV is required
until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is re qui red a fte r retu rn fro m
reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored.
The C UI re sets to read -array mode , the S tatus R egist er is set to 0x 80, and all blo cks ar e lock ed. See
Figure 13, “Reset Operations Waveforms” on page 37.
If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be
aborted; the memory contents at the aborted location (for a program) or block (for an erase) are no
longer valid, since the data may be partially erased or written. The abort process goes through the
following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process which takes
time tPLRH to complete.
2. After time tPLRH, the part will either reset to read-array mode (if RP# is asserted during tPLRH)
or enter reset mode (if RP# is deasserted after tPLRH). See Figure 13, “Reset Operations
Waveforms” on page 37.
In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL
must be observed before a Read or Write operation is initiated, as discussed in the previous
paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when
RP# goes high.
As with any automated device, it is important to assert RP# during a system reset. When the system
comes out of reset, the processor reads from the flash memory. Automated flash memories provide
status information when read during Program or Block-Erase operations. If a CPU reset occurs
with no flash memory reset, proper CPU initialization may not occur because the flash memory
may be providing status information instead of array data. Intel® flash memories allow proper CPU
initialization following a system reset through the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets the system CPU.
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Order Number: 290645, Revision: 022 41
10.0 Modes of O p er a t io n
10.1 Read Mode
The flash memory has four read modes (read array, read identifier, read status, and CFI query) and
two write modes (program and erase). Three additional modes (erase suspend to program, erase
suspend to read, and program suspend to read) are available only during suspended operations.
Table 22, “Command Bus Operations” on page 46 and Table 23, “Command Codes and
Descrip tions” on page 47 summarize the commands used for these modes.
Appendix A, “Write State Machine States” on page 54 is a comprehensive chart showing the state
transitions.
10.1.1 Read Array
When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will
respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
When the device is in read array mode, four control signals control data output.
•WE# must be logic high (VIH)
•CE# must be logic low (VIL)
•OE# must be logic low (VIL)
•RP# must be logic high (VIH)
In addition, the address of the desired location must be applied to the address pins. If the device is
not in read-array mode, as would be the case after a Program or Erase operation, the Read Array
command (0xFF) must be issued to the C UI before array reads can occur.
10.1.2 Read Identifier
The read-identifier mode outputs three types of information: the manufacturer/device identifier , the
block locking status, and the protection register. The device is switched to this mode by issuing the
Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 21
retrieve the specified information. To return to read-array mode, issue the Read Array command
(0xFF).
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10.1.3 CFI Query
The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read Query
Command (0x98). The CFI data structure contains information such as block size, density,
command set, and electrical specifications. Once in this mode, read cycles from addresses shown in
Appendix C, “Common Flash Interface,” retrieve the specified information. T o return to read-array
mode, issue the Read Array command (0xFF).
10.1.4 Read Status Register
The Status Register indicates the status of device operations and the success/failure of that
operation. The Read Status Register (0x70) command causes subsequent reads to output data from
the Status Register until another command is issued. To return to reading from the array, issue a
Read Array (0xFF) command.
The Status Register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 0x00 when a
Read Status Register comman d is issued.
Table 21. Device Identification Codes
Item Address1
Data Description
Base Offset
Manufacturer ID Block 0x00 0 x0089
Device ID Block 0x01
0x88C0 8-Mbit Top Boot Device
0x88C1 8-Mbit Bottom Boot Device
0x88C2 16-Mbi t Top Boot Device
0x88C3 16-Mbit Bottom Boot Device
0x88C4 32-Mbi t Top Boot Device
0x88C5 32-Mbit Bottom Boot Device
0x88C C 64-Mbi t Top Boot Device
0x88CD 64-Mbit Bottom Boot Device
Block Lock Sta t us2Block 0x02 DQ0 = 0b0 Block is unl ocked
DQ0 = 0b1 Block is lock ed
Block Lock-Down Stat us2Block 0x02 D Q 1 = 0b0 Block is not lo cked-do wn
DQ1 = 0b1 Block is lock ed down
Prot ection Reg ister Lock Sta tus B l ock 0x80 Lock Data
Prot ection Reg ist er Block 0x81 - 0x88 Register Data Multip le reads required to read t he
entir e 128-bit Pr ot ect ion Regist er.
Notes:
1.The address is co nst r uct ed from a base address plus an offset. For example, to r ead the Block Lock Sta tu s f or block number
38 in a bott om boot device , set the addre ss to 0x0F800 0 plus the offset (0x02), i.e. 0x0 F8002. Th en examine DQ0 of the dat a
to determin e i f t he block is l o cked .
2.See Section 11.2, “Reading Block-Loc k Status” on page 50 for valid lock stat us.
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Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 43
The contents of the Status Register are latched on the falling edge of OE# or CE# (whichever
occurs last) which prevents possible bus errors that might occur if Status Register contents change
while being read. CE# or OE# must be toggled with each subsequent status read, or the Status
Register will not indicate completion of a Program or Erase operation.
When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits in the
Status Register indicate whether the WSM was successful in performing the preferred operation
See Table 24, “Status Register Bit Definition” on page 48.
10.1.4.1 Clear Status Register
The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7, but the WSM
cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error
conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By
allowing the system software to control the resetting of these bits, several operations may be
performed (such as cumulatively programming several addresses or erasing multiple blocks in
sequence) before reading the Status Register to determine if an error occurred during that series.
Clear the Status Register before beginning another command or sequence. The Read Array
command must be issued before data can be read from the memory array. Resetting the device also
clears the Status Register.
10.2 Program Mode
Programming is executed using a two-write cycle sequence. The Program Setup command (0x40)
is issued to the CUI, followed by a second write that specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program preferred
bits of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If users attempt
to program “1”s, the memory cell contents do not change and no error occurs.
The Status Register indicates programming status. While the program sequence executes, status bit
7 is “0.” The Status Register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the program-status bits must be checked. If the programming
operation was unsuccessful, SR[4] is set to indicate a program failure. If SR[3] is set, then VPP wa s
not within acceptable limits, and the WSM did not execute the program command. If SR[1] is set, a
program operation was attempted on a locked block and the operation was aborted.
The Status Register should be cleared before attempting the next operation. Any CUI instruction
can follow after programming is completed; however , to prevent inadvertent Status Register reads,
be sure to reset the CUI to read-array mode.
10.2.1 12-Volt Production Programming
When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC
pin.
Note: If VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above 1.65 V to
perform in-system flash modifications.
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When VPP is connected to a 12 V power supply, the device draws program and erase current
directly from the VPP pin. This eliminates the need for an external switching transistor to control
VPP. Figure 16 on page 53 shows examples of how the flash power supplies can be configured for
various usage models.
The 12 V VPP mode enhances programming performance during the short period of time typically
found in manufacturing processes; however, it is not intended for extended use. You cna apply
12 V to VPP during Program and Erase operations for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80
hours maximum. Stressing the device beyond these limits may cause permanent damage.
10.2.2 Susp endi ng and Resumi ng Prog ram
The Program Suspend command halts an in-progress program operation so that data can be read
from other locations of memory. Once the programming process starts, issuing the Program
Suspend command to the CUI requests that the WSM suspend the program sequence at
predetermined points in the program algorithm. The device continues to output Status Register data
after the Program Suspend command is issued. Polling SR[7] and SR[2] will determine when the
program operation has been suspended (both will be set to “1”). The program-suspend latency is
specified with tWHRH1/tEHRH1.
A Read-Array command can now be issued to the CUI to read data from blocks other than that
which is suspended. The only other valid commands while program is suspended are Read Status
Register, Read Identifier, CFI Query, and Program Resume.
After the Program Resume command is issued to the flash memory, the WSM will continue with
the programming process and SR[2] and SR[7] will automatically be cleared. The device
automatically outputs Status Register data when read (see Figure 18, “Program Suspend / Resume
Flowchart” on page 57) after the Program Resume command is issued. VPP must remain at the
same VPP level used for program while in program-suspend mode. RP# must also remain at VIH.
10.3 Erase Mode
To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
Whe n t he S tatus Reg is te r i ndi c ate s t hat e rasu re i s co mpl ete, ch ec k the er ase -s ta tus bit to verify th at
the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the Status
Register will be set to a “1,” indicating an erase failure. If VPP is not within acceptable limits after
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR[5] of the Status Register is set to indicate an erase error , and SR[3] is set to a “1” to identify that
VPP supply voltage is not within acceptable limits.
After an Erase operation, clear the Status Register (0x50) before attempting the next operation.
Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status-
register reads, Intel recom mends that you place the flash in read-array mode after the erase is
complete.
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Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 45
10.3.1 Suspending and Resuming Erase
Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption to read data from—or program data to— another
block in memory. Once the erase sequence is started, issuing the Erase Suspend command to the
CUI suspends the erase sequence at a predetermined point in the er ase algorithm. The Status
Register indicates if/when the Erase operation has been suspended. Erase-suspend latency is
specified by tWHRH2/tEHRH2.
A Read Array or Program command can now be issued to the CUI to read/program data from/to
blocks other than that which is suspended. This nested Program command can subsequently be
suspended to read yet another location. The only valid commands while Erase is suspended are
Read Status Register, Read Identifier, CFI Query, Program Setup, Program Resume, Erase
Resume, Lock Block, Unlock Block, and Lock-Down Block. During erase-suspend mode, the
device ca n be placed in a p seudo -standby mode by taking CE# to VIH, which reduces active current
consumption.
Erase Resume continues the erase sequence when CE# = VIL. Similar to the end of a standard
Erase ope ration, the Status Reg ister must be read and cleared before the next instruction is issued.
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Bus operations are defined in Table 20, “Bus Operations” on page 39.
Table 22. Command Bus Operations
Command Notes First Bus Cycle Second Bus Cycl e
Oper Addr Data Oper Addr Data
Read Ar ra y 1,3 Writ e X 0xFF
Read Iden tifie r 1,3 Write X 0x90 Read IA ID
CFI Query 1,3 Write X 0x98 Read QA QD
Read Status Register 1,3 Write X 0x70 Read X SRD
Clear Status Register 1,3 Write X 0x50
Program 2,3 Write X 0x40/
0x10 Write PA PD
Block Erase/Confirm 1,3 Write X 0x20 Write BA D0H
Program/Erase Suspend 1,3 Writ e X 0xB0
Program/Erase Resume 1,3 Write X 0xD0
Lock Block 1,3 Write X 0x60 Write BA 0x01
Unlock Bl ock 1,3 Write X 0x60 Wri t e BA 0xD0
Lock-Down Block 1,3 Writ e X 0x60 W rite BA 0x2F
Protection Program 1,3 Write X 0xC0 Write PA PD
X = "Don’t Care" PA = Prog Addr BA = Block A ddr IA =Iden ti fi er Addr. QA = Query Addr.
SRD = Status Reg.
Data PD = Prog Data ID = Identifier Data QD = Query Data
Notes:
1.Foll owin g the Read I den tifie r or C FI Query com m ands, read ope ratio ns outpu t devi ce ident ificat ion da ta or
CFI qu er y informat ion , respectively. See Sec tion 10.1.2 and Section 10 .1.3.
2.Eith er 0x40 or 0x10 comma nd is valid, but t he Intel st andard is 0x40.
3.When writing commands, the upper data bus [DQ8-DQ15] should be either VIL or VIH, to minimize current
draw.
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Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 47
Table 23. Comman d Codes and Descriptions
Code
(HEX) Device Mode Command Description
FF Read Arr ay This comm and places the device in read -a r ra y mode, which o utputs ar r ay data on the data pin s.
40 Progr a m Set-Up
This is a two-cycle comma nd. The first cycle prep ar es the CUI for a program operation. The
second cycle latch es addresses and dat a in formatio n and initiates the WSM to exe cute the
Progr am algorithm . The flash output s Status Registe r da t a when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See Section 10.2, “Pr ogram
Mo de ” on page 43.
20 Erase Set-Up This is a two-cy cle command. It prepares the CUI for the Erase Co nfirm comma nd. If the next
comma nd is not an Erase Confirm comm and, then t he CUI will (a) set both SR.4 and S R.5 to “1,”
(b) place the device into the read-Stat us Register m ode, and (c) wa it fo r another comm and. See
Sect io n 10.3, “Erase Mode” on page 44.
D0
Eras e Confirm
Program/Erase
Resume
Unlock Block
If the previ ous comman d was an Er ase Se t-U p comma nd, th en the CUI will clo se the add ress an d
data l atch es a nd beg in erasing the b lo ck indi cate d on t he add ress p in s. D uring p rogr am/era se, the
device wi ll respond only to the R ead Stat us Register, Program Su spend and Erase Suspend
comma nds, and will output Status Reg ister data when CE# or O E# is toggle d.
If a Pro gr am or Er ase operation was pr eviously suspended, this command will resume that
operation.
If the previous comm and was Block U nl ock Set-Up, the CUI will latc h t he address and unlock the
block indi cated on the address pin s . If the block had bee n pr evi ously set to Lo ck- Down, this
operat ion will hav e no effect . (S ee Section 11.1)
B0 Program Suspend
Erase Suspend
Issuing this c omman d wil l beg in to suspend the cu rre ntly execut ing P rogram/ Er ase ope rati on. The
S ta tus Regist er will indic ate when the operation has been succes sfully sus pended by setting ei ther
the program-suspend SR[ 2] or erase-suspend SR [6 ] and the WSM status bit SR [7] to a “1”
(ready ) . The WSM will continue to idle in the SU SP END st at e, regardless of the st at e of all input-
contro l pin s except RP #, w hich w ill i mmed iatel y shut dow n the WSM and t he r emaind er of the chip
if RP# is dr iven to VIL. Se e Se ctio n s 3.2. 5.1 and 3.2. 6.1.
70 Read Status
Register
This command places the device into read-Status Register mode. Reading the device will output
the c ont ents of t he Status Register, regardl ess of the address presented to the device. The device
autom atica lly en ters this mod e af te r a Prog ram or Eras e ope ratio n has been in itia ted. See Section
10.1.4, “Read Status Regi ster” on page 42.
50 Clear Status
Register The WSM can set the block-lo ck sta tus SR[ 1], VPP S t at us SR[ 3], program sta tus SR [4] , and erase -
status SR[5] bits in the S tatus Register to “1,” but it cannot clear them to “0.” Issuing this command
clears t hose bits t o “0 .”
90 Read Identifier Th is command puts the device into the read-id ent ifier mode so that reading the device w il l output
the man uf acturer/de v ic e codes or block- l ock status. See Section 10.1.2, “Read Identifier” on
page 41.
60
Bloc k Lock,
Block Un lo ck,
Bloc k Lock-Down
Set-Up
This co m mand prepares the CUI for block-locki ng changes. If the next com mand is not Bloc k
Unlock, Block Lock, or Block Lock- D own, then th e CUI will set both the program a nd erase-Status
Regist er bits to ind ic ate a command- sequence error. See Section 11.0, “Security M odes” on
page 49.
01 Lock-Block If the pr evious command was Lock Set-Up, the CUI will latch t he address and lock the block
indicat ed on the addr ess pins. (Se e Section 11.1)
2F Lock-Down If the previous command was a Lock- D own Set-U p com m and, the C UI will latch the address and
lock-down the block indicated on th e address pins . (See Section 11.1)
98 CFI Query This co m m and puts th e device into t he CFI-Query mode so that reading t he device wil l out put
Common Flash Interface information. See Section 10.1.3 and Appendi x C, “Com m on Flash
Interface”.
C0 Protection
Program
Set-Up
This is a tw o- cycle command. Th e fir s t cycle prepar es the CUI fo r a program op er ation to the
protection regis ter. The second cycle latc hes addresses and data informa ti on and initiat es the
WSM to execute the Protection Program algorithm to the protection register. The flash outputs
S tatus Register data when CE# or OE# is toggled. A Read Array command is required after
programming to read array data. See Section 11.5.
10 Alt. Pr og Set-Up Opera te s th e sam e as Prog r am Set-up command. (See 0x40/Program Set-Up)
00 Invalid/
Reserved Unass igned commands shoul d not be used. Intel reserves the righ t to re def ine these codes for
future function s.
Note: See Appendix A, “ Write State M achine States” fo r mo de transition inform ation.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
48 Order Number: 290645, Revision: 022
Table 24. Status Register Bit Definition
WSMS ESS ES PS VPPS PSS BLS R
76543210
NOTES:
SR[7] WR ITE STATE MACHINE STATUS ( W SMS)
1 = Read y
0=Busy
Befor e checking pr ogram or erase- status bits, check the Write
State Machine bit fir st to determine Wo r d Pr ogram or Block
Erase completion.
SR[6] = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Prog ress/Completed
When Erase S uspend is issued , WSM hal ts execu tion and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until
an Erase Resu m e com m and is iss ued.
SR[5] = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Succe ssf ul Block Erase
When this bit is set to “1 ,” WSM has appl ie d the maximum
number of e ra se pulses to the block and is still unable to ver ify
succe ssful block erasure.
SR[4] = PROGRAM STATUS ( PS )
1 = Error in Programming
0 = Successful Programmin g When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
SR[3] = VPP STAT US (VPPS)
1=V
PP Low Detec t, O per at ion Abort
0=V
PP OK
The VPP status bit does not pr ovide continuous indication of
VPP level. The WSM in te rrogates V PP level only after the
Program or Erase command sequences have been entered
and i nf or ms the system if VPP has not been switched on. The
VPP is also checked befor e th e operatio n is ve r if ied by the
WSM. The VPP status bi t i s not guaranteed to report accurate
feedback between VPPLK and VPP1Min.
SR[2] = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/C om pleted
When Program Suspend is issu ed, WSM halts execu ti on and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
unt il a Pr ogram Resume command is iss ued.
SR [1] = BL O CK LOCK STATUS
1 = Prog/Erase attempted on a locked block; Operation
aborted.
0 = N o operation to locked blocks
If a Program or Erase operation is attempted to one of the
loc ked blocks, th is bi t is set by the WSM. The operation
specified is abor ted and the device is retur ned to read status
mode.
SR[0] = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserve d for future u se and should be masked out
when polling th e Statu s Re gister.
Note: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 49
11.0 Security Modes
11.1 Flexible Block Locking
The Intel® Advanced+ Boot Block Flash Memory (C3) device offers an instant, individual block-
locking scheme that allows any block to be locked or unlocked with no latency, enabling instant
code and data protection.
This locking scheme off ers two levels of protection. The first level allows software-only control of
block locking (useful for data blocks that change frequently), while the second level requires
hardware interaction before locking can be changed (useful for code blocks that change
infrequently).
The following sections will discuss the operation of the locking system. The term “state [abc]” will
be used to specify locking states; for example, “state [001],” where a = value of WP#, b = bit D1 of
the Block Lock Status Register, and c = bit D0 of the Block Lock Status Register. Figure 14,
“Block Locking State Diagram” on page 49 displays all of the possible locking states.
Figure 14. Block Locking State Diagram
[X00]
[X01]
Power-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down
4,5
Software
Locked
[011]
Hardware
Locked
5
Unlocked
WP# Hardware Control
Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D 1 indi c at es blo c k Lo c k -dow n s t atus . D 1 = ‘0’, Lock -dow n ha s not been is s ue d t o
t his block . D 1 = ‘1’, Loc k -do w n has been is s u ed t o t his bloc k .
3. D 0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.
4. Loc k e d-dow n = H ardw are + Sof t w are l oc k ed.
5. [ 01 1] s tat es s houl d be t rac k ed by s y s t em s of tw are t o determ in e dif f erenc e
bet w een H ard wa re Loc k ed an d Loc k ed-D ow n s tat es .
Software Block Lock (0x60/0x01) or Software Block Unloc k (0x60/0xD0)
Softw are Block Loc k-Down (0x 60/0x2F)
WP # hardware control
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
50 Order Number: 290645, Revision: 022
11.1.1 Locki ng Operation
The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which
will be described in the following sections. See Figure 14, “Block Locking State Diagram” on
page 49 and Figure 21, “Locking Operations Flowchart” on page 60.
The following paragraph concisely summarizes the locking functionality.
11.1.1.1 Locked State
The default state of all blocks upon power-up or reset is locked (states [001] or [101]). Locked
blocks are fully protected from alteration. Any Program or Erase operations attempted on a locked
block will return an error on bit SR[1]. The state of a locked block can be changed to Unlocked or
Lock Down using the appropriate software commands. An Unlocked block can be locked by
writing the Lock command sequence, 0x60 followed by 0x01.
11.1 .1.2 Un loc ked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks
return t o t he Locked state when the device is reset or powe red down. Th e status of an unlocked
block can be changed to Locked or Locked Down using the appropriate software commands. A
Locked block can be unlocked by writing the Unlock command sequence, 0x60 followed by 0xD0.
11.1 .1.3 Lo ck-Do wn State
Blocks that are Locked-Down (state [011]) are protected from Program and Erase operations (just
like Locked blocks), but their protection status cannot be changed using software commands alone.
A Locked or Unlocked block can be Locked Down by writing the Lock-Down command sequence,
0x60 followed by 0x2F. Locked-Down blocks revert to the Locked state when the device is reset or
powered down .
The Lock-Down function depends on the WP# input pin. When WP# = 0, blocks in Lock Down
[011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-Down
function is disabled ([111]), and Locked-Down blocks can be individually unlocked by software
command to the [110] state, where they can be erased and programmed. These blocks can then be
relocked [111] and unlocked [110] as required while WP# remains high. When WP# goes low,
blocks that were previously Locked Down return to the Lock-Down state [011], regardless of any
changes made while WP# was high. Device reset or power-down resets all blocks, including those
in Lock-Down, to Locked state.
11.2 Reading Block-Lock Status
The Lock status of each block can be read in read-identifier mode of the device by issuing the read-
identifier command (0x90). Subsequent reads at Block Address + 0x00002 will output the Lock
status of that block. The Lock status is represented by DQ0 and DQ1:
•DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by
the Unlock command. It is also automatically set when entering Lock Down.
•DQ1 indicates Lock-Down status and is set by the Lock-Down command. It cannot be cleared
by software—only by device reset or power-down.
See Table 21, “Device Identification Codes” on page 42 for block-status information.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 51
11.3 Locking Operations during Erase Suspend
Changes to block-lock status can be performed during an erase-suspend by using the standard
locking command sequences to Unlock, Lock, or Lock Down a block. This operation is useful in
the case when another block needs to be updated while an Erase operation is in progress.
T o change block locking during an Erase operation, first issue the Erase Suspend command (0xB0),
and then check the Status Register until it indicates that the Erase operation has been suspended.
Next, write the preferred Lock command sequence to a block and the Lock status will be changed.
After completing any preferred Lock, Read, or Program operations, resume the Erase operation
with the Erase Resume command (0xD0).
If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking
status bits will be changed immediately. But when the Erase is resumed, the Erase operation will
complete.
Locking operations cannot be performed during a Program Suspend. Refer to Appendix A, “Write
State Machine States” on page 54 for detailed information on which commands are valid during
Erase Suspend.
11.4 Status Register Error Checking
Using nested-locking or program-command sequences during Erase Suspend can introduce
ambiguity into Status Register results.
Since locking changes are performed using a two-cycle command sequence, for example, 0x60
followed by 0x01 to lock a block. Following the Block Lock, Block Unlock, or Block Lock-Down
Setup command (0x60) with an invalid command will produce a Lock-Command error (SR[4] and
SR[5] will be set to 1) in the Status Register. If a Lock-Command error occurs during an Erase
Suspend, SR[4] and SR[5] will be set to 1 and will remain at 1 after the Erase is resumed. When
Erase is complete, any possible error during the Erase cannot be detected by the Status Register
beca use of the previous Lock-Command error.
A similar situation happens if an error occurs during a Program-Operation error nested within an
Erase Suspend.
11.5 128-Bit Protection Register
The C3 device architecture includes a 128-bit protection register than can be used to increase the
security of a system design. For example, the number contained in the protection register can be
used to “match” the flash component with other system components, such as the CPU or ASIC,
preventing device substitution. Application note, AP-657 Designing with the Advanced+ Boot
Block Flash Memory Architecture, contains additional application information.
The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other
segment is left blank for customer designs to program, as preferred. Once the customer segment is
programmed, it can be locked to prevent further programming.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
52 Order Number: 290645, Revision: 022
11.5.1 Reading the Protection Register
The protection register is read in the Read-Identifier mode. The device is switched to this mode by
issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown
in Figure 15, “Protection Register Mapping” retrieve the specified information. To return to Read-
Array mode, issue the Read Array command (0xFF).
11.5.2 Program ming th e Protection R egister
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup
command, 0xC0. The next write to the device will latch in address and data and program the
specified location. The allowable addresses are listed in Table 21, “Device Identification Codes”
on page 42. See Figure 22, “Protection Register Programming Flowchart” on page 61. Attempting
to program to a previously locked protection register segment will result in a Status Register error
(Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1).
Note: Do not attempt to address Protection Program commands outside the defined protection register
address space; st atus register can be indeterminate.
11.5.3 Locking the Prot ecti on Reg ister
The user-programmable segment of the protection register is lockable by programming bit 1 of the
PR -LOCK location to 0. See Figure 15, “Protection Register Mapping” on page 52. Bit 0 of this
location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set
using th e Pr otection Progra m comma nd to progra m 0xFFFD to the P R-LOCK loc ation. A fter these
bits have been programmed, no further changes can be made to the values stored in the protection
register. Protection Program commands to a locked section will result in a Status Register error
(Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1). Protection register lockout
state is not reversible.
11.6 VPP Program and Erase Voltages
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range. For fast
production programming, 12 V programming can be used. See Figure 16, “Example Power Supply
Configurations” on page 53.
Figure 15. Protection Register Mapping
0x88
0x85
64-bi t Segment
(User-Programmable)
0x84
0x81
0x80 PR Loc k R egis t er 0
64-bi t Segment
(Intel Factory-Programmed)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128- Bit P rot ect i on R e gis t e r 0
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 53
11.6.1 Program Protection
In addition to the flexible block locking, the VPP programming voltage can be held low for absolute
hardware write protection of all blocks in the flash device. When VPP is below or equal to VPPLK,
any Program or Erase operation will result in an error , prompting the corresponding Status Register
bit (SR[3]) to be set.
0645_06
Note:
1.A resi stor can be use d if the VCC supply ca n sink a dequate cur rent based on r esistor value. See AP-657
Designing with the Advanced+ Boot Block Flash Memory Architecture for det ails.
Figure 16. Example Power Su pply Configurations
V
CC
V
PP
12 V Fast Programming
Absolut e Write Protection With V
PP
≤
V
PPLK
System Supply
12 V Supply
10
≤
K
Ω
V
CC
V
PP
System Supply
12 V Supply
Low V olt age and 12 V Fast P rogramming
V
CC
V
PP
System Supply
Prot#
(Logic Signal)
V
CC
V
PP
System Supply
Low-Volt age Program ming
Low-Volt age Program ming
Absolute Write Protection via Logic S ignal
(Note 1)
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
54 Order Number: 290645, Revision: 022
Appendix A Write State Machine States
Table 25 and Table 26 show the Wr ite State Machine command state transitions based on incoming
commands.
Tab le 25. Write State Machine States
Co m man d I nput (and N ext State)
Current State SR.7 Data
When
Read Read Arra y
(FFH) Program
Setup (10/
40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0)
Read
Status
(70H)
Clear
Status
(50H)
Re ad Arra y “1” Array Read Array Prog. S etup Ers. Setup Read Array Read Sts. Read Array
Read Status “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Read Config. “1” Co nfig Read Array Prog. Setup E rs. Setup Read Array Read Sts. Read Array
Read Query “1” CFI Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Lock S et up “1” Status Lock Comm and Err or Lock (Done) Lock
Cmd. Error Lock
(Done) Lock Cmd. Error
Lock C m d. Error “1” Status Read Arra y Prog. Setup Er s. Setup Read Array Read Sts. Read Array
Lock Oper. (Done) “1” Status Read Array Prog. Setup Ers. Setup R ead Array Read Sts. Read Array
Prot. Prog. Setup “1” Status Protection Register Program
Prot. Prog.
(Not Done) “0” Status Prote ct ion Re gi st er Program (Not Done)
Prot. Prog. (Done) “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Prog. Setup “1” Status Program
Program (Not Done) “0” Stat us Progra m (N ot Done ) Pro g . Sus.
Status Program (Not Done)
Prog. Susp. Status “1” S ta tu s Prog. Sus .
Read Array P rogram Suspend
Re ad A rray Pro g . (Not
Done) Prog . Sus.
Rd. Array Pro gram
(Not Done) Prog. Sus .
Status Prog. Su s.
Rd. Array
Prog. Susp. Read
Array “1” Array Prog. Sus .
Read Array P rogram Suspend
Re ad A rray Pro g . (Not
Done) Prog . Sus.
Rd. Array Pro gram
(Not Done) Prog. Sus .
Status Prog. Su s.
Rd. Array
Prog. Susp. Read
Config “1” Config Prog. Sus .
Read Array P rogram Suspend
Re ad A rray Pro g . (Not
Done) Prog . Sus.
Rd. Array Pro gram
(Not Done) Prog. Sus .
Status Prog. Su s.
Rd. Array
Prog. Susp. Read
Query “1” CFI Prog. Sus.
Read Array P rogram Suspend
Re ad A rray Pro g . (Not
Done) Prog . Sus.
Rd. Array Pro gram
(Not Done) Prog. Sus .
Status Prog. Su s.
Rd. Array
Program (Done) “1” Status Rea d Array Prog. S etup Ers. Setup Read Array Read Status Read Array
Erase Setup “1 ” Status Erase Command Error Erase
(Not Done) Erase Cmd.
Error Erase
(Not Done) Er ase Comman d Error
Erase Cmd. Erro r “1” Stat us Rea d Array Prog. Setup Er s. Setup Read Array Read Status Read Array
Erase (Not Do ne) “0” Stat us Erase (Not Done) E r ase Sus.
Status Eras e ( Not Done)
Ers. Susp. Status “1” Status Erase Sus.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Su s. Rd .
Array Erase Erase Sus.
Status Ers. S us.
Rd. Array
Erase Susp. Array “1” Array Er ase Sus.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Su s. Rd .
Array Erase Erase Sus.
Status Ers. S us.
Rd. Array
Ers. Susp. Read
Config “1” Config Erase Su s.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Su s. Rd .
Array Erase Erase Sus.
Status Ers. S us.
Rd. Array
Ers. Susp. Read
Query “1” CFI Erase Sus.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Su s. Rd .
Array Erase Erase Sus.
Status Ers. S us.
Rd. Array
Erase (Done) “1” Stat us Rea d Array Prog. S etup Ers. Setup Read Array Read Sts. Read Array
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 55
Table 26. Write State Machine States, Continued
Command Input (and Next State)
Current State Re ad Config
(90H) Read Q uery
(98H) Lock Set up
(60H) Prot. P rog. Se tup
(C0H) Lock Confirm
(01H) Lock Down
Confirm
(2FH) Unlock Confirm
(D0H)
Read Arr ay R ead Co nfig. R ead Qu er y Lock Se tup Prot. Pr og. Setup Rea d A rray
Re ad Status Re ad Config. Read Qu er y Lock Se t up Prot. Prog. Setup Read Array
Read C onfig. Read Confi g. Read Q uery L ock Setup Prot. Prog. Setup Read Array
Re ad Query R ead Co nf ig. Read Quer y Lock Setup Prot. Prog. S et up Read Array
Lock S etup Locki ng Command Error Lock Operation (Don e)
Lock C m d. Error Re ad Confi g. Read Q uery L ock Setup Pro t. P r og. Setup Read Array
Lock Oper. (Don e) R ead Config. Read Q uery Lock Set up Pro t. P r og. Setup Read Array
Prot. Prog. Setup Protection Register Program
Prot. Pr o g.
(Not Do ne) Protect ion Regist er P r og r am (Not Don e)
Prot. Prog. (Done) R ead Co nfig. R ead Qu er y Lock Se tup Prot. Pr og. Setup Read Array
Prog. Set up Program
Program
(Not Do ne) Program (Not Done)
Prog. Susp. Status Prog . Sus p. Read
Config. P rog. Susp. Read
Query Program Suspend R ead Arr ay Program
(Not Do ne)
Prog . Susp. Read
Array Pr og. Susp. Read
Config. P rog. Susp. Read
Query Program Suspend R ead Arr ay Program
(Not Do ne)
Prog . Susp. Read
Config. P rog . Sus p. Read
Config. P rog. Susp. Read
Query Program Suspend R ead Arr ay Program
(Not Do ne)
Prog . Susp. Read
Query. Prog . Sus p. Read
Config. P rog. Susp. Read
Query Program Suspend R ead Arr ay Program
(Not Do ne)
Program
(Done) Read Co nf i g. Read Query Lock Se tup Prot. Pr og. Setup Read Array
Erase
Setup Erase Command Error Erase
(Not Do ne)
Erase Cmd. E rror Read Config. Read Q uery Lock Set up Pro t. Prog . Set up Read Array
Erase
(Not Do ne) Erase (Not Done)
Erase Susp .
Status Ers. Susp. Read
Config. Erase Su spend
Read Query Lock Setup Erase Suspend Read Arr a y Erase
(Not Do ne)
Erase Susp end
Array Ers. Susp. Read
Config. Erase Su spend
Read Query Lock Setup Erase Suspend Read Arr a y Erase
(Not Do ne)
Eras Sus. Read
Config Eras e Suspen d
Re ad Confi g. Erase Suspen d
Read Query Lock Setup Erase Suspend Read Arr a y Erase
(Not Do ne)
Eras Sus. Read
Query Eras e Suspend
Re ad Confi g. Erase Suspen d
Read Query Lock Setup Erase Suspend Read Arr a y Erase
(Not Do ne)
Ers. (Done) R ead Co nf i g. Read Query Lock Se t up Prot. Prog. Setup Read Array
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
56 Order Number: 290645, Revision: 022
Appendix B Flow Charts
Figure 17. Word Program Flowchart
Program
Suspend
Loop
Start
Write 0x40,
Word Address
Write Data,
Word Address
Read Status
Register
SR[7] =
Full Status
Check
(if desired)
Program
Complete
Suspend?
1
0
No
Yes
WORD P ROGRAM PROCEDURE
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set to the Read Array
state.
Comments
Bus
Operation Command
Data = 0 x 40
Addr = Location to program
Write Program
Setup
Data = Data to program
Addr = Location to program
Write Data
Status register data: Toggle CE# or
OE# to update Status Register
Read None
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle None
(Se tu p)
(Confi rm)
FULL STATUS CHECK PROCEDURE
Read Status
Register
Program
Successful
SR[3] =
SR[1] =
0
0
SR[4 ] =
0
1
1
1
V
PP
Range
Error
Device
Protect Error
Program
Error
SR[3] MUST be cleared before the Write State Machine will
allow further program attempts.
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register
command clears the Status Register error bits.
Idle
Idle
Bus
Operation
None
None
Command
Che ck S R[3]:
1 = V
PP
Error
Che ck S R[4]:
1 = Data Program Error
Comments
Idle None Check SR[1]:
1 = Block locked; operation aborted
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 57
Figure 18. Program Suspend / Resume Flowchart
Read Status
Register
SR[7] =
SR[2] =
Rea d Array
Data
Program
Completed
Done
Reading
Program
Resumed
Read Array
Data
0
No
0
Yes
1
1
PROGRAM SUSPEND / RESUME PROCEDURE
Write Program
Resume Data = 0 xD0
Addr = Any address
Bus
Operation Command Comments
Write Program
Suspend Data = 0xB0
Addr = Any address
Idle None Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle None Check SR[2]:
1 = Program suspended
0 = Program completed
Write Read
Array Dat a = 0x FF
Addr = Any address
Read None Read array data from block other than
the one be ing programmed
Read None
Status register data
Toggle CE# or OE# to up d ate Status
register
Addr = Any address
Write 0xFF
(Read Array)
Write 0xD0
Any Address
(Program Resume)
Write 0xFF
(Read
Array)
Write Read
Status Data = 0x70
Addr = Any address
Start
Write 0xB0
Any Address
(Program Suspend)
Write 0x70
Any Address
(Read Status)
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
58 Order Number: 290645, Revision: 022
Figure 19. Erase Suspend / Resume Flowchart
Erase
Completed
Rea d A rra y
Data
0
0
1
1
Start
Read Status
Register
SR[7] =
SR[6] =
Erase
Resumed
Done
Reading
Write
Write
Idle
Idle
Write
Erase
Suspend
Read Array
or Program
None
None
Program
Resume
Data = 0xB0
Addr = Any address
Data = 0xFF or 0x40
Addr = Any address
Check SR[7]:
1 = W SM ready
0 = W SM busy
Check SR[6]:
1 = Erase suspended
0 = Erase co mple t e d
Data = 0xD0
Addr = Any address
Bus
Operation Command Comments
Read None Status Register data. Toggle CE# or
OE# to update Status register;
Addr = Any Address
Read or
Write None Read array or program data from/to
block other than the one being erased
ERASE SUSPEND / RESUME PROCEDURE
Write 0x70,
Any Address (Read S tatus)
Write 0xB0,
Any Address (Erase Suspend)
Write 0xD0,
Any Address
(Erase Resume) Write 0xFF (Read Array)
Write Read
Status Data = 0x70
Addr = Any address
Read Array
Data
Write 0xFF
0
(Read Array)
1
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 59
Figure 20. Block Erase Flowchart
Start
FUL L ERASE STAT US CHECK PRO CEDUR E
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Write 0xFF after the last operation to enter read array mode.
SR[1,3] must be cleared b e fore the W rite Sta te Machine will
allow further erase attempts.
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
No
Suspend
Erase
1
0
0
0
1
1,1
1
1
0Yes
Suspend
Erase
Loop
0
Write 0x20,
Block Address
Write 0xD0,
Block Address
Read Status
Register
SR[7] =
Full E ra se
Status Check
(if desi red)
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR[1] = Block Locked
Error
BLOCK E R ASE P ROCE D URE
Bus
Operation Command Comments
Write Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write Erase
Confirm Da ta = 0xD0
Addr = Block to be erased (BA)
Read None Status Register data. Toggle CE# or
OE# to update Status register data
Idle None Check SR[7]:
1 = WSM ready
0 = WSM busy
Bus
Operation Command Comments
SR[3] = V
PP
Rang e
Error
SR[4,5] = Command
Sequence Error
SR[5] = Block Erase
Error
Idle None Check SR[3]:
1 = V
PP
Range Error
Idle None Ch eck SR[4,5]:
Both 1 = Command Sequence Error
Idle None Check SR[5]:
1 = Block Erase Error
Idle None Check SR[1]:
1 = Attempted erase of locked block;
erase aborted.
(Block Erase)
(E rase Confirm)
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
60 Order Number: 290645, Revision: 022
Figure 21. Locking Operations Flowc ha rt
No
Start
Write 0x60,
Block Address
Write 0x90
Read Block
Lock Status
Locking
Change?
Lock Chan ge
Complete
Write either
0x01/0xD0/0x2F,
Block Address
Write 0xFF
An y Ad dress
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Idle
(Optional)
Write
Lock
Setup
Lock,
Unlock , o r
Lock-Down
Confirm
Read
Device ID
Block Lock
Status
None
Read
Array
Data = 0x60
Addr = Any Address
Data = 0x01 (Block Lock)
0xD0 (B l ock Unlo ck)
0x2F (Lock-Down Block)
Addr = Block to lock/unlock/lock-down
Data = 0x90
Addr = Any Address
Block Lock status data
Addr = Block address + offset 2
Confirm locking change on D[1,0] .
Data = 0xFF
Addr = Any address
Bus
Operation Command Comments
LOCKI N G O PER AT IONS P ROCEDURE
(Lock Confirm)
(Read Device ID)
(Read Arra y)
Optional
(Lock Setup)
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 61
Figure 22. Protection Register Programming Flowchart
FULL STATUS CHECK PROCE DURE
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
Repeat for subsequen t programming operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
SR[3] must be cleared before the Write State Machine will
allow further program attempts.
Only the Clear Staus Register command clears SR[1, 3, 4].
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
1
0
1
1
PROTECTION REGISTER PROGRAMMING PROCE DURE
Start
Write 0xC0,
PR Address
Write PR
Address & Data
Read Status
Register
SR[7] =
Full Status
Check
(if desired)
Program
Complete
Read Status
Register Da ta
Program
Successful
SR[3], SR[4] = VPP
Range Error
Program Error
Register Locked;
Program Aborted
Idle
Idle
Bus
Operation
None
None
Command
Check SR[1], SR[3], SR[4]:
0,1,1 = VPP
Range Error
Check SR[1], SR[3], SR[4]:
0,0,1 = Programming Error
Comments
Write
Write
Idle
Program
PR Setup
Protection
Program
None
Data = 0xC0
Addr = First Location to Program
Data = Data to Prog ram
Addr = Location to Program
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Bus
Operation Command Comments
Read None Status Register Data. Toggle CE# or
OE# to Update Status Register Data
Idle None Check SR[1], SR[3], SR[4]:
1,0,1 = Block locked; operation aborted
(Program Setup)
(Confirm Data)
0
0
SR[3], SR[4] =
0
SR[3], SR[4] =
1
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
62 Order Number: 290645, Revision: 022
Appendix C Common Flash Interface
This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software detects which command sets to use to enable flash writes, block erases, and
otherwise control the flash component. The Query is part of an overall specification for multiple
command set and control interface descriptions called Common Flash Interface, or CFI.
C.1 Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-DQ7) only. The numerical offset
value is the address relative to the maximum bus width supported by the device. On this family of
devices, the Query table device starting address is a 0x10, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 0x10 and 0x11. This CFI-compliant device outputs 0x00 data on
upper bytes. The device outputs ASCII “Q” in the low byte (DQ0-DQ7) and 0x00 in the high byte
(DQ8-DQ15).
At Query addresses containing two or more bytes of information, the least-significant data byte is
presented at the lower address, and the most-significant data byte is presented at the higher address.
For tables in this appendix, addresses and data are represented in hexadecimal notation, so the “h”
suffix has been dropped. In addition, since the upper byte of word-wide devices is always “0x00,”
the leading “00” has been dropped from the table notation and only the lower byte value is shown.
Any x16 device outputs can be assumed to have 0x00 on the upper byte in this mode.
Table 27. Summary of Query Structure Output as a Function of Device and Mode
Device Hex Offset Hex Code ASCII Value
Device A ddr esses
00010: 51 "Q"
00011: 52 "R"
00012: 59 "Y"
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 63
C.2 Query Structure Overview
The Query c omman d causes the flash component to display the Com mon Flash Int erface (CF I)
Query structure or “database.” Table 29 summarizes the structure sub-sections and address
locations.
Table 28. Example of Query Structure Output of x16 Devices
Word Addressing:
Offset Hex Code Valu e
A[X-0] DQ[16:0]
0x00010 0051 "Q"
0x00011 0052 "R"
0x00012 0059 "Y"
0x00013 P_IDLO PrVendor
0x00014 P_IDHI ID #
0x00015 PLO PrVendor
0x00016 PHI TblAdr
0x00017 A_IDLO AltVendor
0x00018 A_IDHI ID #
... ... ...
Table 29. Query Structure
Offset Sub-Section Name Description1
0x00000 Manufa cturer Code
0x00001 Device C ode
0x(BA+2)2Blo ck Statu s r egi ster Block -s pecific infor m ation
0x00004-0xF Reserved Reserved for vendor-specific information
0x00010 CFI qu er y id entification
string Command set ID and vend or data offset
0x0001B System i nt er face
information Device timi ng & voltage informa ti on
0x00027 Device geometry definition Flash device layout
P3Primary In tel - s p ecific
Extended Query Table Vendor-defined addition al informat ion speci f ic to the Primar y
Vendor Algorithm
Notes:
1. Refer to the Q uery S tru cture Out put section an d off set 0x28 for t he deta iled defini tion of of fset addr ess
as a func tion of device bus width and m ode.
2. BA = Block Address beginnin g lo cation (i.e. , 0x 08000 is block 1’s be ginning location whe n th e block
size is 32K-word).
3. Offset 15 define s “ P” wh ich points to the Primary Intel-specific Extended Q uer y Table.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
64 Order Number: 290645, Revision: 022
C.3 Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations. See Table 30.
Block Erase Status (BSR[1] ) allows system software to determine the success of the last block
erase operation. BSR[1] can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation.
Notes:
1. BA = Block Add ress begin ning loca tion (i.e., 0x0 8000 is bl ock 1’s beginnin g location wh en the bloc k size
is 32K-word).
Tab le 30. Block Status Register
Offset Length Description Add. Value
0x(BA+2)11
Block Lock Status Register BA+2 --00 or --01
BSR[0] Bl ock lock stat us
0 = Unlocked
1 = Locked BA+2 (bit 0): 0 or 1
BSR[1] Bl ock lock-down st atus
0 = Not locked dow n
1 = Locked down BA+2 (bit 1): 0 or 1
BSR[7:2]: Reserved for future use BA+ 2 (bit 2- 7) : 0
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 65
C.4 CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s). See Table 31.
Table 31. CFI Identification
Offset Length Description Add. Hex Code Value
0x10 3 Query-unique ASCII string “QRY“ 10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
0x13 2 Primary vendor command set and control interface ID code
16-bit ID code for vendor-specif ied algorithms 13:
14: --03
--00
0x15 2 Extended Quer y Table primar y algorithm addr ess 15:
16: --35
--00
0x17 2 Alternate v endor command set and control interface ID code
0x000 0 mean s no second vendor-spe ci fi ed algorithm exists 17:
18: --00
--00
0x19 2 Secondary algorithm Extended Q uery Table addr ess
0x000 0 mean s none exists 19:
1A: --00
--00
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
66 Order Number: 290645, Revision: 022
Table 32. System Interface Information
C.5 Device Geometry Definition
Table 33. Device Geometry Definition
Offset Length Description Add. Hex Code Value
0x1B 1 VCC logic supp ly minimum program/er ase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
0x1C 1 VCC logic supp ly maximum pr ogram/er ase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.6 V
0x1D 1 VPP [programming] supply minimu m pr ogr am / erase voltage
bits 0–3 BCD 100 mV
bits 4–7 H EX volts 1D: -- B4 11.4 V
0x1E 1 VPP [programming] suppl y maximum pro gr am / er ase voltage
bits 0–3 BCD 100 mV
bits 4–7 H EX volts 1E: --C6 12.6 V
0x1F 1 “n” suc h that typical si ngle word program time-out =2n µs 1F : --05 32 µs
0x20 1 “n” suc h th at typical max. buffer w ri t e ti m e-out = 2n µs 20: - -00 NA
0x21 1 “n” suc h th at typical block erase time - out = 2n ms 21: --0A 1 s
0x22 1 “n” suc h th at typical full chi p er ase time-out = 2n ms 22: - -00 NA
0x23 1 “n” suc h th at maximum wo r d pr ogram time- out = 2n ti m es t yp i c al 23: --04 512µs
0x24 1 “n” suc h th at maximum buffer write time-out = 2n times ty pical 24: --00 NA
0x25 1 “n” suc h th at maximum bl ock er ase time -o ut = 2n ti m es t ypical 25: --03 8s
0x26 1 “n” suc h th at maximum chip erase tim e- out = 2n times typical 26: - -00 NA
Offset Length Description Add. Hex
Code Value
0x27 1 “n” such that device size = 2n in number of bytes 27 See T able 34, “Device
Geometry Details” on
page 67
0x28 2 Flash device interface: x8 async
28:00,29:00 x16 asyn c
28:01,29:00 x8/x16 a syn c
28:02,29:00 28:
29: --01
--00 x16
0x2A 2 “n” such that maximum number of bytes in write buffer = 2n2A:
2B: --00
--00 0
0x2C 1
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions
with one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
2C: --02 2
0x2D 4 Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-siz e erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2D:
2E:
2F:
30:
See T able 34, “Device
Geometry Details” on
page 67
0x2D 14 Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-siz e erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
31:
32:
33:
34:
See T able 34, “Device
Geometry Details” on
page 67
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 67
Table 34. Device Geometry Details
Address 16 Mbit 32 Mbit 64 Mbit
-B -T -B -T -B -T
0x27 --15 -15 --16 -16 --17 --17
0x28 --01 --01 --01 --01 --01 --01
0x29 --00 --00 --00 -00 -00 -00
0x2A --00 --00 --00 -00 -00 -00
0x2B --00 --00 --00 -00 -00 -00
0x2C --02 --02 --02 --02 --02 --02
0x2D --07 --1E --07 --3E --07 --7E
0x2E --00 --00 --00 -00 -00 -00
0x2F --20 --00 --20 -00 --20 --00
0x30 --00 --01 --00 --01 --00 --01
0x31 --1E --07 --3E --07 --7E --07
0x32 --00 --00 --00 -00 -00 -00
0x33 --00 --20 --00 --20 --00 --20
0x34 --01 --00 --01 --00 --01 --00
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
68 Order Number: 290645, Revision: 022
C.6 Intel-Specific Extended Query Table
Certain flash features and commands are optional as shown in Table 35, “Primary-Vendor Specific
Extended Query” on page 68. The Intel-specific Extended Query table specifies these features as
well as other similar types of information.
Table 35. Primary-Vendor Specific Extended Query
Offset1
P = 0x15 Length Description
(Optional Flash Feat ures and Commands) Address Hex Code Value
0x(P+0)
0x(P+1)
0x(P+2) 3Pr imary extended query t able
Unique ASCII string “PRI” 35:
36:
37:
--50
--52
--49
“P”
“R”
“I”
0x(P+3) 1 Ma jor version number, ASCII 38: --31 “1”
0x(P+4) 1 Minor version number, ASCII 39: --30 “0”
0x(P+5)
0x(P+6)
0x(P+7)
0x(P+8) 4
Optional feature and command support (1=yes,
0=no)
bits 9– 31 ar e res erved ; und ef ined b it s are “0.” If b it
31 is “1” th en anothe r 31 bit fi eld of optio nal
features follow s at the end of the bit-30 field.
3A:
3B:
3C:
3D:
--66
--00
--00
--00
bit 0 Chip er ase suppor t ed
bit 1 Susp end erase supported
bit 2 Susp end program supporte d
bit 3 Legacy lock/unl ock supported
bit 4 Que ued erase supported
bit 5 Instant indi vidual block l ocki ng supported
bit 6 Prot ection bit s supported
bit 7 Page m ode read supported
bit 8 Synchronous r ead support ed
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
No
Yes
Yes
No
No
Yes
Yes
No
No
0x(P+9) 1
Supp or t ed functions after suspend: Read Array,
St atus, Query
Other supported ope ra ti ons are:
bits 1–7 res erved; undefi ned bits are “0”
3E: --01
bit 0 Progr am suppor te d after erase suspend bit 0 = 1 Yes
0x(P+A)
0x(P+B) 2B lock Statu s Register mask
bits 2–15 are Reserved; un defined bit s are “0”
bit 0 Block Lock-Bit Status Register act ive
bit 1 Block Lock-Down Bit Status active
3F: --03
40: --00
bit 0 = 1 Yes
bit 1 = 1 Yes
0x(P+C) 1 VCC logic supply highes t pe r fo rmance progr am/
erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts 41: --33 3.3 V
0x(P+D) 1 VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 H EX value in volt s 42: --C0 12. 0 V
Notes:
1. The variab le P is a pointe r whic h is defined at C FI offset 0x15.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 69
Table 36. Protection Register Information
Offset1
P = 0x35 Length Description
(Optional Fl as h Fe ature s an d Com m a nd s) Address Hex
Code Value
0x(P+E) 1 Number of Protection register fiel ds i n JEDEC ID space.
“00h,” indicates that 256 prot ection bytes are available 43: --01 01
0x(P+F)
0x(P+10)
(0xP+11)
4
44:
45:
46:
--80
--00
--03
80h
00h
8 byte
0x(P+12)
Prote ction Fiel d 1: Protecti on D escripti on
This field des cribes user-a vailable One T ime Progr ammabl e (OTP)
Prote ction register bytes. Some are pre- programmed with device-
unique serial numbers. Others are user programmable. Bits 0–15
point t o th e Pr otection register L ock byte, the se ct ion’s first byte.
The foll owing bytes are factor y pr e- pr ogrammed and user-
programmable.
bits 0–7 = Lock/bytes JEDEC-p lane physical low address
bits 8–15 = Lock/b yt es JEDEC -pla ne physical hig h address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user pr ogr ammab le bytes
47: --03 8 byte
0x(P+13) Reserv ed f or fu ture use 48:
Notes:
1. The variable P is a pointer which is defined at CFI offset 0x15.
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
70 Order Number: 290645, Revision: 022
Appendix D Additional Information
Order Number Document/Tool
297938 3 Volt Advanc ed+ Boot Block Flash Memory Spe c ification Update
292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block F lash Memory
292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory
Architecture
Conta ct your Inte l
Representative Intel® Flash D a ta Integr ator (Intel® FDI) Software Developer’s Kit
297874 IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC
Notes:
1.Ca ll the Inte l Literature C enter at (80 0) 548- 4725 to requ est Inte l document ation. I nternation al custome rs
shoul d contact their local Intel or distributi on sales office.
2.See the Intel page at ‘http://www.intel.com/design/flash’ for technical documentation and tools.
Intel® Advanced+ Boot Block Flash Memory (C3)
Datasheet Intel® Advanced+ Boot Block Flash Memory (C3) January 2005
Order Number: 290645, Revision: 022 71
Appendix E Ordering Information
Figure 2 3. Component Ordering Informa tion
Package
TE = 48-Lead TSOP
GT = 48-Ball µBGA* CSP
GE = VF BGA C SP
RC = Easy BGA
PC = Pb Fr ee Easy B GA
PH = Pb F r ee VF BGA
JS = Pb Free TSOP
Product line designator
for all Intel
®
F lash pro duc ts
A ccess Sp eed (ns)
(70, 80, 90, 100, 110)
Product Family
C3 = 3 Volt Adv anced+ Boot Bloc k
V
CC
= 2. 7 V –3. 6 V
V
PP
= 2.7 V–3.6 V or
11.4 V–12 .6 V
D evi ce D en si ty
640 = x1 6 (64 Mbi t)
320 = x1 6 (32 Mbi t)
160 = x1 6 (16 Mbi t)
800 = x1 6 (8 Mbi t)
T = T o p Block ing
B = Bot t o m Bl oc kin g
Lithography
A = 0. 25 µm
C = 0.18 µm
D = 0.13 µm
T E 2 8 F 3 2 0 C 3 T C 7 0
Intel® Advanced+ Boot Block Flash Memory (C3)
January 2005 Intel® Advanced+ Boot Block Flash Memory (C3) Datasheet
72 Order Number: 290645, Revision: 022
Ta ble 37. Product Information Ord ering M atrix
VALID COMBINATIONS (All Extended Temperature)
48-Lead TSOP 48-Ball µBGA* CSP 48-Ball VF BGA Easy BGA
Extended
64 Mbit TE28F640C3TC80
TE28F640C3BC80 GE28F640C3TC80
GE28F640C3BC80 RC28F640C3TC80
RC28F640C3BC80
Extended
32 Mbit
TE28F320C3TD70
TE28F320C3BD70
TE28F320C3TC70
TE28F320C3BC70
TE28F320C3TC90
TE28F320C3BC90
TE28F320C3TA100
TE28F320C3BA100
TE28F320C3TA110
TE28F320C3BA110
JS28F320C3BD70
JS28F320C3TD70
JS28F320C3BD90
JS28F320C3TD90
GT28F320C3TA100
GT28F320C3BA100
GT28F320C3TA110
GT28F320C3BA110
GE28F320C3TD70
GE28F320C3BD70
GE28F320C3TC70
GE28F320C3BC70
GE28F320C3TC90
GE28F320C3BC90
PH28F320C3BD70
PH28F320C3TD70
PH28F320C3BD90
PH28F320C3TD90
RC28F320C3TD70
RC28F320C3BD70
RC28F320C3TD90
RC28F320C3BD90
RC28F320C3TC90
RC28F320C3BC90
RC28F320C3TA100
RC28F320C3BA100
RC28F320C3TA110
RC28F320C3BA110
PC28F320C3BD70
PC28F320C3TD70
PC28F320C3BD90
PC28F320C3TD90
Extended
16 Mbit
TE28F160C3TD70
TE28F160C3BD70
TE28F160C3TC70
TE28F160C3BC70
TE28F160C3TC80
TE28F160C3BC80
TE28F160C3TC90
TE28F160C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F160C3TA110
TE28F160C3BA110
JS28F160C3BD70
JS28F160C3TD70
GT28F160C3TA90
GT28F160C3BA90
GT28F160C3TA110
GT28F160C3BA110
GE28F160C3TD70
GE28F160C3BD70
GE28F160C3TC70
GE28F160C3BC70
GE28F160C3TC80
GE28F160C3BC80
GE28F160C3TC90
GE28F160C3BC90
PH28F160C3BD70
PH28F160C3TD70
RC28F160C3TD70
RC28F160C3BD70
RC28F160C3TC70
RC28F160C3BC70
RC28F160C3TC80
RC28F160C3BC80
RC28F160C3TC90
RC28F160C3BC90
RC28F160C3TA90
RC28F160C3BA90
RC28F160C3TA110
RC28F160C3BA110
PC28F160C3BD70
PC28F160C3TD70
Extended
8 Mbit
TE28F800C3TD70
TE28F800C3BD70
TE28F800C3TA90
TE28F800C3BA90
TE28F800C3TA110
TE28F800C3BA110
JS28F800C3BD70
JS28F800C3TD70
GE28F800C3TA70
GE28F800C3BA70
GE28F800C3TA90
GE28F800C3BA90
RC28F800C3TD70
RC28F800C3BD70
RC28F800C3TA90
RC28F800C3BA90
RC28F800C3TA110
RC28F800C3BA110
PC28F800C3BD70
PC28F800C3TD70
Note: The second line of the 48-bal l µB G A p ackage top side mark sp eci fies assem bly codes. For samples
only, the first character signifi es ei ther “E” for engi neering samples or “S” for si li con daisy ch ain
samples. All other assembly codes without an “E” or “S” as the first character are production units.
