70V26S25JG - Integrated Device Technology

JANUARY 2009

DSC 2945/16



I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/W

BUSY

13L

2945 drw 01

-I/O

15L

I/O

-I/O

SEM

M/S

R/W

BUSY

I/O

-I/O

15R

I/O

-I/O

13R

SEM

(1,2)

14 14

IDT70V26S/L

HIGH-SPEED 3.3V

16K x 16 DUAL-PORT

STATIC RAM

Features

◆◆

◆True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆◆

◆High-speed access

– Commercial: 25/35/55ns (max.)

– Industrial: 25ns (max.)

◆◆

◆Low-power operation

– IDT70V26S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V26L

Active: 300mW (typ.)

Standby: 660

W (typ.)

◆◆

◆Separate upper-byte and lower-byte control for multiplexed

bus compatibility

◆◆

◆IDT70V26 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆◆

◆M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆◆

◆TTL-compatible, single 3.3V (±0.3V) power supply

◆◆

◆Available in 84-pin PGA and PLCC

◆◆

◆Industrial temperature range (-40°C to +85°C) is available

for selected speeds

◆Green parts available, see ordering information

Functional Block Diagram

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70V26 is a high-speed 16K x 16 Dual-Port Static RAM. The

IDT70V26 is designed to be used as a stand-alone 256K-bit Dual-Port

RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-

more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM

approach in 32-bit or wider memory system applications results in full-

speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by CE permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 300mW of power.

The IDT70V26 is packaged in a ceramic 84-pin PGA and

84-Pin PLCC.

Pin Configura tions(1,2,3)

NOTES:

1. All VDD pins must be connected to power supply.

2. All VSS pins must be connected to ground supply.

3. Package body is approximately 1.15 in x 1.15 in x .17 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

2945 drw 02

INDEX

11109876543218483

33 34 35 36 37 38 39 40 41 42 43 44 45

I/O

32 46 47 48 49 50 51 52 53

82 81 80 79 78 77 76 75

BUSY

IDT70V26J

J84-1

(4)

84-Pin PLCC

Top View

(5)

M/S

I/O

10L

11L

12L

13L

14L

15L

I/O

BUSY

I/O

R/W

SEM

12L

I/O

11L

10L

I/O

10R

11R

12R

13R

14R

15R

12R

11R

10R

R/W

SEM

13R

13L

07/21/03

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

NOTES:

1. All VDD pins must be connected to power supply.

2. All VSS pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Configurations(1,2,3) (con't.)

Left Po rt Ri ght Por t Names

Chip Enable

R/W

Re ad/Write Enable

Outp ut E nab le

- A

13L

- A

13R

Address

I/O

- I/ O

15L

I/O

- I/O

15R

Data Inp ut/O utput

SEM

Semaphore Enable

Up p er By te Se lect

Lo we r B yte S e le c t

BUSY

Busy Flag

M/SMaster or Slave Select

Powe r (3.3V)

Gro und (0V)

2945 t b l 01

2945 drw 03

I/O

63 61 60 58 55 54 51 48 46 45

125

14 17 20

28 29

32 31

33 35

IDT70V26G

G84-3

(4)

84-Pin PGA

Top View

(5)

ABCDEFGHJKL

59 56 49 50 40

84 3 4 6 9 15 13 16 18

22 24

19 21

57 53 52

47 44

R/W

SEM

R/W

SEM

13R

BUSY

M/S

13L

11L

ndex

I/O

10L

I/O

11L

I/O

13L

I/O

12L

I/O

15L

I/O

14L

I/O

10L

10R

11R

I/O

11R

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

12R

12L

07/21/03

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table II — Semaphore Read/Write Control(1)

Truth Table I — Non-Contention Read/Write Control

NOTE:

1. A0L — A 13L≠ A0R — A13R

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A 0-A2.

Inputs

(1)

Outputs

Mode

CE R/WOE UB LB SEM I/O

8-15

I/O

0-7

HXXXXHHigh-ZHigh-ZDeselected: Power-Down

X X X H H H High-Z Hig h-Z Both Bytes De se le cte d: Powe r-Down

LLXLHHDATA

High-Z Write to Upper Byte Only

LLXHLHHigh-ZDATA

Wr ite to Lower By te O nly

LLXLLHDATA

DATA

Write to Both Bytes

LHLLHHDATA

OUT

Hig h-Z Read Upp er Byte Only

LHLHLHHigh-ZDATA

OUT

Read Lower Byte Only

LHLLLHDATA

OUT

DATA

OUT

Read Both Bytes

XXHXXXHigh-ZHigh-ZOutputs Disabled

2945 tbl 02

Inputs

(1)

Outputs

Mode

CE R/WOE UB LB SEM I/O

8-15

I/O

0-7

HHLXXLDATA

OUT

DATA

OUT

Read Data in Semap hore Flag

XHLHHLDATA

OUT

DATA

OUT

Read Data in Semap hore Flag

H↑XXXLDATA

DATA

Write I/O

into Semaphore Flag

X↑XHHLDATA

DATA

Write I/O

into Semaphore Flag

LXXLXL

____ ____

Not Allo we d

LXXXLL

____ ____

Not Allo we d

2945 tbl 03

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Absolute Maximum Ra tings(1) Maximum Opera ting Temperature

and Supply Voltage(1)

Recommended DC Operating

Conditions(2)

Capacitance(1) (TA = +25°C, f = 1.0MH z)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.

3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed VDD + 0.3V.

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

NOTE:

1. At VDD < 2.0V, input leakages are undefined.

Symbol Rating Commercial

& Ind ustr ial Unit

TERM(2)

Terminal Volt age

wi th Res p e c t to GND -0.5 to +4.6 V

BIAS

Te mp e rature Und er B ias -55 to +125

STG

Sto rag e Te m p e rature -65 to + 150

J unction Tem p e rature +150

OUT

DC Output Cu rrent 5 0 m A

2945 tb l 04

Grade Ambient Temperature GND V

Commercial 0

C to +70

C0V3.3V + 0.3

Industrial -40

C to + 85

C0V3.3V + 0.3

2945 tbl 05

Symbol Parameter Conditions

(2)

Max. Unit

Inp ut Cap acitanc e V

= 3dV 9 pF

OUT

Outp ut Cap ac itance V

OUT

= 3dV 10 pF

2945 tbl 07

Sym bol Parameter Test Conditions

70V26S 70V26L

UnitMin. Max. Min. Max.

| Inp ut L e ak age Curre n t

(1)

= 3.6V, V

= 0V t

___

5µA

| Ou tp ut L e ak age Cur re nt CE = V

, V

OUT

= 0V t

___

5µA

Ou tp ut L o w Vo l tag e I

= +4mA

___

0.4

___

0.4 V

Outp ut Hig h Vo lta ge I

= -4mA 2.4

___

2.4

___

2945 tbl 08

Symbol Parameter Min. Typ. Max. Unit

Sup p ly Vo ltag e 3. 0 3.3 3.6 V

Ground 0 0 0 V

Input High Voltage 2.0

____

+ 0.3

(2)

Inp ut Lo w Vo ltag e -0. 3

(1)

____

0.8 V

2945 tb l 06

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

A C Test Conditions

DC Electrical Characteristics Over the Operating

T emperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VDD = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of

GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

Figure 1. AC Output Test Load Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

70V26X25

Com'l

& Ind

70V26X35

Com'l Only 70V26X55

Com'l Only

S ym bo l P aram et er Test Condi ti on Versi on Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

Dynamic Ope rating

Current

(Both Ports Active )

CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(3)

COM'L S

L100

100 170

140 90

90 140

120 90

90 140

120 mA

IND S

L100

100 200

185

____

SB1

Stand by Current

(B o th Po rts - TTL

L e v e l Inp u ts )

= CE

= V

SEM

= SEM

= V

f = f

MAX

(3)

COM'L S

L14

12 30

24 12

10 30

24 12

10 30

24 mA

IND S

L14

12 60

____

SB2

Stand by Current

(On e P o rt - TTL

L e v e l Inp u ts )

"A"

= V

and CE

"B"

= V

(5)

A c ti v e P o rt Outputs Dis a b l e d ,

f=f

MAX

(3)

SEM

= SEM

= V

COM'L S

L50

50 95

85 45

45 87

75 45

45 87

75 mA

IND S

L50

50 130

105

____

SB3

F ull S tand b y Curre nt

(Bo th Po rts -

CMOS Lev el Inputs)

Both Ports CE

and

> V

- 0.2V,

> V

- 0.2V o r

< 0.2V, f = 0

(4)

SEM

= SEM

> V

- 0. 2V

COM'L S

L1.0

0.2 6

31.0

0.2 6

31.0

0.2 6

3mA

IND S

L1.0

0.2 6

____

SB4

F ull S tand b y Curre nt

(One P o rt -

CMOS Lev el Inputs)

"A"

< 0.2V and

"B"

> V

- 0. 2V

(5)

SEM

= SEM

> V

- 0. 2V

> V

- 0.2V o r V

< 0.2V

A c ti v e P o rt Outputs Dis a b l e d ,

f = f

MAX

(3)

COM'L S

L60

60 90

80 55

55 85

74 55

55 85

74 mA

IND S

L60

60 125

____

2945 tb l 09

Input Pulse Levels

Inp ut Ris e /Fal l Time s

Inp ut Timi ng Refe rence Le v els

Outp ut Re fe re nc e Le v e ls

Outp ut Lo ad

GND to 3. 0V

3ns Max .

1.5V

Fi gures 1 and 2

2945 tbl 10

2945 drw 05

590Ω

30pF

435Ω

3.3V

DATA

OUT

BUSY

590Ω

5pF*

435Ω

3.3V

DATA

OUT

2945 drw 04

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

Timing of Power-Up Power-Down

2945 drw 06

50% 50%

70V26X25

Com'l

& In d

70V26X35

Com'l Only 70V26X55

Com'l Only

UnitSymbol Parameter Min. Max. Min. Max. Min. Max.

RE AD CYCL E

Read Cy cl e Time 25

____

Add ress Access Time

____

55 ns

ACE

Chip Enable Acce ss Time(3)

____

55 ns

ABE

Byte Enab le Acce ss Time (3)

____

55 ns

AOE

Output Enable Access Time

____

30 ns

Outp ut Hold fro m A dd re s s Chang e 3

____

Output Low-Z Time (1,2) 3

____

Output High-Z Time (1,2)

____

25 ns

Chip Enable to Power Up Time(2) 0

____

Chi p Dis able to P ower Down Tim e (2)

____

50 ns

SOP

Semaphore Flag Update Pulse (OE or SEM)15

____

SAA

Semaphore Ad dre ss Access Time

____

65 ns

2945 tb l 1

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Read Cyc les(5)

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and

temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part numbers indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

R/W

ADDR

UB,LB

2945 drw 07

(4)

ACE

(4)

AOE

(4)

ABE

(4)

(1)

(2)

(3,4)

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

Symbol Parameter

70V26X25

Com'l

& Ind

70V26X35

Com'l Only 70V26X55

Com'l O nly

UnitMin. Max. Min. Max. Min. Max.

WR I TE C YCL E

Write Cy cle Time 25

____

Chip Enable to End-o f-Write

(3)

____

Address Valid to End-of-Write 20

____

Address Set-up Time

(3)

____

Write Pulse Width 20

____

Write Recove ry Time 0

____

Da ta Vali d to E nd-o f-W ri te 1 5

____

Outp ut Hig h-Z Time

(1,2)

____

25 ns

Da ta Ho l d Ti me

(4)

____

Write Enab le to Outp ut in Hig h-Z

(1,2)

____

25 ns

Ou tp ut A c tiv e fro m En d -o f-Wri te

(1,2,4)

____

SWRD

SEM Fl ag Wri te to Re ad Tim e 5

____

SPS

SEM Flag Co nte ntio n Wi nd ow 5

____

2945 tbl 12

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Wavefo rm of Write Cycle No. 1, R/ W Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or UB and LB must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/ W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the

bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)

R/W

DATA

OUT

(2)

ADDRESS

DATA

(6)

(4) (4)

(7)

CE or SEM

2945 drw 08

(9)

CE or SEM

(9)

(7)

(3)

2945 drw 09

ADDRESS

DATA

R/W

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

Timing Waveform of Semaphore Write Contention(1,3,4)

NOTES:

1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID' represents all I/O's (I/O0-I/O15) equal to the semaphore value.

SEM

2945 drw 10

SOP

I/O

VALID ADDRESS

SAA

R/W

ACE

VALID ADDRESS

DATA

VALID DATA

OUT

SWRD

AOE

Read CycleWrite Cycle

-A

VALID

(2)

SEM

"A"

2945 drw 11

SPS

MATCH

R/W

"A"

MATCH

0"A"

-A

2"A"

SIDE "A"

(2)

SEM

"B"

R/W

"B"

0"B"

-A

2"B"

SIDE

(2)

"B"

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

2945 drw 12

APS

ADDR

"A"

DATA

OUT "B"

MATCH

R/W

"A"

DATA

IN "A"

ADDR

"B"

VALID

(1)

MATCH

BUSY

"B"

BDA

VALID

BDD

DDD

(3)

WDD

BAA

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6)

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part number indicates power rating (S or L).

Timing W av eform of Write with Port-to-Port Read and BUSY(2,4,5)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

70V26X25

Com'l

& I nd

70V26X35

Com'l Only 70V26X55

Com'l Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

BUSY TIMING (M/S = V

)

BAA

BUSY Access Time from Address Match

____

45 ns

BDA

BUSY Disable Time from Address Not Match

____

45 ns

BAC

BUSY Access Time from Chip Enable Low

____

45 ns

BDC

BUSY Disable Time from Chip Enable High

____

45 ns

APS

Arbitration Prio rity Se t-up Time

(2)

____

BDD

BUSY Disable to Valid Data

(3)

____

50 ns

Write Hold After BUSY

(5)

____

BUSY INPUT TIMING (M/S = VIL)

BUSY Inp ut to Write

(4)

____

Write Hold After BUSY

(5)

____

P ORT-T O-P ORT DE L AY T I MI NG

WDD

Write Puls e to Data Delay

(1)

____

85 ns

DDD

Wr i te D a ta Vali d to R ea d D a ta Del a y

(1)

____

80 ns

2945 tb l 13

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.

Wavef orm of BUSY Arbitration Controlled by CE Timing(1)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing

(1)

2945 drw 13

R/W

"A"

BUSY

"B"

R/W

"B"

(1)

(2)

2945 drw 14

ADDR

"A"

and

"B"

ADDRESSES MATCH

"A"

"B"

BUSY

"B"

APS

BAC

BDC

(2)

2945 drw 15

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

APS

BAA

BDA

(2)

MATCHING ADDRESS "N"

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V26 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70V26 has an automatic power down

feature controlled by CE. The CE controls on-chip power down circuitry

that permits the respective port to go into a standby mode when not

selected (CE HIGH). When a port is enabled, access to the entire

memory array is permitted.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

RAM have accessed the same location at the same time. It also allows

one of the two accesses to proceed and signals the other side that the

RAM is “busy”. The BUSY pin can then be used to stall the access until

the operation on the other side is completed. If a write operation has

been attempted from the side that receives a BUSY indication, the

write signal is gated internally to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applica-

tions. In some cases it may be useful to logically OR the BUSY outputs

together and use any BUSY indication as an interrupt source to flag an

illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in

slave mode with the M/S pin. Once in slave mode the BUSY pin

operates solely as a write inhibit input pin. Normal operation can be

programmed by tying the BUSY pins HIGH. If desired, unintended

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V26 are push

pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.

2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable

inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when

BUSYR outputs are driving LOW regardless of actual logic level on the pin.

Truth Table III — Address BUSY

Arbitration

Truth Table IV — Example of Semaphore Procurement Sequence(1,2,3)

NOTE:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V26.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Inputs Outputs

Function

-A

13L

-A

13R

BUSY

(1)

BUSY

(1)

XXNO MATCH H H Normal

HX MATCH H H Normal

XH MATCH H H Normal

L L MATCH (2) (2) Write Inhib it

(3)

2945 tbl 14

Functions D

- D

Left D

- D

Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Rig ht P ort Wri te s "0" to Se map hore 0 1 No chang e . Rig ht s ide has no write acc es s to se map hore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Po rt Write s "0" to Se map ho re 1 0 No chang e. Left port has no write ac ce ss to s e map hore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

2945 tbl 15

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

write operations can be prevented to a port by tying the BUSY pin for

that port LOW.

The BUSY outputs on the IDT 70V26 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

Width Expansion with BUSY Logic

Master/Slave Arrays

When expanding an IDT70V26 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAM

array will receive a BUSY indication, and to output that indication. Any

are completely independent of each other. This means that the activity

on the left port in no way slows the access time of the right port. Both

ports are identical in function to standard CMOS Static RAM and can

be read from, or written to, at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port SRAM. These devices have an automatic power-

down feature controlled by CE, the Dual-Port SRAM enable, and SEM,

the semaphore enable. The CE and SEM pins control on-chip power

down circuitry that permits the respective port to go into standby mode

when not selected. This is the condition which is shown in Truth Table

I where CE and SEM are both HIGH.

Systems which can best use the IDT70V26 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT70V26's

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V26 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port SRAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that shared

resource is in use. If the left processor wants to use this resource, it

requests the token by setting the latch. This processor then verifies its

success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side

processor has set the latch first, has the token and is using the shared

resource. The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

The eight semaphore flags reside within the IDT70V26 in a

separate memory space from the Dual-Port SRAM. This address

space is accessed by placing a LOW input on the SEM pin (which acts

as a chip select for the semaphore flags) and using the other control

pins (Address, OE, and R/W) as they would be used in accessing a

Figure 3. Busy and chip enable routing for both width and depth expansion

with IDT70V26 RAMs.

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT70V26 SRAM the BUSY pin is an output if the part is used as a

master (M/ S pin = H), and the BUSY pin is an input if the part used as

a slave (M/S pin = L) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actual write pulse can be initiated with either the R/W signal or the byte

enables. Failure to observe this timing can result in a glitched internal

write inhibit signal and corrupted data in the slave.

Semaphores

The IDT70V26 is an extremely fast Dual-Port 16K x 16 CMOS

Static RAM with an additional 8 address locations dedicated to binary

semaphore flags. These flags allow either processor on the left or right

side of the Dual-Port SRAM to claim a privilege over the other

processor for functions defined by the system designer’s software. As

an example, the semaphore can be used by one processor to inhibit

the other from accessing a portion of the Dual-Port SRAM or any other

shared resource.

The Dual-Port SRAM features a fast access time, and both ports

2945 drw 16

MASTER

Dual Port

RAM

BUSY

MASTER

Dual Port

RAM

BUSY

SLAVE

Dual Port

RAM

BUSY

SLAVE

Dual Port

RAM

BUSY

DECODER

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

standard Static RAM. Each of the flags has a unique address which

can be accessed by either side through address pins A0 – A2. When

accessing the semaphores, none of the other address pins has any

effect.

When writing to a semaphore, only data pin D0 is used. If a LOW

level is written into an unused semaphore location, that flag will be set

to a zero on that side and a one on the other side (see Truth Table IV).

That semaphore can now only be modified by the side showing the

zero. When a one is written into the same location from the same side,

the flag will be set to a one for both sides (unless a semaphore request

from the other side is pending) and then can be written to by both sides.

The fact that the side which is able to write a zero into a semaphore

subsequently locks out writes from the other side is what makes

semaphore flags useful in interprocessor communications. (A thor-

ough discussion on the use of this feature follows shortly.) A zero

written into the same location from the other side will be stored in the

semaphore request latch for that side until the semaphore is freed by

the first side.

When a semaphore flag is read, its value is spread into all data bits

so that a flag that is a one reads as a one in all data bits and a flag

containing a zero reads as all zeros. The read value is latched into one

side’s output register when that side's semaphore select (SEM) and

output enable (OE) signals go active. This serves to disallow the

semaphore from changing state in the middle of a read cycle due to a

write cycle from the other side. Because of this latch, a repeated read

of a semaphore in a test loop must cause either signal (SEM or OE) to

go inactive or the output will never change.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Truth Table IV). As an example, assume a

processor writes a zero to the left port at a free semaphore location. On

a subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side during

subsequent read. Had a sequence of READ/WRITE been used

instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag low and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first side’s request latch. The

second side’s flag will now stay low until its semaphore request latch

is written to a one. From this it is easy to understand that, if a

semaphore is requested and the processor which requested it no

longer needs the resource, the entire system can hang up until a one

is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making

the request, the first side to make the request will receive the token. If

both requests arrive at the same time, the assignment will be arbitrarily

made to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is

secure. As with any powerful programming technique, if semaphores

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any sema-

phore request flag which contains a zero must be reset to a one, all

semaphores on both sides should have a one written into them at

initialization from both sides to assure that they will be free when

needed.

Using Semaphores—Some Examples

Perhaps the simplest application of semaphores is their applica-

tion as resource markers for the IDT70V26’s Dual-Port RAM. Say the

16K x 16 RAM was to be divided into two 8K x 16 blocks which were

to be dedicated at any one time to servicing either the left or right port.

Semaphore 0 could be used to indicate the side which would control

the lower section of memory, and Semaphore 1 could be defined as the

indicator for the upper section of memory.

To take a resource, in this example the lower 8K of Dual-Port RAM,

the processor on the left port could write and then read a zero in to

Semaphore 0. If this task were successfully completed (a zero was

read back rather than a one), the left processor would assume control

of the lower 8K. Meanwhile the right processor was attempting to gain

control of the resource after the left processor, it would read back a one

in response to the zero it had attempted to write into Semaphore 0. At

this point, the software could choose to try and gain control of the

second 8K section by writing, then reading a zero into Semaphore 1.

If it succeeded in gaining control, it would lock out the left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could

Figure 4. IDT70V26 Semaphore Logic

2945 drw 17

0DQ

WRITE D

WRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT

RPORT

SEMAPHORE

READ SEMAPHORE

READ

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

undo its semaphore request and perform other tasks until it was able

to write, then read a zero into Semaphore 1. If the right processor

performs a similar task with Semaphore 0, this protocol would allow the

two processors to swap 8K blocks of Dual-Port RAM with each other.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the

Dual-Port RAM or other shared resources into eight parts. Sema-

phores can even be assigned different meanings on different sides

rather than being given a common meaning as was shown in the

example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory

during a transfer and the I/O device cannot tolerate any wait states.

With the use of semaphores, once the two devices has determined

which memory area was “off-limits” to the CPU, both the CPU and the

I/O devices could access their assigned portions of memory continu-

ously without any wait states.

Semaphores are also useful in applications where no memory

“WAIT” state is available on one or both sides. Once a semaphore

handshake has been performed, both processors can access their

assigned RAM segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one

processor may be responsible for building and updating a data

structure. The other processor then reads and interprets that data

structure. If the interpreting processor reads an incomplete data

structure, a major error condition may exist. Therefore, some sort of

arbitration must be used between the two different processors. The

building processor arbitrates for the block, locks it and then is able to

go in and update the data structure. When the update is completed, the

data structure block is released. This allows the interpreting processor

to come back and read the complete data structure, thereby guaran-

teeing a consistent data structure.

6.42

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

2945 drw 18

Power

999

Speed

Package

Process/

Temperature

Range

Blank

(1)

Commercial (0°Cto+70°C)

Industrial (-40°Cto+85°C)

J84-pin PGA (G84-3)

84-pin PLCC (J84-1)

LStandard Power

Low Power

XXXXX

Device

Type

256K (16K x 16) 3.3V Dual-Port RAM70V26

Speed in nanoseconds

Commercial & Industrial

Commercial Only

Blank

(3)

WW Die Stepping Only

(2)

Green

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

3/25/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 and 3 Added additional notes to pin configurations

6/10/99: Changed drawing format

8/6/99: Page 1 Removed Preliminary

8/30/99: Page 1 Changed 660mW to 660µW

11/12/99: Replaced IDT logo

6/6/00: Page 5 Increased storage temperature parameter & Clarified TA parameter

Page 6 DC Electrical parameters–changed wording from "open" to "disabled"

Changed ±200mV to 0mV in notes

07/21/03: Page 2 & 3 Added date revision to pin configurations

Page 2, 3, 5 -8 & 11 Changed naming conventions from VCC to VDD and from GND to V SS

Page 6 Added Industrial temp to DC Electrical Characteristics for standard power and low power for 25ns speed

Page 7, 8 & 11 Added Industrial temp to AC Electrical Characteristics for 25ns speed

Page 1 & 17 Added Industrial temp at 25ns to Features and in ordering information

Page 1 & 17 Updated IDT logo from TM to ®®

®®

02/15/08: Page 1 Added green availability to features

Page 17 Added green indicator to ordering information

Page 17 Added die stepping indicator to ordering information

01/19/09: Page 17 Removed "IDT" from orderable part number

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

NOTES:

1. For other speeds, packages and powers contact your sales office.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

3. All qualified die steppings.

