PCA9554/PCA9554A
8-bit I2C and SMBus I/O port with interrupt
Product data
Supersedes data of 2002 May 13 2002 Jul 26
INTEGRATED CIRCUITS
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2
2002 Jul 26 853-2243 28672
FEATURES
•Operating power supply voltage range of 2.3 to 5.5 V
•5 V tolerant I/Os
•Polarity inversion register
•Active low interrupt output
•Low stand-by current
•Noise filter on SCL/SDA inputs
•No glitch on power-up
•Internal power-on reset
•8 I/O pins which default to 8 inputs
•0 to 400 kHz clock frequency
•ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
•Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
•Four packages offered: SO16, SSOP16, TSSOP16, and
HVQFN16
DESCRIPTION
The PCA9554 and PCA9554A are 16-pin CMOS devices that
provide 8 bits of General Purpose parallel Input/Output (GPIO)
expansion for I2C/SMBus applications and were developed to
enhance the Philips family of I@C I/O expanders. The improvements
include higher drive capability, 5V I/O tolerance, lower supply
current, individual I/O configuration, 400 kHz clock frequency, and
smaller packaging. I/O expanders provide a simple solution when
additional I/O is needed for ACPI power switches, sensors,
pushbuttons, LEDs, fans, etc..
The PCA9554/54A consist of an 8-bit Configuration register (Input or
Output selection); 8-bit Input register, 8-bit Output register and an
8-bit Polarity inversion register (Active high or Active low operation).
The system master can enable the I/Os as either inputs or outputs
by writing to the I/O configuration bits. The data for each Input or
Output is kept in the corresponding Input or Output register. The
polarity of the read register can be inverted with the Polarity
Inversion Register. All registers can be read by the system master .
Although pin to pin and I2C address compatible with the PCF8574
series, software changes are required due to the enhancements and
are discussed in Application Note AN469.
The PCA9554/54A open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C address and
allow up to eight devices to share the same I2C/SMBus. The
PCA9554A is identical to the PCA9554 except that the fixed I2C
address is different allowing up to sixteen of these devices (eight of
each) on the same I2C/SMBus.
ORDERING INFORMATION
PACKAGES TEMPERATURE
RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
16-Pin Plastic SO (wide) –40 to +85 °C PCA9554D PCA9554D SOT162-1
16-Pin Plastic SSOP –40 to +85 °C PCA9554DB 9554DB SOT338-1
16-Pin Plastic TSSOP –40 to +85 °C PCA9554PW 9554DH SOT403-1
16-Pin Plastic HVQFN –40 to +85 °C PCA9554BS 9554 SOT629-1
16-Pin Plastic SO (wide) –40 to +85 °C PCA9554AD PCA9554AD SOT162-1
16-Pin Plastic SSOP –40 to +85 °C PCA9554ADB 9554A SOT338-1
16-Pin Plastic TSSOP –40 to +85 °C PCA9554APW 9554ADH SOT403-1
16-Pin Plastic HVQFN –40 to +85 °C PCA9554ABS 554A SOT629-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
I2C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 3
PIN CONFIGURATION — SO, SSOP, TSSOP
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
su01410
A0
A1
A2
I/O0
I/O1
I/O2
I/O3
VSS
VDD
SDA
SCL
INT
I/O7
I/O6
I/O5
I/O4
Figure 1. Pin configuration — SO, SSOP, TSSOP
PIN CONFIGURATION — HVQFN
12
11
10
9
5
6
7
8
1
2
3
4
16
15
14
13
su01670
TOP VIEW
A2
I/O0
I/O1
I/O2
I/O3 I/O4VSS I/O5
INT
I/O6
I/O7
SDAVDD
A0A1
SCL
Figure 2. Pin Configuration — HVQFN
PIN DESCRIPTION
SO. SSOP,
TSSOP PIN
NUMBER
HVQFN
PIN
NUMBER SYMBOL FUNCTION
1 15 A0 Address input 0
2 16 A1 Address input 1
3 1 A2 Address input 2
4–7 2–5 I/O0–3 I/O0 to I/O3
8 6 VSS Supply ground
9 7–10 I/O4–7 I/O4 to I/O7
13 11 INT Interrupt output (open drain)
14 12 SCL Serial clock line
15 13 SDA Serial data line
16 14 VDD Supply voltage
BLOCK DIAGRAM
POWER-ON
RESET
INPUT
FILTER I2C/SMBUS
CONTROL
INPUT/
OUTPUT
PORTS
WRITE pulse
READ pulse
A0
A1
A2
SCL
SDA
VDD
VSS
8-BIT
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
SU01411
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
VCC
INT
LP
FILTER
Figure 3. Block diagram
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 4
REGISTERS
Command Byte
Command Protocol Function
0Read byte Input port register
1Read/write byte Output port register
2Read/write byte Polarity inversion register
3Read/write byte Configuration register
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Register 0 – Input Port Register
bit I7 I6 I5 I4 I3 I2 I1 I0
default 1 1 1 1 1 1 1 1
This register is a read only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
Register 1 – Output Port Register
bit O7 O6 O5 O4 O3 O2 O1 O0
default 1 1 1 1 1 1 1 1
This register reflects the outgoing logic levels of the pins defined as
outputs by Register 3. Bit values in this register have no effect on
pins defined as inputs. Reads from this register return the value that
is in the flip-flop controlling the output selection, NOT the actual pin
value.
Register 2 – Polarity Inversion Register
bit N7 N6 N5 N4 N3 N2 N1 N0
default 0 0 0 0 0 0 0 0
This register allows the user to invert the polarity of the Input Port
Register data. If a bit in this register is set (written with ‘1’), the
corresponding Input Port data is inverted. If a bit in this register is
cleared (written with a ‘0’), the Input Port data polarity is retained.
Register 3 – Configuration Register
bit C7 C6 C5 C4 C3 C2 C1 C0
default 1 1 1 1 1 1 1 1
This register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs with a weak pull-up to VDD.
Power-on Reset
When power is applied to VDD, an internal power-on reset holds the
PCA9554 in a reset state until VDD has reached VPOR. At that point,
the reset condition is released and the PCA9554 registers and state
machine will initialize to their default states.
Interrupt Output
The open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read.
Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the input port register.
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 5
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
WRITE PULSE
DATA FROM
SHIFT REGISTER
VDD
I/O0 TO I/O7
VSS
WRITE
CONFIGURATION
PULSE
D
CK
FF
Q
D
CK
Q
FF
D
CK
Q
FF
D
CK
Q
FF
INPUT PORT
REGISTER
POLARITY
INVERSION
REGISTER
OUTPUT
PORT
REGISTER
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
CONFIGURATION
REGISTER
OUTPUT PORT
REGISTER DATA
INPUT PORT
REGISTER DATA
POLARITY
REGISTER DATA
READ PULSE
SU01472
Q
Q
Q
Q
TO INT
100 kΩ
Q1
Q2
NOTE: At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/O0 to I/O7
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input with a weak pull-up (100 kΩ typ.) to
VDD. The input voltage may be raised above VDD to a maximum of
5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled,
depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance paths that exist between the
pin and either VDD or VSS.
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 6
Device address
01 0 0A2A1A0
SLAVE ADDRESS
su01669
FIXED HARDWARE SELECTABLE
R/W
Figure 5. PCA9554 address
01 1 1A2A1A0
slave address
su01418
fixed programmable
R/W
Figure 6. PCA9554A address
Bus transactions
Data is transmitted to the PCA9554/PCA9554A registers using the write mode as shown in Figures 7 and 8. Data is read from the
PCA9554/PCA9554A registers using the read mode as shown in Figures 9 and 10. These devices do not implement an auto-increment function
so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte
has been sent.
12
SCL
WRITE TO
PORT
DATA OUT
FROM PORT
345678
SDA S0A A A
0 1 0 0 A2 A1 A0 DATA 1
slave address data to port
start condition R/W acknowledge
from slave acknowledge
from slave acknowledge
from slave
tpv
DATA 1 VALID
su01421
9
1000000 0
command byte
P
Figure 7. WRITE to output port register
12
SCL 345678
SDA S0A A A
0 1 0 0 A2 A1 A0 DATA
slave address data to register
start condition R/W acknowledge
from slave acknowledge
from slave acknowledge
from slave
su01422
9
0000001
command byte
1/0
DATA TO
REGISTER
P
Figure 8. WRITE to configuration or polarity inversion registers
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 7
00 A2 A1 A00 10 0 A2 A1 A00 1
S0A A A
COMMAND BYTE
acknowledge
from slave
R/W
acknowledge
from slave
A
PNA
acknowledge
from slave acknowledge
from master
SDATA
DATA
R/W first byte
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
last byte
su01424
no acknowledge
from master
1
slave address
data from register
data from registerslave address
Figure 9. READ from register
01 0 0A2A1A0
READ FROM
PORT
DATA INTO
PORT
SDA S1A A
DATA 1 DATA 4
slave address data from port data from port
start condition R/W acknowledge
from slave acknowledge
from master stop
condition
tps
DATA 4DATA 2
P
DATA 3
tph
su01465
no acknowledge
from master
NA
INT
tir
tiv
12
SCL 3456789
NOTES:
1. This figure assumes the command byte has previously been programmed with 00h.
2. T ransfer of data can be stopped at any moment by a stop condition.
Figure 10. READ input port register
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 8
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
VDD Supply voltage –0.5 6.0 V
IIDC input current —±20 mA
VI/O DC voltage on an I/O VSS – 0.5 5.5 V
II/O DC output current on an I/O —±50 mA
IDD Supply current — 85 mA
ISS Supply current — 100 mA
Ptot Total power dissipation — 200 mW
Tstg Storage temperature range –65 +150 °C
Tamb Operating ambient temperature –40 +85 °C
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”
Handling MOS devices
”.
DC CHARACTERISTICS
VDD = 2.3 to 5.5 V ; V SS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Supplies
VDD Supply voltage 2.3 — 5.5 V
IDD Supply current Operating mode; VDD = 5.5 V ; no load;
fSCL = 100 kHz — 104 175 µA
Istbl Standby current Standby mode; VDD = 5.5 V ; no load;
VI = VSS; fSCL = 0 kHz; I/O = inputs — 550 700 µA
Istbh Standby current Standby mode; VDD = 5.5 V ; no load;
VI = VDD; fSCL = 0 kHz; I/O = inputs — 0.25 1 µA
VPOR Power-on reset voltage No load; VI = VDD or VSS — 1.5 1.65 V
input SCL; input/output SDA
VIL LOW level input voltage –0.5 —0.3 VDD V
VIH HIGH level input voltage 0.7 VDD — 5.5 V
IOL LOW level output current VOL = 0.4V 3 — — mA
ILLeakage current VI = VDD = VSS –1 — +1 µA
CIInput capacitance VI = VSS — 6 10 pF
I/OsVIL LOW level input voltage –0.5 — 0.8 V
VIH HIGH level input voltage 2.0 — 5.5 V
VOL = 0.5 V ; VDD = 2.3 V; Note 1 8 10 — mA
VOL = 0.7 V ; VDD = 2.3 V; Note 1 10 13 — mA
IO
LOW level out
p
ut current
VOL = 0.5 V ; VDD = 4.5 V; Note 1 8 17 — mA
I
OL
LOW
le
v
el
o
u
tp
u
t
c
u
rrent
VOL = 0.7 V ; VDD = 4.5 V; Note 1 10 24 — mA
VOL = 0.5 V ; VDD = 3.0 V; Note 1 8 14 — mA
VOL = 0.7 V ; VDD = 3.0 V; Note 1 10 19 — mA
IOH = –8 mA; VDD = 2.3 V ; Note 2 1.8 — — V
IOH = –10 mA; VDD = 2.3 V ; Note 2 1.7 — — V
VO
HIGH level out
p
ut voltage
IOH = –8 mA; VDD = 3.0 V ; Note 2 2.6 — — V
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
IOH = –10 mA; VDD = 3.0 V ; Note 2 2.5 — — V
IOH = –8 mA; VDD = 4.75 V ; Note 2 4.1 — — V
IOH = –10 mA; VDD = 4.75 V ; Note 2 4.0 — — V
IIH Input leakage current VDD = 3.6 V ; VI = VDD — — 1 µA
IIL Input leakage current VDD = 5.5 V ; VI = VSS — — –100 µA
CIInput capacitance — 3.7 5 pF
COOutput capacitance — 3.7 5 pF
Interrupt INT
IOL LOW level output current VOL = 0.4 V 3 — — mA
Select Inputs A0, A1, A2
VIL LOW level input voltage –0.5 — 0.8 V
VIH HIGH level input voltage 2.0 — 5.5 V
ILI Input leakage current –1 — 1 µA
NOTES:
1. The total current sunk by all I/Os must be limited to 100 mA.
2. The total current sourced by all I/Os must be limited to 85 mA.
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 10
SDA
SCL
SU01469
tHD;STA
tF
S
tLOW tR
tHD;DAT
tSU;DAT
tHIGH
tF
tSU;STA SR
tHD;STA tSP
tSU;STD P
tRtBUF
S
Figure 11. Definition of timing
AC SPECIFICATIONS
SYMBOL PARAMETER STANDARD MODE
I2C BUS FAST MODE
I2C BUS UNITS
MIN MAX MIN MAX
fSCL Operating frequency 0 100 0 400 kHz
tBUF Bus free time between STOP and START conditions 4.7 — 1.3 — µs
tHD;STA Hold time after (repeated) ST ART condition 4.0 — 0.6 — µs
tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs
tSU;STO Setup time for ST OP condition 4.0 — 0.6 — µs
tHD;DAT Data in hold time 0 — 0 — ns
tVD;ACK Valid time for ACK condition20.3 3.45 0.1 0.9 µs
tVD;DAT Data out valid time3300 — 50 — ns
tSU;DAT Data setup time 250 — 100 — ns
tLOW Clock LOW period 4.7 — 1.3 — µs
tHIGH Clock HIGH period 4.0 — 0.6 — µs
tFClock/Data fall time — 300 20 + 0.1 Cb1300 ns
tRClock/Data rise time — 1000 20 + 0.1 Cb1300 ns
tSP Pulse width of spikes that must be suppressed by the
input filters — 50 — 50 ns
Port Timing
tPV Output data valid — 200 — 200 ns
tPS Input data setup time 100 — 100 — ns
tPH Input data hold time 1 — 1 — µs
Interrupt Timing
tIV Interrupt valid — 4 — 4 µs
tIR Interrupt reset — 4 — 4 µs
NOTES:
1. Cb = total capacitance of one bus line in pF.
2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low.
3. tVD;DAT = minimum time for SDA data out to be valid following SCL low.
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 11
SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 12
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 13
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 14
HVQFN16: plastic heatsink very thin quad flat package; no leads; 16 terminals;
body 4 x 4 x 0.85 mm SOT629-1
Philips Semiconductors Product data
PCA9554/PCA9554A8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26 15
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Date of release: 07-02
Document order number: 9397 750 10163
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
