To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. 38C2 Group (A Version) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 38C2 group (A version) is the 8-bit microcomputer based on the 740 family core technology. The 38C2 (A version) group has an LCD drive control circuit, a 10channel A-D converter, and a serial I/O as additional functions. The various microcomputers in the 38C2 group (A version) include variations of internal memory size and packaging. For details, refer to the section on part numbering. FEATURES Basic machine-language instructions ....................................... 71 The minimum instruction execution time .......................... 0.40 s (at 10 MHz oscillation frequency) Memory size ROM ................................................................ 16 K to 60 K bytes RAM ................................................................. 640 to 2048 bytes Programmable input/output ports ......... 51 (common to SEG: 24) Interrupts ................................................... 18 sources, 16 vectors Timers ............................................................ 8-bit 4, 16-bit 2 A-D converter ................................................. 10-bit 8 channels Serial I/O ........................ 8-bit 2 (UART or Clock-synchronized) PWM .................. 10-bit 2, 16-bit 1 (common to IGBT output) LCD drive control circuit Bias ................................................................................... 1/2, 1/3 Duty ........................................................................... 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ........................................................................ 24 Two clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) Rev.2.00 May 28, 2004 page 1 of 100 REJ03B0096-0200Z Rev.2.00 May 28, 2004 Watchdog timer ............................................................... 8-bit 1 LED direct drive port .................................................................. 8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA) Power source voltage * Mask ROM version In frequency/2 mode ................................................... 4.5 to 5.5 V (at 10 MHz oscillation frequency) In frequency/2 mode ................................................... 4.0 to 5.5 V (at 8 MHz oscillation frequency) In frequency/4 mode ................................................... 1.8 to 5.5 V (at 4 MHz oscillation frequency, A-D operation excluded) In low-speed mode ..................................................... 1.8 to 5.5 V (at 32 kHz oscillation frequency) * Flash memory version In frequency/2 mode ................................................... 4.5 to 5.5 V (at 10 MHz oscillation frequency) In frequency/2 mode ................................................... 4.0 to 5.5 V (at 8 MHz oscillation frequency) In frequency/4 mode ................................................... 2.5 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode ..................................................... 2.5 to 5.5 V (at 32 kHz oscillation frequency) Power dissipation * In frequency/2 mode (at 8 MHz oscillation frequency, VCC = 5 V) Mask ROM version ............................................................ 14 mW Flash memory version ....................................................... 25 mW * In low-speed mode (at 32 kHz oscillation frequency, VCC = 3 V) Mask ROM version ............................................................. 24 W Flash memory version ...................................................... 375 W Operating temperature range ................................... - 20 to 85C 38C2 Group (A Version) P04/SEG4 P05/SEG5 P06/SEG6 P07/SEG7 P10/SEG8 P11/SEG9 P12/SEG10 P13/SEG11 P14/SEG12 P15/SEG13 P16/SEG14 P17/SEG15 P20/SEG16 P21/SEG17 P22/SEG18 P23/SEG19 PIN CONFIGURATION (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 (KW7)/P03/SEG3 (KW6)/P02/SEG2 (KW5)/P01/SEG1 (KW4)/P00/SEG0 (KW3)/P57/SRDY1 (KW2)/P56/SCLK1 (KW1)/P55/TXD1 (KW0)/P54/RXD1 P53/T4OUT/PWM1 P52/T3OUT/PWM0 P51/INT1 P50/INT0 AVSS VREF P47/RTP1/AN7 P46/RTP0/AN6 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 M38C2XMXA-XXXFP/HP M38C29FFAFP/HP 57 58 59 22 21 61 20 62 19 63 18 64 17 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/OOUT1/AN1 P40/OOUT0/AN0 CNVSS RESET P62/XCOUT P61/XCIN VSS X IN XOUT VC C P60/CNTR1 P37/CNTR0/(LED7) 2 Package type : 64P6U-A/64P6Q-A Fig. 1 M38C2XMXA-XXXFP/HP pin configuration May 28, 2004 23 60 1 Rev.2.00 25 24 page 2 of 100 P24/SEG20 P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 VL3 COM0 COM1 COM2 COM3 P30/SRDY2/(LED0) P31/SCLK2/(LED1) P32/TXD2/(LED2) P33/RXD2/(LED3) P34/INT2/(LED4) P35/TXOUT/(LED5) P36/T2OUT//(LED6) Rev.2.00 May 28, 2004 Fig. 2 Functional block diagram page 3 of 100 8 Port P4 (8) Port P0 (8) 8 8 8 Port P5 (8) 4 COM 24 SEG LCD drive control circuit (UART or Clock synchronous) Serial I/O2 (UART or Clock synchronous) Serial I/O1 Serial I/O 10-bit 8-channel A-D conversion 8 3 Port P6 (3) Watchdog timer PWM1 (10 bits) Timer 4 (8 bits) PWM0 (10 bits) Timer 3 (8 bits) Timer 2 (8 bits) Timer 1 (8 bits) CPU core RAM (12 bytes) RAM for LCD display ROM Memory (Sub-clock) XCIN-XCOUT IGBT output Timer Y (16 bits) XIN-XOUT (Main clock) System clock egneration PWM (16 bits) Timer Port P3 (8) 8 Timer X (16 bits) Port P2 (8) Internal peripheral function Port P1 (8) FUNCTIONAL BLOCK DIAGRAM 38C2 Group (A Version) 38C2 Group (A Version) PIN DESCRIPTION Table 1 Pin description (1) Pin VCC, VSS VREF Name Function Power source Analog reference * Apply voltage of 1.8 V to 5.5 V to VCC, and 0 V to VSS. * Reference voltage input pin for A-D converter. Function except a port function voltage AVSS Analog power source * GND input pin for A-D converter. Connect to VSS. RESET Reset input * Reset input pin for active " L." XIN Clock input * Input and output pins for the main clock generating circuit. * Feedback resistor is built in between XIN pin and XOUT pin. XOUT Clock output * Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. When an external clock is used, connect the clock source to XIN, and leave XOUT pin open. VL3 LCD power source * Input 0 VL1 VL2 VL3 VCC voltage. * Input 0 - VL3 voltage to LCD. COM0 - Common output * LCD common output pins. * COM2 and COM3 are not used at 1/2 duty ratio. COM3 * COM3 is not used at 1/3 duty ratio. I/O port P0 P00/SEG0 - P03/SEG3 * 8-bit I/O port. * CMOS compatible input level. P04/SEG4 - * LCD segment output pins * Key input interrupt pins * CMOS 3-state output structure. P07/SEG7 * I/O direction register allows each pin to be individually P10/SEG8 - I/O port P1 P17/SEG15 programmed as either input or output. * Pull-up control is enabled in a bit unit. P20/SEG16 - I/O port P2 P25/SEG21 * LCD power source P26/SEG22/VL1 input pins P27/SEG23/VL2 I/O port P3 P30/SRDY2 P31/SCLK2 * Serial I/O2 function pins P32/TxD2 P33/RxD2 P34/INT2 * External interrupt pin P35/TXOUT * Timer X, Timer 2 output pins P36/T2OUT/ P37/CNTR0 P40/OOUT0/AN0 I/O port P4 P41/OOUT1/AN1 * Timer X function pin * AD converter input * Oscillation external pins output pins P42/AN2- P45/AN5 P46/RTP0/AN6 * Real time port P47/RTP1/AN7 P50/INT0 function pins I/O port P5 * External interrupt pins P51/INT1 P52/T3OUT/PWM0 * Timer 3, Timer 4 output pins P53/T4OUT/PWM1 * PWM output pins P54/RxD1 * Serial I/O1 function pins P55/TxD1 * Key input interrupt input pins P56/SCLK1 P57/SRDY1 Rev.2.00 May 28, 2004 page 4 of 100 38C2 Group (A Version) PIN DESCRIPTION Table 2 Pin description (2) Pin P60/CNTR1 Name I/O port P6 Function Function except a port function * 3-bit I/O port. * Timer Y function pin P61/XCIN * CMOS compatible input level. P62/XCOUT * CMOS 3-state output structure. * Sub clock generating I/O pin (resonator connected) * I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. CNVSS Rev.2.00 CNVSS May 28, 2004 * VPP power input pin in the flash mode. When MCU is operating, connect to VSS. page 5 of 100 38C2 Group (A Version) PART NUMBERING Product M38C2 9 M C A- XXX HP Package type FP : 64P6U-A package HP : 64P6Q-A package ROM number Omitted in Flash memory version. Characteristics A : A version ROM/Flash memory size 1 : 4096 bytes 9 : 36864 bytes 2 : 8192 bytes A : 40960 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 3 Part numbering Rev.2.00 May 28, 2004 page 6 of 100 38C2 Group (A Version) GROUP EXPANSION Packages Renesas plans to expand the 38C2 group (A version) as follows. 64P6Q-A ..................................... 0.5 mm-pitch plastic molded QFP 64P6U-A ..................................... 0.8 mm-pitch plastic molded QFP Memory Type Support for mask ROM, Flash memory versions Memory Size ROM/flash memory size ...................................... 16 K to 60 K bytes RAM size ............................................................. 640 to 2048 bytes Memory Expansion Plan AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA ROM size (bytes) Mass production 60K M38C29FFA 56K Mass production 48 K 40 K 32 K 28 K 24 K 20 K 16 K 12 K 8 K 4 K M38C29MCA Mass production M38C24M6A Mass production M38C24M4A 192 256 384 512 640 768 896 1024 1536 2048 RAM size (bytes) Fig. 4 Memory expansion plan Currently supported products are listed below. As of May.2004 Table 3 Support products Product name M38C29MCA-XXXFP ROM size (bytes) ROM size for User in ( ) RAM size (bytes) 49152 (49022) 2048 M38C29MCA-XXXHP M38C24M6A-XXXFP M38C24M6A-XXXHP M38C24M4A-XXXFP 24576 (24446) 16384 (16254) 640 640 M38C24M4A-XXXHP M38C29FFAFP 61440 (61310) M38C29FFAHP Rev.2.00 May 28, 2004 page 7 of 100 2048 Remarks Package 64P6U-A Mask ROM version 64P6Q-A Mask ROM version 64P6U-A Mask ROM version 64P6Q-A Mask ROM version 64P6U-A Mask ROM version 64P6Q-A Mask ROM version 64P6U-A Flash memory version 64P6Q-A Flash memory version 38C2 Group (A Version) FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) [Stack Pointer (S)] The 38C2 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. The central processing unit (CPU) has six registers. Figure 5 shows the 740 Family CPU register structure. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as arithmetic data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 Stack pointer b0 PCL PCH b7 Program counter b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig. 5 740 Family CPU register structure Rev.2.00 May 28, 2004 page 8 of 100 38C2 Group (A Version) On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) - 1 M (S) (PCL) (S) (S)- 1 M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) Note: Condition for acceptance of an interrupt request here (S) - 1 Push return address on stack (PCL) (S) - 1 (PS) Push contents of processor status register on stack (S) - 1 Interrupt Service Routine Execute RTS (S) (S) (PCH) Execute RTI (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) I Flag is set from "0" to "1" Fetch the jump vector POP contents of processor status register from stack POP return address from stack Interrupt enable bit corresponding to each interrupt source is "1" Interrupt enable bit corresponding to each interrupt source is "0" Fig. 6 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP Rev.2.00 May 28, 2004 page 9 of 100 38C2 Group (A Version) [Processor Status Register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. * Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. * Bit 1: Zero flag (Z) The Z flag is set to "1" if the result of an immediate arithmetic operation or a data transfer is "0", and set to "0" if the result is anything other than " 0" . * Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is " 1" . * Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is " 0" ; decimal arithmetic is executed when it" is1" . Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. * Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. When the BRK instruction is generated, the B flag is set to "1" automatically. When the other interrupts are generated, the B flag is set to "0", and the processor status register is pushed onto the stack. * Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. * Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. * Bit 7: Negative flag (N) The N flag is set to "1" if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction Rev.2.00 May 28, 2004 SEC CLC Z flag - - page 10 of 100 I flag SEI CLI D flag SED CLD B flag T flag V flag N flag - SET CLT - - CLV - - 38C2 Group (A Version) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the control bit for the internal system clock. The CPU mode register is allocated at address 003B16. b7 b0 CPU mode register (CPUM (CM) : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area Not used (returns " 1" when read) (Do not write " 0" to this bit.) Main clock (X IN - XOUT ) division ratio selection bits b5 b4 0 0 : XIN /8 (frequency/8 mode) 0 1 : XIN /4 (frequency/4 mode) 1 0 : XIN /2 (frequency/2 mode) 1 1 : Not available System clock control bits b7 b6 0 0 : XIN stop, X CIN oscillating, system clock = X CIN 0 1 : XIN oscillating, X CIN stop, system clock = X IN 1 0 : XIN oscillating, X CIN oscillating, system clock = X CIN 1 1 : XIN oscillating, X CIN oscillating, system clock = X IN Fig. 7 Structure of CPU mode register Rev.2.00 May 28, 2004 page 11 of 100 38C2 Group (A Version) MEMORY Special Function Register (SFR) Area Zero Page The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. 000016 RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 Address XXXX16 RAM 004016 004C16 SFR area LCD display RAM area Zero page 010016 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 XXXX16 Reserved area 084016 0FE016 100016 Not used SFR area YYYY16 ROM ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Fig. 8 Memory map diagram Rev.2.00 May 28, 2004 page 12 of 100 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 Reserved ROM area (128 bytes) ZZZZ16 FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page 38C2 Group (A Version) 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 002016 Timer 1 (T1) 002116 Timer 2 (T2) 002216 Timer 3 (T3) 002316 Timer 4 (T4) 002416 PWM01 register (PWM01) 002516 Timer 12 mode register (T12M) 002616 Timer 34 mode register (T34M) 002716 002816 Compare register (low-order) (COMPL) 002916 Compare register (high-order) (COMPH) 002A16 Timer X (low-order) (TXL) 002B16 Timer X (high-order) (TXH) 000F16 001016 002C16 Timer X (extension) (TXEX) 002D16 Timer Y (low-order) (TYL) 002E16 Timer Y (high-order) (TYH) 002F16 Timer X mode register (TXM) 003016 Timer Y mode register (TYM) 001116 001216 003116 003216 001316 003316 001416 001516 003416 003516 001616 001716 003616 003716 Watchdog timer control register (WDTCON) 003816 LCD power control register (VLCON) 003916 LCD mode register (LM) 001816 Clock output control register (CKOUT) 001916 A-D control register (ADCON) 001A16 A-D conversion register (low-order) (ADL) 001B16 A-D conversion register (high-order) (ADH) 001C16 Transmit/receive buffer register 1 (TB1/RB1) 001D16 Serial I/O1 status register (SIO1ST S) 001E16 Transmit/receive buffer register 2 (TB2/RB2) 001F16 Serial I/O2 status register (SIO2ST S) 0FE016 Serial I/O1 control register (SIO1CON) 0FE116 UART1 control register (UART1CON) 0FE216 Baudrate generator 1 (BRG1) 0FE316 Serial I/O2 control register (SIO2CON) 0FE416 UART2 control register (UART2CON) 0FE516 Baudrate generator 2 (BRG2) 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) 0FF016 Oscillation output control register (OSCOUT) 0FF116 PULL register (PULL) 0FF216 Key input control register (KIC) 0FF316 Timer 1234 mode register (T1234M) 0FF416 Timer X control register (TXCON) 0FF516 Timer 12 frequency division selection register (PRE12) 0FF616 Timer 34 frequency division selection register (PRE34) 0FF716 Timer XY frequency division selection register (PREXY) 0FF816 Segment output disable register 0 (SEG0) 0FF916 Segment output disable register 1 (SEG1) 0FFA16 Segment output disable register 2 (SEG2) 0FFB16 Timer Y mode register 2 (T YM2) 0FFC16 0FFD16 0FFE16 Flash memory control register (FMCR) 0FFF16 Reserved area (access disabled) 0FEC16 0FED16 0FEE16 0FEF16 Fig. 9 Memory map of special function register (SFR) Rev.2.00 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) May 28, 2004 page 13 of 100 38C2 Group (A Version) I/O PORTS Direction Registers b7 The I/O ports P0-P6 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit of the direction register, the corresponding pin becomes an input pin. As for ports P0-P2, when "1" is written to the bit of the direction register and the segment output disable register, the corresponding pin becomes an output pin. As for ports P3-P6, when "1" is written to the bit of the direction register, the corresponding pin becomes an output pin. If data is read from a pin set to output, the value of the port latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. b0 PULL register (PULL : address 0FF1 16) P30 - P33 pull-up P34 - P37 pull-up P40 - P43 pull-up P44 - P47 pull-up P50 - P53 pull-up P54 - P57 pull-up P60 - P62 pull-up Not used (return " 0" b7 b0 0: No pull-up when read) 1: Pull-up Segment output disable register 0 (SEG0 : address 0FF8 16) P00 pull-up P01 pull-up P02 pull-up P03 pull-up P04 pull-up P05 pull-up P06 pull-up P07 pull-up Pull-up Control Each individual bit of ports P0-P2 can be pulled up with a program by setting direction registers and segment output disable registers 0 to 2 (addresses 0FF816 to 0FFA16). The pin is pulled up by setting " 0" to the direction register and " 1" to the segment output disable register. By setting the PULL register (address 0FF116), ports P3-P6 can control pull-up with a program. However, the contents of PULL register do not affect ports programmed as the output ports. b7 b0 Segment output disable register 1 (SEG1 : address 0FF9 16) P10 pull-up P11 pull-up P12 pull-up P13 pull-up P14 pull-up P15 pull-up P16 pull-up P17 pull-up b7 b0 Segment output disable register 2 (SEG2 : address 0FFA 16) P20 pull-up Segment output disable register Direction register " 0" "1" P21 pull-up " 0" Input port No pull-up Segment output 1"" Initial state Input port Pull-up P22 pull-up P23 pull-up P24 pull-up P25 pull-up P26 pull-up 0: No pull-up P27 pull-up 1: Pull-up Port output Notes 1: The PULL register and segment output disable register affect only ports programmed as the input ports. 2: When the VL pin input selection bit (VLSEL) of the LCD power control register (address 0038 16) is " 1" , settings of6P2 and P2 7 are invalid. Fig. 10 Structure of ports P0 to P2 Fig. 11 Structure of PULL register and segment output disable register Rev.2.00 May 28, 2004 page 14 of 100 38C2 Group (A Version) Table 6 List of I/O port function Pin P00/SEG0 - I/O format Name Input/Output Port P0 Input/Output, CMOS compatible individual bits input level P03/SEG3 Related SFRs Non-port function Segment output disable LCD segment Key input output (key-on wakeup) register 1 CMOS 3-state output Ref. No. (1) interrupt input (2) P04/SEG4 - P07/SEG7 P10/SEG8 - Port P1 P17/SEG15 P20/SEG16 - Port P2 P25/SEG21 Input/Output, CMOS compatible Segment output disable individual bits input level register 2 Input/Output, CMOS 3-state output CMOS compatible Segment output disable individual bits input level P27/SEG23/VL2 P30/SRDY2 register 3 CMOS 3-state output P26/SEG22/VL1 Port P3 P31/SCLK2 LCD power input Serial I/O2 function I/O Input/Output, CMOS compatible PULL register (3) individual bits input level Serial I/O2 control register (4) CMOS 3-state output Serial I/O2 status register (5) UART2 control register (6) PULL register (7) P32/TxD2 P33/RxD2 External interrupt input P34/INT2 Interrupt edge selection register P35/TXOUT Timer X output PULL register (8) P36/T2OUT/ Timer 2 output Timer X mode register (9) Timer 12 mode register Timer X function input P37/CNTR0 PULL register (7) Timer X mode register P40/OOUT0/AN0 Port P4 P41/OOUT1/AN1 Input/Output, CMOS compatible individual bits input level A-D conversion Oscillation input external CMOS 3-state output PULL register (11) A-D control register output (10) P42/AN2- P45/AN5 P46/RTP0/AN6 Real time PULL register P47/RTP1/AN7 port function A-D control register Port P5 P50/INT0 P51/INT1 Input/Output, CMOS compatible individual bits input level output External interrupt input Timer Y mode register PULL register register CMOS 3-state output Timer 3 output PULL register P53/T4OUT/PWM1 Timer 4 output Timer 12 mode register P54/RxD1 PWM output Serial I/O1 P55/TxD1 function I/O P57/SRDY1 P60/CNTR1 Port P6 PULL register (key-on wakeup) Serial I/O1 control register interrupt input Serial I/O1 status register Timer Y function input May 28, 2004 (13) (14) UART1 control register (15) PULL register (7) individual bits input level Timer Y mode register CMOS 3-state output Sub-clock oscillation circuit PULL register (16) CPU mode register (17) LCD mode register (18) Output LCD common output Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.2.00 (12) CMOS compatible P62/XCOUT Common Key input (9) Input/Output, P61/XCIN COM0-COM3 (7) Interrupt edge selection P52/T3OUT/PWM0 P56/SCLK1 (11) page 15 of 100 38C2 Group (A Version) (2) Ports P04-P07, P1, P2 (1) Ports P00-P03 VL2/VL3 VL2/VL3 Segment output disable bit Segment output disable bit Segment data Segment data VL1/VSS VL1/VSS Segment output disable bit Segment output disable bit Direction register Direction register Data bus Data bus Port latch Key-on wakeup interrupt input Port latch Key input control LCD power input (VL1,VL2) only for P26,P27 (4) Port P31 (3) Port P30 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Pull-up control Pull-up control Serial I/O mode selection bit Serial I/O enable bit Direction register Port latch Data bus Serial I/O synchronous clock selection bit Serial I/O enable bit Port latch Data bus Serial I/O clock output Serial I/O ready output Serial I/O clock input (6) Port P33 (5) Port P32 P32/TxD2 P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Data bus Pull-up control Port latch Fig. 12 Port block diagram (1) Rev.2.00 May 28, 2004 Direction register Data bus Serial I/O output page 16 of 100 Pull-up control Serial I/O enable bit Receive enable bit Port latch Serial I/O input 38C2 Group (A Version) (8) Port P35 (7) Ports P34, P37, P50, P51, P60 Pull-up control Pull-up control Direction register Data bus Direction register Port latch Port latch Data bus Pulse output mode Timer X output CNTR0, CNTR1 interrupt input INT0-INT2 interrupt input (10) Ports P42-P45 (9) Ports P36, P52, P53 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch A-D conversion input Port/Timer output selection Timer output/PWM output Timer output/System clock output Analog input pin selection bit (11) Ports P40, P41, P46, P47 (12) Port P54 Pull-up control Pull-up control Serial I/O enable bit Receive enable bit Direction register Direction register Port latch Data bus Data bus Port latch Oscillation output control bit/ Real time control bit Oscillation output/ Data for real time port Serial I/O input A-D conversion input Analog input pin selection bit Key input control Key-on wakeup interrupt input (14) Port P56 (13) Port P55 P55/TxD1 P-channel output disable bit Serial I/O enable bit Transmit enable bit Pull-up control Serial I/O synchronous clock selection bit Serial I/O enable bit Direction register Direction register Data bus Port latch Data bus Serial I/O output Fig. 13 Port block diagram (2) May 28, 2004 Port latch Serial I/O clock output Serial I/O clock input Key-on wakeup interrupt input Rev.2.00 Pull-up control Serial I/O mode selection bit Serial I/O enable bit page 17 of 100 Key input control Key-on wakeup interrupt input Key input control 38C2 Group (A Version) (16) Port P61 (15) Port P57 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Xc oscillation enabled + Pull-up control Pull-up control Xc oscillation enabled Direction register Data bus Port latch Port latch Sub-clock generation circuit input Serial I/O ready output Key input control Key-on wakeup interrupt input (17) Port P62 Xc oscillation enabled + Pull-up control (17) COM0-COM3 VL3 Xc oscillation enabled Direction register VL2 Data bus Oscillator Port P61 Xc oscillation enabled Fig. 14 Port block diagram (3) Rev.2.00 May 28, 2004 Gate input signal of each gate depends on the duty ratio and bias values. VL1 Port latch page 18 of 100 VSS 38C2 Group (A Version) INTERRUPTS Interrupts occur by nineteen sources: six external, twelve internal, and one software. 3. The interrupt jump destination address is read from the vector table into the program counter. Notes on Interrupts Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is " 0" . Interrupt enable bits can be set or cleared by program. Interrupt request bits can be cleared by program, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupt requests occur at the same time, the interrupt with highest priority is accepted first. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set to "1" and the corresponding interrupt request bit is set to " 0" . When setting the followings, the interrupt request bit may be set to " 1" . * When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X control register (address FF416) Timer Y mode register (address 3016) *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt edge selection register (address 3A16) When not requiring the interrupt occurrence synchronous with these setting, take the following sequence. Set the corresponding interrupt enable bit to " 0" (disabled). Set the interrupt edge select bit (polarity switch bit) or the interrupt source selection bit. Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to " 1" (enabled). Table 7 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) Priority 1 Vector Addresses (Note 1) Low High FFFD16 Interrupt Request Generating Conditions Remarks FFFC16 At reset Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) INT0 2 FFFB16 FFFA16 At detection of either rising or falling edge of INT0 input INT1 3 FFF916 FFF816 INT2 4 FFF716 FFF616 At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input Valid when INT 2 interrupt is selected External interrupt (active edge selectable) At falling of ports P00- P03, P54- P57 input logical level AND Valid when key input interrupt is selected External interrupt (falling valid) Key input (key-on wakeup) Serial I/O1 receive 5 FFF516 FFF416 At completion of serial I/O1 data receive Valid only when serial I/O1 is selected Serial I/O1 transmit 6 FFF316 FFF216 At completion of serial I/O1 transmit shift or transmit buffer is empty Serial I/O2 receive 7 FFF116 FFF016 At completion of serial I/O2 data receive Valid only when serial I/O2 is selected Serial I/O2 transmit 8 FFEF16 FFEE16 At completion of serial I/O2 transmit shift or transmit buffer is empty Timer X 9 FFED16 FFEC16 Timer 1 10 FFEB16 FFEA16 At timer X underflow At timer 1 underflow Valid only when timer 1 interrupt is selected Timer 2 11 FFE916 FFE816 At timer 2 underflow Valid only when timer 2 interrupt is selected Timer 3 12 FFE716 FFE616 At timer 3 underflow Timer 4 13 FFE516 FFE416 At timer 4 underflow CNTR0 14 FFE316 FFE216 At detection of either rising or falling edge of CNTR0 input Timer Y 15 FFE116 FFE016 At timer Y underflow CNTR1 Valid when A-D conversion interrupt is selected Non-maskable software interrupt FFDF16 FFDE16 At completion of A-D conversion BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. page 19 of 100 External interrupt (active edge selectable) External interrupt (active edge selectable) 16 May 28, 2004 Valid only when serial I/O2 is selected At detection of either rising or falling edge of CNTR1 input A-D conversion Rev.2.00 Valid only when serial I/O1 is selected 38C2 Group (A Version) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Interrupt request BRK instruction Reset Fig. 15 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A 16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT2/Key input interrupt switch bit Timer Y/CNTR 1 interrupt switch bit Not used (return " 0" when read) (Do not write to " 1" ) b7 b0 0 : Falling edge active 1 : Rising edge active 0 : INT2 interrupt 1 : Key input interrupt 0 : Timer Y interrupt 1 : CNTR1 interrupt Interrupt request register 1 (IREQ1 : address 003C 16 ) b7 b0 INT0 interrupt request bit INT1 interrupt request bit INT2 interrupt request bit Key input interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit Timer X interrupt request bit Interrupt request register 2 (IREQ2 : address 003D 16 ) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CNTR0 interrupt request bit Timer Y interrupt request bit CNTR1 interrupt request bit AD conversion interrupt request bit Not used (returns " 0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E 16) INT0 interrupt enable bit INT1 interrupt enable bit INT2 interrupt enable bit Key input interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit Timer X interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F 16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CNTR0 interrupt enable bit Timer Y interrupt enable bit CNTR1 interrupt enable bit AD conversion interrupt enable bit Not used (returns " 0" when read) (Do not write to " 1" .) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 16 Structure of interrupt-related registers Rev.2.00 May 28, 2004 page 20 of 100 38C2 Group (A Version) Key Input Interrupt (Key-on Wake-Up) A key input interrupt request is generated by detecting the falling edge from any pin of ports P00-P03, P54-P57 that have been set to input mode. In other words, it is generated when AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P54- P57. Port PXx " "L level output Segment output disable register 0 Bit 3 = " "1 Port P03 direction register = " "1 Key input control register = "1" Port P03 latch Key input interrupt request P03 output Segment output Port P02 disable register 0 direction register = " "1 Bit 2 = "1" Key input control register = "1" Port P02 latch P02 output Segment output disable register 0 Bit 1 = " "1 Port P01 direction register = "1" Key input control register = "1" Port P01 latch Port P0 Input reading circuit P01 output Segment output Port P00 disable register 0 direction register = "1" Bit 0 = "1" Key input control register = "1" Port P00 latch P00 output Port P57 direction register = "0" Key input control register = " "1 Port P57 latch P57 input Port P56 direction register = " "0 Key input control register = " "1 Port P56 latch P56 input Port P55 direction register = " "0 Key input control register = " "1 Port P55 latch P55 input Port P5 Input reading circuit Port P54 direction register = "0" Key input control register = " "1 Port P54 latch P54 input PULL register Bit 5 = " "1 P-channel transistor for pull-up CMOS output buffer Fig. 17 Connection example when using key input interrupt and ports P0 and P5 block diagram Rev.2.00 May 28, 2004 page 21 of 100 38C2 Group (A Version) A key input interrupt is controlled by the key input control register and port direction registers. When the key input interrupt is enabled, set "1" to the key input control register. A key input of any pin of ports P00- P03, P54- P57 that have been set to input mode is accepted. b7 b0 Key input control register (KIC : address 0FF2 16) P54 key input control bit P55 key input control bit P56 key input control bit P57 key input control bit P00 key input control bit P01 key input control bit P02 key input control bit P03 key input control bit 0 : Key input interrupt disabled 1 : Key input interrupt enabled Fig. 18 Structure of key input control register Rev.2.00 May 28, 2004 page 22 of 100 38C2 Group (A Version) TIMERS 8-Bit Timer Notes on Timer 3 PWM0 Mode, Timer 4 PWM1 Mode The 38C2 group has four built-in timers : Timer 1, Timer 2, Timer 3, and Timer 4. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches "0016", the contents of the timer latch is reloaded into the timer with the next count pulse. In this mode, the interrupt request bit corresponding to that timer is set to " 1" . The count can be stopped by setting the stop bit of each timer to "1". When PWM output is suspended after starting PWM output, depending on the level of the output pulse at that time to resume an output, the delay of the one section of the short interval may be needed. Stop at " H" : No output delay Stop at " L" : Output is delayed time of 256 ts In the PWM mode, the follows are performed every cycle of the long interval (4 256 ts). * Generation of timer 3, timer 4 interrupt requests * Update of timer 3, timer 4 Frequency Divider For Timer Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for the count source. The count source of the frequency divider is switched to XIN or XCIN by the CPU mode register. The frequency divider is controlled by each timer division ratio selection bit. The division ratio can be selected from as follows; 1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN); or f(XCIN). Timer 1, Timer 2 The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. Also, by the timer 12 mode register, each time timer 2 underflows, the signal of which polarity is inverted can be output from P36/T2OUT pin. At reset, all bits of the timer 12 mode register are set to "0," timer 1 is set to "FF16", and timer 2 is set to "0116". When executing the STP instruction, previously set the wait time at return. Timer 3, Timer 4 The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. Also, by the timer 34 mode register, each time timer 3 or timer 4 underflows, the signal of which polarity is inverted can be output from P52/T3OUT pin or P53/T4OUT pin. Timer 3 PWM0 Mode, Timer 4 PWM1 Mode A PWM rectangular waveform corresponding to the 10-bit accuracy can be output from the P52/PWM0 pin and P53/PWM1 pin by setting the timer 34 mode register and PWM01 register (refer to Figure 21). One output pulse is the short interval. Four output pulses are the long interval. The "n" is the value set in the timer 3 (address 002216) or the timer 4 (address 002316). The "ts" is one period of timer 3 or timer 4 count source. "H" width of the short interval is obtained by n ts. However, in the long interval, "H" width of output pulse is extended for ts which is set by the PWM01 register (address 002416). Rev.2.00 May 28, 2004 page 23 of 100 Writing to Timer 2, Timer 3, Timer 4 When writing to the latch only, if the write timing to the reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the reload latch. 38C2 Group (A Version) b7 b7 b0 b0 PWM01 register (PWM01: address 0024 16) Timer 12 mode register (T12M: address 0025 16) Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count source selection bits b3 b2 0 0 : Frequency divider for Timer 1 0 1 : f(XCIN) 1 0 : Underflow of Timer Y 1 1 : Not available Timer 2 count source selection bits b5 b4 0 0 : Underflow of Timer 1 0 1 : f(XCIN) 1 0 : Frequency divider for Timer 2 1 1 : Not available Timer 2 output selection bit (P3 6) 0 : I/O port 1 : Timer 2 output T2OUT output edge switch bit 0 : Start at " L" output 1 : Start at " H" output b7 PWM0 set bits b1 b0 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods PWM1 set bits b3 b2 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods Not used (returns " 0" when read) b7 b0 b0 Timer 12 frequency division selection register (PRE12: address 0FF5 16) Timer 34 mode register (T34M: address 0026 16) Timer 3 count stop bit 0 : Count operation 1 : Count stop Timer 4 count stop bit 0 : Count operation 1 : Count stop Timer 3 count source selection bit 0 : Frequency divider for Timer 3 1 : Underflow of Timer 2 Timer 4 count source selection bits b4 b3 0 0 : Frequency divider for Timer 4 0 1 : Underflow of Timer 3 1 0 : Underflow of Timer 2 1 1 : Not available Timer 3 operating mode selection bit 0 : Timer mode 1 : PWM mode Timer 4 operating mode selection bit 0 : Timer mode 1 : PWM mode Not used (returns " 0" when read) b7 Timer 1 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Timer 2 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Not used (returns " 0" b0 Timer 1234 mode register (T1234M: address 0FF3 16) T3OUT output edge switch bit 0 : Start at " L" output 1 : Start at " H" output T4OUT output edge switch bit 0 : Start at " L" output 1 : Start at " H" output Timer 3 output selection bit (P5 2) 0 : I/O port 1 : Timer 3 output Timer 4 output selection bit (P5 3) 0 : I/O port 1 : Timer 4 output Timer 2 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 3 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 4 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Not used (returns " 0" when read) b7 when read) b0 Timer 34 frequency division selection register (PRE34: address 0FF6 16) Timer 3 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Timer 4 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Not used (returns "0" when read) Fig. 19 Structure of timer related register Rev.2.00 May 28, 2004 page 24 of 100 38C2 Group (A Version) XIN System clock control bits Frequency divider 12 Clock for Timer 4 Clock for Timer 3 Clock for Timer 2 Clock for Timer 1 XCIN Timer 1 Timer 2 Timer 3 Timer 4 Frequency division selection bits (3 bits for each Timer) XCIN Timer 1 count "00" source selection bits "01" Clock for Timer 1 Timer 1 latch (8) Timer 1 interrupt request Timer 1 (8) "10" Timer Y output Timer 1 count stop bit The following values can be selected the clock for Timer; 1/1,1/2,1/16,1/32, 1/64,1/128,1/256,1/1024 Timer 2 write control bit Timer 2 count "00" source selection bits "01" Clock for Timer 2 P36/T2OUT//(LED6) P36 clock output control bit System clock "1" "0" "0" P36 direction register P36 latch Timer 2 latch (8) Timer 2 interrupt request Timer 2 (8) "10" Timer 2 output control bit Timer 2 count stop bit S 1/2 Q T "1" Q T2OUT output edge switch bit Timer 3 write control bit Timer 2 output selection bit Timer 3 count source "1" selection bit Clock for Timer 3 "0" Timer 3 latch (8) Timer 3 interrupt request Timer 3 (8) Timer 3 count stop bit 10 bit PWM0 circuit Timer 3 operating mode selection bit "1" P52/PWM0/T3OUT Data bus Timer 3 output control bit PWM01 register (2) "0" "0" S Q P52 T "1" latch Q 1/2 T3OUT output Timer 3 output selection bit edge switch bit P52 direction register Timer 4 write control bit "01" Timer 4 count source "10" selection bits Clock for Timer 4 P53/PWM1/T4OUT Timer 4 operating mode selection bit "1" Timer 4 output control bit "0" "0" S Q P53 T "1" latch 1/2 Q T4OUT output Timer 4 output selection bit edge switch bit Fig. 20 Block diagram of timers 1, 2, 3 and 4 May 28, 2004 Timer 4 interrupt request Timer 4 (8) Timer 4 count stop bit 10 bit PWM1 circuit P53 direction register Rev.2.00 "00" Timer 4 latch (8) page 25 of 100 PWM01 register (2) 38C2 Group (A Version) Output waveform of Timer 3 PWM0 or Timer 4 PWM1 Long interval 4 256 ts PWM01 register = "002" Short interval 256 ts Short interval 256 ts Short interval 256 ts n ts n ts n ts n ts n ts n ts PWM01 register = "012" (n+1) ts n ts PWM01 register = "102" (n+1) ts n ts PWM01 register = "112" (n+1) ts (n+1) ts Short interval 256 ts (n+1) ts n ts (n+1) ts n ts Interrupt request Interrupt request n: Setting value of Timer 3 or Timer 4 ts: One period of Timer 3 count source or Timer 4 count source PWM01 register (address 002416) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3) Fig. 21 Waveform of PWM0 and PWM1 16-bit Timer Frequency Divider For Timer Each timer X and timer Y have the frequency dividers for the count source. The count source of the frequency divider is switched to XIN or XCIN by the CPU mode register. The division ratio of each timer can be controlled by each timer division ratio selection bit. The division ratio can be selected from as follows; 1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN); or f(XCIN). Timer X The timer X count source can be selected by setting the timer X mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. The timer X operates as down-count. When the timer contents reach "000016", an underflow occurs at the next count pulse and the timer latch contents are reloaded. After that, the timer continues countdown. When the timer underflows, the interrupt request bit corresponding to the timer X is set to " 1" . Six operating modes can be selected for timer X by the timer X mode register and timer X control register. (1) Timer Mode The count source can be selected by setting the timer X mode register. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). (2) Pulse Output Mode Pulses of which polarity is inverted each time the timer underflows are output from the TXOUT pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the TXOUT pin to output mode. Rev.2.00 May 28, 2004 page 26 of 100 (3) IGBT Output Mode After dummy output from the TXOUT pin, count starts with the INT0 pin input as a trigger. In the case that the timer X output edge switch bit is "0", when the trigger is detected or the timer X underflows, "H" is output from the TXOUT pin. And then, when the count value corresponds with the compare register value, the TXOUT output becomes " L" . After noise is cleared by noise filters, judging continuous 4-time same levels with sampling clocks to be signals, the INT0 signal can use 4 types of delay time by a delay circuit. When using this mode, set the port sharing the INT0 pin to input mode and set the port sharing the TXOUT pin to output mode. When the timer X output control bit 1 or 2 of the timer X control register is set to "1", the timer X count stop bit is fixed to "1" forcibly by the interrupt signal of INT1 or INT2. And then, the TXOUT output can be set to "L" forcibly at the same time that the timer X stops counting. Do not write "1" to the timer X register (extension) when using the IGBT output mode. (4) PWM Mode IGBT dummy output, an external trigger with the INT0 pin and output control with pins INT1 and INT2 are not used. Except for those, this mode operates just as in the IGBT output mode. The period of PWM waveform is specified by the timer X set value. In the case that the timer X output edge switch bit is "0", the "H" interval is specified by the compare register set value. When using this mode, set the port sharing the TXOUT pin to output mode. Do not write "1" to the timer X register (extension) when using the PWM mode. 38C2 Group (A Version) ts Timer X count source Timer X PWM mode IGBT output mode (n-m+1) ts m ts (n+1) ts When the Timer X setting value = n and the compare register setting value = m, and the period of timer X count souce = ts, the following PWM waveform is output; Duty : (n-m+1)/(n+1) Period : (n+1) ts Fig. 22 Waveform of PWM/IGBT (5) Event Counter Mode The timer counts signals input through the CNTR0 pin. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When using this mode, set the port sharing the CNTR0 pin to input mode. In this mode, the window control can be performed by the timer 1 underflow. When the bit 5 (data for control of event counter window) of the timer X mode register is set to "1", counting is stopped at the next timer 1 underflow. When the bit is set to "0", counting is restarted at the next timer 1 underflow. (6) Pulse Width Measurement Mode In this mode, the count source is the output of frequency divider for timer. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When the bit 6 of the CNTR0 active edge switch bits is "0", counting is executed during the "H" interval of CNTR0 pin input. When the bit is "1", counting is executed during the "L" interval of CNTR0 pin input. When using this mode, set the port sharing the CNTR0 pin to input mode. Notes on Timer X (1) Write Order to Timer X * In the timer mode, pulse output mode, event counter mode and pulse width measurement mode, write to the following registers in the order as shown below; the timer X register (extension), the timer X register (low-order), the timer X register (high-order). Do not write to only one of them. When the above mode is set and timer X operates as the 16-bit counter, if the timer X register (extension) is never set after reset is released, setting the timer X register (extension) is not required. In this case, write the timer X register (low-order) first and the timer X register (high-order). However, once writing to the timer X register (extension) is executed, note that the value is retained to the reload latch. * In the IGBT output and PWM modes, do not write "1" to the timer X register (extension). Also, when "1" is already written to the timer X register, be sure to write " 0" to the register before using. Write to the following registers in the order as shown below; Rev.2.00 May 28, 2004 page 27 of 100 the compare register (high- and low-order), the timer X register (extension), the timer X register (low-order), the timer X register (high-order). It is possible to use whichever order to write to the compare register (high- and low-order). However, write both the compare register and the timer X register at the same time. (2) Read Order to Timer X * In all modes, read the following registers in the order as shown below; the timer X register (extension), the timer X register (high-order), the timer X register (low-order). When reading the timer X register (extension) is not required, read the timer X register (high-order) first and the timer X register (loworder). Read order to the compare register is not specified. * If reading to the timer X register during write operation or writing to it during read operation is performed, normal operation will not be performed. (3) Write to Timer X * Which write control can be selected by the timer X write control bit (b3) of the timer X mode register (address 2F16), writing data to both the latch and the timer at the same time or writing data only to the latch. When writing a value to the timer X address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. After reset release, when writing a value to the timer X address, the value is set into the timer and the timer latch at the same time, because they are written at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it. 38C2 Group (A Version) (4) Set of Timer X Mode Register Set the write control bit of the timer X mode register to "1" (write to the latch only) when setting the IGBT output and PWM modes. Output waveform simultaneously reflects the contents of both registers at the next underflow after writing to the timer X register (highorder). (5) Output Control Function of Timer X When using the output control function (INT1 and INT2) in the IGBT output mode, set the levels of INT1 and INT2 to "H" in the falling edge active or to "L" in the rising edge active before switching to the IGBT output mode. (6) Note on Switch of CNTR0 Active Edge * When the CNTR0 active edge switch bits are set, at the same time, the interrupt active edge is also affected. * When the pulse width is measured, set the bit 7 of the CNTR0 active edge switch bits to " 0" . Timer Y Timer Y is a 16-bit timer. The timer Y count source can be selected by setting the timer Y mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. Four operating modes can be selected for timer Y by the timer Y mode register. Also, the real time port can be controlled. (1) Timer Mode The timer Y count source can be selected by setting the timer Y mode register. (2) Period Measurement Mode The interrupt request is generated at rising or falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting. Except for that, this mode operates just as in the timer mode. The timer value just before the reloading at rising or falling of CNTR1 pin input is retained until the timer Y is read once after the reload. The rising or falling timing of CNTR1 pin input is found by CNTR1 interrupt. When using this mode, set the port sharing the CNTR1 pin to input mode. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the CNTR1 pin to input mode. Rev.2.00 May 28, 2004 page 28 of 100 (4) Pulse Width HL Continuously Measurement Mode The interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for that, this mode operates just as in the period measurement mode. When using this mode, set the port sharing the CNTR1 pin to input mode. Notes on Timer Y CNTR1 Interrupt Active Edge Selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. Timer Y Read/Write Control * When reading from/writing to timer Y, read from/write to both the high-order and low-order bytes of timer Y. When the value is read, read the high-order bytes first and the low-order bytes next. When the value is written, write the low-order bytes first and the highorder bytes next. If reading from the timer Y register during write operation or writing to it during read operation is performed, normal operation will not be performed. * When writing a value to the timer Y address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. Normally, when writing a value to the timer Y address, the value is set into the timer and the timer latch at the same time, because they are set to write at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it. Real Time Port Control When the real time port function is valid, data for the real time port is output from ports P47 and P46 each time the timer Y underflows. (However, if the real time port control bit is changed from "0" to "1" after the data for real time port is set, data is output independent of the timer Y operation.) When the data for the real time port is changed while the real time port function is valid, the changed data is output at the next underflow of timer Y. Before using this function, set the corresponding port direction registers to output mode. 38C2 Group (A Version) b7 b0 b7 b0 Timer X mode register (TXM: address 002F16) Timer X control register (TXCON: address 0FF416) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : IGBT output mode 0 1 1 : PWM mode 1 0 0 : Event counter mode 1 0 1 : Pulse width measurement mode 1 1 0 : Not available 1 1 1 : Not available Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer X count source selection bit 0 : Frequency divider output 1 : f(XCIN) Data for control of event counter window 0 : Event count enabled 1 : Event count disabled Timer X count stop bit 0 : Count operation 1 : Count stop Timer X output selection bit (P35) 0 : I/O port 1 : Timer X output b7 Noise filter sampling clock selection bit 0 : f(XIN)/2 1 : f(XIN)/4 External trigger delay time selection bits b2 b1 0 0 : Not delayed 0 1 : (4/f(XIN)) s 1 0 : (8/f(XIN)) s 1 1 : (16/f(XIN)) s Timer X output control bit 1 (P51) 0 : Not used 1 : INT1 interrupt used Timer X output control bit 2 (P34) 0 : Not used 1 : INT2 interrupt used Timer X output edge switch bit 0 : Start at "L" output 1 : Start at "H" output CNTR0 active edge switch bits b7 b6 0 0 : Count at rising edge in event counter mode Falling edge active for CNTR0 interrupt Measure "H" pulse width in pulse width measurement mode 0 1 : Count at falling edge in event counter mode Rising edge active for CNTR0 interrupt Measure "L" pulse width in pulse width measurement mode 1 0 : Count at both edges in event counter mode Both edges active for CNTR0 interrupt 1 1 : Count at both edges in event counter mode Both edges active for CNTR0 interrupt b0 Timer Y mode register (TYM: address 003016) Real time port control bit 0 : Real time port function invalid 1 : Real time port functin valid P46 data for real time port P47 data for real time port Timer Y count source selection bit 0 : Frequency divider output 1 : f(XCIN) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuous measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure falling period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure rising period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y count stop bit 0 : Count operation 1 : Count stop b7 b0 Timer Y mode register 2 (TYM2: address 0FFB16) Timer Y write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Not used (returns "0" when read) Fig. 23 Structure of Timer X, Y related registers Rev.2.00 May 28, 2004 page 29 of 100 b7 b0 Timer XY frequency division selection register (PREXY: address 0FF716) Timer X frequency division selection bits b2 b1 b0 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Timer Y frequency division selection bits b5 b4 b3 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Not used (returns "0" when read) 38C2 Group (A Version) XIN Data bus X IN 3 System clock control bits Frequency divider 3 Frequency divider Timer X frequency division selection bits Timer Y frequency division selection bits 1/2 1/4 " "0 "1 " Noise filter sampling clock selection bit XcIN INT0 interrupt request 0 s P50/INT0 Clock for Timer Y The following values can be selected the clock for Timer; 1/1,1/2,1/16,1/32, 1/64,1/128,1/256,1/1024 Noise filter (4 times same levels judgment) Edge selection * Delay circuit Delay time selection bits " 00" Timer X operating mode bits 4/f(XIN) " 01" "010" 8/f(XIN) " 10" 16/f(XIN)" 11" "000" "001" "011" "100" "101" Clock for Timer X "0" Count source selection bit XcIN "1" D Q Data for control of event counter window Timer X operating Timer X write mode bits control bit "000" "001" Timer X count "010" stop bit "011" Timer X (low-order) latch (8) Timer X (high-order) latch (8) "101" Timer 1 interrupt Latch " 00" P37/CNTR0/(LED7) Timer X (low-order)(8) "01" Extend latch (2) Timer X (high-order)(8) Extend counter (2) Timer X interrupt request "100" Both edges detection " 10" " 11" CNTR0 active edge switch bits CNTR0 interrupt request Pulse width measurement mode Equal Timer X operating mode bits " 010" TXOUT output control bit 1 P51/INT1 Compare register (low-order)(8) Compare register (high-order)(8) Edge detection Edge selection * TXOUT output control bit 2 P34/INT2/(LED4) R S Q Edge selection * T Q " "0 Pulse output mode P35/TXOUT/(LED5) S S Q "1 " P35 direction register P35 latch TXOUT edge switch bit T Q IGBT output mode PWM mode Output selection bit Timer Y operating mode bits " 00 " ", 01 " ", 10 " "0" Clock for Timer Y Pulse width HL continuous measurement mode Rising edge detection XcIN "1" Count source selection bit CNTR1 interrupt request " 11 " Period measurement mode Falling edge detection Timer Y write control bit Timer Y count stop bit CNTR1 active edge switch bit " 00 " ", 01 " ", 11 " " "0 Timer Y (low-order) latch (8) Timer Y (high-order) latch (8) Timer Y (low-order)(8) P60/CNTR1 "10" "1 " Real time port control bit Timer Y (high-order)(8) Timer Y operating mode bits Real time port control bit " "1 Q D "0 " Latch P47 data for real time port " "0 P47/RTP1/AN7 P47 direction register " "1 P47 latch Real time port control bit "1" Q D P46 data for real time port P46/RTP0/AN6 P46 direction register "0 " Latch P46 latch * Interrupt edges of INT0, INT1, INT2 can be selected by the interrupt edge selection register (address 003A16). 0: Falling edge active 1: Rising edge active Fig. 24 Block diagram of Timer X, Y Rev.2.00 May 28, 2004 page 30 of 100 Timer Y mode register write signal Timer Y interrupt request 38C2 Group (A Version) SERIAL I/O (1) Clock Synchronous Serial I/O Mode The 38C2 group has built-in two 8-bit serial I/O. Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register to " 1" . For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Address 001C 16 [Address 001E 16] Receive buffer register P54/RXD1 [P33/RXD2] Serial I/O control register Address 0FE016 [Address 0FE3 16] Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register Shift clock Clock control circuit P56/SCLK1 [P31/SCLK2] Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P57/SRDY1 [P30/SRDY2] Baud rate generator Address 0FE2 16 [Address 0FE5 16] Clock control circuit Falling-edge detector F/F 1/4 Shift clock P55/TXD1 [P32/TXD2] Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer register Address 001C16 [Address 001E16] Data bus Transmit buffer empty flag (TBE) Serial I/O status register Address 001D 16 [Address 001F 16] [ ] : For Serial I/O2 Fig. 25 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY Write pulse to receive/transmit buffer register TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes " 1" . Fig. 26 Operation of clock synchronous serial I/O function Rev.2.00 May 28, 2004 page 31 of 100 38C2 Group (A Version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by setting the serial I/O mode selection bit of the serial I/O control register to " 0" . Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001C16 [Address 001E16] P54/RXD1 [P33/RXD2] Address 0FE0 16 [Address 0FE3 16] Receive buffer full flag (RBF) Receive interrupt request (RI) Serial I/O control register Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register 1/16 8 bits PE FE UART control register SP detector Address 0FE116 [Address 0FE416] Clock control circuit Serial I/O synchronous clock selection bit P56/SCLK1 [P31/SCLK2] BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator (f(XCIN) in low-speed mode) Address 0FE2 16 [Address 0FE5 16] 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P55/TXD1 [P32/TXD2] Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register Character length selection bit Transmit buffer empty flag (TBE) Serial I/O status register Address 001D16 [Address 001F 16] Transmit buffer register Address 001C 16 [Address 001E 16] Data bus [ ] : For Serial I/O2 Fig. 27 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer register write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TSC=1 TBE=1 ST D0 D1 SP ST D0 SP D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode Receive buffer register read signal RBF=0 RBF=1 Serial input RXD ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC flag ="1", 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC flag = "0". Fig. 28 Operation of UART serial I/O function Rev.2.00 May 28, 2004 page 32 of 100 38C2 Group (A Version) [Transmit Buffer Register/Receive Buffer Register (TB/RB)] The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is " 0" . [Serial I/O Status Register (SIO1STS, SIO2STS)] The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is set to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register sets all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively) to "0". Writing "0" to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also sets all the status flags to "0", including the error flags. All bits of the serial I/O status register are set to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become " 1" . [Serial I/O Control Register (SIO1CON, SIO2CON)] The serial I/O control register consists of eight control bits for the serial I/O function. [UART Control Register (UART1CON, UART2CON)] The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P55/TXD1 [P32/TxD2] pin. [Baud Rate Generator (BRG1, BRG2)] The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.2.00 May 28, 2004 page 33 of 100 38C2 Group (A Version) b7 b0 Serial I/O status register (SIO1STS : address 001D 16) [SIO2STS : address 001F 16] Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error when read) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P55/TXD 1 [P32/TxD 2] P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) when read) ( ) : For Serial I/O1 [ ] : For Serial I/O2 Fig. 29 Structure of serial I/O related registers Notes on serial I/O When setting transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronous with the transmision enabled, take the following sequence. Set the serial I/O transmit interrupt enable bit to " 0" (disabled). Set the transmit enable bit to " 1" . Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to " 1" (enabled). May 28, 2004 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. Receive enable bit (RE) 0: Receive disabled 1: Receive enabled UART control register b0 (UART1CON : address 0FE1 16 ) [UART2CON : address 0FE4 16] Rev.2.00 BRG count source selection bit (CSS) 0: f(X IN) (f(X CIN) in low-speed mode) 1: f(X IN)/4 (f(X CIN)/4 in low-speed mode) Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (return " 1" Serial I/O control register (SIO1CON : address 0FE0 16) [SIO2CON : address 0FE3 16] Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Framing error flag (FE) 0: No error 1: Framing error b7 b0 SRDY output enable bit (SRDY) 0: P5 7 [P30] pin operates as ordinary I/O pin 1: P5 7 [P30] pin operates as S RDY output pin Parity error flag (PE) 0: No error 1: Parity error Not used (returns " 1" b7 page 34 of 100 Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P5 4 [P3 0] to P5 7 [P33] operate as ordinary I/O pins) 1: Serial I/O enabled (pins P5 4 [P3 0] to P5 7 [P33] operate as serial I/O pins) 38C2 Group (A Version) A-D CONVERTER b7 b0 The 38C2 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion. A-D control register (ADCON: address 001916) [A-D Conversion Register (ADL, ADH)] Analog input pin selection bits b2 b1 b0 0 0 0: P40/AN0 0 0 1: P41/AN1 0 1 0: P42/AN2 0 1 1: P43/AN3 1 0 0: P44/AN4 1 0 1: P45/AN5 1 1 0: P46/AN6 1 1 1: P47/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed AD conversion clock selection bits b5 b4 0 0: XIN/2 0 1: XIN/4 1 0: XIN/8 1 1: XIN/16 10-bit or 8-bit conversion switch bit 0: 10-bit AD 1: 8-bit AD Booster selection bit (When A-D conveter is used at VCC = 2.5 V or less, write "1" to this bit.) 0: Booster not used 1: Booster used One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored in the A-D conversion register (high-order) (address 001B16), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the A-D conversion register (low-order) (address 001A16). During A-D conversion, do not read these registers. Also, the connection between the resistor ladder and reference voltage input pin (VREF) can be controlled by the VREF input switch bit (bit 0 of address 001A16). When "1" is written to this bit, the resistor ladder is always connected to VREF. When "0" is written to this bit, the resistor ladder is disconnected from VREF except during the A-D conversion. [A-D Control Register (ADCON)] This register controls A-D converter. Bits 2 to 0 are analog input pin selection bits. Bit 3 is an AD conversion completion bit and "0" during AD conversion. This bit is set to " 1" upon completion of A-D conversion. A-D conversion is started by setting " 0" in this bit. [Comparison Voltage Generator] 10-bit reading (Read address 001B16 before 001A16) The comparison voltage generator divides the voltage between AVSS and VREF, and outputs the divided voltages. b7 b0 b7 b0 A-D conversion register 1 b9 b8 b7 b6 b5 b4 b3 b2 (high-order) (Address 001B16) [Channel Selector] A-D conversion register 2 b1 b0 (Address 001A16) The channel selector selects one of the input ports P47/AN7-P40/ AN0 and inputs it to the comparator. The comparator and control circuit compares an analog input voltage with the comparison voltage and store the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to " 1." Note that because the comparator consists of a capacitor coupling, set the A-D clock frequency to 250 kHz or more during an A-D conversion. Also, when the STP instruction is executed during the A-D conversion, the A-D conversion is stopped immediately, the A-D conversion completion bit is set to " 1" , and the interrupt request is generated. Note : The bit 5 to bit 1 of address 001A16 become "0" at reading. Also, bit 0 is undefined at reading. 8-bit reading (Read only address 001B16) b7 (Address 001B16) b7 Fig. 30 Structure of A-D control register b0 A-D control register Channel selector 3 A-D control circuit Comparator A-D interrupt request A-D conversion register (H) A-D conversion register (L) (Address 001B 16) AV SS VREF Rev.2.00 May 28, 2004 page 35 of 100 (Address 001A 16) Resistor ladder b0 b9 b8 b7 b6 b5 b4 b3 b2 Data bus Fig. 31 Block diagram of A-D converter (low-order) * VREF input switch bit 0: ON only during A-D conversion 1: ON [Comparator and Control Circuit] P40/OOUT0/AN0 P41/OOUT1/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 * 38C2 Group (A Version) LCD DRIVE CONTROL CIRCUIT The 38C2 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. * LCD display RAM * Segment output disable register * LCD mode register * Selector * Timing controller * Common driver * Segment driver * Bias control circuit A maximum of 24 segment output pins and 4 common output pins can be used. Up to 96 pixels can be controlled for an LCD display. When the LCD enable bit is set to "1" after data is set in the LCD mode register, the b7 segment output disable register, and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 8 Maximum number of display pixels at each duty ratio Duty ratio b7 b0 Maximum number of display pixels 2 48 dots or 8 segment LCD 6 digits 3 72 dots or 8 segment LCD 9 digits 4 96 dots or 8 segment LCD 12 digits b0 Segment output disable register 0 (SEG0 : address 0FF8 16 ) LCD mode register (LM : address 0039 16 ) Duty ratio selection bits b1 b0 0 0 : Not used 0 1 : 2 (use COM 0,COM1 ) 1 0 : 3 (use COM 0- COM2) 1 1 : 4 (use COM 0- COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON LCD drive timing selection bit 0 : Type A 1 : Type B LCD circuit divider division ratio selection bits b6 b5 0 0 : Clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(XCIN )/32 1 : f(XIN )/8192 (f(X CIN )/8192 in low-speed mode) Segment output disable bit 0 0 : Segment output SEG 0 1 : Output port P0 0 Segment output disable bit 1 0 : Segment output SEG 1 1 : Output port P0 1 Segment output disable bit 2 0 : Segment output SEG 2 1 : Output port P0 2 Segment output disable bit 3 0 : Segment output SEG 3 1 : Output port P0 3 Segment output disable bit 4 0 : Segment output SEG 4 1 : Output port P0 4 Segment output disable bit 5 0 : Segment output SEG 5 1 : Output port P0 5 Segment output disable bit 6 0 : Segment output SEG 6 1 : Output port P0 6 Segment output disable bit 7 0 : Segment output SEG 7 1 : Output port P0 7 Note : LCDCK is a clock for an LCD timing controller. b7 b0 b7 Segment output disable register 1 (SEG1 : address 0FF9 16 ) Segment output disable bit 8 0 : Segment output SEG 8 1 : Output port P1 0 Segment output disable bit 9 0 : Segment output SEG 9 1 : Output port P1 1 Segment output disable bit 10 0 : Segment output SEG 10 1 : Output port P1 2 Segment output disable bit 11 0 : Segment output SEG 11 1 : Output port P1 3 Segment output disable bit 12 0 : Segment output SEG 12 1 : Output port P1 4 Segment output disable bit 13 0 : Segment output SEG 13 1 : Output port P1 5 Segment output disable bit 14 0 : Segment output SEG 14 1 : Output port P1 6 Segment output disable bit 15 0 : Segment output SEG 15 1 : Output port P1 7 b0 Segment output disable register 2 (SEG2 : address 0FFA 16 ) Segment output disable bit 16 0 : Output port P20 1 : Segment output SEG 16 Segment output disable bit 17 0 : Output port P21 1 : Segment output SEG 17 Segment output disable bit 18 0 : Output port P22 1 : Segment output SEG 18 Segment output disable bit 19 0 : Output port P23 1 : Segment output SEG 19 Segment output disable bit 20 0 : Output port P24 1 : Segment output SEG 20 Segment output disable bit 21 0 : Output port P25 1 : Segment output SEG 21 Segment output disable bit 22 0 : Output port P26 1 : Segment output SEG 22 Segment output disable bit 23 0 : Output port P27 1 : Segment output SEG 23 Notes 1: Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable register. 2: When the VL pin input selection bit (VLSEL) of the LCD power control register (address 003816) is " 1" , settings of the segment output disable bit 22 and segment output disable bit 23 are invalid. Fig. 32 Structure of LCD related registers Rev.2.00 May 28, 2004 page 36 of 100 Rev.2.00 May 28, 2004 page 37 of 100 Address 004116 Fig. 33 Block diagram of LCD controller/driver Level shift Level shift Level shift P00/SEG0 P01/SEG1 P02/SEG2 P03/SEG3 Segment Segment Segment Segment driver driver driver driver Level shift Selector Selector Selector Selector Address 004016 P20/SEG16 Data bus Level shift 5 Level Level Level shift shift shift COM0 COM1 COM2 COM3 Common Common Common Common driver driver driver driver Level shift Timing controller 2 LCD circuit divider division ratio selection bits 2 Duty ratio selection bits LCD enable bit Bias control bit LCD power control register Bias control LCD display RAM P26/SEG22/VL1 P27/SEG23/VL2 VSS P26/ P27/ VL3 SEG22/ SEG23/ VL1 VL2 Segment Segment driver driver Level shift Selector Selector Address 004C16 LCDCK LCD divider "1" "0" f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) f(XCIN)/32 LCDCK count source selection bit 38C2 Group (A Version) 38C2 Group (A Version) Bias Control and Applied Voltage to LCD Power Input Pins When the voltage is applied from the LCD power input pins (VL1- VL3), set the VL pin input selection bit (bit 5 of the LCD power control register) and VL3 connection bit (bit 6 of LCD power control register) to "1", apply the voltage value shown in Table 9 according to the bias value. In this case, SEG22 pin and SEG23 pin cannot be used. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 9 Bias control and applied voltage to VL1-VL3 Voltage value Bias value 1/3 bias VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD 1/2 bias VL3=VLCD VL2=VL1=1/2 VLCD Common Pin and Duty Ratio Control The common pins (COM0-COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). When reset is released, VCC voltage is output from the common pin. Table 10 Duty ratio control and common pins used Duty ratio Duty ratio selection bits Common pins used Bit 1 Bit 0 2 0 1 COM0, COM1 3 1 0 COM0-COM2 4 1 1 COM0-COM3 Note: Unused common pin outputs the unselected waveform. Segment Signal Output Pin Note : VLCD is the maximum value of supplied voltage for the LCD panel. The segment signal output pins (SEG0-SEG23) are shared with ports P0-P2. When these pins are used as the segment signal output pins, set the direction registers of the corresponding pins to "1", and set the segment output disable register to " 0" . Also, these pins are set to the input port after reset, the VCC voltage is output by the pull-up resistor. Contrast adjust Contrast adjust VL3 VL3 R1 R4 VL2 VL2 R2 VL1 VL1 R3 R5 R4 = R5 R1 = R2 = R3 1/3 bias 1/2 bias Fig. 34 Example of circuit at each bias (at external power input) Rev.2.00 May 28, 2004 page 38 of 100 38C2 Group (A Version) LCD Power Circuit The LCD power circuit has the dividing resistor for LCD power which can be connected/disconnected with the LCD power control register. b7 b0 LCD power control register (VLCON : address 003816) Dividing resistor for LCD power control bit (LCDRON) 0 : Internal dividing resistor disconnected from LCD power circuit 1 : Internal dividing resistor connected to LCD power circuit Dividing resistor for LCD power selection bits (RSEL) b3 b2 1 0 : Larger resistor 0 1: 0 0: 1 1 : Smaller resistor Not used (return "0" when read) (Do not write to "1") VL pin input selection bit (VLSEL) 0 : Input invalid 1 : VL input function valid VL3 connection bit 0 : Connect LCD internal VL3 to VCC 1 : Connect LCD internal VL3 to VL3 pin Not used (return "0" when read) (Do not write to "1") Notes 1: When voltage is applied to VL1 to VL3 by using the external resistor, write "102" to dividing resistor for LCD power selection bits. 2: Setting to the VL pin input selection bit (VLSEL) = "1" has the most priority than setting to the port P2 direction register (address 0005 16 ) and segment output disable register 2 (address 0FFA16 ). 3: When the LCD drive control circuit is used at VL3 = VCC, apply VCC to VL3 pin and write "1" to VL3 connection bit. Fig. 35 Structure of LCD power control register LCD power control register (bit 6) Vcc VL3 LCD internal VL3 LCD power control register (bit 5) P27/SEG23/ VL2 LCD internal VL2 P26/SEG22/ V L1 LCD internal VL1 LCD power control register (bits 2 and 1) Dividing resistor for LCD power Fig. 36 VL block diagram Rev.2.00 LCD power control register (bit 0) May 28, 2004 page 39 of 100 LCD mode register (bit 2) 38C2 Group (A Version) LCD Display RAM The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; The 12-byte area of address 004016 to 004B16 is the designated RAM for the LCD display. When "1" is written to these addresses, the corresponding segments of the LCD display panel are turned on. f(LCDCK)= LCD Drive Timing For the LCD drive timing, type A or type B can be selected. The LCD drive timing is selected by the timing selection bit (bit 4 of LCD mode register). Type A is selected by setting the LCD drive timing selection bit to "0", type B is selected by setting the bit to "1". Type A is selected after reset. B it 7 6 (frequency of count source for LCDCK) (divider division ratio for LCD) Frame frequency= f(LCDCK) duty ratio Note (1) When the STP instruction is executed, the following bits are set to "0"; * LCD enable bit (bit 3 of LCD mode register) * Bits other than bit 6 of the LCD power control register. (2) When the voltage is applied to VL1 to VL3 by using the external resistor, write "102" to dividing resistor for LCD power selection bits (RSEL) of the LCD power control register (address 003816). (3) When the LCD drive control circuit is used at VL3 = VCC, apply VCC to VL3 pin and write "1" to VL3 connection bit of the LCD power control register (address 003816). 5 4 3 2 1 0 Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 Fig. 37 LCD display RAM map Rev.2.00 May 28, 2004 page 40 of 100 38C2 Group (A Version) Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 VL3 VSS SEG0 OFF LCD COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2=VL1 VSS COM0 COM1 COM2 VL3 VSS SEG0 LCD ON OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2=VL1 VSS COM0 COM1 VL3 VSS SEG0 LCD ON OFF ON OFF ON OFF ON OFF COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 Fig. 38 LCD drive waveform (1/2 bias, type A) Rev.2.00 May 28, 2004 page 41 of 100 38C2 Group (A Version) Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2 VL1 VSS COM0 COM1 COM2 COM3 VL3 SEG0 VSS OFF LCD COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2 VL1 VSS COM0 COM1 COM2 VL3 SEG0 VSS LCD ON OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2 VL1 VSS COM0 COM1 VL3 SEG0 VSS LCD ON OFF ON OFF ON OFF ON OFF COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 Fig. 39 LCD drive waveform (1/3 bias, type A) Rev.2.00 May 28, 2004 page 42 of 100 38C2 Group (A Version) Internal signal LCDCK timing 1/4 duty Voltage level 1 frame 1 frame VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 VL3 SEG0 VSS OFF LCD COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty 1 frame 1 frame VL3 VL2=VL1 VSS COM0 COM1 COM2 VL3 SEG0 VSS LCD ON OFF COM0 COM2 1/2 duty ON COM1 1 frame OFF COM0 1 frame COM2 ON COM1 1 frame OFF COM0 COM2 1 frame VL3 VL2=VL1 VSS COM0 COM1 VL3 SEG0 VSS LCD ON OFF ON OFF ON OFF ON OFF COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 Fig. 40 LCD drive waveform (1/2 bias, type B) Rev.2.00 May 28, 2004 page 43 of 100 38C2 Group (A Version) Internal signal LCDCK timing 1/4 duty Voltage level 1 frame 1 frame VL3 VL2 VL1 V SS COM0 COM1 COM2 COM3 VL3 VL2 VL1 V SS SEG0 OFF LCD COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty 1 frame 1 frame VL3 VL2 VL1 V SS COM0 COM1 COM2 VL3 VL2 VL1 V SS SEG0 LCD 1/2 duty ON OFF COM0 COM2 1 frame ON COM1 OFF COM0 1 frame COM2 ON COM1 1 frame OFF COM0 COM2 1 frame VL3 VL2 VL1 V SS COM0 COM1 VL3 VL2 VL1 V SS SEG0 LCD ON COM1 OFF COM0 Fig. 41 LCD drive waveform (1/3 bias, type B) Rev.2.00 May 28, 2004 page 44 of 100 ON OFF ON COM1 COM0 COM1 OFF COM0 ON COM1 OFF COM0 38C2 Group (A Version) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit counter. Initial Value of Watchdog Timer At reset or writing to the watchdog timer control register, each watchdog timer is set to "FF16." Instructions such as STA, LDM and CLB to generate the write signals can be used. The written data in bits 0 to 5 are not valid, and the above values are set. When reading the watchdog timer control register is executed, the contents of the high-order 6-bit counter and the STP instruction disable bit (bit 6), and the count source selection bit (bit 7) are read out. When the STP instruction disable bit is "0", the STP instruction is valid. The STP instruction is disabled by writing to "1" to this bit. In this time, when the STP instruction is executed, it is handled as the undefined instruction, the internal reset occurs. This bit cannot be set to " 0" by program. This bit" is0" after reset. The time until the underflow of the watchdog timer control register after writing to the watchdog timer control register is executed is as follows (when the bit 7 of the watchdog timer control register is "0") ; * at frequency/2/4/8 mode (f(XIN)) = 8 MHz): 32.768 ms * at low-speed mode (f(XCIN) = 32 KHz): 8.19s Standard Operation of Watchdog Timer The watchdog timer is in the stop state at reset and the watchdog timer starts to count down by writing an optional value in the watchdog timer control register. An internal reset occurs at an underflow of the watchdog timer. Then, reset is released after the reset release time is elapsed, the program starts from the reset vector address. Normally, writing to the watchdog timer control register before an underflow of the watchdog timer is programmed. If writing to the watchdog control register is not executed, the watchdog timer does not operate. Note The watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode. Accordingly, do not underflow the watchdog timer in this time. Data bus Watchdog timer H count source selection bit XCIN "0" 1/1024 System clock control bit (bit 6) "1" 1/4 "0" Watchdog timer L (2) Watchdog timer H (6 ) "1" 16" is set when " FF watchdog timer control register is written to. XIN Undefined instruction Reset STP instruction disable bit Reset circuit STP instruction RESET Internal reset Wait until reset release Fig. 42 Block diagram of Watchdog timer b0 b7 Watchdog timer control register (WDTCON : address 0037 16) Watchdog timer H (for read-out of high-order 6 bit) " FF 16" is set to watchdog timer by writing to these bits. STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer count source selection bit 0: 1/1024 of system clock 1: 1/4 of system clock Fig. 43 Structure of Watchdog timer control register f(XIN) Internal reset signal Watchdog timer detected Fig. 44 Timing diagram of reset output Rev.2.00 May 28, 2004 page 45 of 100 Approx. 32 msec (at f(XIN)=8MHZ) 38C2 Group (A Version) CLOCK OUTPUT FUNCTION b7 A system clock can be output from I/O port P36.The triple function of I/O port, timer 2 output function and system clock output function is performed by the clock output control register (address 001816) and the timer 2 output selection bit of the timer 12 mode register (address 002516). In order to output a system clock from I/O port P36, set the timer 2 output selection bit and bit 0 of the clock output control register to "1". When the clock output function is selected, a clock is output while the direction register of port P36 is set to the output mode. P36 is switched to the port output or the output (timer 2 output and the clock output) except port at the cycle after the timer 2 output control bit is switched. b0 Clock output control register (CKOUT : address 001816) P36 clock output control bit 0: Timer 2 output 1: System clock output Not used (returns "0" when read) (Do not write "1" to these bits.) Fig. 45 Structure of clock output control register Timer 2 output control bit Timer 2 latch (8) S 1/2 Timer 2 (8) T Q Q "0" T2OUT output edge switch bit "0" "1" "1" P36/T2OUT/ P36 clock output control bit P36 direction register P36 latch Timer 2 output selection bit System clock b7 b0 Timer 12 mode register (address 002516) T12M Timer 2 output selection bit 0: I/O port 1: Timer 2 output Fig. 46 Block diagram of Clock output function Rev.2.00 May 28, 2004 page 46 of 100 38C2 Group (A Version) RESET CIRCUIT Poweron To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between VCC (min.) and 5.5 V, and the quartz-crystal oscillator should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage meets VIL spec. when a power source voltage passes VCC (min.). RESET VCC Power source voltage 0V Reset input voltage 0V RESET VIL spec. VCC Power source voltage detection circuit Fig. 47 Reset circuit example XIN RESET Internal reset Reset address from vector table Address ? Data ? ? ? FFFC ADL FFFD ADH SYNC XIN : about 8000 cycles Note 1: The frequency relation of f(X IN) and f() is f(XIN) = 8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 48 Reset sequence Rev.2.00 May 28, 2004 page 47 of 100 ADH, ADL 38C2 Group (A Version) Address Register contents Address Register contents (1) Port P0 000016 0016 (35) Watchdog timer control register 003716 0 0 1 1 1 1 1 1 (2) Port P0 direction register 000116 0016 (36) LCD power control register 003816 0016 (3) Port P1 000216 0016 (37) LCD mode register 003916 0016 (4) Port P1 direction register 000316 0016 (38) Interrupt edge selection register 003A16 0016 (5) Port P2 000416 0016 (39) CPU mode register 003B16 0 1 0 0 1 0 0 0 (6) Port P2 direction register 000516 0016 (40) Interrupt request register 1 003C16 0016 (7) Port P3 000616 0016 (41) Interrupt request register 2 003D16 0016 (8) Port P3 direction register 000716 0016 (42) Interrupt control register 1 003E16 0016 (9) Port P4 000816 0016 (43) Interrupt control register 2 003F16 0016 (10) Port P4 direction register 000916 0016 (44) Serial I/O1 control register 0FE016 0016 (11) Port P5 000A16 0016 (45) UART1 control register 0FE116 1 1 1 0 0 0 0 0 (12) Port P5 direction register 000B16 0016 (46) Serial I/O2 control register 0FE316 (13) Port P6 000C16 0016 (47) UART2 control register 0FE416 1 1 1 0 0 0 0 0 (14) Port P6 direction register 000D16 0016 (48) Oscillation output control register 0FF016 0016 (15) Clock output control register 001816 0016 (49) PULL register 0FF116 0016 (16) A-D control register 001916 0816 (50) Key input control register 0FF216 0016 (17) Serial I/O1 status register 001D16 1 0 0 0 0 0 0 0 (51) Timer 1234 mode register 0FF316 0016 (18) Serial I/O2 status register 001F16 1 0 0 0 0 0 0 0 (52) Timer X control register 0FF416 0016 (19) Timer 1 002016 FF16 (53) Timer 12 frequency division selection register 0FF516 0016 (20) Timer 2 002116 0116 (54) Timer 34 frequency division selection register 0FF616 0016 (21) Timer 3 002216 FF16 (55) Timer XY frequency division selection register 0FF716 0016 (22) Timer 4 002316 FF16 (56) Segment output disable register 0 0FF816 FF16 (23) PWM01 register 002416 0016 (57) Segment output disable register 1 0FF916 FF16 (24) Timer 12 mode register 002516 0016 (58) Segment output disable register 2 0FFA16 FF16 (25) Timer 34 mode register 002616 0016 (59) Timer Y mode register 2 0FFB16 0016 (26) Compare register (low-order) 002816 0016 (60) Flash memory control register 0FFE16 0 0 0 0 1 (27) Compare register (high-order) 002916 0016 (61) Processor status register (28) Timer X (low-order) 002A16 FF16 (62) Program counter (29) Timer X (high-order) 002B16 FF16 (30) Timer X (extension) 002C16 0016 (31) Timer Y (low-order) 002D16 FF16 (32) Timer Y (high-order) 002E16 FF16 (33) Timer X mode register 002F16 0016 (34) Timer Y mode register 003016 0016 Fig. 49 Internal status at reset Rev.2.00 May 28, 2004 page 48 of 100 0016 (PS) 1 (PCH) FFFD16 contents (PCL) FFFC16 contents X: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. 38C2 Group (A Version) CLOCK GENERATING CIRCUIT Notes on Clock Generating Circuit The 38C2 group has two built-in oscillation circuits; main clock XIN- XOUT and sub-clock XCIN-XCOUT. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feedback resistor exists on-chip. However, an external feedback resistor is needed between XCIN and XCOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. If you switch the mode between frequency/2/4, or 8 and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode, set the frequency in the condition that f(XIN) > 3* f(XCIN). Frequency Control (1) Frequency/8 Mode The system clock is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) Frequency/4 Mode The system clock is the frequency of XIN divided by 4. (3) Frequency/2 Mode The system clock is the frequency of XIN divided by 2. Oscillation Control (1) Stop Mode If the STP instruction is executed, the system clock stops at an "H" level, and main clock and sub-clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2) before the STP instruction. The frequency divider for timer 1 is used for the timer 1 count source, and the output of timer 1 is forcibly connected to timer 2. In this time, bits 0 to 5 of the timer 12 mode register are cleared to " 0" . The values of the timer 12 frequency divider selection register are not changed. Set the interrupt enable bits of the timer 1 and timer 2 to disabled (" 0" ) before executing the STP instruction. Oscillator restarts when reset occurs or an interrupt request is received, but the system clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. (4) Low-speed Mode The system clock is the frequency of XCIN divided by 2. In the lowspeed mode, the low-power dissipation operation can be performed when the main clock XIN is stopped by setting the bit 7 of the CPU mode register to "0". In this case, when main clock XIN oscillation is restarted, generate the wait time until the oscillation is stable by program after the bit 7 of the CPU mode register is set to " 1" . (2) Wait Mode If the WIT instruction is executed, only the system clock stops at an "H" state. The states of main clock and sub clock are the same as the state before executing the WIT instruction, and oscillation does not stop. Since supply of system clock is started immediately after the interrupt is received, the instruction can be executed immediately. XCIN XCIN XCOUT XIN XOUT XCOUT Open Rd Rd CCIN CCIN XOUT Rf (Note) Rf XIN CCOUT CIN CCOUT External oscillation circuit COUT VCC Note: An external feed-back resistor may be needed depending on conditions. VSS Fig. 51 External clock input circuit Fig. 50 Ceramic resonator circuit Rev.2.00 May 28, 2004 page 49 of 100 38C2 Group (A Version) System clock control bits "00,10,11" "01" P61/XCIN P62/XCOUT "00,10,11" "01" System clock control bits "00,10" XIN XOUT Timer 1 count source selection bits "01" System clock control bits Frequency divider for Timer Timer 1 Timer 2 count source selection bits "00" Timer 2 "00" "10" "01,11" 1/2 1/2 System clock control bits "01,10,11" 1/2 1/2 Main clock division ratio selection bits Frequency/8"0mode 0" "00" Frequency/4 mode "01" Frequency/2 mode "10" System clock control bits "00,10" "01,11" System clock "00" Q S R S STP instruction Reset Interrupt disable flag I Interrupt request Fig. 52 Clock generating circuit block diagram Rev.2.00 May 28, 2004 page 50 of 100 WIT instruction R Q Q S R STP instruction 38C2 Group (A Version) System clock = Main clock f(XIN) XIN oscillation, XCIN stop CM7=0, CM6=1 Frequency/2 mode Reset System clock : f(XIN)/2 CM5=1 CM4=0 Frequency/4 mode System clock : f(XIN)/4 CM5=0 CM4=1 Frequency/8 mode System clock : f(XIN)/8 CM5=0 CM4=0 CM7="0" XIN oscillation, XCIN oscillation CM7=1, CM6=1 CM7="1" Frequency/2 mode System clock : f(XIN)/2 CM5=1 CM4=0 Frequency/4 mode System clock : f(XIN)/4 CM5=0 CM4=1 Frequency/8 mode System clock : f(XIN)/8 CM5=0 CM4=0 CM6="1" System clock = Sub clock f(XCIN) XIN oscillation, XCIN oscillation CM7=1, CM6=0 b7 b4 CPU mode register (CPUM : address 003B16) CM6="0" Low-speed mode System clock f(:XCIN)/2 CM7="1" XIN stop, XCIN oscillation CM7=0, CM6=0 CM7="0" CM5 CM4 : Main clock division ratio selection bits 00: XIN/8 (frequency/8) 01: XIN/4 (frequency/4) 10: XIN/2 (frequency/2) 11: Not available CM7 CM6 : System clock control bits 00: XIN stop, XCIN oscillation, system clock = XCIN 01: XIN oscillation, XCIN stop, system clock = XIN 10: XIN oscillation, XCIN oscillation, system clock = XCIN 11: XIN oscillation, XCIN oscillation, system clock = XIN Low-power dissipation mode System clock : f(XCIN)/2 Notes 1: When the mode is switched from frequency/2/4/8 to the low-speed mode, or the opposite is performed, change CM7 at first, and then, change CM6 after the oscillation of the changed mode is stabilized. 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer and LCD operate in the wait mode. 4: When the stop mode is ended, a delay time can be set by connecting timer 1 and timer 2. Fig. 53 State transitions of system clock Rev.2.00 May 28, 2004 page 51 of 100 38C2 Group (A Version) Oscillation External Output Function Note The 38C2 group has the oscillation external output function to output the rectangular waveform of the clock obtained by the oscillation circuits from P41 and P40. In order to validate the oscillation external output function, set P40 or P41, or both to the output mode (set the corresponding direction register to " 1" ). The level of the XCOUT external output signal becomes "H" by the P40/P41 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0FF016) in the following states; * the function to output the signal from the XCOUT pin externally is selected * the sub clock (XCIN-XCOUT) is in the stop oscillating or stop mode. Likewise, the level of the XOUT external output signal becomes "H" by the P40/P41 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0FF016) in the following states; * the function to output the signal from the XOUT pin externally is selected * the main clock (XIN- XOUT) is in the stop oscillating or stop mode. When the signal from the XOUT pin or XCOUT pin of the oscillation circuit is input directly to the circuit except this MCU and used, the system operation may be unstabilized. In order to share the oscillation circuit safely, use the clock output from P40 and P41 by this function for the circuits except this MCU. P61/XCIN b7 b0 Oscillation output control register (OSCOUT : address 0FF0 16) P40/P41 oscillation output control bits b1b0 00: P41, P40 = Normal port 01: P41 = Normal port, P4 0 = XOUT 10: P41 = Normal port, P4 0 = XCOUT 11: P41 = XCOUT , P40 = XOUT Not used (return " 0" when read) (Do not write to " 1" ) Fig. 54 Structure of oscillation output control register P62/XCOUT "01" "00", "10", "11" System clock control bits P41 output latch P41 direction register P40 output latch System clock control bits "00", "10", "11" "01" XI N Oscillation output selection circuit P41/OOUT1 P40/OOUT0 XOUT P40 direction register OSCOUT control System clock control bits "01", "10", "11" "00" Q S R STP instruction Reset Interrupt disable flag I Interrupt request Fig. 55 Block diagram of Oscillation output function Rev.2.00 May 28, 2004 page 52 of 100 38C2 Group (A Version) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to " 1." Serial I/O continues to output the final bit from the TXD pin after transmission is completed. A-D Converter Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, set the A-D clock frequency to 250 kHz or more. Also, when the STP instruction is executed during the A-D conversion, the A-D conversion is stopped immediately, the A-D conversion completion bit is set to " 1" , and the interrupt request is generated. Decimal Calculations * To calculate in decimal notation, set the decimal mode flag (D) to "1," then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing an SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers * If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * The timers share the one frequency divider to generate the count source. Accordingly, when each timer starts operating, initializing the frequency divider is not executed. Therefore, when the frequency divider is selected for the count source, the delay of the maximum one cycle of the count source is generated until the timer starts counting or the waveform is output from timer starts operating. Also, the count source cannot be checked externally. Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is " 1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Rev.2.00 May 28, 2004 page 53 of 100 Instruction Execution Time The instruction execution time is obtained by multiplying the number of cycles shown in the list of machine instructions by the period of the internal clock . 38C2 Group (A Version) NOTES ON USE VL3 pin Noise When LCD drive control circuit is not used, connect VL3 to VCC. Countermeasures against noise (1) Shortest wiring length Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit RESET VSS VSS N.G. XIN XOUT VSS N.G. VSS RESET VSS O.K. Fig. 56 Wiring for the RESET pin Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Rev.2.00 May 28, 2004 page 54 of 100 O.K. Fig. 57 Wiring for clock I/O pins (2) Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. AA AA AA AA AA VCC Reset circuit XIN XOUT VSS VSS N.G. AA AA AA AA AA VCC VSS O.K. Fig. 58 Bypass capacitor across the VSS line and the VCC line 38C2 Group (A Version) (3) Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (4) Wiring to VPP pin of flash memory version Connect an approximately 10 k resistor to the VPP pin the shortest possible in series and also to the VSS pin. Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Note: Even when a circuit which included an approximately 10 k resistor is used in the Mask ROM version, the microcomputer operates correctly. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M XIN XOUT VSS Large current Reason The VPP pin of the flash memory version is the power source input pin for the built-in flash memory. When programming/erasing in the built-in flash memory, the impedance of the VPP pin is low to allow the electric current for writing/erasing flow into the flash memory. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in flash memory, which may cause a program runaway. About 10k CNVSS/VPP VSS Fig. 60 Wiring for the VPP pin of flash memory Electric Characteristic Differences Between Mask ROM and Flash memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between the mask ROM and flash memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the flash memory version and then switching to use of the mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. GND Oscillation Circuit Constant Installing oscillator away from signal lines where potential levels change frequently N.G. Do not cross CNTR XIN XOUT VSS Fig. 59 Wiring for a large current signal line/Writing of signal lines where potential levels change frequently Rev.2.00 May 28, 2004 page 55 of 100 (1) Determine an oscillation circuit constant after consulting the oscillator manufacturer about the matching characteristic evaluation. (2) Since oscillation circuit constants may be differences between the flash memory version and the mask ROM version, evaluate them, respectively. 38C2 Group (A Version) FLASH MEMORY MODE Summary The 38C2 group (A version)'s flash memory version has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 4.5 to 5.5 V, and 2 power sources when VCC is 3.0 to 4.5 V. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Table 11 lists the summary of the 38C2 group (A version)'s flash memory version. This flash memory version has some blocks on the flash memory as shown in Figure 61 and each block can be erased. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user's application system. This Boot ROM area can be rewritten in only parallel I/O mode. Table 11 Summary of 38C2 group (A version)'s flash memory version Item Specifications Power source voltage (Vcc) VCC = 2.5 to 5.5 V (Note 1) VCC = 2.5 to (VCC at program/erase) + 0.5 V (Note 2) Program/Erase VPP voltage (VPP) Flash memory mode VPP = 4.5 to 5.5 V, VCC = 3.0 to 5.5 V 3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode Erase block division User ROM area Refer to Fig. 61. Boot ROM area Not divided (4K bytes) (Note 3) Program method In units of bytes Erase method Block erase Program/Erase control method Program/Erase control by software command Number of commands 5 commands Number of program/Erase times 100 times ROM code protection Available in parallel I/O mode and standard serial I/O mode Notes 1: It is the rating value when Vcc = 5.0 to 5.5 V at program/erase. 2: It is the rating value when Vcc = 3.0 to 5.0 V at program/erase. 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be erased and written in only parallel I/O mode. Rev.2.00 May 28, 2004 page 56 of 100 38C2 Group (A Version) Parallel I/O mode User ROM area 100016 800016 Block 1 : 28 Kbytes Block 0 : 32 Kbytes F00016 FFFF16 FFFF16 Boot ROM area 4 Kbytes BSEL=0 BSEL=1 CPU rewrite mode, standard serial I/O mode User ROM area 100016 800016 Block 1 : 28 Kbytes Block 0 : 32 Kbytes F00016 FFFF16 FFFF16 User area / Boot area select bit = " "0 Product name M38C29FFA Flash memory top address 100016 Boot ROM area 4 Kbytes User area / Boot area select bit = " "1 Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. Fig. 61 Block diagram of built-in flash memory (1) CPU Rewrite Mode Boot Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 61 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area before it can be executed. The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 61 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P41(CE) pin high, the CNVSS pin high, the CPU starts operating (start address of program is stored into addresses FFFC16 and FFFD16) using the control program in the Boot ROM area. This mode is called the "Boot mode". Also, User ROM area can be rewritten using the control program in the Boot ROM area. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. Rev.2.00 May 28, 2004 page 57 of 100 38C2 Group (A Version) Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM area before it can be executed. The MCU enters CPU rewrite mode by applying 4.5 V to 5.5 V to the CNVSS pin and setting "1" to the CPU rewrite mode select bit (bit 1 of address 0FFE16). Then, software commands can be accepted. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 62 shows the flash memory control register. Bit 0 of the flash memory control register is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0" (busy). Otherwise, it is " 1" (ready). Bit 1 of the flash memory control register is the CPU rewrite mode select bit. When this bit is set to "1", the MCU enters CPU rewrite mode. And then, software commands can be accepted. In CPU rewrite mode, the CPU becomes unable to access the internal flash b7 memory directly. Therefore, use the control program in the internal RAM for write to bit 1. To set this bit 1 to "1", it is necessary to write "0" and then write "1" in succession to bit 1. The bit can be set to "0" by only writing " 0" . Bit 2 of the flash memory control register is the CPU rewrite mode entry flag. This flag indicates "1" in CPU rewrite mode, so that reading this flag can check whether CPU rewrite mode has been entered or not. Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1", setting "1" for this bit resets the control circuit. To release the reset, it is necessary to set this bit to " 0" . Bit 4 of the flash memory control register is the User area/Boot area select bit. When this bit is set to "1", Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In Boot mode, this bit is set to "1" automatically. Programming of this bit must be executed on program of the internal RAM. Figure 63 shows a flowchart for setting/releasing CPU rewrite mode. b0 Flash memory control register (address 0FFE16) FMCR RY/BY status flag 0: Busy (being written or erased) 1: Ready CPU rewrite mode select bit (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User area / Boot area select bit 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (" 0" at write, undefined at read) Notes 1: The contents of flash memory control register are "XXX00001" just after reset release. 2: For this bit to be set to "1", the user needs to write "0" and then "1" to it in succession. Use the control program in the RAM for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is "1". Set this bit 3 to "0" subsequently after setting bit 3 to "1". Fig. 62 Structure of flash memory control register Rev.2.00 May 28, 2004 page 58 of 100 38C2 Group (A Version) Start Single-chip mode or Boot mode (Note 1) Set CPU mode register (Note 2) Transfer CPU rewrite mode control program to internal RAM Jump to control program transferred to internal RA M (Subsequent operations are executed by control program in this RAM) Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession) Check CPU rewrite mode entry flag Using software command execute erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing "1" and then "0" in succession) (Note 3) Write "0" to CPU rewrite mode select bit End Notes 1: When starting the MCU in the single-chip mode, supply 4.5 to 5.5 V to the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set the main clock as follows depending on the XIN divider select bits of clock control register (bits 4, 5 of address 003F16): 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory. Fig. 63 CPU rewrite mode set/release flowchart Rev.2.00 May 28, 2004 page 59 of 100 38C2 Group (A Version) Notes on CPU Rewrite Mode Take the notes described below when rewriting the flash memory in CPU rewrite mode. Operation speed During CPU rewrite mode, set the system clock to 4.0 MHz or less using the main clock division ratio selection bits (bits 4 and 5 of address 003B16). Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode. Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. Watchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. Reset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVss = "H", so that the program will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area. Rev.2.00 May 28, 2004 page 60 of 100 38C2 Group (A Version) Software Commands Table 12 lists the software commands. After setting the CPU rewrite mode select bit to "1", execute a software command to specify an erase or program operation. Each software command is explained below. The RY/BY status flag of the flash memory control register is "0" during write operation and "1" when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Read Array Command (FF16) The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained until another command is written. Start Write 4016 Write Write address Write data Read Status Register Command (7016) When the command code "7016" is written in the first bus cycle, the contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. Read status register Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code " 50 16" in the first bus cycle. Program Command (4016) Program operation starts when the command code "4016" is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by read _____ status register or the RY/BY status flag. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to "0" at the same time the write operation starts and is returned to "1" upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written. SR7 = 1 ? or RY/BY = 1 ? NO YES NO SR4 = 0 ? Program error YES Program completed Fig. 64 Program flowchart Table 12 List of software commands (CPU rewrite mode) Command Cycle number Mode First bus cycle Data Address (D0 to D7) X Second bus cycle Mode Address Data (D0 to D7) Read X SRD (Note 1) FF16 Read array 1 Write Read status register 2 Write X 7016 Clear status register 1 Write X 5016 Program 2 Write X 4016 Write WA (Note 2) Block erase 2 Write X 2016 Write BA (Note 4) Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address to be erased (Input the maximum address of each block.) 4: X denotes a given address in the User ROM area. Rev.2.00 May 28, 2004 page 61 of 100 (Note 3) WD (Note 2) D016 38C2 Group (A Version) Block Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed by read status register or the RY/BY status flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to " 0" at the same time the block erase operation starts and is returned to " 1" upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. The RY/BY status flag is "0" during block erase operation and "1" when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Start Write 2016 Write D016 Block address Read status register SR7 = 1 ? or RY/BY = 1 ? YES SR5 = 0 ? YES Erase completed (write read command FF16) Fig. 65 Erase flowchart Rev.2.00 May 28, 2004 page 62 of 100 NO NO Erase error 38C2 Group (A Version) Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to " 80 16" . Table 13 shows the status register. Each bit in this register is explained below. *Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is reset to " 0" . *Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to " 1" . The program status is reset to " 0" when it is cleared. If "1" is written for any of the SR5 and SR4 bits, the read array, program, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to " 1" . *Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to "0" (busy) during write or erase operation and is set to " 1" when these operations ends. After power-on, the sequencer status is set to " 1" (ready). Table 13 Definition of each bit in status register Each bit of SRD bits SR7 (bit7) SR6 (bit6) Sequencer status Reserved SR5 (bit5) SR4 (bit4) Erase status Program status SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Rev.2.00 May 28, 2004 Status name Definition "1" Ready - "0" Busy - Terminated normally Terminated normally Terminated normally Terminated normally Reserved Reserved Reserved - - Reserved - - page 63 of 100 38C2 Group (A Version) Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 66 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = 1 and SR5 = 1 ? YES Command sequence error NO SR5 = 0 ? NO Erase error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. YES SR4 = 0 ? NO Program error Should a program error occur, the block in error cannot be used. YES End (block erase, program) Note: When one of SR5 and SR4 is set to "1", none of the read array, program, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 66 Full status check flowchart and remedial procedure for errors Rev.2.00 May 28, 2004 page 64 of 100 38C2 Group (A Version) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control address (address FFDB16) in parallel I/O mode. Figure 67 shows the ROM code protect control address (address FFDB16). (This address exists in the User ROM area.) If one or both of the pair of ROM code protect bits is set to "0", the b7 ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to "00", the ROM code protect is turned off, so that the contents of internal flash memory can be readout or modified. Once the ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM code protect reset bits. b0 ROM code protect control address (address FFDB16) ROMCP (FF16 when shipped) Reserved bits ("1" at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (Note 3) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 1) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite mode. Fig. 67 Structure of ROM code protect control address Rev.2.00 May 28, 2004 page 65 of 100 38C2 Group (A Version) ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD416 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFD416 ID1 FFD516 ID2 FFD616 ID3 FFD716 ID4 FFD816 ID5 FFD916 ID6 FFDA16 ID7 FFDB16 ROM code protect control Interrupt vector area Fig. 68 ID code store addresses Rev.2.00 May 28, 2004 page 66 of 100 38C2 Group (A Version) (2) Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 38C2 Group group (A version)'s flash memory version. For details, refer to the user's manual of each writer manufacturer. User ROM and Boot ROM Areas In parallel I/O mode, the User ROM and Boot ROM areas shown in Figure 61 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed only in the User ROM area. The Boot ROM area is 4 Kbytes in size and located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from our factory. Therefore, using the MCU in standard serial I/O mode, do not rewrite to the Boot ROM area. Rev.2.00 May 28, 2004 page 67 of 100 38C2 Group (A Version) (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting "H" to the P41 (CE) pin and "H" to the CNVSS pin (when VCC = 4.5 to 5.5 V, connect to VCC, and when VCC = 3.0 to 4.5 V, apply 4.5 V to 5.5 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to " L" level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. Figure 69 shows the pin connections for the standard serial I/O mode. In standard serial I/O mode, serial data I/O uses the four UART2 pins SCLK2, RxD2, TxD2 and SRDY2 (BUSY). The SCLK2 pin is the transfer clock input pin through which an external transfer clock is input. The TxD2 pin is for CMOS output. The SRDY2 (BUSY) pin outputs "L" level when ready for reception and " H" level when reception starts. Serial data I/O is transferred serially in 8-bit units. In standard serial I/O mode, only the User ROM area shown in Figure 61 can be rewritten. The Boot ROM area cannot. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Outline Performance (Standard Serial I/O Mode) In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART2). In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK2 pin, and are then input to the MCU via the RxD2 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD2 pin. The TxD2 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the SRDY2 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the SRDY2 (BUSY) pin is " L" level. Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following explains software commands, status registers, etc. Rev.2.00 May 28, 2004 page 68 of 100 38C2 Group (A Version) Table 14 Description of pin function (Flash Memory Serial I/O Mode) Pin name Signal name Function I/O Apply guaranteed voltage of program/erase to the Vcc pin and 0 V to the Vss pin. VCC,VSS Power supply CNVSS CNVSS I Connect this pin to Vcc at Vcc = 4.5 to 5.5 V. RESET Reset input I Connect this pin to VPP at Vcc = 3.0 to 4.5 V. Reset input pin. When XIN oscillation is stable, input " L" level for s2or more. XIN Clock input I Connect a ceramic resonator or crystal oscillator between the XIN and XOUT pins. XOUT Clock output O signal of XIN pin to XOUT pin. AVSS Analog power supply VREF Analog reference voltage P00- P07 I/O port P0 I/O Input " L" or " H" level, or keep open. P10- P17 I/O port P1 I/O Input " L" or " H" level, or keep open. P20- P27 I/O port P2 I/O Input " L" or " H" level, or keep open. P30 P31 BUSY output SCLK input O I BUSY signal output pin. Serial clock input pin. P32 TXD output O Serial data output pin. P33 RXD input I Serial data input pin. P34- P37 I/O port P3 I/O Input " L" or " H" level, or keep open. P40 I/O port P4 I/O Input " L" or " H" level, or keep open. P41 CE input I Input " H" level. P42- P47 I/O port P4 I/O Input " L" or " H" level, or keep open. P50- P57 I/O port P5 I/O Input " L" or " H" level, or keep open. P60 I/O port P6 I/O Input " L" or " H" level, or keep open. P61/XCIN I/O port P6/Sub clock input I/O When these pins are used for sub-clock, connect a quartz-crystal oscillator between the XCIN and XCOUT pins. P62/XCOUT I/O port P6/Sub clock output I/O When entering an externally driven clock, enter it from XCIN and leave XOUT open. COM0-COM3 Common output O VL3 Power supply for LCD When entering an externally driven clock, enter it from XIN and input the inverted Connect to Vss. I Apply reference voltage of A-D to this pin. When these pins are used as port, input " L" May 28, 2004 page 69 of 100 level, or keep open. Apply LCD power source to this pin. When the LCD drive control circuit is not used, connect this pin to Vcc. Rev.2.00 or " H" When the LCD control circuit is not used, keep open. P04/SEG4 P05/SEG5 P06/SEG6 P07/SEG7 P10/SEG8 P11/SEG9 P12/SEG10 P13/SEG11 P14/SEG12 P15/SEG13 P16/SEG14 P17/SEG15 P20/SEG16 P21/SEG17 P22/SEG18 P23/SEG19 38C2 Group (A Version) VCC VSS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 (KW7)/P03/SEG3 (KW6)/P02/SEG2 (KW5)/P01/SEG1 (KW4)/P00/SEG0 (KW3)/P57/SRDY1 (KW2)/P56/SCLK1 (KW1)/P55/TXD1 (KW0)/P54/RXD1 P53/T4OUT/PWM1 P52/T3OUT/PWM0 P51/INT1 P50/INT0 AVSS VREF P47/RTP1/AN7 P46/RTP0/AN6 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 M38C29FFAFP/HP 57 25 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 *2 Mode setup method Signal Value CNVss CE RESET 4.5 to 5.5 V Vcc Vss Vcc 64P6U-A/64P6Q-A *1.Connect to oscillation circuit. *2.Connect to Vcc when Vcc=4.5 to 5.5V. Connect to VPP (=4.5 to 5.5V) when Vcc=3.0 to 4.5V. Fig. 69 Pin connection diagram in serial I/O mode Rev.2.00 May 28, 2004 page 70 of 100 *1 VPP CE RESET P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 CNVSS RESET P62/XCOUT P61/XCIN VSS XIN XOUT VCC P60/CNTR1 P37/CNTR0/(LED7) 1 P24/SEG20 P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 VL3 COM0 COM1 COM2 COM3 P30/SRDY2/(LED0) P31/SCLK2/(LED1) P32/TXD2/(LED2) P33/RXD2/(LED3) P34/INT2/(LED4) P35/TXOUT/(LED5) P36/T2OUT/ /(LED 6) SCLK BUSY TXD RXD 38C2 Group (A Version) Example Circuit Application for Standard Serial I/O Mode Figure 70 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information. SCLK2 Clock input P41(CE) SRDY2(BUSY) BUSY output Data input RXD2 Data output TXD2 M38C29FFA VPP power source input CNVss Notes 1: Control pins and external circuitry will vary according to a programmer. For more information, see the programmer manual. 2: In this example, the Vpp power supply is supplied from an external source (programmer). To use the user' s power source, connect to 4.5 V to 5.5 V. Fig. 70 Example circuit application for standard serial I/O mode Rev.2.00 May 28, 2004 page 71 of 100 38C2 Group (A Version) ELECTRICAL CHARACTERISTICS (Flash memory version) Absolute Maximum Ratings Table 15 Absolute maximum ratings (Flash memory version) Symbol VCC Ratings Unit - 0.3 to 6.5 - 0.3 to VCC+0.3 V Conditions Parameter All voltages are based on Vss. Output transistors are cut off. VI Power source voltage Input voltage P00- P07, P10- P17, P20- P27, P30- P37, P40- P47, P50- P57, P60- P62 VI Input voltage VL1 - 0.3 to VL2 V VI Input voltage VL2 VL1 to VL3 V VI Input voltage VL3 VI VI Input voltage RESET, XIN Input voltage CNVSS VO Output voltage P00- P07, P10- P17, P20- P27 VL2 to 6.5 V V - 0.3 to 6.5 V V At output port - 0.3 to VCC+0.3 V At segment output - 0.3 to VL3+0.3 V - 0.3 to VL3+0.3 - 0.3 to VCC+0.3 V VO Output voltage COM0-COM3 Output voltage P30- P37, P40- P47, P50- P57, P60- P62 VO Output voltage XOUT - 0.3 to VCC+0.3 V Pd Power dissipation Ta = 25C 300 mW Topr Operating temperature At MCU operation - 20 to 85 C 25 5 C C VO - 0.3 to VCC+0.3 At flash memory mode Tstg - 40 to 125 Storage temperature V Recommended Operating Conditions Table 16 Recommended operating conditions (Flash memory version) (Vcc = 2.5 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol VCC Parameter Power source voltage f() = 5 MHz (Note 1) f() = 4 MHz f() = 2 MHz Low-speed mode Oscillation start voltage (Note 2) VSS Power source voltage VL3 Power source voltage for LCD VREF A-D converter reference voltage AVSS Analog power source voltage VIA Analog input voltage AN0- AN7 VIH " H" input voltage VIH " H" input voltage VIH " H" 0P0 - P03, P31, P33, P34, P37, P50, P51, P54- P57, P60, P61 input voltage RESET VIH " H" input voltage IN X VIH " H" input voltage CINX(Note VIL " L" input voltage 4P0 - P07, P10- P17, P36, P40- P47, P52, VIL " L" input voltage 0P0 - P03, P31, P33, P34, P37, P50, P51, P54- P57, P60, P61, CNVSS VIL " L" input voltage VIL " L" input voltage IN X VIL " L" input voltage CINX(Note Limits Typ. Max. 4.5 5.0 5.5 (Note 3) V 4.0 5.0 5.5 (Note 3) V 2.5 5.0 V 2.5 5.0 5.5 (Note 3) 5.5 (Note 3) 0.15 f + 1.3 V 2.5 5.5 2.0 VCC 0 P20- P27, P30, P32, P35, P53, P62 4) RESET 5) P20- P27, P30, P32, P35, P53, P62 V V 0 4P0 - P07, P10- P17, P36, P40- P47, P52, Unit Min. V V V AVSS VCC V 0.7VCC VCC V 0.8VCC VCC V 0.8VCC 0.8VCC VCC V VCC V 1.5 VCC 0 0.3VCC V V 0 0.2VCC V 0 0.2VCC V 0 0.2VCC V 0 0.4 V Notes 1: When using the A-D converter, refer to " A-D Converter Characteristics" . 2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions. f: This is the XIN oscillator's oscillation frequency ( 1 MHz). For example, when oscillation frequency is 8 MHz, substitute" 8" . 3: It is the rating value when VCC = 5.0 to 5.5 V at program/erase. The value is (VCC at program/erase) + 0.5 V when VCC = 3.0 to 5.0 V at program/erase. 4: When the XCIN/P61 pin is not connected to an oscillator, refer to VIH for P61. 5: When the XCIN/P61 pin is not connected to an oscillator, refer to VIL for P61. Rev.2.00 May 28, 2004 page 72 of 100 38C2 Group (A Version) Table 17 Recommended operating conditions (Flash memory version) (Vcc = 2.5 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol Parameter IOH(peak) " H" total peak output current (Note 1) P00- P07, P10- P17, P20- P27, P30- P37 IOH(peak) " H" total peak output current (Note 1) P40- P47, P50- P57, P60- P62 IOL(peak) " L" Limits Min. Typ. Max. - 20 Unit mA - 20 mA total peak output current (Note 1) P00- P07, P10- P17, P20- P27 " L" total peak output current (Note 1) P40- P47, P50, P51, P54- P57, P60- P62 20 mA 20 mA IOL(peak) " L" total peak output current (Note 1) P30- P37, P52, P53 110 mA IOH(avg) " H" total average output current (Note 1) P00- P07, P10- P17, P20- P27, P30- P37 - 10 mA IOH(avg) " H" total average output current (Note 1) P40- P47, P50- P57, P60- P62 - 10 mA IOL(avg) " L" total average output current (Note 1) P00- P07, P10- P17, P20- P27 10 mA IOL(avg) " L" total average output current (Note 1) P40- P47, P50, P51, P54- P57, P60- P62 10 mA IOL(avg) " L" total average output current (Note 1) P30- P37, P52, P53 90 mA IOH(peak) " H" peak output current (Note 2) P00- P07, P10- P17, P20- P27 -1.0 mA IOH(peak) " H" peak output current (Note 2) P30- P37, P40- P47, P50- P57, P60- P62 -5.0 mA IOL(peak) " L" peak output current (Note 2) P00- P07, P10- P17, P20- P27 10 mA IOL(peak) " L" peak output current (Note 2) P40- P47, P50, P51, P54- P57, P60- P62 10 mA IOL(peak) " L" peak output current (Note 2) P30- P37, P52, P53 30 mA IOH(avg) " H" average output current (Note 3) P00- P07, P10- P17, P20- P27 -0.5 mA IOH(avg) " H" average output current (Note 3) P30- P37, P40- P47, P50- P57, P60- P62 -2.5 mA IOL(avg) " L" average output current (Note 3) P00- P07, P10- P17, P20- P27 5.0 mA IOL(avg) " L" average output current (Note 3) P40- P47, P50, P51, P54- P57, P60- P62 5.0 mA IOL(avg) " L" average output current (Note 3) P30- P37, P52, P53 15 mA IOL(peak) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is average value measured over 100 ms. Rev.2.00 May 28, 2004 page 73 of 100 38C2 Group (A Version) Table 18 Recommended operating conditions (Flash memory version) (Vcc = 2.5 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol Parameter f() Min. Typ. f(XCIN) Unit 5.0 MHz (4.0 V VCC < 4.5 V) 2 VCC- 4 MHz (VCC < 4.0 V) VCC MHz Timer X, Timer Y, Timer 1, Timer 2, Timer 3 and (4.5 V VCC 5.5 V) 10.0 MHz Timer 4 Clock input frequency (4.0 V VCC < 4.5 V) 4 VCC- 8 MHz (Count source frequency of each timer) (VCC < 4.0 V) (4.5 V VCC 5.5 V) 2 VCC MHz 5.0 MHz (4.0 V VCC < 4.5 V) 2 VCC- 4 VCC MHz MHz System clock frequency (VCC < 4.0 V) f(XIN) Max. (4.5 V VCC 5.5 V) f(CNTR0) Timer X and Timer Y f(CNTR1) Input frequency (duty cycle 50%) f(Tclk) Limits Test conditions Main clock input oscillation frequency (Notes 1, 3) Sub-clock input oscillation frequency (Notes 1, 2, 3) (4.5 V VCC 5.5 V) 1.0 10.0 MHz (2.5 V VCC < 4.5 V) 1.0 8.0 MHz 50 kHz 32.768 Notes 1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions. Rev.2.00 May 28, 2004 page 74 of 100 38C2 Group (A Version) Electrical Characteristics Table 19 Electrical characteristics (Flash memory version) (Vcc = 4.0 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Parameter Symbol VOH " H" output voltage P00- P07, P10- P17, P20- P27 VOH " H" output voltage P30- P37, P40- P47, P50- P57, P60- P62 Test conditions Limits Min. Typ. Max. Unit IOH = - 1 mA VCC- 2.0 V IOH = -0.25 mA VCC- 0.8 V VCC = 2.5 V IOH = - 5 mA VCC- 2.0 V IOH = - 1.5 mA VCC- 0.5 V IOH = -1.25 mA VCC- 0.8 V VCC = 2.5 V VOL IOL = 10 mA 2.0 V P00- P07, P10- P17, P20- P27, P40- P47, IOL = 3 mA 0.5 V P50, P51, P54- P57, P60- P62 IOL = 2.5 mA 0.8 V IOL = 15 mA 2.0 V IOL = 4 mA VCC = 2.5 V 0.8 V " L" output voltage VCC = 2.5 V VOL " L" output voltage P30- P37, P52, P53 VT+-VT- Hysteresis 0.5 V V INT0- INT2, CNTR0, CNTR1, P00- P03, P54- P57 VT+-VT- Hysteresis SCLK1, SCLK2, RxD1, RxD2 0.5 VT+-VT- Hysteresis RESET 0.5 IIH " H" input current VI = VCC V 5.0 A 5.0 A -5.0 A A P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- P57, P60- P62 IIH " H" IIH IIL " H" input currentIN X " L" input current input current RESET VI = VCC 4.0 VI = VCC VI = VSS P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, Pull-up " OFF" P50- P57, P60- P62 VCC = 5.0 V, VI = VSS - 60 - 120 - 240 A - 25 - 40 - 100 A -5.0 A Pull-up " ON" VCC = 3.0 V, VI = VSS Pull-up " ON" IIL " L" input current IIL " L" input currentIN X Rev.2.00 May 28, 2004 RESET page 75 of 100 VI = VSS VI = VSS -4.0 A 38C2 Group (A Version) Table 20 Electrical characteristics (Flash memory version) (Vcc = 2.5 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol Test conditions Parameter Limits Min. Typ. Max. Unit VRAM RAM hold voltage When clock is stopped 5.5 V ICC Power source current Frequency/2 mode, Vcc = 5 V f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors " OFF" , A-D converter in operating 6.0 8.6 mA Frequency/2 mode, Vcc = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors " OFF" , A-D converter in operating 5.0 7.2 mA Frequency/2 mode, Vcc = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors " OFF" , A-D converter stopped 1.0 2.0 mA Low-speed mode, VCC = 5 V, Ta 55 C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors " OFF" 150 200 A 6 10 A 125 165 A 4 8 A 0.1 1.0 A 10 A 1.8 Low-speed mode, VCC = 5 V, Ta = 25 C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors " OFF" Low-speed mode, VCC = 3 V, Ta 55 C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors " OFF" Low-speed mode, VCC = 3 V, Ta = 25 C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors " OFF" All oscillation stopped Ta = 25 C (in STP state) Output transistors " OFF"Ta = 85 C Table 21 Direct-electrical characteristics (Flash memory version) (Vcc = 4.5 to 5.5 V, Ta = 25 C, unless otherwise noted) Symbol Parameter IPP1 VPP Power source current (at read) IPP2 VPP Power source current Test conditions Limits Min. VPP = VCC, at flash memory mode Typ. Max. Unit 100 A 60 mA 30 mA 5.5 V (at programming) IPP3 VPP Power source current (at erase) VPP VPP Power source voltage Rev.2.00 May 28, 2004 page 76 of 100 At flash memory mode 4.5 38C2 Group (A Version) A-D Converter Characteristics Table 22 A-D converter characteristics (Flash memory version) (Vcc = 2.5 to 5.5 V, Vss = AVSS = 0 V, Ta = - 20 to 85 C, Port state = stopped, unless otherwise noted) Symbol Parameter Test conditions -- Resolution -- Absolute accuracy (quantification error excluded) Min. Limits Typ. Max. VCC = VREF = 5 V Unit 10 Bits 6 LSB AD clock frequency = 5 MHz 10bitAD mode VCC = VREF = 4 V AD clock frequency = 4 MHz 10bitAD mode 5 VCC = VREF = 2.5 V AD clock frequency = 500 kHz 10bitAD mode, booster effective 2 VCC = VREF = 5 V AD clock frequency = 4 MHz 8bitAD mode VCC = VREF = 2.5 V AD clock frequency = 1 MHz Conversion time Tconv tc(XIN)121 8bitAD mode, booster effective AD conversion clock selection bit :XIN/2, RLADDER Ladder resistor IVREF Reference input current IIA Analog input current 10bitAD mode Note: When " Frequency/4, 8 or 16" s (Note) 12 35 100 k 50 150 200 A 5.0 A VREF = 5 V is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8. LCD Power Supply Characteristics Table 23 LCD power supply characteristics (when connecting division resistors for LCD power supply) (Flash memory version) (Vcc = 2.5 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Division resistor RSEL = "10" Limits Typ. 200 RLCD for LCD power supply RSEL = " 11 " 5 (Note) LCD drive timing A LCD circuit division ratio = divided by 1 RSEL = "01" Test conditions Parameter Symbol May 28, 2004 120 RSEL = "00" 90 LCD circuit division ratio = divided by 2 RSEL = "01" 150 RSEL = "00" 120 LCD circuit division ratio = divided by 4 RSEL = "01" 170 RSEL = "00" 150 LCD circuit division ratio = divided by 8 RSEL = "01" RSEL = "00" 190 LCD drive timing B LCD circuit division ratio = divided by 1 RSEL = "01" 170 150 Note: The value is the average of each one division resistor. Rev.2.00 Min. page 77 of 100 RSEL = "00" 120 LCD circuit division ratio = divided by 2 RSEL = "01" 170 RSEL = "00" 150 LCD circuit division ratio = divided by 4 RSEL = "01" 190 RSEL = "00" 170 LCD circuit division ratio = divided by 8 RSEL = "01" 190 RSEL = "00" 190 Max. Unit k 38C2 Group (A Version) Timing Requirements And Switching Characteristics Table 24 Timing requirements 1 (Flash memory version) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol Parameter tw(RESET) Reset input " L" tc(XIN) Main clock input cycle time (XIN input) pulse width Main clock input " H" twH(XIN) Main clock input " L" twL(XIN) Min. pulse width pulse width Limits Typ. Max. Unit s (4.5 V VCC 5.5 V) 2 100 1000 ns (4.0 V VCC < 4.5 V) 1000(4 Vcc - 8) 1000 ns (4.5 V VCC 5.5 V) 40 500 ns (4.0 V VCC < 4.5 V) 45 500 ns (4.5 V VCC 5.5 V) 40 500 ns (4.0 V VCC < 4.5 V) 45 500 tc(XCIN) Sub clock input cycle time 20 ns s twH(XCIN) Sub clock input " H" pulse width 9 s twL(XCIN) Sub clock input " L" pulse width CNTR0, CNTR1 input cycle time 9 s 200 1000(2 Vcc - 4) ns 85 ns tc(CNTR) twH(CNTR) twL(CNTR) (4.5 V VCC 5.5 V) CNTR0, CNTR1 input " H" (4.0 V VCC < 4.5 V) pulse width(4.5 V VCC 5.5 V) 105 ns CNTR0, CNTR1 input " L" (4.0 V VCC < 4.5 V) pulse width(4.5 V VCC 5.5 V) 85 ns (4.0 V VCC < 4.5 V) 105 ns ns twH(INT) twL(INT) INT0- INT2 input " H" pulse width 80 INT0- INT2 input " L" pulse width 80 ns ns tc(SCLK) Serial I/O1, 2 clock input cycle time (Note) 800 ns twH(SCLK) 370 ns twL(SCLK) Serial I/O1, 2 clock input " H" pulse width (Note) Serial I/O1, 2 clock input " L" pulse width (Note) ns tsu(RxD-SCLK) Serial I/O1, 2 input setup time 370 220 th(SCLK-RxD) Serial I/O1, 2 input hold time 100 ns Note : When bit 6 of address 0FE016 or 0FE316 is " 1" (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is " 0" ns (UART). Table 25 Timing requirements 2 (Flash memory version) (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Limits Parameter Symbol Min. Typ. Max. s 2 pulse width Unit tw(RESET) Reset input " L" tc(XIN) Main clock input cycle time (XIN input) 125 1000 ns twH(XIN) Main clock input " H" pulse width 50 500 ns twL(XIN) Main clock input " L" pulse width 50 500 tc(XCIN) Sub clock input cycle time 20 s ns twH(XCIN) Sub clock input " H" pulse width 9 s twL(XCIN) Sub clock input " L" pulse width 9 s tc(CNTR) twH(CNTR) CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input " H" pulse width 750/(VCC- 1) tc(CNTR)/2- 20 ns ns twL(CNTR) CNTR0, CNTR1 input " L" tc(CNTR)/2- 20 ns twH(INT) INT0- INT2 input " H" pulse width 230 ns twL(INT) INT0- INT2 input " L" pulse width 230 ns tc(SCLK) Serial I/O1, 2 clock input cycle time (Note) 2000 ns twH(SCLK) Serial I/O1, 2 clock input " H" pulse width (Note) 950 ns twL(SCLK) Serial I/O1, 2 clock input " L" pulse width (Note) 950 ns tsu(RxD-SCLK) Serial I/O1, 2 input setup time 400 ns th(SCLK-RxD) Serial I/O1, 2 input hold time 200 ns pulse width Note : When bit 6 of address 0FE016 or 0FE316 is " 1" (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is " 0" Rev.2.00 May 28, 2004 page 78 of 100 (UART). 38C2 Group (A Version) Table 26 Switching characteristics 1 (Flash memory version) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol Limits Parameter Typ. Max. Unit twH(SCLK) Serial I/O1, 2 clock output " H" pulse width Min. tc(SCLK)/2- 30 twL(SCLK) Serial I/O1, 2 clock output " L" pulse width tc(SCLK)/2- 30 td(SCLK-TxD) Serial I/O1, 2 output delay time (Note 1) tV(SCLK-TxD) Serial I/O1, 2 output valid time (Note 1) tr(SCLK) Serial I/O1, 2 clock output rising time 30 ns tf(SCLK) Serial I/O1, 2 clock output falling time 30 ns tr(CMOS) CMOS output rising time P00- P07, P10- P17, P20- P27 (Note 2) 25 40 ns 15 30 ns 15 30 ns Typ. Max. ns ns 140 ns ns - 30 P30- P37, P40- P47, P50- P57, P60- P62 (Note 2) CMOS output falling time P00- P07, P10- P17, P20- P27 (Note 2) P30- P37, P40- P47, P50- P57, P60- P62 tf(CMOS) (Note 2) Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is "0." 2: The XOUT, XCOUT pins are excluded. Table 27 Switching characteristics 2 (Flash memory version) (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Limits Parameter Symbol Min. twH(SCLK) Serial I/O1, 2 clock output " H" pulse width tC(SCLK)/2- 80 twL(SCLK) Serial I/O1, 2 clock output " L" pulse width tC(SCLK)/2- 80 td(SCLK-TxD) Serial I/O1, 2 output delay time (Note 1) tV(SCLK-TxD) Serial I/O1, 2 output valid time (Note 1) tr(SCLK) tf(SCLK) Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time tr(CMOS) CMOS output rising time P00- P07, P10- P17, P20- P27 (Note 2) P30- P37, P40- P47, P50- P57, P60- P62 tf(CMOS) ns ns 400 80 80 ns ns 60 120 ns 40 80 ns 40 80 ns P30- P37, P40- P47, P50- P57, P60- P62 (Note 2) Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is "0." 2: The XOUT, XCOUT pins are excluded. 1k Measurement output pin Measurement output pin 100pF CMOS output 100pF N-channel open-drain output (Note) Note: When bit 4 of the UART control register (address 0EF116 or 0FE416) is " 1." (N-channel open-drain output mode) Fig. 71 Circuit for measuring output switching characteristics Rev.2.00 May 28, 2004 page 79 of 100 ns ns - 30 (Note 2) CMOS output falling time P00- P07, P10- P17, P20- P27 (Note 2) Unit 38C2 Group (A Version) tC(CNTR) tWL(CNTR) tWH(CNTR) CNTR0,CNTR1 0.8VCC 0.2VCC tWL(INT) tWH(INT) INT0 to INT2 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN 0.2VCC tC(XCIN) tWL(XCIN) tWH(XCIN) 0.8VCC XCIN tf SCLK1 SCLK2 0.2VCC tC(SCLK) tr tWL(SCLK) 0.8VCC 0.2VCC tsu(RXD-SCLK) RXD1 RXD2 TXD1 TXD2 Fig. 72 Timing chart May 28, 2004 th(SCLK-RXD) 0.8VCC 0.2VCC td(SCLK-TXD) Rev.2.00 tWH(SCLK) page 80 of 100 tv(SCLK-TXD) 38C2 Group (A Version) ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 28 Absolute maximum ratings (Mask ROM version) Ratings Unit - 0.3 to 6.5 - 0.3 to VCC+0.3 V V VL1 - 0.3 to VL2 V VL2 VL3 VL1 to VL3 VL2 to 6.5 V - 0.3 to VCC+0.3 V At output port - 0.3 to VCC+0.3 V At segment output - 0.3 to VL3+0.3 V Symbol Conditions Parameter VCC VI Power source voltage Input voltage P00- P07, P10- P17, P20- P27, P30- P37, P40- P47, P50- P57, P60- P62 VI Input voltage VI VI Input voltage Input voltage VI Input voltage RESET, XIN, CNVSS VO Output voltage P00- P07, P10- P17, P20- P27 All voltages are based on Vss. Output transistors are cut off. V VO Output voltage COM0-COM3 - 0.3 to VL3+0.3 V VO VO Output voltage P30- P37, P40- P47, P50- P57, P60- P62 - 0.3 to VCC+0.3 Output voltage XOUT - 0.3 to VCC+0.3 V V Pd Power dissipation 300 mW Topr Operating temperature - 20 to 85 C Tstg Storage temperature - 40 to 125 C Rev.2.00 May 28, 2004 Ta = 25C page 81 of 100 38C2 Group (A Version) Recommended Operating Conditions Table 29 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol VCC Limits Parameter Power source voltage (Note 1) Unit Min. Typ. f() = 5 MHz f() = 4 MHz 4.5 5.0 4.0 5.5 V f() = 2 MHz 5.5 V f() = 1 MHz 2.0 1.8 5.0 5.0 5.0 5.5 Low-speed mode 1.8 5.0 5.5 V V Oscillation start voltage (Note 2) Max. 5.5 0.15 f + 1.3 V V VSS Power source voltage VL3 Power source voltage for LCD 2.5 5.5 V VREF A-D converter reference voltage 2.0 VCC V AVSS Analog power source voltage VIA VIH Analog input voltage AN0-AN7 "H" input voltage P04-P07, P10-P17, P20-P27, P30, P32, P35, P36, P40-P47, P52, P53, P62 AVSS VCC V 0.7VCC VCC V VIH "H" input voltage P00-P03, P31, P33, P34, P37, P50, P51, P54-P57, P60, P61 0.8VCC VCC V VIH "H" input voltage RESET 2.2 V VCC 5.5 V 0.8VCC VCC V VCC 2.2 V 65 VCC-99 VCC 0 V 0 VCC - V 100 0.8Vcc VCC V 1.5 V VIH "H" input voltage XIN VIH "H" input voltage XCIN (Note 3) VIL "L" input voltage P04-P07, P10-P17, P20-P27, P30, P32, P35, P36, P40-P47, P52, P53, P62 0 VCC 0.3VCC VIL "L" input voltage P00-P03, P31, P33, P34, P37, P50, P51, P54-P57, P60, P61, CNVSS 0 0.2VCC V VIL "L" input voltage RESET V 2.2 V VCC 5.5 V 0 0.2VCC VCC 2.2 V 0 65 VCC-99 V 100 VIL "L" input voltage XIN 0 0.2Vcc V VIL "L" input voltage XCIN (Note 4) 0 0.4 V Notes 1: When using the A-D converter, refer to "A-D Converter Characteristics". 2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillation start time differ accordance with an oscillator, a circuit constant, or temperature, etc. When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions. f: This is an oscillator's oscillation frequency ( 1 MHz). For example, when oscillation frequency is 8 MHz, substitute "8". 3: When the XCIN/P61 pin is not connected to an oscillator, refer to VIH for P61. 4: When the XCIN/P61 pin is not connected to an oscillator, refer to VIL for P61. Rev.2.00 May 28, 2004 page 82 of 100 38C2 Group (A Version) Table 30 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = - 20 to 85C, unless otherwise noted) Symbol Parameter IOH(peak) " H" total peak output current (Note 1) P00- P07, P10- P17, P20- P27, P30- P37 IOH(peak) " H" total peak output current (Note 1) P40- P47, P50- P57, P60- P62 IOL(peak) " L" Limits Min. Typ. Max. - 20 Unit mA - 20 mA total peak output current (Note 1) P00- P07, P10- P17, P20- P27 " L" total peak output current (Note 1) P40- P47, P50, P51, P54- P57, P60- P62 20 mA 20 mA IOL(peak) " L" total peak output current (Note 1) P30- P37, P52, P53 110 mA IOH(avg) " H" total average output current (Note 1) P00- P07, P10- P17, P20- P27, P30- P37 - 10 mA IOH(avg) " H" total average output current (Note 1) P40- P47, P50- P57, P60- P62 - 10 mA IOL(avg) " L" total average output current (Note 1) P00- P07, P10- P17, P20- P27 10 mA IOL(avg) " L" total average output current (Note 1) P40- P47, P50, P51, P54- P57, P60- P62 10 mA IOL(avg) " L" total average output current (Note 1) P30- P37, P52, P53 90 mA IOH(peak) " H" peak output current (Note 2) P00- P07, P10- P17, P20- P27 -1.0 mA IOH(peak) " H" peak output current (Note 2) P30- P37, P40- P47, P50- P57, P60- P62 -5.0 mA IOL(peak) " L" peak output current (Note 2) P00- P07, P10- P17, P20- P27 10 mA IOL(peak) " L" peak output current (Note 2) P40- P47, P50, P51, P54- P57, P60- P62 10 mA IOL(peak) " L" peak output current (Note 2) P30- P37, P52, P53 30 mA IOH(avg) " H" average output current (Note 3) P00- P07, P10- P17, P20- P27 -0.5 mA IOH(avg) " H" average output current (Note 3) P30- P37, P40- P47, P50- P57, P60- P62 -2.5 mA IOL(avg) " L" average output current (Note 3) P00- P07, P10- P17, P20- P27 5.0 mA IOL(avg) " L" average output current (Note 3) P40- P47, P50, P51, P54- P57, P60- P62 5.0 mA IOL(avg) " L" average output current (Note 3) P30- P37, P52, P53 15 mA IOL(peak) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is average value measured over 100 ms. Rev.2.00 May 28, 2004 page 83 of 100 38C2 Group (A Version) Table 31 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = - 20 to 85C, unless otherwise noted) Symbol Limits Parameter f(CNTR0) Timer X and Timer Y f(CNTR1) Input frequency (duty cycle 50%) Min. Typ. 5.0 MHz (4.0 V VCC < 4.5 V) 2VCC-4 MHz (2.0 V VCC < 4.0 V) VCC MHz 5VCC-8 MHz Timer X, Timer Y, Timer 1, Timer 2, Timer 3 and (4.5 V VCC 5.5 V) 10.0 MHz Timer 4 Clock input frequency (4.0 V VCC < 4.5 V) (2.0 V VCC < 4.0 V) 4VCC-8 MHz 2VCC MHz (4.5 V VCC 5.5 V) 10VCC- 16 5.0 MHz MHz (4.0 V VCC < 4.5 V) 2VCC-4 MHz (2.0 V VCC < 4.0 V) VCC MHz 5VCC-8 MHz (Count source frequency of each timer) (VCC < 2.0 V) f() System clock frequency (VCC < 2.0 V) f(XIN) f(XCIN) Unit (4.5 V VCC 5.5 V) (VCC < 2.0 V) f(Tclk) Max. Main clock input oscillation frequency (Notes 1, 3) (4.5 V VCC 5.5 V) 1.0 10.0 MHz (2.0 V VCC < 4.5 V) 1.0 8.0 MHz 1.0 20VCC- 32 MHz 50 kHz (VCC < 2.0 V) Sub-clock input oscillation frequency (Notes 1, 2, 3) 32.768 Notes 1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions. Rev.2.00 May 28, 2004 page 84 of 100 38C2 Group (A Version) Electrical Characteristics Table 32 Electrical characteristics (Mask ROM version) (Vcc = 4.0 to 5.5 V, Ta = - 20 to 85C, unless otherwise noted) Parameter Symbol VOH " H" output voltage P00- P07, P10- P17, P20- P27 VOH " H" output voltage P30- P37, P40- P47, P50- P57, P60- P62 Test conditions Limits Min. Typ. Max. Unit IOH = - 1 mA VCC- 2.0 V IOH = -0.25 mA VCC- 0.8 V VCC = 1.8 V IOH = - 5 mA VCC- 2.0 V IOH = - 1.5 mA VCC- 0.5 V IOH = -1.25 mA VCC- 0.8 V VCC = 1.8 V VOL IOL = 10 mA 2.0 V P00- P07, P10- P17, P20- P27, P40- P47, IOL = 3 mA 0.5 V P50, P51, P54- P57, P60- P62 IOL = 2.5 mA 0.8 V IOL = 15 mA 2.0 V IOL = 4 mA VCC = 1.8 V 0.8 V " L" output voltage VCC = 1.8 V VOL " L" output voltage P30- P37, P52, P53 VT+-VT- Hysteresis 0.5 V V INT0- INT2, CNTR0, CNTR1, P00- P03, P54- P57 VT+-VT- Hysteresis SCLK1, SCLK2, RxD1, RxD2 0.5 VT+-VT- Hysteresis RESET 0.5 IIH " H" input current VI = VCC V 5.0 A 5.0 A -5.0 A A P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- P57, P60- P62 IIH " H" IIH IIL " H" input currentIN X " L" input current input current RESET VI = VCC 4.0 VI = VCC VI = VSS P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, Pull-up " OFF" P50- P57, P60- P62 VCC = 5.0 V, VI = VSS - 60 - 120 - 240 A -5.0 - 20 - 40 A -5.0 A Pull-up " ON" VCC = 1.8 V, VI = VSS Pull-up " ON" IIL " L" input current IIL " L" input currentIN X Rev.2.00 May 28, 2004 RESET page 85 of 100 VI = VSS VI = VSS -4.0 A 38C2 Group (A Version) Table 33 Electrical characteristics (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = - 20 to 85C, unless otherwise noted) Symbol Parameter Test conditions Limits Min. Typ. Max. Unit VRAM RAM hold voltage When clock is stopped 5.5 V ICC Power source current Frequency/2 mode, Vcc = 5 V f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors " OFF" , A-D converter in operating 3.4 5.1 mA Frequency/2 mode, Vcc = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors " OFF" , A-D converter in operating 2.7 4.2 mA Frequency/2 mode, Vcc = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors " OFF" , A-D converter stopped 1.0 2.0 mA Low-speed mode, VCC = 5 V, Ta 55 C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors " OFF" 14 21 A Low-speed mode, VCC = 5 V, Ta = 25 C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors " OFF" 6 10 A Low-speed mode, VCC = 3 V, Ta 55 C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors " OFF" 8 13 A Low-speed mode, VCC = 3 V, Ta = 25 C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors " OFF" 4 8 A 0.1 1.0 A 10 A All oscillation stopped Ta = 25 C (in STP state) Output transistors " OFF"Ta = 85 C Rev.2.00 May 28, 2004 page 86 of 100 1.8 38C2 Group (A Version) A-D Converter Characteristics Table 34 A-D converter characteristics (Mask ROM version) (Vcc = 2.2 to 5.5 V, Vss = AVSS = 0 V, Ta = - 20 to 85C, Port state = stopped, unless otherwise noted) Parameter Symbol Test conditions -- Resolution -- Absolute accuracy (quantification error excluded) Min. Limits Typ. Max. VCC = VREF = 5 V Unit 10 Bits 5 LSB AD clock frequency = 5 MHz 10bitAD mode VCC = VREF = 4 V AD clock frequency = 4 MHz 10bitAD mode 4 VCC = VREF = 2.2 V AD clock frequency = 500 kHz 10bitAD mode, booster effective 2 VCC = VREF = 5 V AD clock frequency = 4 MHz 8bitAD mode VCC = VREF = 2.2 V AD clock frequency = 1 MHz 8bitAD mode, booster effective Conversion time Tconv tc(XIN)121 AD conversion clock selection bit :XIN/2, 10bitAD mode RLADDER Ladder resistor IVREF Reference input current IIA Analog input current Note: When " Frequency/4, 8 or 16" s (Note) VREF = 5 V 12 35 100 k 50 150 200 A 5.0 A is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8. LCD Power Supply Characteristics Table 35 LCD power supply characteristics (when connecting division resistors for LCD power supply) (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = - 20 to 85C, unless otherwise noted) RLCD Test conditions Parameter Symbol Min. Limits Typ. Division resistor RSEL = "10" 200 for LCD power supply RSEL = " 11 " 5 (Note) LCD drive timing A LCD circuit division ratio = divided by 1 RSEL = "01" May 28, 2004 90 LCD circuit division ratio = divided by 2 RSEL = "01" 150 RSEL = "00" 120 LCD circuit division ratio = divided by 4 RSEL = "01" RSEL = "00" 170 LCD circuit division ratio = divided by 8 RSEL = "01" 150 190 RSEL = "00" 170 LCD drive timing B LCD circuit division ratio = divided by 1 RSEL = "01" 150 RSEL = "00" 120 LCD circuit division ratio = divided by 2 RSEL = "01" 170 RSEL = "00" 150 LCD circuit division ratio = divided by 4 RSEL = "01" 190 RSEL = "00" 170 LCD circuit division ratio = divided by 8 RSEL = "01" RSEL = "00" 190 190 Note: The value is the average of each one division resistor. Rev.2.00 120 RSEL = "00" page 87 of 100 Max. Unit k 38C2 Group (A Version) Timing Requirements And Switching Characteristics Table 36 Timing requirements 1 (Mask ROM version) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85C, unless otherwise noted) Symbol Parameter Min. Max. Unit s tw(RESET) Reset input " L" tc(XIN) Main clock input cycle time (XIN input) (4.5 V VCC 5.5 V) 100 1000 ns 1000/(4 Vcc - 8) 40 1000 ns Main clock input " H" (4.0 V VCC < 4.5 V) (4.5 V VCC 5.5 V) 500 ns (4.0 V VCC < 4.5 V) 45 500 ns (4.5 V VCC 5.5 V) 40 500 ns (4.0 V VCC < 4.5 V) 45 500 twH(XIN) pulse width Limits Typ. Main clock input " L" twL(XIN) 2 pulse width pulse width tc(XCIN) Sub clock input cycle time 20 ns s twH(XCIN) Sub clock input " H" pulse width 9 s twL(XCIN) Sub clock input " L" pulse width 9 s tc(CNTR) CNTR0, CNTR1 input cycle time 200 ns 1000/(2 Vcc - 4) ns ns (4.0 V VCC < 4.5 V) 85 105 pulse width (4.5 V VCC 5.5 V) 85 ns (4.0 V VCC < 4.5 V) 105 ns twH(CNTR) CNTR0, CNTR1 input " H" twL(CNTR) CNTR0, CNTR1 input " L" (4.5 V VCC 5.5 V) (4.0 V VCC < 4.5 V) pulse width(4.5 V VCC 5.5 V) ns twH(INT) twL(INT) INT0- INT2 input " H" pulse width INT0- INT2 input " L" pulse width 80 80 ns ns tc(SCLK) Serial I/O1, 2 clock input cycle time (Note) 800 ns twH(SCLK) Serial I/O1, 2 clock input " H" pulse width (Note) 370 ns twL(SCLK) Serial I/O1, 2 clock input " L" pulse width (Note) 370 ns tsu(RxD-SCLK) Serial I/O1, 2 input setup time 220 ns th(SCLK-RxD) Serial I/O1, 2 input hold time 100 ns Note : When bit 6 of address 0FE016 or 0FE316 is " 1" (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is " 0" Rev.2.00 May 28, 2004 page 88 of 100 (UART). 38C2 Group (A Version) Table 37 Timing requirements 2 (Mask ROM version) (Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = - 20 to 85C, unless otherwise noted) Limits Parameter Symbol Min. Typ. Max. s 2 tw(RESET) Reset input " L" tc(XIN) Main clock input cycle time (XIN input) pulse width 2.0 V VCC 4.0 V VCC < 2.0 V twH(XIN) Main clock input " H" pulse width twL(XIN) Main clock input " L" pulse width 2.0 V VCC 4.0 V VCC < 2.0 V 2.0 V VCC 4.0 V VCC < 2.0 V Unit 125 1000 ns 250/(5VCC- 8) 1000 ns 50 tc(XIN)/2- 12.5 500 500 ns ns 50 500 ns tc(XIN)/2- 12.5 500 ns tc(XCIN) Sub clock input cycle time 20 s twH(XCIN) Sub clock input " H" pulse width 9 s twL(XCIN) Sub clock input " L" pulse width 9 s tc(CNTR) CNTR0, CNTR1 input cycle time 1000/VCC ns 1000/(5VCC- 8) ns 2.0 V VCC 4.0 V VCC < 2.0 V twH(CNTR) CNTR0, CNTR1 input " H" pulse width tc(CNTR)/2- 20 ns twL(CNTR) twH(INT) CNTR0, CNTR1 input " L" pulse width INT0- INT2 input " H" pulse width tc(CNTR)/2- 20 230 ns ns twL(INT) INT0- INT2 input " L" 230 ns tc(SCLK) Serial I/O1, 2 clock input cycle time (Note) 2000 ns twH(SCLK) Serial I/O1, 2 clock input " H" pulse width (Note) 950 ns twL(SCLK) Serial I/O1, 2 clock input " L" pulse width (Note) 950 ns tsu(RxD-SCLK) Serial I/O1, 2 input setup time 400 ns th(SCLK-RxD) Serial I/O1, 2 input hold time 200 ns pulse width Note : When bit 6 of address 0FE016 or 0FE316 is " 1" (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is " 0" Rev.2.00 May 28, 2004 page 89 of 100 (UART). 38C2 Group (A Version) Table 38 Switching characteristics 1 (Mask ROM version) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85C, unless otherwise noted) Symbol Limits Parameter Typ. Max. Unit twH(SCLK) Serial I/O1, 2 clock output " H" pulse width Min. tc(SCLK)/2- 30 twL(SCLK) Serial I/O1, 2 clock output " L" pulse width tc(SCLK)/2- 30 td(SCLK-TxD) Serial I/O1, 2 output delay time (Note 1) tV(SCLK-TxD) Serial I/O1, 2 output valid time (Note 1) tr(SCLK) Serial I/O1, 2 clock output rising time 30 ns tf(SCLK) Serial I/O1, 2 clock output falling time 30 ns tr(CMOS) CMOS output rising time P00- P07, P10- P17, P20- P27 (Note 2) 25 40 ns 15 30 ns 15 30 ns Typ. Max. ns ns 140 ns ns - 30 P30- P37, P40- P47, P50- P57, P60- P62 (Note 2) CMOS output falling time P00- P07, P10- P17, P20- P27 (Note 2) P30- P37, P40- P47, P50- P57, P60- P62 tf(CMOS) (Note 2) Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is "0." 2: The XOUT, XCOUT pins are excluded. Table 39 Switching characteristics 2 (Mask ROM version) (Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = - 20 to 85C, unless otherwise noted) Limits Parameter Symbol Min. twH(SCLK) Serial I/O1, 2 clock output " H" pulse width tC(SCLK)/2- 80 twL(SCLK) Serial I/O1, 2 clock output " L" pulse width tC(SCLK)/2- 80 td(SCLK-TxD) Serial I/O1, 2 output delay time (Note 1) tV(SCLK-TxD) Serial I/O1, 2 output valid time (Note 1) tr(SCLK) tf(SCLK) Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time tr(CMOS) CMOS output rising time P00- P07, P10- P17, P20- P27 (Note 2) P30- P37, P40- P47, P50- P57, P60- P62 tf(CMOS) ns ns 400 80 80 ns ns 60 120 ns 40 80 ns 40 80 ns P30- P37, P40- P47, P50- P57, P60- P62 (Note 2) Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is "0." 2: The XOUT, XCOUT pins are excluded. 1k Measurement output pin Measurement output pin 100pF CMOS output 100pF N-channel open-drain output (Note) Note: When bit 4 of the UART control register (address 0EF116 or 0FE416) is " 1." (N-channel open-drain output mode) Fig. 73 Circuit for measuring output switching characteristics Rev.2.00 May 28, 2004 page 90 of 100 ns ns - 30 (Note 2) CMOS output falling time P00- P07, P10- P17, P20- P27 (Note 2) Unit 38C2 Group (A Version) tC(CNTR) tWL(CNTR) tWH(CNTR) CNTR0,CNTR1 0.8VCC 0.2VCC tWL(INT) tWH(INT) INT0 to INT2 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN 0.2VCC tC(XCIN) tWL(XCIN) tWH(XCIN) 0.8VCC XCIN tf SCLK1 SCLK2 0.2VCC tC(SCLK) tr tWL(SCLK) 0.8VCC 0.2VCC tsu(RXD-SCLK) RXD1 RXD2 TXD1 TXD2 Fig. 74 Timing chart May 28, 2004 th(SCLK-RXD) 0.8VCC 0.2VCC td(SCLK-TXD) Rev.2.00 tWH(SCLK) page 91 of 100 tv(SCLK-TXD) 38C2 Group (A Version) PACKAGE OUTLINE 64P6U-A Plastic 64pin 14 14mm body LQFP EIAJ Package Code LQFP64-P-1414-0.8 Weight(g) Lead Material Cu Alloy MD e JEDEC Code -- b2 ME HD D 48 33 l2 49 32 Recommended Mount Pad 64 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 17 1 A 16 L1 F A3 A2 e A3 x M c b A1 y L x y Lp b2 I2 MD ME Detail F 64P6Q-A Plastic 64pin 10 10mm body LQFP Weight(g) Lead Material Cu Alloy MD ME JEDEC Code -- e EIAJ Package Code LQFP64-P-1010-0.5 b2 HD D 48 33 49 I2 Recommended Mount Pad 32 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 17 64 1 16 A F e L M Detail F May 28, 2004 page 92 of 100 Lp c A1 x A3 A2 L1 y b Rev.2.00 Dimension in Millimeters Min Nom Max -- -- 1.7 0.1 0.2 0 1.4 -- -- 0.32 0.37 0.45 0.105 0.125 0.175 13.9 14.1 14.0 13.9 14.1 14.0 0.8 -- -- 16.0 15.8 16.2 15.8 16.2 16.0 0.3 0.5 0.7 1.0 -- -- 0.75 0.6 0.45 -- 0.25 -- -- -- 0.2 0.1 -- -- 0 8 -- 0.5 -- -- -- -- 0.95 -- 14.4 -- -- -- 14.4 A3 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max -- -- 1.7 0.1 0.2 0 -- -- 1.4 0.13 0.18 0.28 0.105 0.125 0.175 9.9 10.0 10.1 9.9 10.0 10.1 -- 0.5 -- 11.8 12.0 12.2 11.8 12.0 12.2 0.3 0.5 0.7 1.0 -- -- 0.75 0.6 0.45 -- 0.25 -- 0.08 -- -- 0.1 -- -- 0 10 -- 0.225 -- -- -- -- 1.0 -- -- 10.4 -- -- 10.4 38C2 Group (A Version) APPENDIX NOTES ON PROGRAMMING 1. Processor status register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. <Reason> After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is " 1" . Reset Initializing of flags Main program (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to "1" if a carry is generated as a result of the calculation, or is cleared to "0" if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to "0" before each calculation. To check for a borrow, the C flag must be initialized to " 1" before each calculation. Set D flag to "1" ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Fig. 4 Status flag at decimal calculations Fig.1 Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction should be executed after every PLP instruction. PLP instruction execution NOP Fig. 2 Sequence of PLP instruction execution (S) (S)+1 Stored PS Fig. 3 Stack memory contents after PHP instruction execution 2. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to "1" with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. Rev.2.00 May 28, 2004 page 93 of 100 3. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. BRK instruction When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address of interrupt vector which has the highest priority. * Interrupt request bit and interrupt enable bit are set to " 1" . * Interrupt disable flag (I) is set to " 1" to disable interrupt. 5. Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. 6. Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (memory and SFR). The read-modify-write instruction operates in the following sequence: read one-byte of data from memory, modify the data, write the data back to original memory. The following instructions are classified as the read-modify-write instructions in the 740 Family. * Bit management instructions: CLB, SEB * Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF * Add and subtract instructions: DEC, INC * Logical operation instructions (1's complement): COM Add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = "1" operate in the way as the readmodify-write instruction. Do not execute the read invalid memory and SFR. <Reason> When the read-modify-write instruction is executed to read invalid memory and SFR, the instruction may cause the following consequence: the instruction reads unspecified data from the memory due to the read invalid condition. Then the instruction modifies this unspecified data and writes the data to the memory. The result will be random data written to the memory or some unexpected event. 38C2 Group (A Version) NOTES ON PERIPHERAL FUNCTIONS Notes on I/O Ports 1. Pull-up control register When using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. <Reason> Pull-up control is effective only when each direction register is set to the input mode. 2. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction (Note), the value of the unspecified bit may be changed. <Reason> I/O ports can be set to input or output mode in a bit unit. When reading or writing are performed to the port Pi (i = 0-7) register, the microcomputer operates as follows. * Port in input mode -Read-access: reads pin' s level (The contents of port latch and pin's level are unrelated.) -Write-access: writes data to port latch (The contents of port latch and pin's level are unrelated.) * Port in output mode -Read-access: reads port latch (The contents of port latch and pin's level are unrelated.) -Write-access: writes data to port latch (The contents of port latch are output from the pin.) The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Therefore, when the bit managing instructions are executed to the port set to input mode, the instruction read the pin's states, modify the specification bit, and then write data to the port latch. At this time, if the contents of the original port latch are different from the pins's level, the contents of the port latch of bit which is not specified by instruction will change. In addition to this, if the bit managing instructions are executed to the port Pi register in order to setting output data when port Pi is configured as a mixed input and output port, the contents of the port latch of bit in the input mode which is not specified by instruction may change. Notes on Termination of Unused Pins 1. Terminate unused pins Perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) I/O ports Set the I/O ports for the input mode and connect each pin to VCC or VSS through each resistor of 1 k to 10 k. The port which can select a built-in pull-up resistor can also use the built-in pull-up resistor. When using the I/O ports as the output mode, open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. Termination remarks (1) Input ports Do not open them. <Reason> * If the input level is undefined, the power source current may increase. * An effect due to noise may be easily produced as compared with "1. (1) I/O ports" shown on the above. (2) I/O ports setting as input mode [1] Do not open in the input mode. <Reason> * The power source current may increase depending on the firststage circuit. * An effect due to noise may be easily produced as compared with "1. (1) I/O ports" shown on the above. [2] I/O ports : Do not connect to VCC or VSS directly. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur. Note: Bit managing instructions: SEB instruction, CLB instruction 3. Port direction register The port direction registers are write-only registers. Therefore, the following instructions cannot be used to this register: * LDA instruction * Memory operation instruction when T flag is " 1" * Instructions operating in addressing mode that modifies direction register * Bit test instructions such as BBC and BBS * Bit modification instructions such as CLB and SEB * Arithmetic instructions using read-modify-write form instructions such as ROR The LDM, STA instructions etc. are used for setting of the direction register. Rev.2.00 May 28, 2004 page 94 of 100 [3] I/O ports : Do not connect multiple ports in a lump to VCC or VSS through a resistor. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. 38C2 Group (A Version) Notes on Interrupts Notes on Timer 1. Unused interrupts Set the interrupt enable bit for unused interrupts to " 0" (disabled). 2. Change of relevant register settings When not requiring for the interrupt occurrence synchronous with the following case, take the sequence shown in Figure 5. * When selecting external interrupt active edge *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Set the corresponding interrupt enable bit to "0" (disabled) . Set the interrupt edge select bit, active edge switch bit, or the interrupt source select bit. NOP (One or more instructions) Set the corresponding interrupt request bit to "0" (no interrupt request issued). Set the corresponding interrupt enable bit to "1" (enabled). Fig. 5 Sequence of changing relevant register <Reason> When setting the followings, the interrupt request bit may be set to "1". * When selecting external interrupt active edge INT0 interrupt edge selection bit (bit 0 of interrupt edge selection register (address 003A16)) INT1 interrupt edge selection bit (bit 1 of interrupt edge selection register (address 003A16)) INT2 interrupt edge selection bit (bit 2 of interrupt edge selection register (address 003A16)) CNTR0 active edge switch bit (bit 6 of timer X control register (address 0FF416)) CNTR1 active edge switch bit (bit 6 of timer Y mode register (address 003016)) *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Interrupt edge selection register (address 003A16) 3. Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to " 0" , take the following sequence. <Reason> If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to "0", the value of the interrupt request bit before being cleared to " 0" is read. Set the interrupt request bit to "0" (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Fig. 6 Sequence of check of interrupt request bit Rev.2.00 May 28, 2004 page 95 of 100 1. When n (0 to 255) is written to a timer latch, the frequency divisin ratio is 1/(n+1). 2. The timers share the one frequency divider to generate the count source. Accordingly, when each timer starts operating, initializing the frequency divider is not executed. Therefore, when the frequency divider is selected for the count source, the delay of the maximum one cycle of the count source is generated until the timer starts counting or the waveform is output from timer starts operating. Also, the count source cannot be checked externally. 3. Set the timer which is not used as follows: * Stop the count (when using a timer with stop control) * Set " 0" to the corresponding interrupt enable bit Notes on Timer X 1. CNTR0 active edge selection * The CNTR0 active edge selection bit (bit 6 of timer X mode register) also effects the active edge of the generation of the CNTR0 interrupt request. * When the pulse width is measured, set the bit 7 of the CNTR0 active edge switch bits to " 0" . 2. Write order to timer X * In the timer mode, pulse output mode, event counter mode and pulse width measurement mode, write to the following registers in the order as shown below; the timer X register (extension), the timer X register (low-order), the timer X register (high-order). Do not write to only one of them. When the above mode is set and timer X operates as the 16-bit counter, if the timer X register (extension) is never set after reset is released, setting the timer X register (extension) is not required. In this case, write the timer X register (low-order) first and the timer X register (high-order). However, once writing to the timer X register (extension) is executed, note that the value is retained to the reload latch. * In the IGBT output and PWM modes, do not write "1" to the timer X register (extension). Also, when "1" is already written to the timer X register, be sure to write " 0" to the register before using. Write to the following registers in the order as shown below; the compare register (high- and low-order), the timer X register (extension), the timer X register (low-order), the timer X register (high-order). It is possible to use whichever order to write to the compare register (high- and low-order). However, write both the compare register and the timer X register at the same time. 38C2 Group (A Version) 3. Read order to timer X * In all modes, read the following registers in the order as shown below; the timer X register (extension), the timer X register (high-order), the timer X register (low-order). When reading the timer X register (extension) is not required, read the timer X register (high-order) first and the timer X register (loworder). Read order to the compare register is not specified. * If reading to the timer X register during write operation or writing to it during read operation is performed, normal operation will not be performed. *When setting the timer X output control bit 1 or 2 (bit 3 or 4 of timer X control register (address 0FF416)) to "1" and initializing the output of the TXOUT pin by interrupt signal of INT1 or INT2, while the output level from the TXOUT pin changes after setting the timer X output control bit 1 or 2 to " 1" , the following delay will occur. Minimum: Analog delay Maximum: Timer X count source 1 cycle + Analog delay *In the following case, the timer X interrupti request bit (bit 7 of interrupt request register 1 (address 003C16)) is set to " 1" . * When Timer X underflow *When input from INT0 pin is detected at the time of IGBT output mode 4. Write to timer X * Which write control can be selected by the timer X write control bit (b3) of the timer X mode register (address 002F16), writing data to both the latch and the timer at the same time or writing data only to the latch. When writing a value to the timer X address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. After reset release, when writing a value to the timer X address, the value is set into the timer and the timer latch at the same time, because they are written at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it. Notes on Timer Y 5. Set of timer X mode register Set the write control bit of the timer X mode register to "1" (write to the latch only) when setting the IGBT output and PWM modes. Output waveform simultaneously reflects the contents of both registers at the next underflow after writing to the timer X register (highorder). 6. When selecting timer X pulse width measurement mode When selecting the timer X pulse width measurement mode, enable (set "0") data for the event couter window control (bit 5 of timer X mode register (address 002F16)). <Reason> When data for the event counter window control is set to "1" (disabled), the CNTR0 input is not accepted after timer 1 underflow because this bit controls the CNTR0 input. 7. IGBT output mode *Do not write "1" to the timer X register (extension) when using the IGBT output mode. *When using the IGBT output mode, set the port sharing the INT0 pin to input mode and set the port sharing the TXOUT pin to output mode. When using the output control function (INT1, INT2), set the port sharing the INT1, INT2 pin to input mode. * When using the output control function (INT1 and INT2) in the IGBT output mode, set the levels of INT1 and INT2 to "H" in the falling edge active or to "L" in the rising edge active before switching to the IGBT output mode. Set the level of INT0 to "H" in the falling edge active or to "L" in the rising edge active before switching to the IGBT output mode. Rev.2.00 May 28, 2004 page 96 of 100 1. Timer Y read/write control * When reading from/writing to timer Y, read from/write to both the high-order and low-order bytes of timer Y. When the value is read, read the high-order bytes first and the low-order bytes next. When the value is written, write the low-order bytes first and the highorder bytes next. If reading from the timer Y register during write operation or writing to it during read operation is performed, normal operation will not be performed. * When writing a value to the timer Y address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. Normally, when writing a value to the timer Y address, the value is set into the timer and the timer latch at the same time, because they are set to write at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it. 2. CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 38C2 Group (A Version) Notes on Timers 1 to 4 1. Cascading connection * When using cascading connection, set the value of timer in the order of the timer 1 register, the timer 2 register, the timer 3 register, and the timer 4 register after the count source selection of timer 1 to 4. <Reason> * When the count source of timers 1 to 4 is selected, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. 2. Timer 3PWM0 mode, timer 4PWM1 mode * When PWM output is suspended after starting PWM output, depending on the level of the output pulse at that time to resume an output, the delay of the one section of the short interval may be needed. Stop at " H" : No output delay Stop at " L" : Output is delayed time of 256 ts * In the PWM mode, the follows are performed every cycle of the long interval (4 256 ts). * Generation of timer 3, timer 4 interrupt requests * Update of timer 3, timer 4 * When "L" is output from the P52/T3OUT/PWM0 pin continuously in the timer 3PMW0 mode, set the P52/T3OUT/PWM0 pin as I/O port by set the timer 3 output selection bit to " 0" before " L" is output. Do not set "0016" to timer 3 in this mode. The value which can be set are 1-255. * When "L" is output from the P53/T4OUT/PWM1 pin continuously in the timer 4PMW1 mode, set the P53/T4OUT/PWM1 pin as I/O port by set the timer 4 output selection bit to " 0" before " L" is output. Do not set "0016" to timer 4 in this mode. The value which can be set are 1-255. 3. Writing to Timer 2, Timer 3, Timer 4 When writing to the latch only, if the write timing to the reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the reload latch. Notes on Serial I/O1 1. Writing to baud rate generator (BRG) Write data to BRG while the transmission and reception operations are stopped. 2. Setting procedure when using serial I/O1 transmit interrupt When the serial I/O1 transmit interrupt is used, take the following sequence. Set the serial I/O1 transmit interrupt enable bit (bit 4 of interrupt control register 1 (address 003E16)) to " 0" (disabled). Set the transmit enable bit (bit 4 of serial I/O1 control register (address 0FE016)) to " 1" . Set the serial I/O1 transmit interrupt request bit (bit 3 of interrupt request register 1 (address 003C16)) to "0" (no interrupt request issued) after 1 or more instruction has executed. Set the serial I/O1 transmit interrupt enable bit to " 1" (enabled). <Reason> When the transmission enable bit is set to "1", the transmit buffer empty flag (bit 0 of serial I/O1 status register (address 001D16)) and the transmit shift register completion flag are set to " 1" . Therefore, the serial I/O1 transmit interrupt request bit is set to "1" regardless of the state of the transmit interrupt source selection bit (bit 3 of serial I/O1 control register). Rev.2.00 May 28, 2004 page 97 of 100 3. Data transmission control with referring to transmit shift register completion flag After the transmit data is written to the transmit buffer register (address 001816), the transmit shift register completion flag (bit 2 of serial I/O1 status reguster (address 001D16)) changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 4. Setting serial I/O1 control register again Set the serial I/O1 control register again after the transmission and the reception circuits are reset by setting both the transmit enable bit and the receive enable bit to " 0" . Set both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Can be set with the LDM instruction at the same time Fig. 7 Sequence of setting serial I/O1 control register again 5. Pin state after transmit completion The TxD pin holds the state of the last bit of the transmission after transmission completion. When the internal clock is selected for the transmit clock in the clock synchronous serial I/O mode, the SCLK1 pin holds " H" . 6. Serial I/O1 enable bit during transmit operation When the serial I/O1 enable bit (bit 7 of serial I/O1 control register (address 0FE016)) is set to "0" (serial I/O1 disabled) when data transmission is in progress, the transmission progress internally. However, the external data transfer is terminated because the pins become regular I/O ports. In addition to this, when data is written to the transmission buffer register, data transmission is started internally. When the serial I/O1 enable bit is set to " 1" , the transmission is output to the TxD pin in the middle of the transfer. 7. Transmission control when external clock is selected When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK1 input level. Also, write the transmit data to the transmit buffer register at " H" of the S input level. CLK1 8. Receive operation in clock synchronous serial I/O mode When receiving data in the clock synchronous serial I/O mode, set not only the receive enable bit but also the transmit enable bit to "1". Then write dummy data to the transmission buffer register. When the internal clock is selected as the synchronous clock, the synchronous clock is output at this point and the receive operation is started. When the external clock is selected as the transfer clock, the serial I/O becomes ready for data receive at this point and, when the external clock is input to the clock input pin, the receive operation is started. The P45/TxD pin outputs the dummy data written in the transmission buffer register. 38C2 Group (A Version) 9. Transmit and receive operation in clock synchronous serial I/O mode When stopping transmitting and receiving operations in the clock synchronous serial I/O mode, set the receive enable bit and the transmit enable bit to "0" simultaneously. If only one of them is stopped the receive or transmit operation may loose synchronization, causing a bit slippage. Notes on Serial I/O2 1. Switching synchronous clock When switching the synchronous clock by the serial I/O2 mode selection bit (bit 6 of serial I/O2 control register (address 0FE316)), initialize the serial I/O2 counter (write data to transmit/receive buffer register 2 (address 001E16)). 2. Notes when selecting external clock When an external clock is selected as the synchronous clock, the TxD2 pin holds the output level of D7 after transmission is completed. However, if the clock is input to the serial I/O continuously, the transmit/receive buffer register continue the shift operation and output data from the TxD2 pin continuously. A write operation to the transmit/receive buffer register 2 must be performed when the SCLK2 pin is " H" . When the internal clock is selected as the synchronous clock, the TxD2 pin holds the high-impedance state after transmission. Notes on Programming for Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to " 1." Serial I/O continues to output the final bit from the TXD pin after transmission is completed. Notes on A-D Converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. Further, be sure to verify the operation of application products on the user side. <Reason> An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A-D conversion precision to be worse. 2. Read A-D conversion register How to read the A-D conversion register at 10-bit A-D conversion and 8-bit A-D conversion is shown in Fig. 8. 10-bit reading (Read address 001B16 before 001A16) b7 b0 b7 b0 A-D conversion register 1 b9 b8 b7 b6 b5 b4 b3 b2 (high-order) (Address 001B16) A-D conversion register 2 b1 b0 (Address 001A16) * (low-order) * VREF input switch bit 0: ON only during A-D conversion 1: ON Note : The bit 5 to bit 1 of address 001A16 become "0" at reading. Also, bit 0 is undefined at reading. 8-bit reading (Read only address 001B16) b7 (Address 001B16) b0 b9 b8 b7 b6 b5 b4 b3 b2 Fig. 8 A-D conversion register reading 3. Analog power source input pin AVss The AVss pin is an analog power source input pin. Regardless of using the A-D conversion function or not, connect it as following : * AVSS : Connect to the VSS line <Reason> If the AVss pin is opened, the microcomputer may have a failure because of noise or others. 4. Reference voltage input pin VREF Connect an approximately 1000 pF capacitor across the AVss pin and the VREF pin. Besides, connect the capacitor across the VREF pin and the AVss pin at equal length as close as possible. 5. Clock frequency during A-D conversion Use the A-D converter in the following conditions: * Select XIN-XOUT as system clock by the system clock selection bit (bit 7 of CPU mode register (address 003B16)). When selecting XCINXCOUT as system clock , the A-D conversion function cannot be used. * f(XIN) is 500 kHz or more. * Do not execute the STP or WIT instruction during A-D conversion. <Reason> The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. This may cause the A-D conversion precision to be worse. 6. Write to A-D conversion completion bit durng A-D conversion When "0" is set to the A-D conversion completion bit by the program during A-D conversion, re-conversion is performed. 7. Write during A-D conversion The A-D converter will not operate normally if one of the following operation is applied during the A-D conversion: * Writing to CPU mode register * Writing to A-D control register 8. Notes on programming for A-D conversion The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, set the A-D clock frequency to 250 kHz or more. Also, when the STP instruction is executed during the A-D conversion, the A-D conversion is stopped immediately, the A-D conversion completion bit is set to "1", and the interrupt request is generated. Rev.2.00 May 28, 2004 page 98 of 100 38C2 Group (A Version) Notes on LCD Drive Control Circuit (1)Right process example Contents of addres 004016 are " FF 16" 1. Count source for LCDCK The LCDCK count source selection bit (bit 7 of LCD mode register (address 003916)) is set to "0" after reset, selecting f(XCIN)/32. The sub clock has stopped after reset. Therefore, turn on LCD after starting the oscillation and stabilizing the oscillation. Select the LCDCK count source after the corresponding clock source becomes stable. 2. STP instruction When executing the STP instruction, bits 0 to 5 and bit 7 of the LCD power supply control register and the LCD enable bit (bit 3 of LCD mode register) are set to "0". Set these bits again after returning from stop mode. 3. When not using LCD When not using an LCD, leave the LCD segment and common pins open. Connect the VL1 pin to Vss, and the VL2 and VL3 pins to Vcc. LCD ON LCD display ON or OFF ? ON LCD ON or OFF Sets LCD display RAM data Sets LCD display RAM data LRAM0 (Address : 4016) " FF 16" LRAM0 (Address : 4016) " 16 00" * Sets determinate data to LCD diplay RAM (2) Error process example LCD ON Contents of addres 004016 are " FF 16" Sets LCD display RAM data LRAM0 (Address : 4016) " 16 00" LCD OFF 4. LCD drive power supply (1) Power supply capacitor may be insufficient with the division resistance for LCD power supply, and the characteristic of the LCD panel. In this case, there is the method of connecting the bypass capacitor about 0.1-0.33 F to VL1-VL3 pins. The example of a strengthening measure of the LCD drive power supply is shown in Figure 9. OFF LCD display ON or OFF ? * Sets turn off data to LCD display RAM OFF ON LCD ON or OFF Sets LCD display RAM data LRAM0 (Address : 4016) " FF 16" * Sets determinate data to LCD display RAM Fig. 10 Write procedure for LCD display RAM when LCD is on VL3 * Connect by the shortest possible wiring. * Connect the bypass capacitor to the VL1- VL3 pins as short as possible. (Referential value: 0.1- 0.33 F) VL2 VL1 38C2 group (A version) Fig. 9 Strengthening measure example of LCD drive power supply (2) When the LCD drive control circuit is used at VL3 = VCC, apply VCC to VL3 pin and write "1" to VL3 connection bit (bit 6 of the LCD power control register (address 003816)). (3) When the voltage is applied to VL1 to VL3 by using the external resistor, write "102" to dividing resistor for LCD power selection bits (RSEL) of the LCD power control register (address 003816). 5. Segment output disable register (1) Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable register. (2) When the VL pin input selection bit (VLSEL) of the LCD power control register (address 0038 16) is "1", settings of the segment output disable bit 22 and segment output disable bit 23 are invalid. 6. Data setting to LCD display RAM When writing a data into the LCD display RAM during LCD being turned ON (LCD enable bit = "1"), write the confirmed data. Do not write temporarily on the LCD display RAM because this might cause the LCD display flickering. Figure 10 shows the write procedure for LCD display RAM when LCD is on. Rev.2.00 May 28, 2004 page 99 of 100 Notes on Watchdog Timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the wait time (time set by timer 1 and timer 2) and the watchdog timer control register must be written just before executing the STP instruction. 3. The count source of the watchdog timer is affected by the system clock selected by the system clock selection bits (bits 6, 7 of CPU mode register (address 003B16)). 38C2 Group (A Version) Notes on Reset Circuit Notes on Oscillation External Output Function 1. Reset input voltage control Make sure that the reset input voltage is less than 0.2 Vcc for Vcc(min). When the signal from the XOUT pin or XCOUT pin of the oscillation circuit is input directly to the circuit except this MCU and used, the system operation may be unstabilized. In order to share the oscillation circuit safely, use the clock output from P40 and P41 by the oscillation external output function for the circuits except this MCU. 2. Countermeasures for reset signal slow rising In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the Vss pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following: *Make the length of the wiring which is connected to a capacitor as short as possible. *Be sure to verify the operation of application products on the user side. <Reason> If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. 3. Port state immediately after reset Table 1 shows the each pin state during RESET pin is " L" . Table 1 Each pin state during RESET pin is " L" Pin state Pin name P0- P2 (SEG0- SEG23) Input mode (with pull-up) P3, P4, P5, P60- P62 Input mode (high-impedance) COM0-COM3 Vcc level input 4. Frequency relation of f(XIN) and f() The frequency relation of f(XIN) and f() is f(XIN) = 8 * f(). Notes on Reset Circuit 1. Mode transition (1) Both the main clock (XIN-XOUT) and sub-clock (XCIN-XCOUT) need time for the oscillations to stabilize. The mode transition between middle-/high-speed and low-speed mode must be performed after the corresponding clock becomes stable. The sub-clock, needs extra time to stabilize particularly when executing operations after power-on and stop mode. The main and sub clocks require the following condition for mode transition. f(XIN) > 3 f(XCIN) (2) The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 2. State transitions of system clock When the mode is switched from frequency/2/4/8 to the low-speed mode, or the opposite is performed, change CM7 (bit 7 of system clock control bits of CPU mode register (address 003B16)) at first, and then, change CM6 (bit 6 of system clock control bits of CPU mode register (address 003B16)) after the oscillation of the changed mode is stabilized. 3. Wait mode Timer and LCD operate in the wait mode. Rev.2.00 May 28, 2004 page 100 of 100 NOTES ON HARDWARE Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F- 0.1F is recommended. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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Date Description Page 1.00 Feb. 13, 2003 2.00 May. 28, 2004 38C2 Group (A VERSION) Data Sheet - 28 49 70 72 93 to 100 Summary First edition issued Explanations of " (5) Output Control Function of Timer "X are partly eliminated. Figure 50 is partly revised. Explanations of " Software Commands " of Rev.1.00 are eliminated. Note 2 of Table 16 is partly revised. " APPENDIX" is added.