LTC3413
1
3413fc
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
3A, 2MHz Monolithic
Synchronous Regulator for
DDR/QDR Memory Termination
The LTC
®
3413 is a high effi ciency monolithic synchro-
nous step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from
an input voltage range of 2.25V to 5.5V and provides a
regulated output voltage equal to (0.5)VREF while sourcing
or sinking up to 3A of output current. An internal voltage
divider reduces component count and eliminates the need
for external resistors by dividing the reference voltage in
half. The internal synchronous power switch with 85mΩ
on-resistance increases effi ciency and eliminates the need
for an external Schottky diode. Switching frequencies up
to 2MHz are set by an external resistor.
Forced-continuous operation in the LTC3413 reduces
noise and RF interference. Fault protection is provided
by an overcurrent comparator that limits output current
during both sourcing and sinking operations. Adjustable
compensation allows the transient response to be optimized
over a wide range of loads and output capacitors.
Figure 1a. High Effi ciency Bus Termination Supply
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178.
n High Effi ciency: Up to 90%
n ±3A Output Current
n Symmetrical Source and Sink Output Current Limit
n Low RDS(ON) Internal Switch: 85mΩ
n No Schottky Diode Required
n 2.25V to 5.5V Input Voltage Range
n V
OUT = VREF/2
n ±1% Output Voltage Accuracy
n Programmable Switching Frequency: Up to 2MHz
n Power Good Output Voltage Monitor
n Overtemperature Protected
n Available in 16-Lead TSSOP Exposed Pad Package
n Bus Termination: DDR and QDR™ Memory,
SSTL, HSTL, ...
n Notebook Computers
n Distributed Power Systems
PVIN
SVIN
PGOOD
SWVREF
22μF
4.7M
309k
L1: VISHAY DALE IHLP-2525CZ-01 0.47
COUT: TDK C4532X5R0J107M
VIN
2.5V
COUT
100μF
s2
3413 F01a
VOUT
1.25V
±3A
L1
0.47μH
LTC3413
PGNDRUN/SS
SGND
ITH
RTVFB
330pF
2200pF
5.11k
Figure 1b. Effi ciency vs Load Current
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1 1 10
3413 F01b
30
20
10
0
90
100
VIN = 2.5V
f = 1MHz
LTC3413
2
3413fc
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
SVIN, PVIN Supply Voltages ......................... –0.3V to 6V
ITH, RUN/SS, VFB, PGOOD Voltages ............ –0.3V to VIN
VREF Voltage ................................................ –0.3V to VIN
SW Voltage ................................... –0.3V to (VIN + 0.3V)
Operating Ambient Temperature Range
(Note 2) ................................................... –40°C to 85°C
Junction Temperature (Notes 5, 8)....................... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
(Note 1)
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
SVIN
PGOOD
ITH
VFB
RT
VREF
RUN/SS
SGND
PVIN
SW
SW
PGND
PGND
SW
SW
PVIN
17
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) MUST BE SOLDERED TO PGND
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3413EFE#PBF LTC3413EFE#TRPBF 3413EFE 16-Lead Plastic TSSOP –40°C to 85°C
LTC3413IFE#PBF LTC3413IFE#TRPBF 3413IFE 16-Lead Plastic TSSOP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3413EFE LTC3413EFE#TR 3413EFE 16-Lead Plastic TSSOP –40°C to 85°C
LTC3413IFE LTC3413IFE#TR 3413IFE 16-Lead Plastic TSSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi
cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.3V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Voltage Range 2.25 5.5 V
VFB Feedback Voltage Accuracy (Note 3) l±1 %
IFB Voltage Feedback Leakage Current 0.4 μA
IRUN RUN/SS Leakage Current 1μA
ΔVFB Feedback Voltage Line Regulation VIN = 2.7V to 5.5V (Note 3) l0.04 0.2 %/V
VLOADREG Feedback Voltage Load Regulation Measured in Servo Loop, VITH = 0.36V
Measured in Servo Loop, VITH = 0.84V
l
l
0.02
–0.02
0.2
–0.2
%
%
ΔVPGOOD Power Good Range ±10 ±12 %
RPGOOD Power Good Pull-Down Resistance 120 200 Ω
IQInput DC Bias Current
Active Current
Shutdown
(Note 4)
VFB = 1.5V, VITH = 1.4V, VREF = 2.5V
VRUN = 0V (Note 7)
250
0.02
330
1
μA
μA
LTC3413
3
3413fc
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.3V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fOSC Switching Frequency
Switching Frequency Range
ROSC = 309k
(Note 6)
0.88
0.30
1.00 1.12
2.00
MHz
MHz
RPFET RDS(ON) of P-Channel FET ISW = 300mA 85 110 mΩ
RNFET RDS(ON) of N-Channel FET ISW = 300mA 65 90 mΩ
ILIMIT Peak Current Limit 3.8 5.4 A
VUVLO Undervoltage Lockout Threshold 1.75 2 2.25 V
ILSW SW Leakage Current VRUN = 0V, VIN = 5.5V (Note 7) 0.1 1 μA
VRUN RUN Threshold 0.5 0.65 0.8 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3413E is guaranteed to meet performance specifi cations
from 0°C to 70°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. LTC3413I is guaranteed to meet specifi ed
performance from –40°C to 85°C.
Note 3: The LTC3413 is tested in a feedback loop that adjusts VFB to
achieve a specifi ed error amplifi er output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
TYPICAL PERFORMANCE CHARACTERISTICS
Effi ciency vs Load Current Effi ciency vs Input Voltage Load Regulation
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1 1 10
3413 G01
30
20
10
0
90
100
VIN = 2.5V
VOUT = 1.25V
TA = 25°C
VIN = 3.3V
INPUT VOLTAGE (V)
2.5
EFFICIENCY (%)
50
60
70
4.0 5.0
3413 G02
40
30
20 3.0 3.5 4.5
80
90
100
5.5
LOAD = 1A
LOAD = 3A
LOAD = 100mA
VOUT = 1.25V
TA = 25°C
LOAD CURRENT (A)
0
–0.30
ΔVOUT/VOUT (%)
–0.25
–0.20
–0.15
–0.10
0
0.5 1.0 1.5 2.0
3413 G03
2.5 3.0
–0.05
TA = 25°C
Note 5: TJ is calculated from the ambient temperature TA and power
dissipation PD as follows: LTC3413E: TJ = TA + (PD • 38°C/W)
Note 6: 2MHz operation is guaranteed by design and not production tested.
Note 7: Shutdown current and SW leakage current are only tested during
wafer sort.
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.
LTC3413
4
3413fc
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current vs Input Voltage Load Step Transient
20μs/DIVVIN = 2.5V
VOUT= 1.25V
LOAD STEP = 0A to 3A
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
1A/DIV
3413 G11
INPUT VOLTAGE (V)
2.0
200
250
350
3.5 4.5
3413 G10
150
100
2.5 3.0 4.0 5.0 5.5
50
0
300
QUIESCENT CURRENT (μA)
TA = 25°C
Frequency vs ROSC Frequency vs Input Voltage Frequency vs Temperature
ROSC (kΩ)
54
0
FREQUENCY (kHz)
500
1500
2000
2500
654 754 854 954
4500
3413 G07
1000
154 254 354 454 554
3000
3500
4000
VIN = 3.3V
TA = 25°C
INPUT VOLTAGE (V)
2.5
990
FREQUENCY (kHz)
1000
1010
1020
1030
1050
33.5 4 4.5
3213 G08
5 5.5
1040
TA = 25°C
TEMPERATURE (°C)
–40
990
FREQUENCY (kHz)
992
996
998
1000
1010
1004
040 60
3413 G09
994
1006
1008
1002
–20 20 80 100 120
VIN = 3.3V
Switch On-Resistance
vs Temperature
Switch On-Resistance
vs Input Voltage Switch Leakage vs Input Voltage
TEMPERATURE (°C)
–40
0
ON-RESISTANCE (mΩ)
20
40
60
80
04080 120
3413 G04
100
120
–20 20 60 100
PFET
ON-RESISTANCE
NFET
ON-RESISTANCE
VIN = 3.3V
INPUT VOLTAGE (V)
2.5
0
ON-RESISTANCE (mΩ)
20
40
60
80
100
120
3 3.5 4 4.5
3413 G05
5
PFET ON-RESISTANCE
NFET ON-RESISTANCE
TA = 25°C
INPUT VOLTAGE (V)
2.5
0
LEAKAGE CURRENT (nA)
0.5
1.0
1.5
2.0
2.5
33.5 4 4.5
3413 G06
5 5.5
PFET
NFET
TA = 25°C
LTC3413
5
3413fc
Start-Up
1ms/DIVVIN = 2.5V
VOUT = 1.25V
LOAD = 0.4Ω
OUTPUT
VOLTAGE
500mV/DIV
INDUCTOR
CURRENT
1A/DIV
3413 G13
Load Step Transient
20μs/DIVVIN = 2.5V
VOUT = 1.25V
LOAD STEP = 0A TO –3A
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
1A/DIV
3413 G12
TYPICAL PERFORMANCE CHARACTERISTICS
SVIN (Pin 1): Signal Input Supply. Decouple this pin to
SGND with a capacitor. SVIN must be greater or equal to
PVIN, however, the difference between SVIN and PVIN must
be less than 0.5V.
PGOOD (Pin 2): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not within ±10% of regulation point.
ITH (Pin 3): Error Amplifi er Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V
to 1.4V with 0.6V corresponding to the zero-sense voltage
(zero current).
VFB (Pin 4): Feedback Pin. Receives the feedback voltage
from the output.
RT (Pin 5): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
VREF (Pin 6): Reference Voltage Input. The positive input
of the internal error amplifi er senses one-half of the volt-
age at this pin through a resistor divider.
RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3413. In shutdown
all functions are disabled drawing < 1μA of supply current.
A capacitor to ground from this pin sets the ramp time to
full output current.
SGND (Pin 8): Signal Ground. All small-signal components
and compensation components should connect to this
ground, which in turn connects to PGND at one point.
PVIN (Pins 9, 16): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 10, 11, 14, 15): Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
PGND (Pins 12, 13): Power Ground. Connect this pin
closely to the (–) terminal of CIN and COUT
.
Exposed Pad (Pin 17): Should be connected to PCB
ground.
PIN FUNCTIONS
LTC3413
6
3413fc
Main Control Loop
The LTC3413 is a monolithic, constant frequency, current
mode step-down DC/DC converter that is capable of sourc-
ing and sinking current at the output. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifi er adjusts the voltage on the ITH pin by
comparing the feedback signal on the VFB pin with a ref-
erence voltage that is equal to one-half of the voltage on
the VREF pin. When the load current increases, it causes
a reduction in the feedback voltage relative to the refer-
ence. The error amplifi er raises the ITH voltage until the
average inductor current matches the new load current.
When the top power MOSFET shuts off, the synchronous
power switch (N-channel MOSFET) turns on until either
the bottom current limit is reached or the beginning of the
next clock cycle. The bottom current limit is set at –7A.
The operating frequency is set by an external resistor
connected between the RT pin and ground. The switching
frequency can range from 300kHz to 2MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±10%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Dropout Operation
When the input supply voltage decreases toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces the
–
+
–
+
–
+
–
+
–
+
16
10
9
PVIN
3
ITH
6
VREF
1
8
SVIN
SGND
4
VFB
PGOOD
SVIN
PVIN
SLOPE
COMPENSATION
RECOVERY
SLOPE
COMPENSATION
PMOS CURRENT
COMPARATOR
NMOS CURRENT
COMPARATOR
OSCILLATOR
ERROR
AMPLIFIER
LOGIC
RUN
RUN/SSRT
11
14
15
SW
SW
SW
SW
13
75
PGND
3413 BD
12 PGND
2
1.1VREF
2
0.9VREF
2
FUNCTIONAL DIAGRAM
OPERATION
LTC3413
7
3413fc
OPERATION
main switch to remain on for more than one cycle until it
reaches 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
Low Supply Operation
The LTC3413 is designed to operate down to an SVIN input
supply voltage of 2.25V. One important consideration at low
input supply voltages is that the RDS(ON) of the P-channel
and N-channel power switches increases. The user should
calculate the power dissipation when the LTC3413 is used
at 100% duty cycle with low input voltages to ensure that
thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency
architectures by preventing subharmonic oscillations at
duty cycles greater than 50%. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, the
maximum inductor peak current is reduced when slope
compensation is added. In the LTC3413, however, slope
compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles.
Short-Circuit Protection
When the output is shorted to ground, the inductor cur-
rent decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases greater than 5A, the top
power MOSFET will be held off and switching cycles will
be skipped until the inductor current is reduced.
Pre-Biased Load
It is important to sequence the start-up of the LTC3413
prior to any external circuitry that might drive the VOUT pin.
If the VOUT pin is externally driven to a voltage more than
10% (the OV threshold) above the desired VOUT voltage,
the LTC3413 may enter a latched state where it no longer
switches. To avoid this scenario, the user should ensure
there is not a pre-biased load during start-up. This can
be accomplished by sequencing the LTC3413’s RUN pin
before the load’s supply.
APPLICATIONS INFORMATION
The basic LTC3413 application circuit is shown in Figure 1a.
External component selection is determined by the
maximum load current and begins with the selection of
the inductor value and operating frequency followed by
CIN and COUT
.
Operating Frequency
Selection of the operating frequency is a tradeoff between
effi ciency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves effi ciency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3413 is determined by
an external resistor that is connected between pin RT and
ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation.
Rfk
OSC =Ω
()
Ω
323 10 10
11
.• –_
Although frequencies as high as 2MHz are possible, the
minimum on-time of the LTC3413 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 110ns. Therefore, the minimum duty cycle is
equal to 100 • 110ns • f (Hz).
LTC3413
8
3413fc
APPLICATIONS INFORMATION
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN or VOUT and
decreases with higher inductance.
Δ= ⎛
⎝
⎜⎞
⎠
⎟
IfLVV
V
L OUT OUT
IN
11
()( ) –
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors and
the output voltage ripple. Highest effi ciency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specifi ed maximum, the inductor value should
be chosen according to the following equation:
LV
fI
V
V
OUT
LMAX
OUT
IN MAX
=Δ
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
() ()
–1
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fi xed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core losses and are used
often at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements and
any radiated fi eld/EMI requirements.
Table 1 shows some recommended surface mount induc-
tors for LTC3413 applications.
Table 1. Recommended Surface Mount Inductors
MANUFACTURER PART NUMBER
VALUE
(μH)
DCR
(mΩ)
Murata LQH55DNR47M01 0.47 13.0
Vishay/Dale IHLP252CZPJR47M01 0.47 4.2
Pulse P1166.681T 0.44 6.0
Cooper SD20-R47 0.47 20.0
CIN and COUT Selection
The input capacitance, CIN, is needed to fi lter the trapezoidal
wave current at the source of the top MOSFET. To prevent
large voltage transients from occurring, a low ESR input
capacitor sized for the maximum RMS current should be
used. The maximum RMS current is given by:
II V
V
V
V
RMS OUT MAX OUT
IN
IN
OUT
=() –1
This formula has a maximum at VIN = 2VOUT
, where IRMS =
IOUT/2. This simple worst-case condition is commonly used
for design because even signifi cant deviations do not offer
much relief. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
LTC3413
9
3413fc
APPLICATIONS INFORMATION
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, ΔVOUT
, is determined by:
Δ≤Δ +
⎛
⎝
⎜⎞
⎠
⎟
V I ESR fC
OUT L OUT
1
8
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capaci-
tors placed in parallel may be needed to meet the ESR
and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic and ceramic capaci-
tors are all available in surface mount packages. Special
polymer capacitors offer very low ESR but have lower
capacitance density than other types. Tantalum capacitors
have the highest capacitance density but it is important
to only use types that have been surge tested for use in
switching power supplies.
Aluminum electrolytic capacitors have signifi cantly higher
ESR, but can be used in cost-sensitive applications pro-
vided that consideration is given to ripple current ratings
and long term reliability. Ceramic capacitors have excel-
lent low ESR characteristics but can have a high voltage
coeffi cient and audible piezoelectric effects. The high Q
of ceramic capacitors with trace inductance can also lead
to signifi cant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
In most applications, VOUT is connected directly to VFB.
The output voltage will be equal to one-half of the volt-
age on the VREF pin for this case.
VV
OUT REF
=2
If a different output voltage relationship is desired, an
external resistor divider from VOUT to VFB can be used.
The output voltage will then be set according to the fol-
lowing equation:
VVR
R
OUT REF
=+
⎛
⎝
⎜⎞
⎠
⎟
212
1
Figure 2. Setting the Output Voltage
R2
VOUT
R1
3413 F02
VFB
SGND
LTC3413
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3413 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3413 in a low
quiescent current shutdown state (IQ < 1μA).
The LTC3413 contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
LTC3413
10
3413fc
APPLICATIONS INFORMATION
in Figure 1a. The soft-start duration can be calculated by
using the following formula:
tR VV
SS SS IN
=⎛
⎝
⎜⎞
⎠
⎟
•C ln V(Seconds)
SS IN
–.18
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
Effi ciency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses.
The VIN quiescent current loss dominates the effi ciency loss
at very low load currents whereas the I2R loss dominates
the effi ciency loss at medium to high load currents. In a
typical effi ciency plot, the effi ciency curve at very low load
currents can be misleading since the actual power lost is
of no consequence.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the Electrical Characteris-
tics and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f(QT + QB) where QT and
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW
, and external inductor RL. In con-
tinuous mode the average output current fl owing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
R
SW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative losses
and inductor core losses generally account for less than
2% of the total loss.
Thermal Considerations
In most applications, the LTC3413 does not dissipate much
heat due to its high effi ciency.
But, in applications where the LTC3413 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3413 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
R = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
LTC3413
11
3413fc
APPLICATIONS INFORMATION
The junction temperature, TJ, is given by:
T
J = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC3413 in dropout at an
input voltage of 3.3V, a load current of 3A and an ambi-
ent temperature of 70°C. From the Typical Performance
graph of switch resistance, the RDS(ON) of the P-channel
switch at 70°C is approximately 97mΩ. Therefore, power
dissipated by the part is:
P
D = (ILOAD2)(RDS(ON)) = (3A)2(97mΩ) = 0.87W
For the TSSOP package, the θJA is 38°C/W. Thus the junc-
tion temperature of the regulator is:
T
J = 70°C + (0.87W)(38°C/W) = 103°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction temperature
is lower due to reduced switch resistance (RDS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD(ESR), where ESR is the effective series
resistance of COUT
. ΔILOAD also begins to charge or dis-
charge COUT generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem. The ITH
pin external components and output capacitor shown in
Figure 1a will provide adequate compensation for most
applications.
Output Voltage Tracking of VREF
For applications in which the VREF pin is connected to
the VIN pin, the output voltage will be equal to one-half
of the voltage on the VIN pin. Because the output voltage
will track the input voltage, any disturbance on VIN will
appear on VOUT
. For example, a load step transient could
cause the input voltage to drop if there is insuffi cient bulk
capacitance at the VIN pin. The corresponding drop in the
output voltage during the load step transient is caused by
the VOUT tracking of VIN and should not be confused with
poor load regulation.
Design Example
As a design example, consider using the LTC3413 in an
application with the following specifi cations: VIN = 2.5V,
VOUT = 1.25V, IOUT(MAX) = ±3A, f = 1MHz.
First, calculate the timing resistor:
Rkk
OSC =Ω=Ω
323 10
110 10 313
11
6
.•
•–
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current:
LV
MHz A
V
V
=⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟=
125
112
1125
25 04
.
•. –.
..77μH
Using a 0.47μH inductor results in a maximum ripple
current of:
Δ= μ
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
IV
MHz H
V
V
L
125
1047
1125
25
.
•. –.
.== 133.A
COUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
two 100μF ceramic capacitors will be used. CIN should be
sized for a maximum current rating of:
IA
V
V
V
VA
RMS RMS
=⎛
⎝
⎜⎞
⎠
⎟=3125
25
25
125 115
.
.
.
.–.
Decoupling the PVIN pins with two 100μF capacitors is
adequate for most applications. Connect the VREF pin
directly to SVIN. Connecting the VFB pin directly to VOUT
will set the output voltage equal to one-half of the volt-
age on the VREF pin. The complete circuit for this design
example is illustrated in Figure 3.
LTC3413
12
3413fc
APPLICATIONS INFORMATION
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PVIN, SVIN, VOUT
, PGND, SGND or any other DC rail
in your system).
5. Connect the VFB pin directly to the VOUT pin.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3413. Check the following in your layout.
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
be segregated with all small-signal components returning
to the SGND pin at one point which is then connected to
the PGND pin close to the LTC3413.
2. Connect the (+) terminal of the input capacitor(s), CIN, as
close as possible to the PVIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
RPG
100k
RITH
5.11k
ROSC
309k
*VISHAY DALE IHLP-2525CZ-01 0.47μH
**TDK C4532X5R0J107M
RSS
4.7M
CSS
330pF X7R
CITH
2200pF
X7R
CC
100pF
PGOOD
SVIN
PGOOD
ITH
VFB
RT
VREF
RUN/SS
SGND
PVIN
SW
SWVFB
PGND
PGND
SW
SW
PVIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC3413
L1*
0.47μH
CIN1**
100μF
CIN2**
100μF
COUT**
100μF
s2
GND
3413 F03
VOUT
1.25V
±3A
VIN
2.5V
Figure 3. One-Half VREF
, ±3A DDR Memory Termination Supply at 1MHz
(Effi ciency Curve is Shown in Figure 1b)
LTC3413
13
3413fc
APPLICATIONS INFORMATION
(4a) Top Layer (4b) Bottom Layer
(4c) PCB Photo
Figure 4. LTC3413 Layout Design
LTC3413
14
3413fc
TYPICAL APPLICATIONS
RPG
100k
RITH
5.11k
ROSC
309k
*VISHAY DALE IHLP-2525CZ-01 0.47μH
**TDK C4532X5R0J107M
RSS
4.7M
CSS
330pF X7R
CITH
2200pF
X7R
CC
100pF
PGOOD
2.5V
SVIN
PGOOD
ITH
VFB
RT
VREF
RUN/SS
SGND
PVIN
SW
SWVFB
PGND
PGND
SW
SW
PVIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC3413
L1*
0.47μH
CIN1**
100μF
CIN2**
100μF
COUT**
100μF
s2
3413 TA01
VOUT
1.25V
±3A
VIN
3.3V
GND
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
00.1 1 10
1.25V, ±3A DDR Memory Termination Supply at 1MHz
Effi ciency vs Load Current,
VIN = 3.3V, VOUT = 1.25V, f = 1MHz
LTC3413
15
3413fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663,
Exposed Pad Variation BA)
FE16 (BA) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.74
(.108)
2.74
(.108)
0.195 – 0.30
(.0077 – .0118)
TYP
2
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
RECOMMENDED SOLDER PAD LAYOUT
3. DRAWING NOT TO SCALE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.74
(.108)
2.74
(.108)
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3413
16
3413fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0708 REV C • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC3406 600mA, (IOUT) 1.5MHz Synchronous Step-Down Regulator VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ThinSOT
LTC3407 Dual 600mA, (IOUT) 1.5MHz, Synchronous Step-Down Regulator VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, MS10E
LTC3411 1.25A, (IOUT) 4MHz, Monolithic Synchronous Step-Down Regulator VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, MS, DFN-10
LTC3412 2.5A, (IOUT) 4MHz, Monolithic Synchronous Step-Down Regulator VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, TSSOP-16
LTC3414 4A, (IOUT) 4MHz, Monolithic Synchronous Step-Down Regulator VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA, TSSOP-20E
LTC3713 Low Input Voltage, No RSENSE™ Synchronous Controller VIN: 1.5V to 10V, VOUT(MIN) = 0.8V, SSOP-24
LTC3717 No RSENSE Controller for DDR Memory Termination VIN: 5V to 36V, VOUT(MIN) = 0.8V, SSOP-24
LTC3718 Low Input Voltage, No RSENSE Controller for DDR Memory Termination VIN: 1.5V to 10V, VOUT(MIN) = 0.8V, SSOP-24
No RSENSE is a trademark of Linear Technology Corporation.
RPG
100k
RITH
10k
ROSC
309k
*VISHAY DALE IHLP-2525CZ-01 0.47μH
**TDK C4532X5R0J107M
†TAIYO YUDEN JMK325BJ226MM
††SANYO POSCAP 4TPD470M
RSS
4.7M
CSS
330pF X7R
CITH
2200pF
X7R
CC
100pF
PGOOD
1.5V
SVIN
PGOOD
ITH
VFB
RT
VREF
RUN/SS
SGND
PVIN
SW
SWVFB
PGND
PGND
SW
SW
PVIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC3413
L1*
0.47μH
CIN1**
100μF
CIN2**
100μF
COUT1†
22μF
COUT2††
470μF
GND
3413 TA02
VOUT
0.75V
±3A
VIN
3.3V
+
3.3V to 0.75V, ±3A HSTL Application
