Intel® Xeon® Processor E7-4809 v4
20M Cache, 2.10 GHz
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Essentials
Product Collection Intel® Xeon® Processor E7 v4 Family
Code Name Products formerly Broadwell
Vertical Segment Server
Processor Number E7-4809V4
Status Launched
Launch Date Q2'16
Lithography 14 nm
Recommended Customer Price
Performance
# of Cores 8
# of Threads 16
Processor Base Frequency 2.10 GHz
Cache 20 MB
Bus Speed 6.4 GT/s QPI
# of QPI Links 3
TDP 115 W
Supplemental Information
Embedded Options Available No
Datasheet View now
Memory Specifications
Max Memory Size (dependent on memory type) 3.07 TB
Memory Types DDR4-1333/1600/1866 DDR3-1066/1333
Max # of Memory Channels 4
Max Memory Bandwidth 85 GB/s
Physical Address Extensions 46-bit
ECC Memory Supported ‡Yes
Expansion Options
Scalability S4S
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PCI Express Revision 3.0
PCI Express Configurations ‡x4, x8, x16
Max # of PCI Express Lanes 32
Package Specifications
Sockets Supported FCLGA2011
Max CPU Configuration 4
TCASE 69°C
Package Size 45mm x 52.5mm
Advanced Technologies
Intel® Turbo Boost Technology ‡No
Intel® Hyper-Threading Technology ‡Yes
Intel® Virtualization Technology (VT-x) ‡Yes
Intel® Virtualization Technology for Directed I/O (VT-d) ‡Yes
Intel® VT-x with Extended Page Tables (EPT) ‡Yes
Intel® TSX-NI Yes
Intel® 64 ‡Yes
Instruction Set 64-bit
Instruction Set Extensions Intel® AVX2
Idle States Yes
Enhanced Intel SpeedStep® Technology Yes
Thermal Monitoring Technologies Yes
Intel® Instruction Replay Technology No
Security & Reliability
Intel® AES New Instructions Yes
Secure Key Yes
Intel® OS Guard Yes
Intel® Trusted Execution Technology ‡Yes
Execute Disable Bit ‡Yes
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“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.
Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM, i7-2670QM/i7-
2675QM, i5-2430M/i5-2435M, i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor configuration update.
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System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.
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