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Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

32Mx8, 16Mx16 DDR2 DRAM

per clock cycle

with CK

reduced strength options

32Mx8 (8Mx8x4 banks) IS43/46DR83200A

16Mx16 (4Mx16x4 banks) IS43/46DR16160A

x8: 60-ball TW-BGA (8mm x 10.5mm)

Commercial (0°C ≤ Tc ≤ 85°C)

Industrial (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A1 (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A2 (-40°C ≤ Tc; Ta ≤ 105°C)

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double-data rate architecture is essentially a 4n-prefetch

Speed Grade -25E -3D -37C -5B

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Output (read) data is referenced to the crossings of CK and CK (both directions of

crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals

and device input buffers and output drivers. Taking CKE LOW provides Precharge

Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row

Active in any bank). CKE is synchronous for power down entry and exit, and for self

refresh entry. CKE is asynchronous for self refresh exit. After VREF has become

stable during the power on and initialization sequence, it must be maintained for

proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF

ODT Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal

to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DM

signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being

entered.

DM (x8) or

UDM, LDM (x16) Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH coincident with that input data during a Write access. DM

register or one of the extended mode registers is to be accessed during a MRS or

EMRS command cycle.

A0 - A12 Input

Address Inputs: Provide the row address for Active commands and the column

address and Auto Precharge bit for Read/Write commands to select one location

out of the memory array in the respective bank. A10 is sampled during a Precharge

command to determine whether the Precharge applies to one bank (A10 LOW) or all

banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 -

BA1. The address inputs also provide the op-code during MRS or EMRS commands.

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/RAS, /CAS, /WE Command input VREF Input reference voltage

CKE Clock enable VDDL Supply voltage for DLL circuit

CK, /CK Differential clock input VSSDL Ground for DLL circuit

DM Write data mask NC No connection

RDQS, /RDQS Differential Redundant Data Strobe

Pin name Function Pin name Function

A0 to A12 Address inputs ODT ODT control

BA0, BA1 Bank select VDD Supply voltage for internal circuit

CK, /CK Differential clock input VSSDL Ground for DLL circuit

LDM to UDM Write data mask NC No connection

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Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

AC & DC Recommended Operating Conditions

VDD Supply Voltage 1.7 1.8 1.9 V 1

VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 5

VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1, 5

Deviation of VM with respect to VDDQ/2 ΔVM - 6 + 6 % 1

60-ball BGA 4-layer 39.71 34.21 32.17 3.27 C/W

84-ball BGA 4-layer 34.66 30.07 28.66 6.68 C/W

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Symbol Parameter Min. Max. Units Notes

VIH(dc) dc input logic HIGH VREF + 0.125 VDDQ + 0.3 V

VIL(dc) dc input logic LOW - 0.3 VREF - 0.125 V

Symbol Parameter DDR2-400, DDR2-533 DDR2-667, DDR2-800 Units Notes

VIH (ac) ac input logic HIGH VREF + 0.250 VDDQ + Vpeak VREF + 0.200 VDDQ + Vpeak V 1

Refresh to active/Refresh command time tRFC 75 ns 1

Average periodic refresh interval tREFI

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Average clock HIGH pulse width tCH(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36

Average clock LOW pulse width tCL(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36

DQS latching rising transitions to associated

clock edges tDQSS - 0.25 0.25 - 0.25 0.25 tCK(avg) 30

DQS falling edge to CK setup time tDSS 0.2 – 0.2 – tCK(avg) 30

DQS falling edge hold time from CK tDSH 0.2 – 0.2 – tCK(avg) 30

DQS input HIGH pulse width tDQSH 0.35 – 0.35 – tCK(avg)

DQS input LOW pulse width tDQSL 0.35 – 0.35 – tCK(avg)

Write preamble tWPRE 0.35 – 0.35 – tCK(avg)

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK(avg) 10

DQ and DM input setup time tDS(base) 100 – 50 – ps 6, 7, 8, 20,

28, 31

DQ and DM input hold time tDH(base) 175 – 125 – ps 6, 7, 8, 21,

28, 31

DQ and DM input pulse width for each input tDIPW 0.35 – 0.35 – tCK(avg)

DQ output access time from CK/CK tAC - 450 450 - 400 400 ps 40

DQS output access time from CK/CK tDQSCK - 400 400 - 350 350 ps 40

Data-out high-impedance time from CK/CK tHZ – tAC,max – tAC,

max ps 18,40

DQS/DQS low-impedance time from CK/CK tLZ(DQS) tAC,min tAC,max tAC,min tAC,

Min(

DQ hold skew factor tQHS – 340 – 300 ps 38

DQ/DQS output hold time from DQS tQH tHP - tQHS – tHP - tQHS – ps 39

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK(avg) 19,41

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK(avg) 19,42

(For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.)

tAC,max + 1

tAC,min

2 x tCK(avg) +

tAC,max + 1 ns

+ tAC,max + 1

tAC,min

2.5 x tCK(avg) +

tAC,max + 1 ns

tCK(avg)

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1. DDR2 SDRAM AC Timing Reference Load

Figure "AC Timing Reference Load" represents the timing reference load used in defining the relevant timing

parameters of the part. It is not intended to be either a precise representation of the typical system environment or

a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation

tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test

conditions (generally a coaxial transmission line terminated at the tester electronics).

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing

reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS)

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = +

500 mV (+ 250 mV to - 500 mV for falling edges).

c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between

DQS and DQS for differential strobe.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown in Figure "Slew Rate Test Load".

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of

the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method

by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships

relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing

methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via

the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure

proper operation.

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Power-up and Initialization Sequence (cont'd)

f) Issue an EMRS command to EMR(3).

g) Issue EMRS to enable DLL.

h) Issue a Mode Register Set command for DLL reset.

i) Issue a precharge all command.

j) Issue 2 or more auto-refresh commands.

k) Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user

defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable

function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD (off chip

executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR, or EMR(1),

EMR(2), or EMR(3) variables, all variables within the addressed register must be redefined when the MRS or EMRS

commands are issued.

MRS, EMRS and Reset DLL do not affect memory array contents, which means re-initialization including those can be

executed at any time after power-up without affecting memory array contents.

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