SMSC COM20020I 3.3V Rev.E 1 Revision 09-11-06
DATASHEET
COM20020I 3.3V Rev.E
5Mbps ARCNET (ANSI
878.1) Controller with
2K x 8 On-Chip RAM
Datasheet
Product Features
New Features:
- Data Rates up to 5 Mbps
- Programmable Reconfiguration Times
28 Pin PLCC and 48 Pin TQFP packages;
Lead-Free RoHS Compliant packages also
available
Ideal for Industrial/Factory/Building Automation
and T ransportation Applications
Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
Minimal Microcontroller and Medi a Interface
Logic Required
Flexible Interface For Use With All
Microcontrollers or Microproc essors
Automatically Detects Type of Microcontroller
Interface
2Kx8 On-Chip Dual Port RAM
Command Chaining for Packet Queuing
Sequential Access to Internal RAM
Software Programmable Node ID
Eight, 256 Byte Pages Allow Four Pages TX and
RX Plus Scratch-Pad Memory
Next ID Readable
Internal Clock Scaler and Clock Multiplier for
Adjusting Network Speed
Operating Temperature Range of -40oC to +85oC
3.3V power supply with 5V tolerant I/O
Self-Reconfiguration Protocol
Supports up to 255 Nodes
Supports Various Network Topologies (Star, Tree,
Bus...)
CMOS, Single +3.3V Supply
Duplicate Node ID Detection
Powerful Diagnostics
Receive All Pa ckets Mode
Flexible Media Interface:
- T raditional Hybrid Interface For Long Distances
at 2.5Mbps
- RS485 Differential Driver Interface For Low
Cost, Low Power, High Re liability
ORDERING INFORMATION
Order Number(s):
COM20020I 3VLJP for 28 pin PLCC * package
COM20020I 3V-DZD for 28 pin PLCC * Lead-Free RoHS Compli ant package
COM20020I 3V-HD for 48 pin TQFP package
COM20020I 3V-HT for 48 pin TQFP Lead-Free RoHS Compliant package
* TQFP package is recommended for new design
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 2 Revision 09-11-06
DATASHEET
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © 2006 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purcha ser of the d escribed semicondu ctor dev ices any licen ses under any pa tent righ ts o r other i ntellectual property ri ghts of SMSC or
others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms
of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as
anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC
products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or
contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing
and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement,
may be obtained by v isiting SMSC’ s website at h ttp://w ww.smsc.com . SMSC is a registered trade mark of Standard M icrosy stems Corporation (“SMSC”).
Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES AN Y AND ALL WARRANTIES, INCLUDING WI THOUT LIMITATION ANY AND ALL IMPLIED WARR ANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL
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OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS;
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ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 3 Revision 09-11-06
DATASHEET
TABLE OF CONTENTS
CHAPTER 1 GENERAL DESCRIPTION................................................................................................................5
CHAPTER 2 PIN CONFIGURATIONS...................................................................................................................6
CHAPTER 3 DESCRIPTION OF PIN FUNCTIONS ...............................................................................................8
CHAPTER 4 PROTOCOL DESCRIPTION...........................................................................................................11
4.1 NETWORK PROTOCOL ...................................................................................................................................11
4.2 DATA RATES ................................................................................................................................................11
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps....................................................................................11
4.3 NETWORK RECONFIGURATION........................................................................................................................12
4.4 BROADCAST MESSAGES ................................................................................................................................12
4.5 EXTENDED TIMEOUT FUNCTION......................................................................................................................12
4.6 LINE PROTOCOL............................................................................................................................................13
CHAPTER 5 SYSTEM DESCRIPTION ................................................................................................................15
5.1 MICROCONTROLLER INTERFACE .....................................................................................................................15
5.2 TRANSMISSION MEDIA INTERFACE ..................................................................................................................19
CHAPTER 6 FUNCTIONAL DESCRIPTION........................................................................................................24
6.1 MICROSEQUENCER........................................................................................................................................24
6.2 INTERNAL REGISTERS............................................................................................................................25
6.3 INTERNAL RAM..............................................................................................................................................35
6.4 COMMAND CHAINING.....................................................................................................................................40
6.5 INITIALIZATION SEQUENCE..............................................................................................................................42
6.6 IMPROVED DIAGNOSTICS................................................................................................................................42
CHAPTER 7 OPERATIONAL DESCRIPTION.....................................................................................................45
7.1 MAXIMUM GUARANTEED RATINGS*.................................................................................................................45
7.2 DC ELECTRICAL CHARACTERISTICS ................................................................................................................45
CHAPTER 8 TIMING DIAGRAMS .......................................................................................................................48
CHAPTER 9 PACKAGE OUTLINES ...................................................................................................................63
CHAPTER 10 APPENDIX A...................................................................................................................................65
CHAPTER 11 APPENDIX B...................................................................................................................................68
CHAPTER 12 APPENDIX C...................................................................................................................................69
12.1 SOFTWARE IDENTIFICATION OF THE COM20020I 3V REV D AND REV E ............................................................69
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 4 Revision 09-11-06
DATASHEET
LIST OF FIGURES
Figure 1 - COM20020I 3V Operation ...........................................................................................................................10
Figure 2 - Multiplexed, 8051-Like Bus Interface With RS-485 Interface.......................................................................16
Figure 3 - Non-Multiplexed, 6801-Like Bus Interface With RS-485 Interface...............................................................17
Figure 4 - High Speed Cpu Bus Timing - Intel CPU Mode...........................................................................................18
Figure 5 - COM 2 002 0I 3 V Network U s ing RS- 4 8 5 Di ffe r e ntial T r ans c eivers..................................................................20
Figure 6 - Dipulse Waveform For Data Of 1-1-0...........................................................................................................20
Figure 7 - Internal Block Diagram.................................................................................................................................22
Figure 8 – Sequential Access Operation......................................................................................................................35
Figure 9 – Ram Buffer Packet Configuration................................................................................................................38
Figure 10 - Command Chaining Status R e g i s t er Queu e............................................................................. ...................40
Figure 11 - Multiplexed Bus, 68xx-Like Control Signals; Read Cycle...........................................................................48
Figure 12 - Multiplexed Bus, 80xx-Like Control Signals; Read Cycle...........................................................................49
Figure 13 - Multiplexed Bus, 68xx-Like Control Signals; Write Cycle...........................................................................50
Figure 14 - Multiplexed Bus, 80xx-Like Control Signals; Write Cycle...........................................................................51
Figure 15 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle...................................................................52
Figure 16 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle...................................................................53
Figure 17 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle...................................................................54
Figure 18 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle...................................................................55
Figure 19 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle...................................................................56
Figure 20 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle...................................................................57
Figure 21 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle...................................................................58
Figure 22 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle...................................................................59
Figure 23 – Normal Mode Transmit Or Receive Timing...............................................................................................60
Figure 24 – Backplane Mode Transmit or Receive Timing...........................................................................................61
Figure 25 – TTL Input Timing On XTAL1 Pin...............................................................................................................62
Figure 26 – Reset And Interrupt Timing.......................................................................................................................62
Figure 27 - 28 Pin PLCC Package Dimensions............................................................................................................63
Figure 28 - 48 Pin TQFP Package Outline...................................................................................................................64
Figure 29 - Effect Of The EF Bit On The TA/RI Bit.......................................................................................................66
Figure 30 - Example Of Interface Circuit Diagram To ISA Bus ....................................................................................68
LIST OF TABLES
Table 1 - Typical Media ................................................................................................................................................23
Table 2 - Read Register Summary...............................................................................................................................24
Table 3 - Write Register Summary...............................................................................................................................25
Table 4 - STATUS REGI STER.....................................................................................................................................28
Table 5 - DIAGNOSTIC STA T U S RE G I STE R........................................................................................... ...................29
Table 6 - COMMA ND REGIS TER ................................................................................................................................30
Table 7 - Address Pointer High R egister.......................................................................................................................30
Table 8 - Address Point er Low Regi ster........................................................................................................................31
Table 9 - SU B A D DRESS REGISTER.......................................................................................................................31
Table 10 - Configuration Register ................................................................................................................................31
Table 11 - SETUP 1 REGISTER ..................................................................................................................................33
Table 12 - SETUP 2 REGISTER ..................................................................................................................................34
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 5 Revision 09-11-06
DATASHEET
Chapter 1 General Description
SMSC's COM20020I 3V is a member of the family of Embedded ARCNET Controllers from Standard Microsystems
Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent
peripherals in industrial and embedded control environments using an ARCNET protocol engine. The flexible
microcontroller and media interfaces, eight-page message support, and extended temperature range of the COM20020I
3V make it the only true network controller optimized for use in industrial and embedded applications. Using an
ARCNET protocol engine is the ideal solution for embedded control applications because it provides a deterministic
token-passing protocol, a highly reliable and proven networking scheme, and a data rate of up to 5 Mbps when using the
COM20020I 3V.
A token-passing protocol provides predictable response times because each network event occurs within a
predetermined time interval, based upon the number of nodes on the network. The deterministic nature of ARCNET is
essential in real time applications. The integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the 5
Mbps maximum data rate, and the internal diagnostics make the COM20020I 3V the highest performance embedded
communications device available. With only one COM20020I 3V and one microcontroller, a complete communications
node may be implemented.
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer to
the ARCNET Local Area Network Standard, available from Standard Microsystems Corporation or the
ARCNET Desig ner 's Handboo k, av ailabl e from Datapoint Corporation.
For more detailed information on cabling options including RS485, transformer-coupled RS-485 and Fiber
Optic int erfaces, pl ease refer to the fol lowing techn ical no te which i s availabl e from S t andard Microsy stems
Corporat ion : Technical Not e 7-5 - C abling Guide l in es for the CO M2 00 20 I 3 V ULANC.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 6 Revision 09-11-06
DATASHEET
Chapter 2 Pin Configurations
24
23
22
21
20
19
18
17
16
15
14
13
nRD/nDS
nWR/DIR
nCS
nINTR
nRESET IN
nTXEN
RXIN
nPULSE2
nPULSE1
XTAL2
XTAL1
VDD
25 24 23 22 21 20 19
nCS
nINTR
nRESET IN
VSS
nTXEN
RXIN
nPULSE2
567891011
AD1
VSS
AD2
D3
D4
D5
D6
18
17
16
15
14
13
12
nPULSE 1
XTAL2
XTAL1
VDD
VSS
N/C
D7
1
2
3
4
5
6
7
8
9
10
11
12
A0/nMUX
A1
A2/ALE
AD0
AD1
AD2
D3
D4
D5
D6
D7
VSS
26
27
28
1
2
3
4
nWR/DIR
nRD/nDS
VDD
A2/ALE
AD0
A1
A0/nMUX
Packages: 2 4- Pin DIP or 2 8- Pin PL CC
Ordering Information:
COM20019
PACKA GE TYPE: P = Plastic , L JP = PLCC
TEMP RANGE: (Blank) = Commercial: 0°C to +70°C
I = Industrial: -40°C to +85°C
DEVICE TYPE: 20019 = Univ ersal Local Area Network Controller
(with 2K x 8 RAM)
P
I
Package: 28-Pin PLCC
Ordering Information:
COM20020I 3V P
PACKAGE TYPE: P = Plastic, LJP = PLCC
TEMP RANGE: 1 = Industrial: -40° C to 75° C
DEVICE TYPE: 20020 = Universal Local Area Network
(with 2K x 8
RAM)
COM20020I 3V
28 PIN PLCC
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 7 Revision 09-11-06
DATASHEET
NOTE: BUSTMG pin is only TQFP package
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
N/C
N/C
A2/ALE
A1
A0/nMUX
VDD
N/C
VSS
N/C
nRD/nDS
VDD
nWR/DIR
D7
N/C
N/C
N/C
N/C
VSS
N/C
VDD
XTAL1
XTAL2
VSS
nPULSE1
AD0
AD1
N/C
AD2
N/C
VSS
D3
VDD
D4
D5
VSS
D6
nCS
VDD
nINTR
N/C
VDD
nRESET
VSS
nTXEN
RXIN
N/C
BUSTMG
nPULSE2
COM20020I
48 PIN TQFP
COM20020I 3V
48 PIN TQFP
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 8 Revision 09-11-06
DATASHEET
Chapter 3 Description of Pin Functions
PIN NO NAME SYMBOL I/O DESCRIPTION
PLCC TQFP MICROCONTROLLER INTERFACE
1, 2,
3 44, 45,
46 Address
0-2 A0/nMUX
A1
A2/ALE
IN
IN
IN
On a non-multiplexed mode, A0-A2 are address
input bits. (A0 is the LSB) On a multiplexed
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A1 is connected to an internal pull-up resistor.
4, 5, 6,
8, 9, 10,
11, 12
1, 2, 4,
7, 9, 10,
12, 13
Data 0-7 AD0-AD2,
D3-D7 I/O On a non-multiplexed bus, these signals are used
as the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address lines
(latched by ALE) and as the low data lines. D3-D7
are always used for data only. These signals are
connected to internal pull-up r esistors.
26 37 nWrite/
Direction nWR/DIR IN
nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
27 39 nRead/
nData
Strobe
nRD/nDS IN
nRD is for 80xx CPU, nRD is Read signal in put.
Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signa l
input. Active Low .
23 31 nReset In nRESET IN
Hardware reset signal. Active Low.
24 34 nInterrupt nINTR OUT
Interrupt signal output. Active Low.
25 36
nChip
Select nCS IN
Chip Select input. Active Low .
- 26
Read/Write
Bus Timing
Select
BUSTMG IN
Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU Timing.
L: High speed timing mode (only for non-multiplexed
bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
NOTE:
BUSTMG pin does not exist in PLCC package.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 9 Revision 09-11-06
DATASHEET
PIN NO NAME SYMBOL I/O DESCRIPTION
PLCC TQFP TRANSMISSION MEDIA INTERFACE
18
19
24
25
nPulse 1
nPulse 2
nPULSE1
nPULSE2
OUT
I/O
In Normal Mode, these active low signals carry the
transmit data information, encoded in pulse format
as DIPULSE waveform. In Backplane Mode, the
nPULSE1 signal driver is pro grammable (push/pull
or open-drain), while the nPULSE2 sig nal provides
a clock with frequency of doubled data rate.
nPULSE1 is connected to a weak internal pull-up
resistor on the open/drain driver in backplane mode.
20 28 Receive In RXIN IN
This signal carries the receive data information from
the line transceiver.
21 29
nTransmit
Enable nTXEN OUT
Transmission Enable sig na l. Active polarity is
programmable through the nPULSE2 pin.
nPULSE2 floating before power-up;
nTXEN active lo w
nPULSE2 grounded before power-up;
nTXEN active high (this opti on is only availa ble in
Back Plane mode)
16
17 21
22 Crystal
Oscillator XTAL1
XTAL2 IN
OUT An external crystal should be connected to these
pins. Oscillation frequency range is from 10 MHz to
20 MHz. If an external TTL clock is used instead, it
must be connected to XTAL1 with a 390ohm pull-up
resistor, and XTAL2 should be left floating.
15, 28 8, 20,
32, 43 Power
Supply VDD PWR
+3.3 Volt power supply pins.
7, 14,
22 6, 11,
18, 23,
30, 41
Ground VSS PWR
Ground pins.
13 3, 5,
14-17,
19, 27,
33, 35,
38, 40,
42, 47,
48
N/C N/C
Non-connection
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 10 Revision 09-11-06
DATASHEET
Figure 1 - COM20020I 3V Operation
Invitation
to Transmit to
this ID?
YN
Free Buffer
Enquiry to
this ID? SOH?
YN
YN
RI?
Wr it e S ID
to Buffer
DID
=0?
DID
=ID?
Wr i te B uff er
with Packet
CRC
OK?
LENGTH
OK?
DID
=0?
DID
=ID?
SEND ACK
N
Y
N
Y
N
YN
Broadcast
Enabled? N
Y
N
No Activity
for 41
uS?
Y
N
Set NI D=ID
Start Timer:
T=(255-ID)
Activity
On Line? Y
N
T=0?
Set RI
RI?
Transmit
NAK
Transmit
ACK
Set NID=I D
Write ID to
RAM Buffer
Send
Reconfigure
Burst
Power O n
Reconfigure
Timer has
Timed Out
Start
Reconfiguration
Timer (420 mS)*
TA?
Broadcast? Transmit
Free Buffer
Enquiry No
Activity
Pass the
Token
Set TA
Y
N
ACK?
NAK?
1
No
Activity NY
Increment
NID
Send
Packet
Was Packet
Broadcast?
No
Activity
N
ACK? Set TMA
Set TA
x 73 us
for 37.4
us?
for 37 .4
us?
for 37.4
us?
YN
N
Y
YN
NY
N
N
N
N
1
Y
Y
Y
YY
Y
Y
N
Y
Read Node ID
ID refers to th e i dent i ficat ion number of the ID assigned to this node.
NID refers to the next identification number that receives t he token
after this ID passes it.
-
-
-
-
SID refers to the source identific ation.
DID refers to the destination identification.
SOH refers to the start of header character; preceeds all data packets.
-
YN
* Reconfig ti mer is pro gr ammable via setup2 register bit s 1, 0 .
Note - All time values are valid for 5 Mbps.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 11 Revision 09-11-06
DATASHEET
Chapter 4 Protocol Description
4.1 Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network configuration and
management of the network protocol are handled entirely by the COM20020I 3V's internal microcoded sequencer. A
processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the
COM20020I 3 V's interna l RAM buffer, and issuing a command to enable the tran smitter. When the COM20020I 3V next
receives the token, it verifies that the receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message.
If the receiving node transmits an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If
the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge
message and the transmitter passes the token. Once it has been established that the receiving node can accept the
packet and t ransmission is co mplete, the receivi ng node verifies th e packet. If the packet is received successfully, the
receiving node transmits an ACKnowledge message (or nothing if it is not received successfully) allowing the transmitter
to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. An interrupt mask permits
the COM20020I 3V to generate an interrupt to the processor when selected status bits become true. Figure 1 is a flow
chart illustra ting the in ternal opera tion of the COM20020I 3V connected to a 20 MHz crystal oscillator.
4.2 Data Rates
The COM20020I 3V is capable of supporting data rates from 156.25 Kbps to 5 Mbps. The following protocol description
assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled by the internal clock
multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency. Thus all
timeout valu es a re scaled as shown in the follow ing table:
Example: IDLE LINE T i meout @ 5 Mbp s = 41 μs. IDL E LINE Timeout for 156.2 Kbps is 41 μs * 32 = 1.3 ms
INTERNAL
CLOCK
FREQUENCY
CLOCK
PRESCALER
DATA RATE
TIMEOUT SCALING
FACTOR (MULTIPLY BY)
40 MHz Div. by 8 5 Mbps 1
20 MHz Div. by 8
Div. by 16
Div. by 32
Div. by 64
Div. by 128
2.5 Mbps
1.25 Mbps
625 Kbps
312.5 Kbps
156.25 Kbps
2
4
8
16
32
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps
To realize a 5 Mbps network, an external 40 MHz clock must be input. However, since 4 0 MHz is near the frequenc y
of FM radio band, it is not practical for use for noise emission reasons. Therefore, higher frequency clocks are
generated from the 20 MHz crystal as selected through two bits in the Setup2 register, CKUP as shown below. The
selected clock is supplied to the ARCNET controller.
CKUP CLOCK FREQUENCY (DATA RATE)
0 20 MHz (Up to 2.5Mbps) Default (Bypass)
1 40 MHz (Up to 5Mbps)
This clock multiplier is powered-down (bypassed) on default. Af ter changing the CKUP bit, the ARCNET core operation
is stopped and the internal PLL in the clock generator is awakened and it starts to generate the 40 MHz. The lock out
time of the internal PLL is 8uSec typically. After more than 8 μsec (this wait time is defined as 1 msec in this data
sheet), it is necessary to write command da ta '18H' to the command regi ster to re-start the ARCNET core operation.
This clock generator is called “clock multip lier”.
Changing the CKUP bit must be one time or less after releasing hardware reset.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 12 Revision 09-11-06
DATASHEET
The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps.
4.3 Network Reconfiguration
A significant advantage of the COM20020I 3V is its ability to adapt to cha nges on the net work. Whenever a ne w node
is activated or deactivated, a NET WORK RECONFIGURATION is performed. When a n ew COM20020I 3V is turned
on (creating a new active node on the network), or if the COM20020I 3V has not received an INVITATION TO
TRANSMIT for 420mS, or if a software reset occurs, the COM20020I 3V causes a NET WORK RECONFIGURATION
by sending a RECONFIGURE BURST consisting of eight marks and one space repeated 765 times. The pur pose of
this burst is to terminate all activit y on the network. Since this burst is longer than any other type of transmission, the
burst will interfere with the next INVITATION TO TRANSMIT, destroy the token and keep any other node from
assuming control of the line.
When any COM20020I 3V se nses an idle line for greater than 41μS, which occurs only when the toke n Is lost, each
COM20020I 3V starts an internal timeout equal to 73μs times the quantity 255 minus its own ID. The COM20020I 3V
starts network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by
decrementing the destination Nod e ID. If the timeout expires with no line activit y, the COM20020I 3V starts sending
INVITATION TO TRANSMIT with the Destination ID (DID) equal to the currently stored NID. W ithin a given network,
only one COM20020I 3V will timeout (the one with the highest ID number). After sending the INVITATION TO
TRANSMIT, the COM20020I 3V waits for activity on the line. If there is no activity for 37.4μS, the COM20020I 3V
increments the NID value and transmits another INVITATION TO TRANSMIT using the NID equal to the DID. If
activity appears before the 37.4μS timeout expires, the COM20020I 3V releases control of the line. During
NETWORK RECONFIGURATION, INVITATIONS TO TRANSMIT are sent to all NIDs (1-255).
Each COM20020I 3V on the net work will finally hav e saved a NID value equal to the ID of the COM20020I 3V that it
released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO
TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs. When a
node is powered off, the previous node attempts to pass the token to it by issuing an INVITATION TO TRANSMIT.
Since this node does not respon d, the previous node times out and tra nsmits another INVITATION TO TRANSMIT to
an incremented ID and eventually a response will be rece ived.
The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the propagation delay
between nodes, and the highest ID number on the network, but is typically within the range of 12 to 30.5 mS.
4.4 Broadcast Messages
Broadcasting gives a particular node the abilit y to transmit a data packet to all nodes on the network simultaneously.
ID zero is reserved for this feature and no node on the network can be assigned ID zero. To broadcast a message,
the transmitting node's processor simply loads the RAM buffer with the data packet and sets the DID equal to zero.
Figure 4 illustrates the positio n of each byte in the packet with the DID residing at address 0X01 or
Hex of the current page selected in the "Enable Transmit from Page fnn" command. Each individual node has the
ability to ignore broadcast messages by setting the most significa nt bit of the "Enable Receive to Page fnn" command
to a logic "0".
4.5 Extended Timeout Function
There are three timeouts associated with the COM20020I 3V operation. The values of these timeouts are
controlled by bits 3 and 4 of the Configuration Register and bit 5 of the Setup 1 Register.
Response Time
The Respon se T i me determines th e maximum p ropag ation delay allowed be tween any tw o nodes, and shoul d be chosen
to be larger than the round trip propagation delay between the two furthest nodes on the network plus the maximum turn
around time (the ti me it takes a p articular COM20 020I 3V to sta rt sending a message in re sponse to a rece ived message)
which is approximately 6.4 μS. The round trip propagation delay is a function of the transmission media and network
topolog y. For a typic al system usin g RG62 coax in a base band system, a one way cable propagation delay of 15.5 μS
translates to a distance of about 2 miles. The flow chart in Figure 1 uses a value of 37.4uS (15.5 + 15.5 + 6.4) to
determine if any node will respond.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Idle Time
The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 1 illustrates that during a NETWORK
RECONFIGURATION one node will continual ly tran smi t INVITATIONS TO TRANSMIT until it encounters an active nod e .
All other nodes on the network must distinguish between this operation and an entirely idle line. During NETWORK
RECONFIGURATION, activity will appear on the li ne every 41 μS. This 41 μS is equal to the Respo nse T ime of 37.4 μS
plus the time it takes the COM20020I 3V to start retransmitting another message (usually another INVITATION TO
TRANSMIT).
Reconfiguration Time
If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK
RECONFIGURATION. The ET2 and ET1 bits of the Configuration Register allow the network to operate over longer
distances than the 2 miles stated earlier. The logic levels on these bits control the maximum distances over which the
COM20020I 3V can operate by controlling the three timeout values described above. For proper network operation, all
COM20020I 3V's connected to the same network must have the same Response Time, Idle Time, and Reconfiguration
Time.
4.6 Line Protocol
The ARCNET line p rotocol is cons idered isochron ous be cause e ach by te is pre ceded by a start interval and ended w ith a
stop interval. Unlike asynchronous protocols, there is a constant amount of time separating each data byte. On a 5
Mbps network, each byte takes exactly 11 clock intervals of 200ns each. As a result, one byte is transmitted every
2.2uS and the time to transmit a message can be precisely determined. The line idles in a spacing (logic "0") condition.
A logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 100nS duration. A transmission
starts with an ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data characters are then sent,
with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of transmission can
be performed as described below :
Invitations To Transmit
An Invit ation To Transmit is used to pa ss the to ken from one node to a nother and is se n t by the follow ing sequen ce:
An ALERT BURST
An EOT (End Of Transmission: ASCII code 04H)
Two (repeated) DID (Destination ID) characters
ALERT
BURST EOT DID DID
Free Buffer Enquiries
A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the following
sequence:
An ALERT BURST
An ENQ (ENQuiry: ASCII code 85H)
Two (repeated) DID (Destination ID) characters
ALERT
BURST ENQ DID DID
Data Packets
A Data Packet consists of the actual da ta being sent to an other node. It is sent by the following sequence:
An ALERT BURST
An SOH (Start Of Header--ASCII code 01H)
An SID (Source ID) character
Two (repeated) DID (Destination ID) characters
A single COUNT character which is the 2's complement of the number of data bytes to follow if a short packet is sent,
or 00H followed by a COUNT character if a long packet is sent.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 14 Revision 09-11-06
DATASHEET
N data bytes where C OUNT = 256-N (or 512 -N for a long p acket)
T wo CRC (Cyclic Redundancy Check) chara c te rs. The CRC polynomial used is: X16 + X15 + X2 + 1.
A
LERT
BURST SOH SID DID DID COUNT data data CRC CRC
Acknowledgements
An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER
ENQUIRIES and is sent by the follow ing se quence :
An ALERT BURST
An ACK (ACKnowledgement--ASCII co de 86H) characte r
ALERT BURST ACK
Negative Acknowledgement s
A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the
following sequen ce :
An ALERT BURST
A NAK (Negative Acknowledgement--ASC II code 15H ) characte r
ALERT BURST NAK
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Chapter 5 System Description
5.1 Microcontroller Interface
The top halves of Figure 2 and Figure 3 illustrate typical COM20020I 3V interfaces to the microcontrollers. The
interfaces consist of a 8-bit data bus, an address bus and a control bus. In order to support a wide range of
microcontrollers without requiring glue logic and without increasing the number of pins, the COM20020I 3V automatically
detects and adapts to the type of microcontroller being used. Upon hardware reset, the COM20020I 3V first determines
whether the read and write control signals are separate READ and WRITE signals (like the 80XX) or DIRECTION and
DATA ST ROBE (like th e 68XX). To determine the t ype of cont rol signals, the device requires the software to execute at
least one write access to external memory before attempting to access the COM20020I 3V. The device defaults to
80XX-like signals. Once the type of control signals are determi ned, the COM20020I 3V remains in this interface mode
until the next hardware reset occurs. The second determination the COM20020I 3V makes is whether the bus is
multiplexed or non-multiplexed. To determine the type of bus, the device requires the software to write to an odd
memory location followed by a read from an odd location before attempting to access the COM20020I 3V. The signal on
the A0 pin during the odd lo cation a cce ss te ll s the C OM2 0020I 3 V th e ty pe o f bu s. Since multiplexed operation requ ires
A0 to be active low, activity on the A0 line tells the C OM20020I 3V that the bus i s non-multiplexed. The device default s to
multiplexed operation. Both determinations may be made simultaneously by performing a WRITE followed by a READ
operation to an odd location within the COM20020I 3V Address space 20020 registers. Once the type of bus is
determined, the COM2 0020I 3V remain s in this interfa ce mo de until ha rdware re set oc curs.
Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be changed until
hardware reset. Refer to Chapter 3 Description of Pin Functions f or d etail s on the re lated signa ls. All ac cesses to the
internal RAM and the internal registers are controlled by the COM20020I 3V. The internal RAM is accessed via a
pointer-ba sed scheme (refer to the Seq uential Access Memory section), and the internal registers are accessed via direct
addressing. Many peripherals are not fast enough to take advantage of high-speed microcontrollers. Since
microcontrollers do not typically have READY inputs, standard peripherals cannot extend cycles to extend the access
time. The access time of the COM20020I 3V, on the other hand, is so fast that it does not need to limit the speed of the
microcontroller. The COM20020I 3V is designed to be flexib le so tha t it is indepen dent of the micro contro ller spe ed .
The COM20020 I 3V provides for no w ait state arbi tration via di rect addressing to its in ternal registe rs and a pointe r based
addressin g schem e to acc ess its internal RAM. T he point er may be used in auto-increment mode for typical sequential
buffe r emptying or lo ading, or it can be t a ken out o f auto-incremen t mode to perfo rm random ac cesses to the RAM. The
data within th e RAM is access ed through t he data register. Data being read is prefetche d from memory and placed i nto
the data register for the microcontroller to read. It is important to notice that only by writing a new address pointer
(writing to an address pointer low), one obtains the contents of COM20020I 3V internal RAM. Performing only read from
the Data Register does not load new data from the internal RAM. During a write operation, the data is stored in the data
register and then written into memory. Whenever the pointer is loaded for reads with a new value, data is immediately
prefetched to prep are fo r the first read opera tion.
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DATASHEET
Figure 2 - Multiplexed, 8051-Like Bus Interface With RS-485 Interface
AD0-AD7
nINT1
RESET
nRD
nWR
A15
AD0-AD2, D3-D7
nCS
nRESET
nRD/nDS
nWR/DIR
nINTR
A2/BALE
ALE
XTAL1
XTAL2
GND
RXIN
nPULSE1
nPULSE2
nTXEN
8051
COM20022
Differential Driver
Configuration
Media Interface
may be replac ed
with Figure A, B or C.
*
RXIN
nPULSE1
nPULSE2
TXEN
GND
+5V
100 Ohm
BACKPLANE CONFIGURATION
FIGUR E A
RXIN
nPULSE1
FIGURE B
Receiver
HFD3212-002
2
+5V
7
6
Transmitter
HFE4211-014
+5V
3
2 Fiber Interface
(ST Connectors)
2
6
7
NOTE: COM20022 must be in backplane mode
75176B or
Equiv.
A0/nMUX
27 pF 27 pF
XTAL2
XTAL1
20 MHz
XTAL
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Figure 3 - Non-Multiplexed, 6801-L i ke Bus Interface With RS-485 Interface
D0-D7
nIRQ1
nRES
nIOS
R/nW
A7
D0-D7
A0/nMUX
A0
XTAL1
XTAL2
A1
A1
nCS
nRESET
nRD/nDS
nWR/nDIR
nINTR
A2/BALE
A2
RXIN
nPULSE1
nPULSE2
TXEN
GND
Different ial Driv er
Configuration
6801
COM20022
Media Interface
may be replaced
with Figure A, B or C.
*
75176B or
Equiv.
XTAL1 XTAL2
27 pF 27 pF
20MHz
XTAL
RXIN
nPULSE1
nPULSE2
nTXEN
GND
Traditiona l Hy brid
Configuration
RXIN
nPULSE1
nPULSE2
17, 19,
4, 13, 14
5.6K
1/2W
5.6K
1/2W
0.01 uF
1KV
12
11
-5V
0.47
uF 10
uF
+
3
0.47
uF
+
+5V
uF
10
6
FIGURE C
HYC9088
HYC9068 or
N/C
*Valid for 2. 5 M bps only.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 18 Revision 09-11-06
DATASHEET
High Speed CPU Bus Timing Support
High speed CPU bus support was added to the COM20020I 3V. The reasoning behind this is as follows: With the
Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read
signal is active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to
these timings. For example, a RISC type single chip microcontroller (like the HITACHI SuperH series) changes I/O
address at the same time as the read signal. Therefore, several external logic ICs would be required to connect to this
microcontroller.
In addition, the Diagnostic Status (DIAG) register is cleared automatically by readi ng itself. The internal DIAG register
read signal is generated by decoding the Address (A2-A0), Chip Se lect (nCS) and Read (nRD) signals. The decoder
will generate a noise spike at the above tight timing. T he DIAG register is cleared by the spike signal without rea ding
itself. This is unexpected operation. Reading the internal RAM and Next Id Register have the same mechanism as
reading the DIAG register.
Therefore, the address decode and host interface mode blocks were modified to fit the above CPU interface to support
high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address (A2-A0) and Chip Select (nCS)
are sampled internally by Flip-Flops on the falling edge of the internal delayed nRD signal. The internal real read signal
is the more delayed nRD signal. But the rising edge of nRD doesn't delay. By this modification, the internal real
address and Chip Select are stable while the internal real read signal is active. Refer to Figure 4 below.
Figure 4 - High Speed Cpu Bus Timing - Intel CPU Mode
The I/O address and Chi p Select signals, which are supplied to the data output logic, ar e not sampled. Also, the n RD
signal is not delayed, because the above sampling and delaying paths decrease the data access time of the read
cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which generates the
clearing pulse f or the Diagn ostic register a nd generates th e starting pulse of the RAM Arbitration. Typical delay time
between nRD and nRD1 is ar ound 15nS and between nRD1 and nRD2 is around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However , the CPU can insert some wait cycles to
extend the width without any impact on performance.
The RBUSTMG bit was added to Dis able/Enable the Hi gh Speed CPU Read function. It is defined as: RBUSTMG=0,
Disabled (Default); RBUSTMG=1, Enabled.
The BUSTMG pin (TQFP package only) is used to support this function. It is used to Enable/Disable the High Sp eed
CPU Read and Write function. It is defined as: BUSTMG = 0, the High Speed CPU Read and Write operations are
enabled; BUSTMG = 1, the High Speed CPU Read and Write operations are disabled if the RBUSTMG bit is 0. If
BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are enabled (see definition of RBUSTMG bit
below).
A2-A0, nCS
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS
More delayed nRD
(nRD2)
VALID
VALID
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 19 Revision 09-11-06
DATASHEET
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
z For 28-Pin PLCC package (BUSTMG is tied to 1 internally)
RBUSTMG BIT BUS TIMING MODE
0 Normal Speed CPU Read and W r ite
1 High Speed CPU Read and Normal Speed CPU Write
z For 48-Pin TQFP package
BUSTMG PIN RBUSTMG BIT BUS TIMING MODE
0 X High Speed CPU Read and Write
1 0 Normal S peed CPU Read and Write
1 1 High S peed CPU Read and Normal Speed CPU Write
5.2 Transmission Media Interface
The bottom halves of Figure 2 and F igure 3 illustrate the COM200 20I 3V interface to the transmission media used t o
connect the node to the network. Table 1 - Typica l Media lists different types of cable which are suitable for ARCNET
applications. The user may interface to the cable of choice in one of three ways:
Traditional Hybrid Interface
The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid Interface is
recommended if the node is to be placed in a network with other Hybrid-Interfaced nodes. The Traditional Hybrid
Interface i s fo r use w ith node s opera ting at 2.5 Mbps only. The transformer couplin g of th e Hybri d offers isolation for the
safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like
SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20020I 3V. The
COM20020I 3V transmits a logic "1" by genera ting two 100nS non-overlapping negative pulses, nPUL SE1 and n PULSE2.
Lack of pulses i ndic ates a logic "0". Th e nPUL SE1 a nd nPU LSE 2 signa ls are se nt to th e Hybr id, which cr eates a 200nS
dipulse signal on the media.
A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse appearing on the media is
coupled through the RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the
COM20020I 3V. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically,
RXIN pulses occur at multiples of 400nS. The COM20020I 3V can tolerate distortion of plus or minus 100nS and still
correctly capture and convert the RXIN pulses to NRZ format. Figure 5 illustrates the events which occur in
transmission or reception of data consisting of 1, 1, 0.
Please refer to TN7-5 – Cabling Guidelines for the COM20020I 3V ULANC, available from SMSC, for recommended
cabling distan ce , termi nation , and node count fo r ARCNET nodes.
Backplane Configuration
The Backpla ne Open Drain Configuration is recommended for cost-sensitive, short-distance applications like backplanes
and instru men tation. This mode i s advantageo us because it saves comp onents, co st, and power.
Since the Backplane Configuration encodes data differently than the traditional Hybrid Configuration, nodes utilizing the
Backplane Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. The
Backplane Configuration does not isolate the node from the media nor protects it from Common Mode noise, but
Common Mode N oi se i s le ss of a problem i n short distan ces.
The COM20020I 3V supplies a programmable output driver for Backplane Mode operation. A push/pull or open drain
driver can be selected by programming the P1MODE bit of the Setup 1 Register (see register descriptions for details).
The COM200 20I 3V de faults to an open d rai n output.
The Backplane Configuration provides for direct connection between the COM20020I 3V and the media. Only one
pull-up resistor (in open drain configuration of the output driver) is required somewhere on the media (not on each
individual node ). The nPULSE1 signal , in this mode, is an open drain or push/pull dri ver and is used to directly drive the
media. It issues a 200nS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the
COM20020I 3V does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up
resistor. This pull-up sh ould not t a ke the place of the resistor requ ired on the me dia for open drain mo de.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 20 Revision 09-11-06
DATASHEET
Figure 5 - COM20020I 3V Network Us ing RS-485 Differential Tra nsceivers
Figure 6 - Dipulse Waveform For Data Of 1-1-0
20MHZ
CLOCK
(FOR R E F.
ONLY)
nPULSE1
nPULSE2
DIPULSE
RXIN
10
100ns
100ns
200ns
400ns
1
COM20022I 3V COM20022I 3V COM20022I 3V
+VCC
RBIAS +VCC +VCC
RBIAS RBIAS
RT RT
75176B or
Equiv.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 21 Revision 09-11-06
DATASHEET
In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up
resistor .
The RXIN signal is directly connected to the cable via an internal Schmitt trigger . A negative pulse on this input indicates
a logic "1". Lack of pulse indicates a logic "0". For typical single-ended backplane applications, RXIN is connected to
nPULSE1 to ma ke the serial backplane dat a line. A ground line (fro m the coax or twisted pair) sh ould run in p arallel with
the sign al. For a ppl ic atio ns r equ ir i ng d ifferent tr eat me nt of the rece ive signal (like filtering or squelching), nPULSE1 and
RXIN remain as independent pins. External differential drivers/receivers for increased range and common mode noise
rejection, for example , would req uire the signals to be indepen dent of one anothe r.
When the d evice is in Backpl ane Mode, the clock provided by the nPULSE2 signal may be used for enc oding the data
into a differen t en coding scheme o r other synchronous operations need ed on the serial data strea m .
Differential Driver Configuration
The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled configuration
recommended for applications like car-area networks or other cost-sensitive applications which do not require direct
compat ibili ty with ex isting ARCNET nod es and do no t requ ire isola tion.
The Dif ferential Dri ver Configura tion canno t communicate di rectly with node s utilizing the T rad itional Hybrid Configuration .
Like the Backplane Configuration, the Differential Driver Configuration does not isolate the node from the media.
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable and the
COM20020I 3V. The nPULSE1 signal transmits the data, pro vided the T ransmi t Enable signal is active. The nPULSE1
signal issue s a 200nS (at 2 .5Mbps) ne gative pu lse to tra nsmit a l ogic "1". Lack of pul se indicate s a logic "0" . The RXIN
signal receives the data, the transmitter portion of the COM20020I 3V is disabled during reset and the nPULSE1,
nPULSE2 and nTXEN pins are inactive.
Programmable TXEN Polarity
To accommodate transcei vers with ac tive high ENABLE pins, the COM20020I 3 V contai ns a programmable TXEN output.
To program the TXEN pin fo r an active high pulse , the nPU LSE2 p in should be co nnected to grou nd. To ret ain the normal
active low polarity, nPULSE2 should be lef t open . The po larity determin ation is mad e at pow er on reset and is va lid o nly
for Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high polarity is
desired.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Figure 7 - Internal Block Diagram
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
STATUS/
COMMAND
REGISTER
RESET
LOGIC
RECONFIGURATION
TIMER NODE ID
LOGIC
OSCILLATOR
TX/RX
LOGIC
ADDITIONAL
REGISTERS
ADDRESS
DECODING
CIRCUITRY 2K x 8
AD0-AD2,
BUS
ARBITRATION
CIRCUITRY
nPULSE1
nPULSE2
nTXEN
nINTR
nRESET
RAM
A0/nMUX
A1
A2/BALE
nRD/nDS
nWR/DIR
nCS
D3-D7
RXIN
XTAL1
XTAL2
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 23 Revision 09-11-06
DATASHEET
Table 1 - Typica l Media
CABLE TYPE NOMINAL
IMPEDANCE ATTENUATION PER 1000 FT.
AT 5 MHz
RG-62 Be lden #86262 93Ω 5.5dB
RG-59/U Belden #8910 8 75Ω 7.0dB
RG-11 /U Beld en # 89108 75Ω 5.5dB
IBM Type 1* Belden #89688 150Ω 7.0dB
IBM Type 3* Telephone Twisted
Pair Belden #1155A
100Ω
17.9dB
COMCODE 26 AWG Twisted
Pair Part #105-064-703
105Ω
16.0dB
*Non-plenu m-rated cables of this ty pe are also ava ila ble.
Note: For mor e detailed informati on on Cabling opt ions including R S-485, transformer- coupled RS-485 and Fiber Optic
interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020I 3V ULANC, available from Standard
Microsystems Corporation.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Chapter 6 Functional Description
6.1 Microsequencer
The COM20020I 3V contains an internal microsequencer which performs all of the control operations necessary to
carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a progr am counter, two instruction
registers, an instruction decoder, a no-op generator, jump logic, and reconfigurati on logic.
The COM20020I 3V derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks
provide the rate at which the instructions are executed within the COM20020I 3V. The 10 MHz clock is the rate at
which the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed. The
microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers.
One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20020I 3V proceeds to execute the instruction.
When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is
temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is loaded
with the jump address from the ROM. The COM20020I 3V contains an internal reconfiguration timer which interrupts
the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of the
Diagnostic Status Register is set.
Table 2 - Read Register Summary
REGISTER
MSB READ
LSB
ADDR
STATUS RI/TRI X/RI X/TA POR TEST RECON TMA TA/
TTA 00
DIAG.
STATUS MY-RECON DUPID RCV-
ACT TOKEN EXC-N
AK TENTID NEW
NEXT
ID
X 01
ADDRESS
PTR HIGH RD-DATA AUTO-
INC X X X A10 A9 A8
02
ADDRESS
PTR LOW A7 A6 A5 A4 A3 A2 A1 A0
03
DATA D7 D6 D5 D4 D3 D2 D1 D0
04
SUB ADR (R/W)* (R/W)* X X X SUB-AD
2 SUB-
AD1 SUB-A
D0 05
CONFIG-
URATION RESET CCHE
N TXEN ET1 ET2 BACK-P
LANE SUB-
AD1 SUB-A
D0 06
TENTID TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0
07-0
NODE ID NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0
07-1
SETUP1 P1 MODE FOUR
NAKS X RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB 07-2
NEXT ID NXT ID7 NXT
ID6 NXT
ID5 NXT
ID4 NXT
ID3 NXT
ID2 NXT
ID1 NXT
ID0 07-3
SETUP2 RBUS-TMG X X CKUP EF
NO-SYN
C RCN-
TM1 RCM-T
M2 07-4
Note*: (R/W) These bits can be Written or Read. For more information see Appendix C.
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Table 3 - Write Register Summary
ADDR
MSB WRITE
LSB
REGISTER
00 RI/TR1 0 0 0 EXCNAK
RECO
N NEW
NEXTID TA/
TTA INTERRUPT
MASK
01 C7 C6 C5 C4 C3 C2 C1 C0
COMMAND
02 RD-DA
TA AUTO-
INC 0 0 0 A10 A9 A8
ADDRESS
PTR HIGH
03 A7 A6 A5 A4 A3 A2 A1 A0
ADDRESS
PTR LOW
04 D7 D6 D5 D4 D3 D2 D1 D0 DATA
05 (R/W)* (R/W)* 0 0 0 SUB-A
D2 SUB-
AD1 SUB-
AD0 SUBADR
06 RESE
T CCHEN TXEN ET1 ET2 BACK-
PLANE SUB-
AD1 SUB-
AD0 CONFIG-
URATION
07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID
07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID
07-2 P1-MO
DE FOUR
NAKS 0 RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB SETUP1
07-3 0 0 0 0 0 0 0 0 TEST
07-4 RBUS-
TMG 0 0 CKUP EF NO-
SYNC RCN-
TM1 RCN-
TM0 SETUP2
Note*: (R/W) These bits can be Written or Read. For more information see Appendix C.
6.2 INTERNAL REGISTERS
The COM20020 I 3V con tain s 14 in tern al registers. Table 2 and Table 3 illustrate the COM20020I 3V register map. All
undefined b its are read as unde fined and must be written a s logic "0".
Interrupt Mask Re gister (IMR)
The COM20020I 3 V is cap able o f genera ting an interrup t signal when certain sta tus bit s become true . A write to the IMR
specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position
as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular position
enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver Inhibited bit,
New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. No other Status or
Diagnostic Status b it s can gene rate an inte rrup t.
The six maskabl e sta tus bit s are ANDed with thei r respective mask bits , and the result s are OR ed to produce the inte rrupt
signal. An RI or TA int err upt is mas ked when the corr es ponding m ask bit is reset to logic "0", but will reappear when the
corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this time. A
RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when the
"POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading the Next ID Register. The
Interrupt Ma sk Register defaults to the value 000 0 0000 upon hardware reset.
Data Register
This read/ write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is
placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data
Register are un defined upon hard ware res et. In case of RE AD oper ation, the Data Register is loaded with the contents
of COM20020I 3V Inte rn al Memo ry upon writing Address Pointer low only once.
Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly
(please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the
node is on-line to build a network map of those nodes existing on the network. It minimizes the need for operator
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interaction with the network. The node determines the existence of other nodes by placing a Node ID value in the
Tentative ID Register and w aiting to see if the Tenta tive ID bit o f the Diag nostic Status Registe r get s set. The network map
developed by this method is only valid for a short period of time, since nodes may join or depart from the network at any
time. When using the Tentative ID feature, a node cannot detect the existence of the next logical node to which it
passes the token. The Next ID Register will hold the ID value of that node. The Tentative ID Register defaults to the
value 0000 0000 upon hardware reset only.
Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (please
refer to the Configuration Register and SUB ADR Register). The Node ID Register contains the unique value which
identifies this particular node. Each node on the network must have a unique Node ID value at all times. The Duplicate
ID bit of the Diagnostic Status Register helps the user find a unique Node ID. Refer to the Initialization Sequence section
for further detail on the use of the DUPID bit. The core of the COM20020I 3V does not wake up until a Node ID other
than zero is written int o the Node ID Register. During this time, no microcode is executed, no tokens are passed by this
node, and no reconfigurati ons are cause d by this node. Once a n on-zero NodeID is placed into the Node ID Register,
the core wakes up but will not join the network until the TXEN bit of the Configuration Register is set. While the
Transmitter is disabled, the Receiver portion of the device is still functional and will provide the user with useful
informa tion about th e netw ork. The Node ID Register defaul t s to the va lue 0000 0000 upon hardw are rese t only.
Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up accordingly (please
refer to the Configuration Register and SUB ADR Register). The Next ID Register holds the value of the Node ID to which
the COM20020I 3V will pass the token. When used in conjunction with the Tentative ID Register, the Next ID Register
can prov ide a complet e network map. The Next ID Regist er is updat ed each time a node enters/leaves the network or
when a network reconfiguration occurs. Each time the microsequencer updates the Next ID Register, a New Next ID
interrupt is generated. This bit is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware or
software reset.
St atus Register
The COM20020I 3V Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software
compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status
was provided in bits 5 and 6 of the Status Register. In the COM20020I 3V, the COM20020, the COM90C66, and the
COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration
Register. The Status Register contents are defined as in Table 4, but are defined differently during the Command
Chaining operation. Please refer to the Command Chaining section for the definition of the Status Register during
Command Ch aining operati on. The Status Re gister defaults to the value 1XX1 0001 upon either hardware or software
reset.
Diagnostic Status Register
The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network or node
operation. Va rious combinations o f these bits and th e TXEN bit of the Configuration Register represent different situations.
All of these bits, except the Excessive NAcK bit and the New Next ID bit, are reset to logic "0" upon reading the
Diagnostic Status Register or upon software or hardware reset. The EXCNAK bit is reset by the "POR Clear Flags"
command or upon software or hardware reset. The Diagnostic Status Register defaults to the value 0000 000X upon
either hardware or software reset.
Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any combinations of written
data other than those listed in Table 5 are not permitted an d may result in incorrect chip and /o r network operation.
Address Pointer Registers
These read/ write registers are each 8-bits wide and are used for addressing the internal RAM. New pointer addresses
should be written by first writing to the High Register and then writing to the Low Register because writing to the Low
Register loa d s t h e ad dr es s. T he c ontents of th e A ddr ess Po inter High and Low Registers are undefined upon hardware
reset. Writing to Address Pointer low loads the address.
Configuration Register
The Config urat ion Regist er is a re ad/ write register which is us ed to confi gure th e different mo des of the C OM20020I 3 V.
The Configu ration Registe r default s to the val ue 0001 1000 upon hardware reset only. SUBAD0 and SUBAD1 point to the
selection in Register 7.
Sub-Address Register
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The sub-address register is new to the COM20020I 3V, previously a reser ve d regist er. Bits 2, 1 and 0 ar e use d to sele ct
one of the r egisters a ssigned to addres s 7h. S UB AD 1 an d SUBAD0 already exist in the Configuration register on the
COM20020B. They are exactly same as those in the Sub-Address register. If the SUBAD1 and SUBAD0 bits in the
Configuration register are changed, the SUBAD1and SUBAD0 in the Sub-Address register are also changed.
SUBAD2 is a new sub-address bit. It Is used to access the 1 new Set Up register , SETUP2. This register is selected by
setting SUBAD2=1. The SUBAD2 bit is cleared automat ically by writing the Configuration register.
Setup 1 Register
The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (see the
bit definitions of the Configuration Register). The Setup 1 Register allows the user to change the network speed (data
rate) or the arbitration speed independently, invoke the Receive All feature and change the nPULSE1 driver type. The
data rate may be slowed to 156.25Kbps and/or the arbitration speed may be slowed by a factor of two. The Setup 1
Register de faults to the value 000 0 0000 upon hardware re set only.
Setup 2 Register
The Setup 2 Register is new to the COM20020I 3V. It is an 8-bit read/w rite reg ister acce ssed when the Sub Ad dress Bit s
SUBAD[2: 0] are set up acc ordingly (see t he bit defi nitions of the S ub Address Re gister). Th is regi ste r co ntai ns b its for
various functions. The CKUP bit select the clock to be generated from the 20 MHz cryst al. The RBUSTMG bit is used
to Disable/Enable Fast Read function for High S peed CPU bus support. The EF bit is used to enable the new timing for
certain functions in the COM20020I 3V (if EF = 0, the timing is the same as in the COM20020I 3V Rev. B). See
Appendix “A”. The NOSYNC bit is used to enable the NOSYNC function during in itialization. If this bit is reset, the
line has to be idle for the RAM initialization sequence to be written. If set, the line does not have to be idle for the
initialization sequence to be written. See Appendix “A”.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for shorter time
periods has the benefit of shortened network reconfiguration periods. The time periods shown in the table on the
following page are limited by a maximum number of nodes in the network. These time-out period values are for 5Mbps.
For other data rates, scale the time-out period time values accordingly; the maximum node count remains the same.
RCNTM1
RCNTM0 TIME-OUT
PERIOD MAX NODE
COUNT
0 0 420 mS Up to 255 nodes
0 1 105 mS Up to 64 nodes
1 0 52.5 mS Up to 32 n odes
1 1 26.25 mS* Up to 16 nodes*
Note*: The node ID value 255 must e xist i n the network for the 26.25 mS time-out to be valid.
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Tabl e 4 - STATUS REGISTER
BIT BIT NAME SYMBOL DESCRIPTION
7 Receiver
Inhibited RI Thi s bit, if high , indicates that the re ceiver is n ot enabled be cause
either an "Enable Recei ve to Page fnn " command was neve r
issued, or a packet has bee n deposited into the RAM b uffer page
fnn as specified by the last "Enab le Recei ve to Page fnn"
command. No messages will be received until thi s co mmand is
issued, and once the message has been rece ived , the R I bit i s se t,
thereby inhibiting the receiver. The RI bit is cleared by issuing an
"Enable Recei ve to Pa ge fnn " command . This bit, when set, will
cause an interrupt if the corresponding bit of the Interrupt Mask
Register (IMR) is also se t. When this bit is set and another sta tion
attemp ts to se nd a p a ck e t to thi s s t a tio n, thi s station w ill se nd a
NAK.
6,5 (Reserved) These bits are undefined.
4 Power On Reset POR This bit, i f high, indica tes that the COM20020I 3V has been reset by
either a software reset, a hardware reset, or writing 00H to the
Node ID Register. The POR bit is cleared by the "Clear Flags"
command.
3 Test TEST This bit is intende d fo r te st and diagnostic purpo ses. It is a logic
"0" under no rmal operating conditions.
2 Reconfiguration RECON
This bit, i f h igh , indicates th at the Line Idle Timer has timed out
because the RX IN pin w a s idle fo r 41μS. The RECON bit is
cleared during a "Cl ea r Flag s" co mmand. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
The interrupt service routine should consist of examining the
MYRECON bit o f the Diagnostic Sta tu s Re gister to determine
whether there are consecutive reconfigurations caused by this
node.
1
Transmitter
Message
Acknowledged
TMA This bit, if high, indicates that the packet transmitted as a result of
an "Enable Transmit fro m Page fn n" co mmand has been
acknowledged. This bit should o nly be considered valid after the
TA bit (bit 0 ) is set. Broadcast me ssages are ne ver acknow ledged.
The TMA bit is cleared by issuing the "Enable Transmit from Page
fnn" command.
0 Transmitter
Available TA This bit, i f high, indica te s that the transmitter is available for
transmitting. This bit is set when the last byte of scheduled packet
has been transmitted out, or upon execution of a "Disable
T ransmitter" command. The TA bit is cleared by issuing the
"Enable Transmit from Page fnn" co mmand af ter the node next
receives the token. This bit, when set, w ill cause an interrup t if the
corresponding bi t in the IMR is also se t.
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Tabl e 5 - DIAGNOSTIC STATUS REGISTER
BIT BIT NAME SYMBOL DESCRIPTION
7 My
Reconfiguration MY-
RECON This bit, if hig h, indi cat es that a past reconf i gur ati on was c aus e d by
this node. It is set when the Lost Token Timer times out, and
should be typically read following an interrupt caused by RECON.
Refer to the Imp roved Diagnosti cs se ction for fu rthe r det ai l.
6 Duplicate ID DUPID This bit, if high, indicates that the value in the Node ID Register
matches both Destination ID characters of the token and a
response to this token has occurred. Trailing zero's are also
verified. A logic "1" on this bit indicates a duplicate Node ID, thus
the user should write a new value into the Node ID Register . This bit
is only useful for dupl icate ID detection when the devi ce is off line,
that is, when the transmitter is disabled. When the device is on
line thi s bit will be set every time the de vice get s the token. This bit
is reset automatically upon reading the Diagnostic Status Register.
Refer to the Imp roved Diagnosti cs se ction for fu rthe r det ai l.
5 Receive
Activity RCVACT This bit, if high, indicates that data activity (logic "1") was detected
on the RX IN pin of the d evice. Refer to the Improved Diagnostics
section for further detail.
4 Token Seen TOKEN This bit, if high, indicates that a token has been seen on the
network, sent by a node other than this one. Refer to the
Improved Diagnostic sectio n for fu rther de t ail .
3 Excessive NAK EXCNAK
This bit, if high, indicates that either 128 or 4 Negative
Acknowledgements have occurred in response to the Free Buffer
Enquiry. This bit is cleared upon the "POR Clear Flags"
command. Readi ng the Diagnostic Status Register does not clear
this bit. This bit, when set, will cause an interrupt if the
corresponding bit in the IMR is also set. Refer to the Improved
Diagnostics section for further det ail.
2 Tentative ID TENTID This bit, if high, indicates that a response to a token whose DID
matc hes t he valu e in t he Tenta tive ID Register has oc curred. T he
second DID and the trailing zero's are not checked. Since each
node sees every token pa ssed a round the ne tw ork, this feat ure can
be used with the device on-line in order to build and update a
network map. Refer to the Improved Diagnostics section for
further detail.
1 New Next ID NEW
NXTID This bit, if high, indicates that the Next ID Register has been
updated and that a node has either joined or left the network.
Reading the Diagnostic Status Register does not clear this bit. This
bit, when set, will cause an interrupt if the corresponding bit in the
IMR is also set. The bit is cleared by readi ng the Nex t ID Reg iste r.
0 (Rese r ved) This bit i s undefined.
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Tabl e 6 - COMMAND REGIST ER
DATA COMMAND DESCRIPTION
0000 0000 Clear
Transmit
Interrupt
This command is used only in the Command Chaining operation.
Please refer to the Command Chaining section fo r definition of this
command.
0000 0001 Disable
Transmitter This command will cancel any pending transmit command
(transmission that has not yet started) and will set the TA
(T ransmitter Available) status bit to logic "1" when the COM20020I
3V next receives the token.
0000 0010 Disable
Receiver This command will cancel any pending receive command. If the
COM20020I 3V is not yet receiving a packet, the RI (Receiver
Inhibited) bit will be set to logic "1" the next time the token is
received. If packet reception is already underway, reception will
run to it s normal co nclusion .
b0fn n100 Enable
Receive to
Page fnn
This command allows the COM20020I 3V to receive data packets
into RAM buffer page fnn and resets the RI status bit to logic "0".
The values placed in the "nn" bits ind icate the page that the data
will be received into (page 0, 1, 2, or 3). If the value of "f" is a
logic "1", an offset of 256 bytes will be added to that page
specified in "n n", allowing a finer resolut ion of the buffer. Ref er to
the Selecting RAM Page Size section for further detail. If the
value of "b" is logic "1", the device will also receive broadcasts
(transmissions to ID zero). The RI status bit is set to logic "1"
upon successful re cep tion o f a message .
00fn n011 Enable
Transmit from
Page fnn
This command prepares the COM20020I 3V to begin a transmit
sequence from RAM buffer page fnn the next time it receives the
token. The values of the "nn" bits indicate which page to transmit
from (0, 1, 2, or 3). If "f" is logic "1", an offset of 256 bytes is the
start of the page specified in "nn", allowing a finer r esolution of th e
buffer. Refer to the Selecting RAM Page Size section for further
detail. When this command is loaded, the TA and TMA bits are
reset to logic " 0 ". The TA bit is set to logic "1" upon completion of
the transmit sequence. The TMA bit will have been set by this
time if the device has received an ACK from the destination node.
The ACK is strictly hardware level, sent by the receiving node
before its microcontroller is even aware of message reception.
Refer to Figure 1 for details of the transmit sequence and its
relation to the TA and TMA status bits.
0000 c101 Define
Configuration This command defines the maximum length of packets that may
be handled by the device. If "c" is a logic "1", the device handles
both long and short packets. If "c" is a logic "0", the device
handles only short packets.
000r p110 Clear Flags This command rese ts certai n st atus bi ts of the COM20020 I 3V. A
logic "1" on "p" resets the POR status bit and the EXCNAK
Diagnosti c status bit. A logic "1" on "r" resets the RECON status
bit.
0000 1000 Clear
Receive
Interrupt
This command is used only in the Command Chaining operation.
Please refer to the Command Chaining section fo r definition of this
command.
0001 1000 Sta r t In te rna l
Operation This command restarts the stopped internal operation after
changing CKUP bit.
Table 7 - Address Pointer High Register
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BIT BIT NAME SYMBOL DESCRIPTION
7 Read Data RDDATA This bit tells the COM20020I 3V whether the following
access will be a read or write. A logic "1" prepares the
device for a read, a logic "0" prepares it for a write.
6 Auto Increment AUTOINC This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic
increment of th e pointer after each acces s, while a logic "0 "
disables this function. Please refer to the Sequential
Access Memory section for further detail.
5-3 (Reserved) These bits are undefined. They must be 0.
2-0 Address 10-8 A10-A8 These bits hold the upper three address bits which provide
addresses to RAM.
Table 8 - Address Pointer Low Register
BIT BIT NAME SYMBOL DESCRIPTION
7-0 Address 7-0 A7-A0
These bits hold the lower 8 address bits which provide the
addresses to RAM.
Table 9 - SUB ADDRESS REGISTER
BIT BIT NAME SYMBOL DESCRIPTION
7-3 R eserved These bits are un defined. They must be 0 .
2,1,0 Sub Address 2,1,0 SUBAD
2,1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0 0 0 Tentative ID (Same
0 0 1 Node ID as in
0 1 0 Setup 1 Config
0 1 1 Next ID Register)
1 0 0 Setup 2
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
Table 10 - Configuration Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Reset RESET A softwar e reset of t he COM 20020I 3V i s execut ed by writing
a logic "1" to this bit. A software reset does not reset the
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register, and
the Diagnostic Status Register. This bit must be brought
back to logic "0" to release the reset.
6 Command
Chaining Enable CCHEN
This bit, if high, enables the Command Chaining operation of
the device. Please refer to the Command Chaining section
for further details. A low level on this bit ensures software
compatibility with previous SMSC ARCNET devices.
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BIT BIT NAME SYMBOL DESCRIPTION
5 Transmit Enable TXEN When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN
pin inactive. When high, it enables the above signals to be
activated during transmissions. This bit defaults low upon
reset. This bit is typically enabled once the Node ID is
determined, and never disabled during normal operation.
Please refe r to the Improved Diagnostics se ction for det ails on
evaluating network activity.
4,3 Extended
T imeout 1,2 ET1, ET 2 These bits allow the network to operate over longer distances
than the default maximum 2 miles by controlling the
Response, Idle, and Reconfiguration Times. All nodes
should be conf igured with the same timeo ut values for pr oper
network operation. For the COM20020I 3V with a 20 MHz
crystal oscilla tor, the bit co mbina tion s fo llow :
ET2
0
0
1
1
ET1
0
1
0
1
Response
Time (μS)
596.6
298.4
149.2
37.4
Idle Ti me
(μS)
656
328
164
41
Reconfig
Time (mS)
840
840
840
420
Note: These values are for 5Mbps and RCNTMR[1,0]=00.
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
2 Backplane BACK-
PLANE
A logic "1" on this bit puts the device into Backplane Mode
signalin g which is us ed for Open Dr ain and Different ial Driv er
interfaces.
1,0 Sub Address 1,0 SUBAD
1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD1 SUBAD0 Register
0 0 Tentative ID
0 1 Node ID
1 0 Setup 1
1 1 Next ID
See also the Sub Address Register .
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Table 11 - SETUP 1 REGISTER
BIT BIT NAME SYMBOL DESCRIPTION
7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used
in Backplane Mod e. When high, a push/pull output is used.
When low, an open drain output is used. The default is
open drain.
6 Four NACKS FOUR
NACKS This bit, when set, will cause the EXNACK bit in the
Diagnostic Status Register to set after four NACKs to Free
Buffer Enquiry are detected by the COM20020I 3V. This
bit, when reset, will set the EXNACK bit after 128 NACKs to
Free Buffer Enquiry. The default is 128.
5 Reserved Do not set. It must be 0.
4 Receive All RCVALL This bit, when set, allows the COM20020I 3V to receive all
valid data packets on the network, regardless of their
destination ID. This mode can be used to implement a
network monitor wi th the transmi tter on- or off-line. Note that
ACKs are only sent for packets received with a destination
ID equal to the COM20020I 3V's programmed node ID.
This feature can be used to put the COM20020I 3V in a
'listen-only' mode, where the transmitter is disabled and the
COM20020I 3V i s not p a ssing token s. Defaults low.
3,2,1 Clock Pres caler Bits
3,2,1 CKP3,2,1 These bits are used to determine the data rate of the
COM20020I 3V. The following table is for a 20 MHz
crystal: (Clock Multiplier is bypassed)
CKP3
0
0
0
0
1
CKP2
0
0
1
1
0
CKP1
0
1
0
1
0
DIVISOR
8
16
32
64
128
SPEED
2.5Mbs
1.25Mbs
625Kbs
312.5Kbs
156.25Kbs
NOTE: The lowest data rate achievable by the
COM20020I 3V is 156.25Kbs. Defaults to 000 or 2.5Mbs.
For Clock Multiplier output clock speed greater than 20
MHz, CKP3, CKP2 and CKP1 must all be zero.
0 Slow Arbitration
Select SLOW ARB This bit, when set, will divide the arbitration clock by 2.
Memory cycle times will increase when slow arbitration is
selected.
NOTE: For clock multiplier output clock speeds greater
than 40 MHz, SLOW ARB must be set. Defaults to low.
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Table 12 - SETUP 2 REGISTER
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Bus Timing
Select RBUSTMG This bit is used to Disable/Enable the High Speed CPU
Read function for High Speed CPU bus support.
RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable.
That is, if BUSTMG (pin 26: Only for TQF P package) = 1
and RBUSTMG = 1, High Speed CPU Read operations ar e
enabled.
It does not influence write operation. High speed CPU
Read operation is only for non-multiplexed bus.
6,5 Reserved These bit s are undefined. They must be 0.
4 Clock Multiplier CKUP Higher frequency clocks are generated from the 20 MHz
crystal through the selection of these two bits as shown.
This clock multiplier is powered-down on default. After
changing the CKUP bit, the ARCNET core operation is
stopped and the internal PLL in the clock multiplier is
awakened and it starts to generate the 40 MHz. The lock out
time of the internal PLL is 8μSec typically. After 1 mS it is
necessary to write command data '18H' to command
register for re-starting the ARCNET core operation.
CAUTION: Changing the CKUP bit must be one time or less
after releasing a hardware reset.
CKUP Clock Frequency (Data Rate)
0 20 MHz (Up to 2.5Mbps) Default
1 40 MHz (Up to 5Mbps)
Note: After changing the CKUP bit, it is necessary to write a
command data '18H' to the command register. Because
after changing the CKUP bits, the internal operation is
stopped temporarily. The writing of the command is to start
the operation.
These initializing steps are shown below.
1) Hardware reset (Power ON)
2) Change CKUP bit
3) Wait 1mSec (wait until stable oscillation)
4) Write command '18H' (start internal
operation)
5) Start initializing routine (Execute existing
software)
3 Enhanced
Functions EF This bit is used to enable the new enhanced functions in the
COM20020I 3V. EF = 0: Disable (Default), EF = 1: Enable. If
EF = 0, the timing and function is the same as in the
COM20020I, Revision B. See appendix “A”. EF bit must
be ‘1’ if the data rate is over 5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
2 No Synchronous NOSYNC This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Default) The line must
be idle for the RAM initialization sequence to be written.
NOSYNC= 1, Disable:) The line d oes not have to be idle for
the RAM initialization sequenc e to be written. See appendix
“A”.
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BIT BIT NAME SYMBOL DESCRIPTION
1,0 Reconfiguration
T imer 1, 0 RCNTM1,0 These bits are used to program the reconfiguration timer as a
function of maximum node count. These b its set t he t im e ou t
period of the reconfiguration timer as shown below. The time
out periods shown are for 5 Mbps.
RCNTM1 RCNTM0 T ime Out Period Max Node Coun t
0 0 420 mS Up to 25 5 nod es
0 1 105 mS Up to 64 node s
1 0 52.5 mS Up to 32 node s
1 1 26.25 mS* Up to 16 node s
Note*: The node ID value 255 must exist in the network for
26.25 mS timeout to be valid.
Address P ointer Register
Low
2K x 8
RAM
11
D a ta R e gis ter
8
I/O A ddress 04H
I/O Address 03H
11-Bit Counter
Memory
Address Bus
Memory
D ata B us
D0-D7
High
I/O Address 02H
INTERNAL
Figure 8 – Sequential Access Operation
6.3 Internal Ram
The inte gration of the 2K x 8 RAM in the COM20020I 3 V represents signifi cant real estate savings. T he most obvious
benefit is the 48 pin p ackage in w hich the devi ce is now placed (a direct resul t of the integ ration of RAM). In addition , the
PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control
functions which were necessary to interface to the RAM. The integration of RAM represents significant cost savings
because it isolates t he system designer f rom the changing costs of external RAM and it minimizes r eliability problems,
assembly time and costs, and layout complexity.
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Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory, the internal
RAM is indirectly accessed through the Address High and Low Pointe r Registe rs. The data i s channeled to and from the
microcontroller via the 8-bit data register . For example: a packet in the internal RAM buffer is read by the microcontroller
by writing th e corresponding address into the Add ress Pointer High an d Low Registe rs (of fset s 02H and 03 H). Note that
the High Register should be written first, followed by the Low Register, because writing to the Low Register loads the
add ress. At t his p oint t he de vice access es that location an d places the corresp onding data into the d ata register. The
microcontroller then reads the da ta regi ster (of fset 04H) to obtain the data at the specified location. If the Auto Increment
bit is set to logic "1", the device will automatically increment the address and place the next byte of data into the data
register, again to be read by the microcontroller. This process is continued until the entire packet is read out of RAM.
Refer t o Fig ur e 8 for an illustr ation of th e Sequent ial Acces s operat ion. When switching between reads and writes, the
pointer must fi rst be written with the starting address. At least one cycle time should separate the pointer being loaded
and the first read (see timing parameters).
Access Speed
The COM20020I 3V is able to accommodate very fast access c ycles t o its registe rs and buffers. Arbitrati on to the buffer
does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and
stored in a temporary register. Likewise, data to be written is stored in the temporary register and then written to memory.
For systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the
Setup1 Register equal to log ic "1". Since the Slow Arbitration feature divides the inpu t clock by two, the duty cycle of the
input clock may be relaxed.
SOFTWA RE INTERFACE
The microcontroller interfaces to the COM20020I 3V via software by accessing the various registers. These actions are
desc rib ed in t he Int erna l Regi sters sect ion. The softwa re fl ow for acce ssing the data buffer is base d on the Sequential
Access s che me. The basic seq uen ce is as follows:
Disable Interrupts
Write to Pointer Register High (spe cify ing Auto-In crement mode )
Write to Po in ter R egi ster Low (this load s th e addre ss)
Enable Interrupts
Read or Write the Data Reg ister (repeat as many time s as nece ssary to empty or fi ll the buffe r)
The pointer may now be read to determine how many transfers w ere co mpleted .
The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is generally limited to the
initializa tion sequ ence and the main tena nce of the ne twork map .
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the transmit and
receive sequences and to know how the internal RAM buffer is properly set up. The sequence of events that tie these
actions togeth er is discusse d as follow s.
Selecting RAM Page Size
During normal operation, the 2K x 8 of R AM is divided into four pa ges of 51 2 bytes ea ch. The page to be used is specified
in the "Enable T ransmit (Receive) from (to) Page fnn" command, where "nn" specifies page 0, 1, 2, or 3.
This allows the user to have constant control over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set to logic "1", an
offse t o f 256 byte s is a dded to the page speci fied. For exa mple: to transmit from the second hal f of page 0, the co mmand
"Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing 0010 0011 to the Command Register. This
allows a finer resolution of the buffer pages without affecting software compatibility. This scheme is useful for applications
which frequently use packet sizes of 256 bytes or less, especially for microcontroller systems with limited memory
capacity. The remaining portions of the buffer pages which are not allocated for current transmit or receive packets may
be used as temporary storage for previous network data, packets to be sent later, or as extra memory for the system,
which may be indi rectly accessed .
If the device is configured to handle both long and short packets (see "Define Configuration" command), then receive
pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. In
this case, the transmit page s may be made 256 bytes long, lea ving at least 512 bytes free at any given time. Even if the
Command Chaining operation is being used, 512 bytes is still guaranteed to be free because Command Chaining only
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requires two page s for tran smit and two fo r receive (in this case , two 256 byte p ages fo r transmit and two 512 byte page s
for receive, leaving 512 bytes free). Please note that it is the responsibility of software to reserve 512 bytes for each
receive page if the device is configured to handle long packets. The COM20020I 3V does not check page boundaries
during reception. If the device is configured to handle only sh ort pac kets, then bot h transm it and receiv e pages may be
allocate d as 256 bytes long, free ing at lea s t 1KByte at any given time .
Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because Command
Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K
free).
The general rule which may be applied to de termine where i n RAM a page begin s is as follows:
Address = (nn x 512) + (f x 256).
Transmit Sequence
During a tra nsmit sequence, the micro con troller selects a 256 or 512 byte segme n t o f the RAM buffer and w ri te s into it.
The appropriate buffer size is specified in the "Define Configuration" command. When long packets are enabled, the
COM20020I 3V interpre ts the packet as either a long or short packet, depending on whether the bu ffer address 2
contains a zero or non-zero value. The format of the buffer is shown in Figure 9. Address 0 contains the Source
Identifier (SID); Address 1 contains the Destination Identifier (DID); Address 2 (COUNT) contains, for short packets, the
value 256-N, where N represents the number of information bytes in the message, or for long packets, the value 0,
indicating that it is indeed a long p acket. In the latte r case, Address 3 (COUNT) would con tain the value 512-N, where N
represents the number of information bytes in the message.
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Figure 9 – Ram Buffer Packet Configuration
The SID in Address 0 is use d by the receiving node to repl y to the transmitting node. The COM20020I 3V puts the
local ID in this location, therefore it is not necessary to write into this loca tion. Please note that a short packet may
contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes. A
minimum value of 257 exists on a long packet so that the COUNT is expressible in eight bits. This leaves three
exception packet lengt hs which do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes.
If packets of these lengths must be sent, the user must add dummy bytes to the packet in order to make the
packet fit into a long packet.
Once the packet is written into the buffer, the microcontroller awaits a logic "1" on the TA bit, indicating that a previous
transmit command has concluded and another may be issued. Each time the message is loaded and a transmit
command issued, i t will ta ke a variable amoun t of time befo re the me ssag e is tran smitted , depend ing on the tra ffic on the
network and the location of the token at the time the transmit command was issued. The conclusion of the Transmit
Command will generate an interrup t if the In terrupt Mask allow s it. If the device is co nfigured fo r the Command Ch aining
operation, please see the Command Chaining section for further detail on the transmit sequence. Once the TA bit
becomes a logic "1", the microcontroller may issue the "Enable Transmit from Page fnn" command, which resets the TA
and TMA bits to logic "0". If the message is not a BROADCAST, the COM20020I 3V automatically sends a FREE
BUFFER ENQUIRY to the destination node in order to send the message. At this point, one of four possibilities may
SID
DID
COUNT = 256- N
NO T USED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
NO T USED
SID
DID
0
COUNT = 512-N
NO T USED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
SHORT PACKET
FORMAT LONG PACKET
FORMAT
A
DDRESS ADDRESS
0
1
2
COUNT
255
511
N = D ATA PACKET LENG TH
SID = SOURCE ID
DID = DESTINATION ID
(DI D = 0 FOR BROA DCA STS)
0
1
2
COUNT
511
3
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occur.
The first possibility is if a free buffer is available at the destination node, in which case it responds with an
ACKnowledgement. At this point, the C OM20020I 3V fetches the dat a from the T ran smit Buf fer and perfo rms the transmit
seq uenc e. If a s ucc essfu l transmit s equence is complet ed, the TMA bit and the TA bit are s et to logic "1". If th e packet
was not transmitted successfully, TMA will not be set. A successful transmission occurs when the receiving node
responds t o the packet with an ACK. An unsucce ssful transmi ssion occurs when the receiving node does not respond
to the packet.
The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative AcKnowledgement.
A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the token is passed on from the
transmitting node to the next node. The next time the transmitter receives the token, it will again transmit a FREE
BUFFER E N QUIRY. If a NAK is aga in r ece ived , the to ken is agai n passe d onto the next node. The Exce ssive NAK bit
of the Diagnostic Status Register is used to prevent an endless sending of FBE's and NAK's. If no limit of FBE-NAK
sequences existed, the transmitting node would continue issuing a Free Buffer Enquiry, even though it would
continuously receive a NAK as a response. The EXCNAK bit generates an interrupt (if enabled) in order to tell the
microcontroller to disable the transmitter via the "Disable Transmitter" command. This causes the transmission to be
abandoned and the TA bit to be set to a logic "1" when the node next receives the token, while the TMA bit remains at a
logic "0". Please refe r to the Imp roved Diag no stics section fo r furthe r det ai l on the EXCNAK bi t.
The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node does not
respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0". The user should
determine whether th e node should try to reissue the tran smit command .
The fourth pos sibility is if a non-traditio nal response is receiv ed (some pattern othe r than ACK or NAK, su ch as noise).
In this case, the token i s not passed onto the next node, which causes the Lost Token T imer of the nex t node to time out,
thus generating a network reconfiguration.
The "Disable Transmitter" command may be used to cancel any pending transmit command when the COM20020I 3V
next receives the token. Normally, in an active network, this command will set the TA status bit to a logic "1" when the
token is received. If the "Disable Transmitter" command does not cause the TA bit to be set in the time it takes the token
to make a round trip through the network, one of three situations exists. Either the node is disconnected from the
network, or the re are no o ther nodes o n th e netw ork, or th e ex ternal receive circuitry ha s fai led. These situa tions can be
determined by either using the improved diagnostic features of the COM20020I 3V or using another software timeout
which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum
length me ssage.
Receive Sequence
A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous reception has
concluded. The microcontroller will be interrupted if the corresponding bit in the Interrup t Mask Register is set to logic "1".
Otherwise, the microcontroller must periodically check the Status Register. Once the microcontroller is alerted to the
fact that the previous reception has co ncluded, it may issue the "En able Receive to Page fn n" command, which reset s the
RI bit to logic "0" and selects a new page in the RAM buffer. Again, the appropriate buffer size is specified in the "Define
Configu ration" comman d. Typically, the page which just received the data packet will be read by the microcontroller at
this point. Once the "Enable Receive to Page fnn" command is issued, the microcontroller attends to other duties.
There is no way of knowing how long the new reception will take, since another node may transmit a packet at any time.
When another node does transmit a packet to this node, and if the "Define Configuration" command has enabled the
reception of long packets, the COM20020I 3V interprets the packet as either a long or short packet, depending on
whether the co ntent of t he buffer loc ation 2 is zer o or non-z er o. The format of the buffer is shown in Figure 1 0. Addr ess
0 contains the Source Identifier (SID), Address 1 contains the Destination Identifier (DID), and Address 2 contains, for
short packets, the value 256-N, where N represents the message length, or for long packets, the value 0, indicating that it
is indeed a lon g p acket. In the latte r case , Address 3 contains the value 512-N, where N rep resent s the message len gth.
Note that on reception, the COM20020I 3V deposits packets into th e RAM buff er in the same format that the transm itting
node arranges them, which allows for a message to be received and then retransmitted without rearranging any bytes in
the RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the
COM20020I 3V se t s the R I bit to logic "1" to sign al the microcontro lle r tha t the re ception is co mple te .
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Figure 10 - Command Chaining Status Register Queue
6.4 Command Chaining
The Command Chain ing operati on allow s consecu tive transmi ssions and recep tions to occur w ithout host mi crocontroller
intervention.
Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are
pipelined.
In order for the COM20020I 3V to be compatible with previous SMSC ARCNET device drivers, the devi ce defaults to the
non-chaining mode. In order to t ake advant age of the Command Chaini ng opera tion, the Command Cha ining Mode must
be enabled via a logic "1" on bit 6 of the Con figuration Registe r.
In Command Chaining, the Statu s R egi ster appears as i n Figure 10.
The follo wing is a list of Command Ch aining guide lines for the s oftware program mer. Furth er detail can b e found in t he
T ransmit Command Chaining and Receive Command Chaining sections.
The device is designed su ch tha t the inte rru pt service routine l a tency doe s not affect performance.
Up to two outstanding transmissions and two outstanding receptions can be pending at any given time. The
commands may be g iven in any order.
Up to two outstanding transmit inte rrup ts and two outstandi ng receive interrupts are sto red by the device, along with
their respective status bits.
The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Available) for transmit operations and TRI
(Rising Transition of Receiver Inhibited) for receive operations. TTA is set upon completion of a packet
transmission only. TRI is set upon completion of a packet reception only. Typically there is no need to mask the TTA
and TRI bi t s af te r clearing the inte rrupt.
The traditional TA and RI bits are still available to reflect the present status of the device.
Transmit Command Chaining
When the processor issues the first "Enable Transmit to Page fnn" command, the COM20020I 3V responds in the usual
manner by resetting the TA and TMA bits to prepare for the transmission from the specified page. The TA bit can be
used to see i f there is curre ntly a transmission pending, but the TA bit is really meant to be used in the non-chaini ng mode
only. The TTA bits provide the relevant information for the device in the Command Chaining mode.
In the Command Chaining Mode , at any time af ter the fi rst command is issued, the processor can issue a second "Enable
T ransmit from Page fnn" command. The COM20020I 3V stores the fact that the second transmit command was issued,
along with the page number.
After the first transmission is completed, the COM20020I 3V updates the Status Register by setting the TTA bit, which
generat es an i nterru pt. T he interrupt serv ice routine should read the Status Register. At this point, the TTA bit will be
found to be a logic "1" and the TMA (Transmit Message Acknowledge ) bit will tell the processo r whethe r the transmi ssion
was successful. After reading the Status Register, the "Clear Transmit Interrupt" command is issued, thus resetting the
TTA bit and clearing th e interrupt. Not e that only t he "Clear Transmit Interrupt" command will clear the TTA bit and the
interrupt. It is not necessary, however, to clear the bit or the interrupt right away because the status of the transmit
TRI RI TA POR TEST RECON
TMA TTA
TMA TTA
TRI
MSB LSB
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operation is double buffered in order to retain the results of the first transmission for analysis by the processor. This
information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note that the
interrupt will remain active until the command is issued, and the second interrupt will not occur until the first interrupt is
acknowledged. The COM 20020I 3V guarantees a minimum of 2 00nS (at EF=1) interrupt inactive time interval between
interrupts. The TMA bit is also double buffered to reflect whether the appropriate transmission was a success. The
TMA bit should o nly be c onsider ed val id after the c orrespo nding TTA bit has been set to a logic "1". The TMA bit never
causes an interrupt.
When the token is received again, the second transmission will be automatically initiated after the first is completed by
using the stored "Enable Transmit from Page fnn" command. The operation is as if a new "Enable Transmit from Page
fnn" command has just been issued. After the first Transmit status bits are cleared, the Status Register will again be
updated with the results of the second transmission and a second interrupt resulting from the second transmission will
occur. The COM20020I 3V guarantees a minimum of 200ns (at EF=1) interrupt inactive time interval before the
following edge .
The Transmitter Available (TA) bit of the I nterrupt Mask Re gister now mask s only the TTA bit of the Status Register, not
the TA bit as in the n on-chain ing mode. Since the TTA bit i s only se t upon tran smission of a pa cket (n ot by R ESET), and
since the TTA bit may easily be reset by issuing a "Clear Transmit Inte rrupt" command, there is no need to use the TA bit
of the Interrupt Mask Register to mask interrupts generated by the TTA bit of the Status Register.
In Command Chaining mode, the "Disable Transmitter" command will cancel the oldest transmission. This permits
canceling a packet destined for a node not ready to receive. If both packets should be canceled, two "Disable
T ra nsmi tter" commands shou ld be issued.
Receive Comma nd C hai ning
Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable Receive from Page
fnn" commands.
After the first packet is received into the first specified page, the TRI bit of the Status Register will be set to logic "1",
causing an interrupt. Aga in, the interrupt need not be serviced immediately. Typically, the interrupt service routine will
read the Status Register. At this point, the RI bit will be found to be a logic "1". After reading the Status Register, the
"Clear Receive In terrupt" co mmand sho uld be i ssued, th us rese tting the TRI bit and clea ring the inte rrupt. Note that only
the "Clear Receive Interrupt" command will clear the TRI bit and the interrupt. It is not necessary, however, to clear the
bit or the interrupt right away because the status of the receive operation is double buffered in order to retain the results of
the first reception for analysis by the processor , therefore the information will remain in the S tatus Register until the "Clear
Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive Interrupt"
command is issued, and the second interrupt will be stored until the first interrupt is acknowledged. A minimum of
200nS (at EF=1) i n terrupt inacti ve time interval between interrup ts is guaranteed.
The second reception will occur as soon as a second packet is sent to the node, as long as the second "Enable Receive
to Page fnn" c omma nd was issued. The oper ation i s as if a new "Enable Receive to Page fnn" command has just been
issued. After the first Receive status bits are cleared, the Status Register will again be updated with the results of the
second recep tion and a se co nd in te rrupt re sulti ng fro m the second rece p tion w ill occur.
In the COM20020I 3V, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status
Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon reception of a packet (not by
RESET), and since the TRI bit may easily be reset by issuing a "Clear Receive Interrupt" command, there is no need to
use the RI bit of the Interrupt Mask Register to mask interrupts generated by the TRI bit of the Status Register. In
Command Chaining mode, the "Disable Receiver" command will cancel the oldest reception, unless the reception has
already begun . If both receptions sh ould be canceled, two "Disable Receiver" commands should b e issued.
RESET DETAILS
Internal Reset Logic
The COM20020I 3V incl udes speci al reset circuitr y to guarantee sm ooth oper ation during res et. Spec ial care is taken to
assure proper operation in a variety of systems and modes of operation. The COM20020I 3V contains digital filter
circuitry and a Schmitt Trigger on the nRESET signal to rej ect gli tches in order to en sure fau lt-free operat ion.
The COM20020I 3V supports two reset options; software and hardware reset. A software reset is generated when a
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logic "1" is written to bit 7 of the Configuration Register. The device remains in reset as long as this bit is set. The
software reset does not affect the microcontroller interface modes determined after hardware reset, nor does it affect the
contents of the Addr ess Pointer Registers, t he Configuration Register, or th e Setup1 Register. A hard ware reset occurs
when a low signal is asserted on the nRESET input. The minimum reset pulse width is 5TXTL . This pulse width is used
by the internal digital filter , which filters short glitches to allow only valid resets to occur.
Upon reset, the tran smitte r po rtion of the devi ce is disa bled and the internal registers assume those states outlined in the
Internal Regi sters section . Af ter the nR ESET sign al is remo ved the use r may write to the internal registers. Since writing
a non-zero value to the Node ID Register wakes up the COM20020I 3V core, the Setup1 Register should be written
before the Node ID Registe r. Once the Node ID Register is written to, the COM20020 I 3V reads the va lue and execu tes
two write cycles to the RAM buffer. Address 0 is written with the dat a D1H and add ress 1 is w ritten with the Node ID. The
data pattern D1H was chosen arbitrarily, and is meant to provide assurance of prope r microsequencer operation.
6.5 Initialization Sequence
Bus Determination
Writing to and reading from an odd address location from the COM20020I 3V's address space causes the COM20020I
3V to determine the appropriate bus interface. When the COM20020I 3V is powered on the internal registers may be
written to. Since writing a non-zero value to the Node ID Register wakes up the core, the Setup1 Register should be
written to before the Node ID Register. Until a non-zero value is placed into the NID Register , no microcode is executed,
no tokens are passed by this node, and no reconfigurations are generated by this node. Once a non-zero value is
placed in the register, the core wakes up, but the node will not attempt to join the network until the TX Enable bit of the
Configuration Register is set.
Before setting the TX Enable bit, the software may make some determinations. The software may first observe the
Receive Activity and the Token Seen bits of the Diagnostic Status Register to verify the health of the receiver and the
network.
Next, the uniqueness of the Node ID value placed in the Node ID Register is determined. The TX Enable bit should still
be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the Duplicate ID bit of the
Dia gno st ic Sta tu s Re gi st er i s s et aft er a m axi mu m of 42 0mS (o r 8 40mS if the ET1 and ET2 bits ar e other than 1,1). To
determine if another node on the network already has this ID, the COM20020I 3V compares the value in the Node ID
Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status
Register is read, the DUPID bit is cleared. The user may then attempt a new ID value, wait 420mS before checking the
Duplicate ID bit, and repeat the process until a unique Node ID is found. At this point, the TX Enable bit may be set to
allow the n ode to join t he net work. Once the node joins t he net work, a recon figurat ion occur s, as usual, t hus setti ng the
MYRECON bit of th e Di agnostic Status Register.
The Tentative ID Register may be used to build a network map of all the nodes on the network, even once the
COM20020I 3V has joined the network. Once a value is placed in th e Tentative ID Register, the COM20020I 3V looks
for a response to a tok en whose DID matches the Tentative ID Register. The soft ware can record this information and
continue p lacing Tentative ID values into the regi ster to cont inue bui lding the network map. A complete network map is
only valid until nodes are added to or deleted from the network. Note that a node cannot de tect th e exi ste nce of t he ne x t
logical node o n the net work wh en using the Tentative ID. To determi ne the next logical node, the software should read
the Next ID Register .
6.6 Improved Diagnostics
The COM20020I 3V allows the user to better manage the operation of the network through the use of the internal
Diagnostic Status Register.
A high l evel on the My Reconf iguration (MYR ECON) bit indicates t hat the Token Rece ption Tim er of this node expired,
causing a reconfiguration by this node. After the Reconfiguration (RECON) bit of the Status Register interrupts the
microcontroller, the interrupt service routine will typically read the MYRECON bit of the Diagnostic Status Register.
Reading the Diagnostic Status Register resets the MYRECON bit. Successive occurrences of a logic "1" on the
MYRECON bit indicates that a problem exists with this node. At that point, the transmitter should be disabled so that the
entire netw ork is not held down w hile the node is being evaluate d .
The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with the same ID
does not exist on the network. Once it is determined that the ID in the Node ID Register is unique, the software should
write a l ogic "1" to bit 5 of t he Confi guration Register to enable th e basic transmit function. This allows the node to join
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 43 Revision 09-11-06
DATASHEET
the network.
The Receive Activity (RCVACT ) bit of the Diagnostic Status Register will be set to a logic "1" whenever activity (logic "1")
is detected on the RXIN pin.
The Token Seen (TOKEN) bit is set to a logic "1" whenever any token has been seen on the network (except those
tokens transmi tted by this node).
The RCVACT and TOKEN bits may help the user to troubleshoot the network or the node. If unusual event s are occurring
on the network, the user may find it valuable to use the TXEN bit of the Configuration Register to qualify events.
Diff eren t combinations of the RCVACT, TOKEN, and TXEN bits, as show n indicate different situations:
Normal Results:
RCVACT=1, TOKEN=1, T XEN=0: The no de is not part of the network. The net work is oper ating properly without t his
node.
RCVACT=1, TOKEN=1, TXEN=1: The node sees receive activity and sees the token. The basic transmit function is
enabled. Network and node are operating properly.
MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOKEN=1: Single node netw ork.
Abnormal Result s:
RCVACT=1, TOKEN=0, TXEN=X: T he node sees receive activity, but does not see the token. Either no other nodes
exist on the network, some type of data corruption exists, the media driver is malfunctioning, the topology is set up
incorrectly, there is noise on the network, or a reconfiguration is occurring.
RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled. The
transmitter and/or receiver are not functioning properly.
RCVACT=0, TOKEN=0, TXEN=0: No receive acti vity and basic transmit function disabled . This n ode is no t connected
to the netw ork.
The Excessive NAK (EXCNAK) bit is used to replace a timeout function traditionally implemented in software. This
function is necessary to limit the number of times a sender issues a FBE to a node with no available buffer. When the
destination node replies to 128 FBEs with 128 NAKs or 4 FBEs with 4 NAKs, the EXCNAK bit of the sender is set,
generating an interrupt. At this point the software may abandon the transmission via the "Disable Transmitter"
command. This sets the TA bit to logic "1" when the node next receives the token, to allow a different transmission to
occur. The timeout value for the EXNACK bit (128 or 4) is determined by the FOUR-NAKS bit on the Setup1 Register.
The user may choose to wait for more NAK's before disabling the transmitter by taking advantage of the wraparound
counter of the EXCNAK bit. When the EXCNAK bit goes high, indicating 128 or 4 NAKs, the "POR Clear Flags"
comm and ma ybe is sued t o rese t the b it so th at it will go h igh ag ain after an other count of 128 or 4. The software may
count the number of times the EXCNAK bit goes high, and once the final count is reached, the "Disable Transmitter"
command may be i ssued .
The New Nex t ID bi t permi t s the software to dete ct the withd raw al or addi tion of nodes to the network.
The Tentative ID bit allow s the user to build a netw ork map of those nodes existing on the network. This feature is useful
because it minimizes the need for human intervention. When a value placed in the Tentative ID Register matches the
Node ID of another node on the network, the TENTID bit is set, telling the software that this NODE ID already exists on
the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID bit to
maintain an updated network map.
OSCILLATOR
The COM20020I 3V contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms
an oscillator.
If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external
resistor is required, since the COM20020I 3V contains an internal resistor. The crysta l must have an accuracy of 0.020%
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
or better. The oscil latio n frequen cy rang e is fro m 10 MHz to 20 MHz.
The crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turned on. The oscillation
frequency must be 20 MHz when the internal clo ck multiplie r is turned on.
The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other
devices.
The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up
resistor is required on XTAL1, while XTAL2 should be left unconnected.
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Chapter 7 Operational Description
7.1 Maximum Guaranteed Ratings*
Operating Temperature Range........................................................................................................................-40oC to +85oC
S torage Temperature Range .........................................................................................................................-55oC to +150oC
Lead Temperature (soldering, 10 seconds).................................................................................................................+325 oC
Positive Voltage o n any pin excep t XTAL1 and XTAL2, with respec t to ground ..........................................................+5.5V
Positive Voltage on XTAL1 and XTAL2 pin, with respect to ground ......................................................................VDD+0.3V
Negative Voltage on any pin, with respect to ground......................................................................................................-0.3V
Maximum VDD ...................................................................................................................................................................+5V
*Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this
specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be excee ded or devic e failure c an result. Some po wer suppli es exhibit voltage spikes or "glitches" on their
output s when the AC power is switch ed on or of f. In addition, volt age transient s on the AC power line may appear on the
DC output. If this possibility exist s it is suggested tha t a clamp circui t be used.
7.2 Dc Electrical Characteristics
VDD=3.3V±5%
TA=-40oC to +85oC
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low Inpu t Voltage 1
(All inputs ex cept XTAL1)
High Inpu t Voltag e 1
(All inputs except XTAL1 )
VIL1
VIH1
-0.3
2.0
0.8
5.5
V
V
TTL Level
Low Inpu t Voltage 2
(XTAL 1 )
High Inpu t Voltag e 2
(XTAL1)
VIL2
VIH2
-0.3
0.8xVDD
0.2xVDD
VDD+0.3
V
V
External Clock Input
Low Output V oltage 1
(nTXEN)
High Outpu t Voltage 1
(nTXEN)
VOL1
VOH1
2.4
0.4
V
V
ISINK=4mA
ISOURCE=-2mA
Low Output V oltage 2
(AD0-AD2, D3-D7, nINTR,
nPULSE1 in Push/Pull
Mode, nPULSE2)
High Outpu t Voltage 2
(AD0-AD2, D3-D7, nINTR,
nPULSE1 in Push/Pull
Mode, nPULSE2)
VOL2
VOH2
2.4
0.4 V
V
ISINK=8mA
ISOURCE=-4mA
Low Output V oltage 3
(nPULSE1 in Open-Drain
Mode)
VOL3 0.4 V ISINK=8mA
Open Drain Driver
Dynamic VDD Supply
Current IDD
40 mA
5 Mbps
All Outpu ts Open
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Input Pull-up Current
(nPULSE1 in Open-Drain
Mode, A1, AD0-AD2,
D3-D7, BUSTMG)
Input Leakage Current
(All inputs except A1,
AD0-AD2, D3-D7,
XTAL1, BUSTMG)
IP
IL
80 200
±10
µA
µA
VIN=0 .0V
VSS < VIN < VDD
CAPACITANCE (TA = 25°C; fC = 1MHz; VDD = 0V)
Output and I/O pins capacitive load specified as follows:
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Input Capacitance CIN 5.0 pF
Output Capacitance 1
(All outputs except
XTAL2)
COUT1
45
pF
Maximum Capacitive
Load which can be
supported by ea ch
output.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
0.4V
AC Measurements are taken at the following points:
Inputs:
2.4V
1.4V 50%
50%
0.4V
2.4V
1.4V
0.8V
Outputs:
2.0V
0.8V
2.0V
Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin.
Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".
t
t
t
t
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Chapter 8 Timing Diagrams
Figure 11 - Multiplexed Bus, 68xx-Like Control Signals; Read Cycle
A
D0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
DIR t9 t10
nDS
t11
t12
t13 t14
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nDS Low to Valid Data
nDS High to Data High Impedance
Cycle Time (nDS Low to Next Time Low)
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
20
10
10
10
15
0
4TARB*
10
10
20
20
60
20
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
MUST BE: RBUSTMG bit = 0
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
PLCC Package: Must be RBUSTMG bit = 0,
TQFP Package: Must be BUSTMG pin = HIGH and RBUSTMG bit =0
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 49 Revision 09-11-06
DATASHEET
Figure 12 - Multiplexed Bus, 80xx-Like Control Signals; Read Cycle
A
D0-AD2, VALID
nCS
t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
nRD t9
t10
nWR t13 t11 t12
Note 3
Note 2
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
nWR to nRD Low
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Address Setup to ALE Lo w
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nRD L ow t o Valid Data
nRD High to Data High Impedance
Cycle Time (nRD Lo w to Next Time Low)
20
10
10
10
15
0
4TARB*
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
MUST BE: RBUSTMG bit = 0
20
20
60
20
20
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore , the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
TARB is the Arbitration Clock P eriod
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
PLCC Package: Must be RBUSTMG bit = 0,
TQFP Package: Must be BUSTMG pin = HIGH and RBUSTMG bit =0
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 50 Revision 09-11-06
DATASHEET
Figure 13 - Multiplexed Bus, 68xx-Like Control Signals; Write Cycle
A
D0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
DIR
t9 t10
Note 2
t8**
nDS
t11
t12
t13 t14
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
20
10
10
10
15
10
4TARB*
10
10
20
20
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
DIR Setup to nDS Active
DIR Hold from nDS Inactive
30
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
Cycle Time (nDS to Next )**
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Note 2:
**
TARB is the Arbitration Cloc k Period
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLO W ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Write cycle for Address P o in ter Lo w Register occurring after an access to
Data Register requires a minimum of 5TARB from the trail ing edge o f nDS to
the leading edge of the next nDS.
PLCC Packa
g
e: Don’t care RBUSTMG bit, TQFP Packa
g
e: Must be BUSTMG
p
in = HIGH
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 51 Revision 09-11-06
DATASHEET
Figure 14 - Multiplexed Bus, 80xx-Like Control Signals; Write Cycle
A
D0-AD2, VALID
nCS t1
t3
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
Note 2
t8**
nWR
t9
t10
nRD t13 t11 t12 t8
Note 3
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
20
10
10
10
15
10
4TARB*
20
20
20
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Set up to AL E Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High 30
ALE High Width
ALE Low Width
nWR Low Width
nWR High Width
nRD to nWR Low
Cycle Time (nWR to Next )**
TARB is the Arbitration Clock Period
TARB is identi cal to Topr if SL OW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, th e cycl e tim e specif i ed in the mi cr o contro ller' s d atash e et
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Note 2:
**
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the ne xt nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a mi nimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
PLCC Packa
g
e: Don’t care RBUSTMG bit, TQFP Packa
g
e: Must be BUSTMG
p
in = HIGH
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 52 Revision 09-11-06
DATASHEET
Figure 15 - Non-Multiplexed Bus, 80xx-L ike Control Signals; Read Cycle
A
0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
15
10
5**
0
nS
nS
nS
nS
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
4TARB*
0
60
20
20
40**
20
nS
nS
nS
nS
nS
nS
CASE 1: RBUSTMG bit = 0
nRD Low Width
nRD High Width
nWR to nRD Low
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
nCS may become active after control becomes act i ve, b u t the a cce ss time (t6)
will now be 45nS m ea sured from the lea ding e dg e of nCS .
**
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Note 2: Read cycle for Address Pointer Low /H igh Registers occurrin g afte r a read from
Data Register requires a minimum of 5TARB from the tr ailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low /H igh Re giste rs occurring a fter a writ e to
Data Register requires a minimum of 5TARB from the tr ailing edge of nWR to the
leading edge of nRD .
**
CASE 1 PLCC Package: Must be RBUSTMG bit = 0,
TQFP Package: Must be BUSTMG pin = HIGH and RBUSTMG bit =0
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Figure 16 - Non-Multiplexed Bus, 80xx-L ike Control Signals; Read Cycle
A
0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
-5
0
-5
0
nS
nS
nS
nS
Address Setup to nRD Active
Addre ss Ho ld from nRD Ina ctive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (n RD L ow to Next Time L ow)
nRD Low to Valid Data
nRD High t o D a ta High Impedance
4TARB*+30
0
100
30
20
60**
20
nS
nS
nS
nS
nS
nS
nRD Low Width
nRD High Width
nWR to nRD Low
CASE 2: RBUSTMG bit = 1
The Microcontroller typically access es the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2.**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Add ress Pointer L ow/High Registers occu rring af ter a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Add r e s s Pointer Low/High Registers oc cu r ring af ter a writ e to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
C
A
SE 2 PLCC Package: Must be RBUSTMG bit = 1,
TQFP Package: Must be BUSTMG pin = LOW or RBUSTMG bit =1
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 54 Revision 09-11-06
DATASHEET
Figure 17 - Non-Multiplexed Bus, 68xx-L ike Control Signals; Read Cycle
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
15
10
5**
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Lo w)
DIR Hold from nDS Inactive 4TARB*
nS
nS
nS
nS
nS
nS
t8 nS
nDS Low to Valid Data 40**
t9
t10
t11
nS
nS
nS
nDS High to Data High Impede nce
nDS Low Width
nDS High Width
20
10
10
0
60
20
CASE 1: RBUS TMG bit = 0
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
nCS may become active after control becomes active, but the access time (t8) will
now be 45n S measured from the le ad ing edge of nCS.
**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clo ck. It depen ds on CKUP1 and CK UP0 bit s
Note 2: Read cycle for Address Pointer Low/High Reg isters occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge o f nDS to
the leading edge of the next nDS.
CASE 1 PLCC Package: Must be RBUSTMG bit = 0,
TQFP Package: Must be BUSTMG pin = HIGH and RBUSTMG bit =0
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 55 Revision 09-11-06
DATASHEET
Figure 18 - Non-Multiplexed Bus, 68xx-L ike Control Signals; Read Cycle
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
-5
0
-5
0
nS
Address Setup to nDS Active
Addre ss Hold from nDS Inactiv e
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS A ctive
Cycle Time (nDS Low to Next Time Lo w)
DIR Hold from nDS Inactive 4TARB*+30
nS
nS
nS
nS
nS
nS
t8 nSnDS Low to Valid Data 60**
t9
t10
t11
nS
nS
nS
nDS High to Data High Impedence
nDS Low Width
nDS High Wid th
20
10
10
0
100
30
CASE 2: RBUSTMG bit = 1
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
** t8 is measured from the latest active (valid) timing among nCS, nDS, A0-A2.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of ope ration clock. It depends on CKUP1 an d CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Regi sters occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
CASE 2 PLCC Package: Must be RBUSTMG bit = 1,
TQFP Package: Must be BUSTMG pin = LOW or RBUSTMG bit =1
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 56 Revision 09-11-06
DATASHEET
Figure 19 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle
Data Hold from nWR High
nWR Low Wid t h
nWR High Width
nRD to nWR Low
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t4
t2
Note 2
nWR
nRD t10 t8 t9 t5
Note 3
t5**
t1
t3
t5
t6
t7
t8
t9
t10
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup to nWR High
min
15
5
10
20
20
20
max
4TARB*
30***
units
nS
nS
nS
nS
nS
nS
nS
nS
t4 nCS Hold from nWR Inactive 0nS
t2 Address Hold from nWR Inactive 10 nS
Cycle Time (nWR to Next )**
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, t he cycle time specified in the mi crocontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitration Clock Period
TARB is iden tica l to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
**
CASE 1 PLCC Package: Don’t care RBUSTMG bit,
TQFP Package: Must be BUSTMG pin = HIGH
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 57 Revision 09-11-06
DATASHEET
Figure 20 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle
Data Hold from nWR High
nWR Low Wid t h
nWR High Width
nRD to nWR Low
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t4
t2
Note 2
nWR
nRD t10 t8 t9 t5
Note 3
t5**
t1
t3
t5
t6
t7
t8
t9
t10
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup to nWR High
min
15
5
10
20
20
20
max
4TARB*
30***
units
nS
nS
nS
nS
nS
nS
nS
nS
t4 nCS Hold from nWR Inactive 0nS
t2 Address Hold from nWR Inactive 10 nS
Cycle Time (nWR to Next )**
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, t he cycle time specified in the mi crocontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitration Clock Period
TARB is iden tica l to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
**
0
0
0
0
4TARB *
30
10
65
30
20
CASE 2 PLCC Packa
g
e: Not su
pp
orted
,
TQFP Packa
g
e: Must be BUSTMG
p
in = LOW
C
A
S
E 2 is su
pp
orted
f
or T
Q
FP Packa
g
e
O
NLY
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 58 Revision 09-11-06
DATASHEET
Figure 21 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t10
t4
t2
Note 2
t5
DIR
t7
nDS t11
t6
t6**
Parameter min max units
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inact ive
DIR Setup to nDS Active
Cycle Time (nDS to Next Time )**
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
nDS Low Width
nDS High Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
15
10
5
0
10
4TARB*
10
30***
10
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
***: nCS may become active after control becomes active, bu t th e data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available .
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
**Note 2: Any cycle occu rring after a writ e to the Add r ess Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the leading edge
of the ne xt nDS.
Write cycle for Addr ess Pointer Low Reg isters occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
CASE 1 PLCC Package: Don’t care RBUSTMG bit, TQFP Package: Must be BUSTMG pin = HIGH
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 59 Revision 09-11-06
DATASHEET
Figure 22 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t10
t4
t2
Note 2
t5
DIR
t7
nDS t11
t6
t6**
Parameter min max units
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS to Next Time )**
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
nDS Low Width
nDS High Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
15
10
5
0
10
4TARB*
10
30***
10
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
***: nCS may become active after control becomes active, b u t the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available .
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
**Note 2: Any cycle occu rring after a writ e to the Add r ess Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the lead i ng edge
of the ne xt nDS.
Write cycle for Addr ess Pointer Low Reg isters occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
0
0
0
0
10
4TARB *
10
30
10
65
30
CASE 2 PLCC Packa
g
e: Not su
pp
orted
,
TQFP Packa
g
e: Must be BUSTMG
p
in = LOW
C
A
S
E 2 is su
pp
orted
f
or T
Q
FP Packa
g
e
O
NLY
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 60 Revision 09-11-06
DATASHEET
Figure 23 – Normal Mode Transmit Or Receive Timing
(These signals are to and from the hybrid)
nPULSE2
t1
t3
t7
t8
Parameter
nPULSE1, nPULSE2 Pulse Width
nPULSE1, nPU LSE2 Over lap
RXIN Period
RXIN Inactive Pulse Width
min
100
-10
max units
nS
nS
nPULSE1
t1
t6 RXIN Active Pulse Width
t2
t2 nPULSE1, nPU LSE2 Period nS
t1
t3
400
0+10
typ
RXIN
t6
t7
10 400
nTXEN
nS
nS
t2
t4 t5
LAST BIT
(400 nS BIT TIME)
t4 nTXEN Low to nPULSE1 Low 850 950 nS
t5 Beginn i ng of Last Bit Time t o nTXEN High 250 350 nS
100
t8
20 nS
Note: Use Only 2.5 Mbps
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 61 Revision 09-11-06
DATASHEET
Figure 24 – Backplane Mod e T ran smit or Receive Timing
(THESE SIGNALS ARE TO AND FROM THE DIFFERENTIAL DRIVER OR THE CABLE)
nPULSE1 t2 t3
RXIN t10
t11
nPULSE2 t5 t6
(Internal Clk)
t4
Parameter min typ max units
t2
t3
t4
t5
t6
t7
t8
t10
t11
t12
nPULSE1 Pulse Width
nPULSE1 Pe riod
nPULSE2 Low to nPULSE 1 Low
nPULSE2 High Time
nPULSE2 Low Time
nPULSE2 Pe riod
nPULSE2 High to nTXEN High
RXIN Active Pulse Width
RXIN Period
nS
nS
nS
nS
nS
nS
nS
nS
nS
200*
400*
100*
100*
200*
200*
400*
50
50
-25
10
t1
t7
nTXEN
t9 t8
LAST BIT
(400 nS BIT TIME)
t1 nPULSE2 High to nTXEN Low -25 50 nS
(First Rising Edge on nPULSE2 after Last Bit Time)
t9 nTXEN Low to first nPULSE1 Low** 650 750 nS
t13
t12
-25
RXIN Inactive Pulse W i dth 20 nS
t13 Beginning Last Bit Time to nTXEN High** 450 nS
Abov e values are f or 2.5 Mbps.
Other Data Rates are shown below.
550
TDR is the Data Rate Period
*t5, t6 = TDR/4
*t2, t7, t10 = TDR/2
*t3, t11 = TDR
**t9 = x TDR +/- 50 nS
7
4
**t13 = x TDR +/- 50 nS
5
4
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 62 Revision 09-11-06
DATASHEET
Figure 25 – TTL Input Timing On XTAL1 Pin
Figure 26 – Reset And Interru pt Timing
t1
Parameter
nRESET Pulse Width***
min max units
nRESET
t1
t2 nINTR High to Next nINTR Low
typ
t2
nINTR
5TXTL
*
EF = 0
EF = 1 TDR**/2
4T
XTL*
Note*: T
XTL is period of external XTAL oscillation frequency.
Note**: T
DR is period of Data Rate (i.e. at 2.5 Mbps, TDR= 400 nS)
Note***: When the po wer is turned on, t1 is measur ed from stable XTAL
oscillation after V DD was over 3V.
t1
t3
Parameter
Input Clock High Time
Input Clock Period*
min
20
50
max units
nS
nS
XTAL1
t1
t4 Input Clock Frequency* 100
t2 Input Clock Low Time nS
t3
20
typ
10
t2
20 MHz
t5 F r e quency Accur acy* -200 200 ppm
Note*: Input clock frequency must be 20 MHz ( 100ppm or better) to use the internal Clock Multiplier.
+
-
t4and t5are applied to crystal oscillaton.
4.0V 1.0V 50% of VDD
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 63 Revision 09-11-06
DATASHEET
Chapter 9 Package Outlines
Figure 27 - 28 Pin PLCC Packag e Dimensions
A
A1
B
B1
C
D
D1
D2
D3
E
F
G
R
.160-.180
.090-.120
.013-.021
.026-.032
.020-.045
.485-.495
.450-.456
.390-.430
.300 REF
.050 BSC
.042-.056
.042-.048
.025-.045
DIM 28L
J .000-.020
NOTES:
All dim e nsions are in inches.
Circle indicatin g pin 1 can appe ar on a to p surfa ce as shown on the drawing o r
right above it on a beve led edge.
1.
2.
PIN NO.
1
GEJ
D3
JD1
D
J
B1
B
A
A1
C
D2
F
R
Base
Plane
Seating
Plane
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 64 Revision 09-11-06
DATASHEET
Figure 28 - 48 Pin TQFP Package Outline
MIN NOMINAL MAX REMARK
A ~ ~ 1.6 Overall Package Height
A1 0.05 0.10 0.15 Standoff
A2 1.35 1.40 1.45 Body Thickness
D 8.80 9.00 9.20 X Span
D/2 4.40 4.50 4.60
1/2 X Span Measure from Centerline
D1 6.90 7.00 7.10 X body Size
E 8.80 9.00 9.10 Y Span
E/2 4.40 4.50 4.60
1/2 Y Span Measure from Centerline
E1 6.90 7.00 7.10 Y body Size
H 0.09 ~ 0.20 Lead Frame Thickness
L 0.45 0.60 0.75 Lead Foot Length fro m Cen terline
L1 ~ 1.00 ~ Lead Length
e 0.50 Basic Lead Pitch
θ 0o ~ 7o Lead Foot Angle
W 0.17 ~ 0.27 Lead Width
R1 0.08 ~ ~ Lead Shoulder Radius
R2 0.08 ~ 0.20 Lead Foot Radius
ccc ~ ~ 0.0762 Coplanarity (Assemblers)
ccc ~ ~ 0.08 Coplanarity (Test House)
Note 1: Controlling Unit: millimeter
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 65 Revision 09-11-06
DATASHEET
Chapter 10 Appendix A
This appendix describes the function of the NOSYNC and EF bits.
NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by enabling or
disabling the SYNC command during initialization. It is defined as foll ows:
NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line has to be idle
for the RAM initialization seq uence to be written, NOSYNC= 1, Disable: the line does not have to be idle for the RAM
initialization sequence to be written.
The following discussion describes the function of this bit:
During initialization, after the CPU writes the Node ID, the COM20020I 3V will write "D1"h data to Address 00 0h and
Node-ID to Address 001h of its internal RAM within 6uS. These values are read as part of the diagnostic test. If the D1
and Node-ID initialization sequence cannot be read, the initialization routine will report it as a device diagnostic failure.
These writes are controlled by a micro-program which sometimes waits if the line is active; SYNC is the micro-program
command that causes the wait. When the micro-program waits, the initial RAM write does not occur, which causes the
diagnostic error. Thus in this case, if the line is not idle, the initializ ation sequence may not be written, which will be
reported as a device diagnostic failure.
However, the initialization sequence and diagnostics of the COM20020I 3V should be independent of the network
status. This is accomplished through some additi onal logic to decode the program counter, enabled by the NOSYNC
bit. When it finds that the micro-program is in the initialization routine, it disables the SYNC comman d. In this case,
the initialization will not be he ld up by the line status.
Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to be written.
EF Bit
The EF bit controls several modifications to internal operation timing and logic. It is defined as follows:
EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the new internal
operation timing (the timing is the same as in the COM20020I Rev. B); EF=1: Enable the new internal operation timing.
The EF bit controls the following timing/logic refinements in the COM20020I 3V:
A) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear T x/Rx interrupt and Clear Flag
command and by reading the Next-ID register. This minimum disable time is changed by the Data Rate. For
example, it is 200 nS at 2.5 Mbps and 100 nS at 5 Mbps. The 100 nS width will be too short to for the Interrupt to be
seen.
Setting the EF bit will change the minimum disable time to always be more than 200 nS even if the Data Rate is 5
Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock
is always less than 20MHz even if the data rate is 5 Mbps.
B) Synchronize the Pre-Scalar Output
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Set-Up register. The
CKP3-1 bits are changed by writing the Set-Up register from outside the CPU. It's not sync hronize d be t ween the CPU
and COM20020I 3V. Thus, changing the CKP3-1 timing does not synchronize with the internal clocks of Pre-Scalar,
and changing CKP3-1 may cause spike noise to appear on the output clock lin e.
Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for synchronizing
the CKP3-1 with Pre-Scalar’s internal clocks.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 66 Revision 09-11-06
DATASHEET
Never change the CKP3-1 when the data rate is over 5 Mbps. They must all be zero.
C) Shorten The Write Interval Time To The Command Register
The COM20020I 3V limits the write interval time for continuous writing to the Command register . The minimum interval
time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μS at the 156.25 Kbps. This 1.6 μS is very long
for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XT AL clock which
is not changed by the data rate, such that the minimum interval time becomes 100 nS.
D) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20020I 3V has a write prohibition p eriod for writing the En able Transmit/Receive Commands. This period is
started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by setting the TA/RI bit with
a pulse signal. It is 3.2 μS at 156.25 Kbps. This period may be a problem when using interrupt processing. The
interrupt occurrs when the RI bit returns to High. The CPU writes the next Enable Receive Command to the other page
immediately. In this case, the interval time between the interrupt and writing Command is shorter than 3.2 μS.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the pulse signal for setting the TA/RI bit,
instead of at the start of the pulse. This is illustrated in Figure 29.
Tx/Rx comp leted
TA /R I bit
S e tt in g P u l s e
nINT R pi n
prohibition period
EF=1 Tx/Rx com pleted
TA /R I bit
Setting Pulse
nINT R pi n
EF=0
Figure 29 - Effect Of The EF Bit On The TA/RI Bit
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 67 Revision 09-11-06
DATASHEET
The EF bit also controls the resolution of the following issues from the COM20020I Rev. B:
A) Network MAP Generation
Tentative ID is used for generating the Net work MAP, but it sometimes detects a non-existent node. Every time the
Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an incorrect
network map. It can be avoided b y a carefull y coded software routine, but this requires the pr ogrammer to have de ep
knowledge of how the COM20020I 3V works. Duplicate-ID is mainly used for generating the Network MAP. This has
the same issue as Tentative-ID.
A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when the
COM20020I 3V detects a write operation to Tentative-ID or Node-ID register. With this change, programmers can use
the Tentative-ID or Duplicate-ID for generati ng the net work MAP without any issues. This change is Enabled/Disabled
by the EF bit.
B) Mask Register Reset
The Mask register is reset by a soft reset in the COM20020I 3V Rev. A, but is not reset in Rev. B. The Mask register is
related to the S tatus and Diagnostic register, so it should be reset by a soft reset. Otherwise, every time the soft reset
happens, the COM20020I 3 V Rev. B generates an unnecessary int errupt since the status bits RI and TA are back to
one by the soft reset.
This is resolved by changing the lo gic to reset the Mask regi ster both b y the hard reset and by the soft reset. The soft
reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration register.
This solution is Enabled/Disabled by the EF bit.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 68 Revision 09-11-06
DATASHEET
Chapter 11 Appendix B
Figure 30 - Example Of Interface Circuit Diagram To ISA Bus
ISA Bus
A
EN
SA15-SA4
SD7-SD0
nIOR
nIOW
SA2-SA0
IRQm
nIOCS16
DRQn
nDACK
TC
nREFRESH
RESETDRV
12
12 bit
Comparators
LS688x2
nG
P P=Q QI/O Address Seeting (DIP Switches)
16 bit Bus
Transceivers
LS245
A
B
DIR nG
3
D7-D0
nRD
nWR
A
2-A0
nINTR
nRESET
nCS
8
3
Schmitt-Trigger Buffe
r
12 COM20020I
8
A
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V Rev.E Page 69 Revision 09-11-06
DATASHEET
Chapter 12 Appendix C
12.1 Software Identification of the COM20020I 3V Rev D and Rev E
In order to properly write software to work with the COM20020I 3V Rev D and E it is nec essary to be able to identify
the different revisions of the part.
To identify the COM20020I 3 V Revision follow the following procedure:
1. Write 0x00 to Register-5
2. Read Register-5 Æ The value read from Register-5 must be 0x00.
3. Write 0xC0 to Register-5
4. Read Register-5*
* If the value read from Register-5 is 0x80 then the part is a COM20020I 3V Rev D
* If the value read from Register-5 is 0xC0 then the part is a COM20020I 3V Rev E
