January 2008 Rev 9 1/62
1
M25PE40
4 Mbit, page-er asable serial Flash memory with
byte alterability, 75 MHz SPI bus , standard pinout
Features
■SPI bus compatible serial interface
■4 Mbit page-erasable Flash memory
■Page size: 256 bytes
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
■Subsector Erase (4 Kbytes)
■Sector Erase (64 Kbytes)
■Bulk Erase (4 Mbits)
■2.7 V to 3.6 V single supply voltage
■75 MHz cloc k rate (maximum)
■Deep Power-down mode 1 µA (typical)
■Electronic signatu re
– JEDEC standard two-byte signature
(8013h)
■Software write pr otection on a 64-Kbyt e sector
basis
■Hardware write prote ction of the m emo ry area
selected using the BP0, BP1 and BP2 bits
■More than 100 000 Write cycles
■More than 20 year data retention
■Packages
– ECOPACK® (RoHS compliant)
VFQFPN8 (MP)
6 × 5 mm (MLP8)
SO8W (MW) 208 mils
SO8N (MN) 150 mils
www.numonyx.com
Contents M25PE40
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) or Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13
4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.1 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.2 Specific hardware and software protections . . . . . . . . . . . . . . . . . . . . . 15
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
M25PE40 Contents
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6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.4 SR WD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 29
6.8 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.9 Page Wr ite (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.10 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.11 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.12 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.13 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.14 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.15 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.16 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.17 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
List of tables M25PE40
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Software protection truth table (Sectors 0 to 7, 64-Kbyte granularity) . . . . . . . . . . . . . . . . 16
Table 3. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Read Identification (RDID) Data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Protection modes (T9HX process only, see Important note on page 6). . . . . . . . . . . . . . . 27
Table 9. Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 12. Device status after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 13. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 14. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 15. Measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 16. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 17. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 18. DC characteristics (75 MHz operation, T9HX (0.11 µm) process) . . . . . . . . . . . . . . . . . . . 47
Table 19. AC characteristics (25 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 20. AC characteristics (33 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21. AC characteristics (50 MHz operation, T9HX (0.11µm) process). . . . . . . . . . . . . . . . . . . . 50
Table 22. AC characteristics (75 MHz operation, T9HX (0.11µm) process). . . . . . . . . . . . . . . . . . . . 51
Table 23. Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 24. Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 25. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 26. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 57
Table 27. SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data. . . . 58
Table 28. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 29. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M25PE40 List of figures
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List of figures
Figure 1. Logic diagram - previous T7X process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 23
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 25
Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 28
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14. Read Lock Register (RDLR) instruction sequence and data-out sequence. . . . . . . . . . . . 30
Figure 15. Page Write (PW) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Page Erase (PE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. Subsector Erase (SSE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. Release from Deep Power-down (RDP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 25. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 26. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 27. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 28. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 29. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 30. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 31. SO8N – 8 lead plastic small out line , 150 mils body width, pack ag e outlin e . . . . . . . . . . . . 57
Figure 32. SO8W – 8 lead plastic sma ll out line , 20 8 mils bod y wi dt h, pa ck ag e ou tlin e. . . . . . . . . . . . 58
Description M25PE40
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1 Description
The M25PE40 is a 4 Mbit (512Kbit × 8 bit) serial paged Flash memory accessed by a high
speed SPI-compatible bus.
The memory can be written or program med 1 to 256 b ytes at a time, using the P age Write or
Page Program instruction. The Page Write instruction consists of an integrated Page Erase
cycle followed by a Page Program cycle.
The memory is organized as 8 sectors that are further divided up into 16 subsectors each
(128 subsectors in total). Each sector contains 256 pages and each subsect or contains 16
pages. Each page is 256 bytes wide. Thus, the whole memory can be viewe d as consisting
of 2048 pages, or 524,288 bytes.
The memory can be erased a page at a time , usin g the Page Erase instruction, a subsecto r
at a time , using the Subsector Erase instruction, a sector at a time , using the Sector Erase
instruction or as a whole, using the Bulk Erase (BE) instruction.
The memory can be write protected by either hardware or software using a mix of volatile
and non-volatile protection features, depending on the application needs . The protection
granularity is of 64 Kbytes (sector granularity).
Important note
This datasheet details the fun ctionality of the de vices, based on the pr evious T7X pro cess or
based on the current T9HX process (availab le since July 20 07). Delivery of parts operating
with a maximum clock rate of 75 MHz starts from week 8 of 2008.
What are the changes?
The M25PE40 in T9HX process offers the following additional features:
●the whole memory array is partitioned into 4-Kbyte subsectors
●five new instructions: Write Status Register (WRSR), Write to Lock Register (WRLR),
Read Loc k Register (RDLR), 4-Kbyte Subsector Erase (SSE) and Bulk Erase (BE)
●Status Register: 4 bits can be written (BP0, BP1, BP2, SRWD)
●WP input (pin 3): write protection limits are extended, depending on the value of the
BP0, BP1, BP2, SRWD bits. The WP write protection remains the same if bits (BP2,
BP1, BP0) are set to (0, 0, 1)
●smaller die size allowing assembly into an SO8N package.
M25PE40 Description
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Figure 3. VFQFPN and SO connections
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Section 12: Package mechanical for package dimensions, and how to identify pin-1.
Figure 1. Logic diagram - previous T7X
process Figure 2. Logic diagram - new T9HX
process
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
S Chip Select Input
TSL or W(1)
1. In the previous T7X process the pin is a Top Sector Lock input whereas in the new T9HX process, the pin
is a Write Protect input (see Figure 1 and Figure 2).
Top Sector Lock or Write Protect Input
Reset Reset Input
VCC Supply voltage
VSS Ground
Reset
AI09704C
S
VCC
M25PE40
VSS
TSL
Q
C
D
Reset
AI13781
S
VCC
M25PE40
VSS
W
Q
C
D
1
AI09703d
2
3
4
8
7
6
5DVSS C
ResetQ
SV
CC
TSL or W
M25PE40
Signal description M25PE40
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2 Signal description
2.1 Serial Data output (Q)
This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is desel ected and Serial Data outpu t (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5 Reset (Reset)
The Reset (Reset) input provides a har dware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mod e. When
Reset (Reset) is driv en Low, the memory will enter the Reset mode. In this mode, the output
is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will aff e ct this operation
(writ e, program or erase cycle) and da ta may be lost.
M25PE40 Signal description
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2.6 Write Protect (W) or Top Sector Lock (TSL)
●The Write Protect function is available in the T9HX process only (see Impor tant
note on page 6).
The Write Protect (W) input is used to freeze the size of the area of memory that is
protected against write, program and erase instructions (as specified by the values in
the BP2, BP1 and BP0 bits of the Stat us Register. See Section 6.4: Read Status
Register (RDSR) for a description of these bits.
●The Top Sector Lock function is available in the T7X process only (see Important
note on page 6).
The input signal sets the device in the Hardware Protected mode, when Top Sector
Loc k (TSL) is connected to VSS, causing the top 256 pages (upper addresses) of the
memory to become read-only (protected f rom write, program and erase operations).
When Top Sector Lock (TSL) is connected to VCC, the top 256 pages of memory
behave like the other pages of memory.
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
SPI modes M25PE40
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3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two follo wing modes:
●CPOL=0, CPHA=0
●CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the f alling edge of Serial Clock (C).
The difference betw een t he t w o mod es, as shown in Figure 5, is the clock polarity when the
bus mast er is in Standby mode and not transferring data:
●C remains at 0 for (CPOL=0, CPHA=0)
●C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus master and memory devices on the SPI bus
1. The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.
Figure 4 shows a n examp le of three de vices connected t o an MCU , on an SPI bus . Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance . Resistors R (represented in Figure 4) ensure
that the M25PE40 is not selected if the Bus Master leaves the S line in the high impedance
state . As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so tha t, when all inputs/output s become high
impedance, the S line is pulled High while the C line is pulled Lo w ( thus ensuring that S a nd
C do not become High at the same time , and so, that the tSHCH requirement is met). The
typical v alue of R is 100 kΩ, assuming th at the tim e const an t R*C p (Cp = parasitic
capacitance of the bus line) is shorter than t he time during which the Bus Ma ster leaves the
SPI bus in high impe dance.
AI13558b
SPI Bus Master
SPI memory
device
SDO
SDI
SCK
CQD
S
SPI memory
device
CQD
S
SPI memory
device
CQD
S
CS3 CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
or
TSL
Reset W
or
TSL
Reset W
or
TSL
Reset
RRR
VCC
VCC VCC VCC
VSS
VSS VSS VSS
R
M25PE40 SPI modes
11/62
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must en sure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 5. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M25PE40
12/62
4 Operating features
4.1 Sharing the overhead of modifying data
To write or program one (or more) data bytes, two instructions are required: Write Enable
(WREN), which is one b yte , and a Page Write (PW) or Page Progr am (PP) sequence , wh ich
consists of f our by tes plus data. This is f ollo w ed b y the internal cycle (of duration t PW or tPP).
To share this overhead, the Page Write (PW) or Page Progr am (PP) in struction allows up to
256 b ytes to be prog rammed (c hanging bits from 1 t o 0) or written (changing b its to 0 or 1) a t
a time, provided that they lie in consecutive addresses on the same page of memory.
4.2 An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
The Page Wr ite (PW) instruction is entered by driving Chip Select (S) Low, and then
transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte,
and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data
bytes are written to the data buffer, starting at the address given in the third address byte
(A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining,
unchanged, bytes of the data buffer are automatically load ed with the values of the
correspond in g bytes of the add re sse d mem o ry page. The addressed me m ory page then
automatically put into an erase cycle. Finally, the addressed memory page is programmed
with the contents of the data buffer.
All of this buffer mana gement is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a b yte-by-byte basis.
F o r op ti mized timings , it is reco mmen de d to us e the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few bytes (see Section 6 .9: Page Write (PW),
Tab le 21: A C characteristics (50 MHz operation, T9 HX (0.11µm) process), and Table 22: AC
characteristics (75 MHz operation, T9HX (0.11µm) process)).
M25PE40 Operating features
13/62
4.3 A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only in volves resetting bits to 0 that had
previously been set to ‘1’.
This might be:
●when the designer is programming the device for the first time
●when the designer knows that the page has already been erased by an earlier Page
Erase (PE) or Sector Erase (SE) inst ruction. This is useful, f or e xamp le, when storing a
fast stream of data, having first performed the erase cycle when time was available
●when the designer knows that the only changes involve resetting bits to ‘0’ that are still
set to ‘1’. When this method is possible, it has the additional a dvantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few bytes (see Section 6.10: Page
Program (PP), Table 21: AC characteristics (50 MHz operat ion, T9HX (0.11µm) process),
and Table 22: AC characteristics (75 MHz operation, T9HX (0.11µm) process)).
4.4 Polling during a Write, Program or Erase cycle
A further improv emen t in the write, progr am or erase t ime can be achie v ed b y not waiting fo r
the w or st case del ay (tPW, tPP
, tPE, or tSE). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
4.5 Reset
An internal Power-on Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the power-on process, and only
driving it High when VCC has reached the correct voltage level, VCC(min).
4.6 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is sele cted, and in the Active Power mode.
When Chip Select (S) is High, the de vice is deselected, b ut could remain in the Activ e Power
mode until all in ternal cycles ha ve completed (Progr am, Erase , Write). The de vice then g oes
in to the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until the Release from Deep Power-down instruction is
executed.
All other instructions are ignored while the d evice is in the Deep Powe r-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Er ase instructions.
Operating features M25PE40
14/62
4.7 Status Register
The Status Regist er conta ins a n umber o f stat us and cont rol bit s that can be rea d or set (a s
appropriate) by using specific instructions. See Section 6.4: Read Status Register (RDSR)
for a detailed description of the Status Reg ister bits.
4.8 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
features the following data protection mechanisms:
4.8.1 Protocol-related protections
●P ow er On Reset and an internal timer (tPUW) can pr ovide protection against inadv ertent
changes while the power supply is outside the operating specif ication.
●Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
●All instructions that modify data m ust be preceded by a Write Enab le (WREN)
instruction to set the Write Enab le Latch (WEL) bit. This bit is retu rned to its rese t st ate
by the following events:
–Power-up
– Reset (Reset) driven Low
– Write Disable (WRDI) instruction completion
– Page Write (PW) instruction completion
– Page Program (PP) instruction completion
– Write to Lock Register (WRLR) instruction completion
– Page Erase (PE) instruction completion
– Subsector Erase (SSE) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
●The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For
the specific cases of Program and Write cycles, the designer should refer to
Section 6.5: Write Status Register (WRSR), Section 6.9: Page Write (PW),
Section 6.10: P age Program (PP), Section 6.12: P age Eras e (PE), Section 6.14: Sector
Erase (SE), Section 6.13: Subsector Erase (SSE), and to Table 12: Device status after
a Reset Low pulse.
●In addition to the low power consumption feature, the Deep Power-down mode offer s
e x tra software pr otect ion f rom in advertent Write, Prog ram and Erase inst ructions wh ile
the device is not in active use.
M25PE40 Operating features
15/62
4.8.2 Specific hardware and software protections
The M25PE40 features a Hardware Protected mode, HPM, and two Software Protected
modes , SPM1 and SPM2 that can be combined to protect the memory array as required.
They are described below:
HPM
●HPM in T7X process (see Important note on page 6):
The Hardware Protected mode (HPM) is entered when Top Sector Lock (TSL) is driven
Low, causing the top 256 pa ges of memory to become read-only. When Top Sector
Loc k (TSL) is drive n High, t he top 2 56 pages of memory behave like the other pages of
memory and the protection depends on the Block Protect bits (see SPM2 below).
●HPM in T9HX process (see Important note on page 6):
The Hardware Protected mode (HPM) is used to write-protect the non-volatile bits of
the Status Register (that is, the Block Protect bits, BP2, BP1 and BP0, and the Status
Register Write Disable bit, SRWD).
HPM is entered by driving the Write Protect (W) signal Low with the SRWD bit set to
High. This additional protection allows the Status Register to be hardware-protected
(see also Section 6.4.4: SRWD bit).
SPM1 and SPM2
●The first Software Protected mode (SPM1) is managed by specific Lock Registers
assigned to each 64-Kbyte sector.
The Loc k Regist ers can be r ead and written using t he Read Lock Register (RDLR) and
Write to Lo ck Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock bit
and the Lock Down bit.
– Write Lock bit:
The Write Lock bit det ermines whether the conten ts of the sect or can be modif ied
(using the Write, Program or Erase instructions). When the Write Lock bit is set to
‘1’, the sector is write protected – any operations that attempt to change the dat a
in the sector will fail. When the Write Lock bit is reset to ‘0’, the sector is not write
protected by the Lock Register, and may be modified.
– Lock Down bit:
The Loc k Down bit p rovides a me chanism f or protect ing softw are data from simple
hacking and malicious attack. When the Lock Down bit is set to ‘1’, fu rther
modification to the Write Lock and Lock Down bits cannot be performed. A reset,
or power-up, is required before changes to these bits can be made. When the
Lock Down bit is reset to ‘0’, the Write Lock and Lo ck Down bits can be changed.
The Write Lock bit and t he Lock Down bit are volatile and their value is reset to ‘0’ after
a power-down or a reset.
Operating features M25PE40
16/62
●The second Software Protected mode (SPM2) uses the Block Protect bits (BP2,
BP1, BP0, see Section 6.4.3)) to allow part of the memory to be configured as read-
only.
Table 2. Software protection truth table (Sectors 0 to 7, 64-Kbyte granularity)
Sector Lock Register
Protectio n st atus
Lock
Down bit Write
Loc k bit
00
Sector unprotected from Program/Erase/Write operations, protection status
reversible
01
Sector protected from Program/Erase/Write operations, protection status
reversible
10
Sector unprotected from Program/Erase/Write operations,
sector protection status cannot be changed except by a reset or power-up.
11
Sector protected from Program/Erase/Write operations,
sector protection status cannot be changed except by a reset or power-up.
Table 3. Protected area sizes
Status Register
content Memory content
BP2
bit BP1
bit BP0
bit Pr otected area Unprotected area
0 0 0 none All sectors(1) (eight sectors: 0 to 7)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect bits (BP2, BP1, BP0)
are 0.
0 0 1 Upper eighth (sector 7) Lower seven-eighths (seven sectors: 0 to 6)
0 1 0
Upper quarter (two sectors: 6 and
7) Lower three-quarters (six sectors: 0 to 5)
0 1 1 Upper half (four sectors: 4 to 7) Lower half (four sectors: 0 to 3)
1 0 0 All sectors (eight sectors: 0 to 7) none
1 0 1 All sectors (eight sectors: 0 to 7) none
1 1 0 All sectors (eight sectors: 0 to 7) none
1 1 1 All sectors (eight sectors: 0 to 7) none
M25PE40 Memory organization
17/62
5 Memory organization
The memory is organized as:
●2048 pages (256 bytes each)
●524,288 bytes (8 bits each)
●128 subsectors (32 Kbits, 4096 bytes each)
●8 sectors (512 Kbits, 65536 bytes each)
Each page can be individually:
– programmed (bits are pr ogramme d fr om 1 to 0)
– erased (bits are erased from 0 to 1)
– written (bits are changed to either 0 or 1)
The device is page or sector erasable (bits are erased fr om 0 to 1).
Table 4. Memory organization
Sector Subsector Address range Sector Subsector Address range
7
127 7F000h 7FFFFh
0
15 0F000h 0FFFFh
...
...
...
...
...
...
112 70000h 70FFFh 4 04000h 04FFFh
6
111 6F000h 6FFFFh 3 03000h 03FFFh
...
...
...
2 02000h 02FFFh
96 60000h 60FFFh 1 01000h 01FFFh
5
95 5F000h 5FFFFh 0 00000h 00FFFh
...
...
...
80 50000h 50FFFh
4
79 4F000h 4FFFFh
...
...
...
64 40000h 40FFFh
3
63 3F000h 3FFFFh
...
...
...
48 30000h 30FFFh
2
47 2F000h 2FFFFh
...
...
...
32 20000h 20FFFh
1
31 1F000h 1FFFFh
...
...
...
16 10000h 10FFFh
Memory organization M25PE40
18/62
Figure 6. Block diagram
1. These features (in gray) are only available in the T7X process.
AI13782
S
TSL or Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 byte
Data Buffer
256 bytes (page size)
X Decoder
Y Decoder
C
D
Q
Status
Register
00000h
7FFFFh
000FFh
Reset
6FFFFh
Top 256 pages can
be made read-only
by using the TSL pin(1)
Whole memory array can
be made read-only
on a 64-Kbyte basis
through the Lock
Registers
W
M25PE40 Instructions
19/62
6 Instructions
All instruct ion s, addresses and dat a are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Cloc k (C ) aft er Ch ip Se lect
(S) is drive n L ow. Then, the one-byte instruction code must be shifte d in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed inTable 5.
Every instruction sequence starts with a one-byte instruction code. Dependin g on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(FAST_READ), Read Status Register (RDSR) or Read to Loc k Register (RDLR) inst ruction,
the shifted-in ins truction sequence is followed by a data-out sequence. Chip Select (S) can
be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), Subsector Erase
(SSE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI),
Write Status Register (WRSR), Write to Lock Register (WRLR), Deep Power-down (DP) or
Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven High
e xactly at a b yte boundary, otherwise the instruction is rejected, and is not ex ecuted. That is,
Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)
being driven Low is an exact multiple of eight.
All attempts to access the memory arra y during a Write cycle, Program cycle or Erase cycle
are ignored, and t he internal Write cycle, Program cycle or Erase cycle continues
unaffected.
Instructions M25PE40
20/62
Table 5. Instruction set
Instruction Description One-byte
instruction code Addr
bytes Dummy
bytes Data
bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR(1) Read Status Register 0000 0101 05h 0 0 1 to ∞
WRLR(1) Write to Lock Register 1110 0101 E5h 3 0 1
WRSR(1)
1. Instruction available only in the T9HX process (see Important note on page 6).
Write Status Register 0000 0001 01h 0 0 1
RDLR Read Lock Register 1110 1000 E8h 3 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PW Page Write 0000 1010 0Ah 3 0 1 to 256
PP Page Program 0000 0010 02h 3 0 1 to 256
PE Page Erase 1101 1011 DBh 3 0 0
SSE(1) Subsector Erase 0010 0000 20h 3 0 0
SE Sector Erase 1101 1000 D8h 3 0 0
BE(1) Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RDP Release from Deep Power-down 1010 1011 ABh 0 0 0
M25PE40 Instructions
21/62
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page
Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.
The Write Enable (WREN) instruction is entered b y d riving Chip Select (S) Lo w, sending the
instruction code, an d then driving Chip Select (S) High.
Figure 7. Write Enable (WREN) instruction sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
Instructions M25PE40
22/62
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable La tch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, an d then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditio ns:
●Power-up
●Write Disable (WRDI) instruction completion
●Page Write (PW) instruction completion
●Page Program (PP) instruction completion
●Write Status Register (WRSR) instruction completion
●Write to Lo ck Register (WRLR) ins truction completion
●Page Erase (PE) instruction completion
●Subsector Erase (SSE) instruction completion
●Sector Erase (SE) instruction completion
●Bulk Erase (BE) instruction completion
Figure 8. Write Disable (WRDI) instruction sequence
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25PE40 Instructions
23/62
6.3 Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned by JEDEC, and has the value 20h for Numonyx. The device identification is
assigned by the device manufacturer, and indicates the memory type in the first byte (80h),
and the memor y capacity of the device in the second byte (13h).
Any Read Id entification (RDID) instruction while an Erase or Pr ogram cycle is in progress , is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standb y Power mode , the de vi ce waits t o be selected, so that it ca n receiv e, decode and
execute instructions.
Figure 9. Read Identification (RDID) instru ction sequence and data-out sequence
Table 6. Read Identification (RDID) Data-out sequence
Manufacturer identification Device identification
Memory type Memory capacity
20h 80h 13h
C
D
S
21 3456789101112131415
Instruction
0
AI06809b
Q
Manufacturer identification
High Impedance
MSB
15 1413 3210
Device identification
MSB
16 17 18 28 29 30 31
Instructions M25PE40
24/62
6.4 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Th e
Status Register may be read at any time, even while a Program, Erase or Write cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In
Progress (WIP) bit before sending a new instruction to the de vice . It is also possible to read
the Status Register continuously, as shown in Figure 10.
The status bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progr ess (WIP) bit indicates whether the memory is busy with a Write, Progr am
or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is
in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to ‘1’ the internal Write Enable Latch is set, when set to ‘0’ the internal Write
Enable Latch is reset and no Write, Program or Erase instruction is accepted.
6.4.3 BP2, BP1, BP0 bits
The Block Protect bits (BP2, BP1, BP0) are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 3) becomes
protected against Page Program (PP), Page Erase (PE), Sector Erase (SE) and Subsector
Erase (SSE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided
that the Hardw are Protected mode has not been set. The Bulk Erase (BE) instruction is
executed if, and only if:
●all Block Protect (BP2, BP1, BP0) bits are 0
●the Lock Register protection bits are not all set (‘1’).
6.4.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with th e Write
Protect (W) signal. When the Status Register Write Disable (SRWD) bit is set to ‘1’, and
Write Protect (W) is driven Low, the non-volatile bits of the Status Register (SRWD, BP2,
BP1, BP0) become read-only bits. In such a state, as the Write Status Register (WRSR)
instruction is no longer accepted for execution, the definition of the size of the Write
Protected area cannot be further modified.
Table 7. Status Register format(1)(2)(3)
1. WEL (Write Enable Latch) and WIP ((Write In Program) are volatile read-only bits (WE L is set and reset by
specific instructions; WIP is automatically set and reset by the internal logic of the device).
2. SRWD = Status Register Write Protect bit; BP0, BP1, BP2 = Block Protect bits.
3. The BP bits and the SRWD bit exist only in the T9HX process.
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
M25PE40 Instructions
25/62
Figure 10. Read Status Register (RDSR) instruction sequence and data-out
sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M25PE40
26/62
6.5 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register.
Note: The Status Register BPi and SRWD bits are a vailable in the M2 5PE40 in t he T9HX process
only. See Important note on pa ge 6 for more details.
Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driv en Hig h after the eighth bit of the d ata b yte has bee n latched in.
If not, the Write Status Register ( WRSR) instruction is not e x e cuted. As soon as Chip Sele ct
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progr ess (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enab le Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allo ws the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 3. The Write Status Register (WRS R) ins truction also allows
the user to set or reset th e Status Register Write Disable (SR WD) bit in accordance with the
Write Protect (W) signal (see Section 6.4.4).
If a Write Status Register (WRSR) instruction is interrupted by a Reset Low pulse, the
internal cycle of the Write Status Register opera tion (whose duratio n is tW) is first completed
(provided that the supply voltage VCC remains within the ope rating range). After that the
device enters the Reset mode (see also Table 12: Device status after a Reset Low pulse
and Table 24: Timings after a Reset Low pulse).
Figure 11. Write Status Register (WRSR) instruction sequence
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register in
0
765432 0
1
MSB
M25PE40 Instructions
27/62
The protection features of the device are summarized in Table 8.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
●If Write Protect (W) is driv en High, it is possible to write to the Status Register pro vided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Lat ch (WEL) bi t has previously been set b y a Write Enab le (WREN)
instruction (attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM2) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protect ed again st da ta mo dific at i on .
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Softwar e Protected mode (SPM2), us ing the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Table 8. Protection modes (T9HX process only, see Important note on page 6)
W
signal SRWD
bit Mode Write protection of the
Status Register
Memory content
Prot ected area (1)
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 3.
Unprotected area(1)
10
Second
software
protected
(SPM2)
Status Register is writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
00
11
01
Hardware
protected
(HPM)
Status Register is
hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
Instructions M25PE40
28/62
6.6 Read Data Bytes (READ)
The de vice is first selected by driving Chip Select (S) Low. The instruction code f or the Read
Data Bytes (READ) instruction is follo wed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase , Progr am or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A19 are Don’t care.
AI03748D
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-bit address
0
MSB
MSB
2
39
Data Out 2
M25PE40 Instructions
29/62
6.7 Read Data Bytes at Higher Speed (FAST_READ)
The de vice is first selected by driving Chip Select (S) Low. The instruction code f or the Read
Data Bytes at Higher Speed (FAST_READ) instruction is f ollo w ed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memo ry contents , at that addre ss, is shif ted out on Serial Data ou tput (Q), each b it
being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continue d indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is ter minated by driving
Chip Select (S) High. Chip Select (S) can be driv en High at an y time during data output. An y
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruc tion seque n ce
and data-out sequence
1. Address bits A23 to A19 are Don’t care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24-bit address
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M25PE40
30/62
6.8 Read Lock Register (RDLR)
Note: The Read Lock Register (RDLR) instruction is decoded only in the M25PE40 in the T9HX
process (see Important note on pa ge 6).
The de vice is first selected by driving Chip Select (S) Low. The instruction code f or the Read
Lock Register (RDLR) instruction is followed by a 3-byte addr ess (A23-A0) pointing to any
location inside the concerned sector (or subsector). Each address bit is latched- in du ring
the rising edge of Serial Clock (C). Then the value of the Lock Re gister is shifted out on
Serial Data output (Q), each bit being shifted out, at a maximum frequency fC, during the
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 14. Read Lock Register (RDLR) instruction sequence and data-out sequence
Table 9. Lock Registers
Bit Bit name Value Function
b7-b4 Reserved
b1 Sector Lock
Down
‘1’ The Write Lock and Lock Down bits cannot be changed. Once a
‘1’ is written to the Lock Down bit it cannot be cleared to ‘0’,
except by a reset or power-up.
‘0’ The Write Lock and Lock Down bits can be changed by writing
new values to them (default value).
b0 Sector Write
Lock
‘1’ Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
‘0’ Write, Program and Erase operations in this sector are e xecuted
and will modify the sector contents (default value).
C
D
AI10783
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 10
High Impedance Lock Register Out
Instruction 24-bit address
0
MSB
MSB
2
39
M25PE40 Instructions
31/62
6.9 Page Write (PW)
The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must pre viously hav e been ex ecuted. After the
Write Enable (WREN) instruction ha s been decoded, the de vice sets th e Write Enable Latch
(WEL).
The Page Wr ite (PW) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address bytes and at least one data byte on Serial Data input (D).
The rest of the page remains unchanged if no power failure occurs during this write cycle.
The Page Write (PW) instruction performs a page erase cycle even if only one b yt e is
updated.
If the 8 least significant addre s s bits (A7 -A0) are no t all zero , all tr a nsmitte d data exceeding
the addressed page boundary roll over, and are written from the start address of the same
page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence .
The instruction sequence is shown in Figure 15.
If more tha n 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data b yt es are guar antee d to be written correctly with in the sa me page . If less than
256 Data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page.
F o r op ti mized timings , it is reco mmen de d to us e the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few b ytes (see Tab le 21: AC char acteristics (50 MHz
operation, T9HX (0.11µm) process) and Table 22: AC characteristics (75 MHz operation,
T9HX (0.11µm) process)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Write (PW) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration
is tPW) is initiated. While the Page Write cycle is in progress, the Status Register may be
read to chec k the v alue of the Write In Prog ress (WIP) bit. The Write In Prog ress (WIP) bit is
1 during the self-timed P age Write cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page that is hardware protected is not executed.
Any Page Write (PW) instr u ct ion, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Instructions M25PE40
32/62
Figure 15. Page Write (PW) instruction sequence
1. Address bits A23 to A19 are Don’t care.
2. 1 ≤ n ≤ 256.
C
D
AI04045
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte n
765432 0
1
MSB MSB
MSB MSB MSB
M25PE40 Instructions
33/62
6.10 Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address b ytes and at least one data byte on Serial Data input ( D).
If the 8 least significant addre s s bits (A7 -A0) are no t all zero , all tr a nsmitte d data exceeding
the addressed page boundary roll over, and are programmed from the start address of the
same page (the one whose 8 least significant a ddress bits (A7-A0) are all z ero). Chip Select
(S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
If more tha n 256 bytes are sent to the device, previously latched data are discarded and the
last 256 dat a bytes ar e guaranteed to be progr ammed corr ectly within the same pag e. If less
than 256 Data bytes are sent to device, they are correctly prog rammed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few bytes (see Table 20: AC
characteristics (33 MHz operation)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed .
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Prog ram cycle is in progre ss, th e Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page that is hardware protected is not
executed.
Any P age Prog ram (PP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Instructions M25PE40
34/62
Figure 16. Page Program (PP) instruction sequence
1. Address bits A23 to A19 are Don’t care.
2. 1 ≤ n ≤ 256.
C
D
AI04044
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte n
765432 0
1
MSB MSB
MSB MSB MSB
M25PE40 Instructions
35/62
6.11 Write to Lock Register (WRLR)
Note: The Write to Lock Regist er (WRLR) instruction is decoded only in th e M25PE40 in the T9HX
process (see Important note on pa ge 6).
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
f ollowed b y the instruction code , three address b ytes (pointing to an y address in the targeted
sector and one data byte on Serial Data input (D). The instruction sequence is shown in
Figure 17. Chip Select (S) must be driv en High aft er the eighth bit of th e data b yt e has been
latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed.
Lock Register bits are volatile, and ther efore do not require time to be written. When the
Write to Lock Regist er (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset aft er a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase, Progr am or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Write to Lock Register (WRL R) instructio n sequence
Table 10 . Lock Register in(1)
1. The table rows in gray are true for products processed in the T7X process only (see Important note on
page 6).
Sector Bit Value
All sectors
b7-b2 ‘0’
b1 Sector Lock Down bit value
b0 Sector Write Lock bit value
AI10784b
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Lock Register
value
39
MSB MSB
Instructions M25PE40
36/62
6.12 Page Erase (PE)
The Page Erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Page Erase (PE) instruction is entered b y driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (D). Any address inside the
page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 18.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self -timed P age Era se cycle (whose duration is tPE) is initiated.
While the Page Erase cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Prog ress (WIP) bit is 1 during the self-
timed Page Erase cycle, and is 0 when it is completed. At some unspecified time bef ore the
cycle is complete, the Write Enable Latch (W EL) bit is reset.
A Page Erase (PE) instruction applied to a page that is hardwar e protected is not executed.
Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 18. Page Erase (PE) instruction sequence
1. Address bits A23 to A19 are Don’t care.
24-bit address
C
D
AI04046
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25PE40 Instructions
37/62
6.13 Subsector Erase (SSE)
Note: The Subsector Erase (SSE) instruction is decoded only in the M25PE40 in the T9HX
process (see Important note on pa ge 6).
The Subsector Er ase (SSE) instruction sets to ‘1’ ( FFh) all bits inside the chos en subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously ha ve been
e x ecuted. After the Write Enable (WREN) instruction has been decoded, the de vice sets th e
Write Enable Latch (WEL).
The Subsector Erase (SE) instruction is entered by driving Chip Select (S) Low, f ollowed by
the instruction code, and three address bytes on Serial Data input (D). Any address inside
the Subsector (see Table 4) is a valid address for the Subsector Erase (SE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 20.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwi se the Sub sector Er ase (SE) instruction is not executed . As soon as Chip
Select (S) is driven High, the self -timed Subsector Erase cycle (whose duration is tSSE) is
initiated. While th e Subsector Era se cycle is in prog ress , the Sta tus Register ma y be re ad to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction applied to a subsector that contains a page that is
hardware or software protected is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
If Reset (Reset ) is driven Low while a Subsector Erase (SSE) cycle is in progress, the
Subsector Erase cycle is inter rupted and data may not be erased correctly (see Table 12:
Device status after a Reset Low pulse). On Reset going Low, the device enters the Rese t
mode and a time of tRHSL is then required before the device can be re-selected by driving
Chip Select (S) Lo w. Fo r the v alue of tRHSL see Tab le 24: Timings after a Reset Lo w pulse in
Section 11: DC and AC parameters.
Figure 19. Subsector Erase (SSE) instruction sequence
1. Address bits A23 to A19 are Don’t care.
24-bit address
C
D
AI12356
S
21 3456789 293031
Instruction
0
23 22 20
1
MSB
Instructions M25PE40
38/62
6.14 Sector Erase (SE)
The Sector Er ase (SE) instruction se ts to ‘1’ (FFh) a ll bits inside t he chosen se ctor. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Lo w, followed by the
instruction code, an d three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 4) is a valid address for the Sector Erase (SE) inst ruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 20.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (S E) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspe cified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector that contains a page that is hardware
protected is not executed.
Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 20. Sector Erase (SE) instruction sequence
1. Address bits A23 to A19 are Don’t care.
24-bit address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25PE40 Instructions
39/62
6.15 Bulk Erase (BE)
Note: The Bulk Erase (BE) instruction is deco ded o nly in the M25PE4 0 in th e T9HX p rocess (see
Important note o n page 6).
The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 21.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progre ss (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
Any Bulk Erase (BE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress. A Bulk Erase (BE)
instruction is ignored if at least one sector or subsector is write-protected (hardware or
software protection).
If Reset (Reset ) is driven Low while a Bulk Erase (BE) cycle is in progress, the Bulk Erase
cycle is interrupted and data may not be erased correctly (see Table 12: Device status after
a Reset Low pulse). On Reset going Low, the device enters the Reset mode and a time of
tRHSL is then required before the device can be re-selected by driving Chip Select (S) Low.
F o r t he value of tRHSL see Table 24: Timings after a Reset Low pulse in Section 11: DC and
AC parameters.
Figure 21. Bulk Erase (BE) instruction sequence
C
D
AI03752D
S
21 345670
Instruction
Instructions M25PE40
40/62
6.16 Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
softwar e protecti on mechanism, wh ile the device is not in active use, since in t his mode , the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the de vice in the Stan dby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Pow er-down mode. The Deep Power-down mode can only be entered by executing the
Deep P o wer-do wn (DP) instruction, subsequently reducing th e standby current (from ICC1 to
ICC2, as specified in Table 17).
Once the device has entered the Deep Power-down mode, all instructions are ignored
e xcept the Release from Deep Power-do wn (RDP) instruction. This releases the de vice from
this mode.
The Deep Power-down mode automatically stops at power-down, and the device always
powers-up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 22.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP bef or e the su pply cu rrent is r educe d
to ICC2 and the Deep Power-down mode is entered.
Any Deep Powe r-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 22. Deep Power-down (DP) instruction sequence
C
D
AI03753D
S
21 345670t
DP
Deep Power-down mode
Standby mode
Instruction
M25PE40 Instructions
41/62
6.17 Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from De ep Power- down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-d own (RDP) instruction is entered b y driving Chip Select (S )
Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 23.
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driv en High, followed b y a de la y, tRDP
, the de vice is put in the
Standb y P ow er mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from De ep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 23. Release from Deep Power-down (RDP) instruction sequence
C
D
AI06807
S
21 345670t
RDP
Standby mode
Deep Power-down mode
QHigh Impedance
Instruction
Power-up and power-down M25PE40
42/62
7 Power-up and power-down
At power-up and power- down, the de vice must not be selected (that is Chip Select (S ) m ust
follow the voltage applied on VCC) until VCC reaches the correct value:
●VCC(min) at power-up, and then for a further delay of tVSL
●VSS at power-down.
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has
elapsed afte r the moment that VCC rises above the VWI threshold. However, the correct
operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No
Write, Program or Erase instructions should be sent until the later of:
●tPUW after VCC passed the VWI threshold
●tVSL after VCC passed the VCC(min) level.
These values are specified in Table 11.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
As an extra pr otection, the Reset (Reset) signal could be driv en Low for the whole duratio n
of the power-up and power-down phases.
At power-up, the de vice is in the following state:
●The device is in the Standby Power mode (not the Deep Power-down mode)
●The Write Enable Latch (WEL) bit is reset
●The Write In Progress (WIP) bit is reset
●The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0).
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each de vice in a system should ha v e the V CC rail decoupled b y a suitab le capacitor close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from th e operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operatio ns are disab led and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in prog ress, some data corruption can result.)
M25PE40 Power-up and power-down
43/62
Figure 24. Power-up timing
Table 11. Power-up timing and VWI threshold
Symbol Parameter Min. Max. Unit
tVSL(1)
1. These parameters are characterized only, over the temperature range –40 °C to +85 °C.
VCC(min) to S low 30 µs
tPUW(1) Time delay before the first Write, Program or Erase instruction 1 10 ms
VWI(1) Write Inhibit voltage 1.5 2.5 V
VCC
AI04009C
VCC(min)
VWI
Reset state
of the
device
Chip selection not allowed
Program, Erase and Write commands are rejected by the device
tVSL
tPUW
time
Read access allowed Device fully
accessible
VCC(max)
Reset M25PE40
44/62
8 Reset
Driving Reset (Reset) Low while an internal operation is in progress will aff e ct this operation
(writ e, program or erase cycle) and da ta may be lost.
All the Lock bits are reset to ‘0’ after a Reset Lo w pulse.
Table 12 shows the status of the device after a Reset Low pulse.
Table 12. Device statu s af te r a Reset Low pulse
Conditions:
Reset pulse occurred Loc k bits status Internal logic
status Addressed data
While decoding an instruction(1): WREN,
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
1. S remains Low while Reset is Low.
Reset to ‘0’ Same as POR Not significant
Under completion of an Erase or Program
cycle of a PW, PP, PE, SSE, SE, BE
operation Reset to ‘0’ Equivalent to
POR Addressed data
could be modified
Under completion of a WRSR operation Reset to ‘0’ Equivalent to
POR (after tW)Write is correctly
completed
Device deselected (S High) and in Standby
mode Reset to ‘0’ Same as POR Not significant
M25PE40 Initial delive ry st at e
45/62
9 Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). All usable Status Register bits are 0.
10 Maximum rating
Stressing the device above the rating listed in Table 13: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exp osur e to abso lute maximum rating conditions for
extended periods may affect device reliability. Ref er also to the Numonyx SURE Program
and other relevant quality documents .
Table 13. Absolute maxim um ratings
Symbol Parameter Min. Max. Unit
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering See note (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS) 2002/95/EU.
°C
VIO Input and output voltage (with respect to ground) –0.6 VCC +0.6 V
VCC Supply voltage –0.6 4.0 V
VESD Electrostatic discharge voltage (human body model)(2)
2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
–2000 2000 V
DC and AC parameters M25PE40
46/62
11 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurem ent conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurem ent conditions when relying on the quoted parameters.
Figure 25. AC measurement I/O waveform
Table 14. Operating conditions
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.7 3.6 V
TAAmbient operating temperature –40 85 °C
Table 15. Measurement conditions(1)
1. Output Hi-Z is defined as the point where data out is no longer driven.
Symbol Parameter Min. Max. Unit
CLLoad capacitance 30 pF
Input rise and fall times 5 ns
Input pulse voltages 0.2VCC to 0.8VCC V
Input and output timing reference voltages 0.3VCC to 0.7VCC V
Table 16. Capacitance(1)
1. Sampled only, not 100% tested, at TA= 25 °C and a frequency of 25 MHz.
Symbol Parameter Test condition Min. Max. Unit
COUT Output capacitance (Q) VOUT =0V 8 pF
CIN Input capacitance (other pins) VIN =0V 6 pF
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and output
timing reference levels
Input levels
M25PE40 DC and AC parameters
47/62
Table 17. DC characteristics
Symbol Parameter Test condition
(in addition to those in Table 14)Min. Max. Unit
ILI Input Leakage current ± 2 µA
ILO Output Leakage current ± 2 µA
ICC1 Standby current
(Standby and Reset modes) S=V
CC, VIN =V
SS or VCC 50 µA
ICC2 Deep Power-down current S =V
CC, VIN =V
SS or VCC 10 µA
ICC3 Operating current
(FAST_READ) C=0.1V
CC/0.9.VCC at 25 MHz, Q = open 6 mA
C=0.1V
CC/0.9.VCC at 50 MHz, Q = open 8 mA
ICC4 Operating current (PW) S =V
CC 15 mA
ICC5 Operating current (SE) S =V
CC 15 mA
VIL Input Low voltag e – 0.5 0.3VCC V
VIH Input High voltage 0.7VCC VCC+0.4 V
VOL Output Low voltage IOL =1.6mA 0.4 V
VOH Output High voltage IOH = –100 µA VCC–0.2 V
Table 18. DC characteristics (75 MHz operation, T9HX (0.11 µm) process)(1)
Symbol Parameter Test condition
(in addition to those in Table 14)Min. Max. Unit
ILI Input Leakage current ± 2 µA
ILO Output Leakage current ± 2 µA
ICC1 Standby current
(Standby and Reset modes) S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 µA
ICC3 Operating current
(FAST_READ) C = 0.1VCC/0.9.VCC at 33 MHz, Q = open 4 mA
C = 0.1VCC/0.9.VCC at 75 MHz, Q = open 12 mA
ICC4 Operating current (PW) S = VCC 15 mA
ICC5 Operating current (SE) S = VCC 15 mA
VIL Input Low voltage – 0.5 0.3VCC V
VIH Input High voltage 0.7VCC VCC+0.4 V
VOL Output Low voltage IOL = 1.6 mA 0.4 V
VOH Output High voltage IOH = –100 µA VCC–0.2 V
1. Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
DC and AC parameters M25PE40
48/62
M
Table 19. AC characteristics (25 MHz operation)
Test conditions specified in Table 14 and Table 15
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP,
WREN, WRDI, RDSR D.C. 25 MHz
fRClock frequency for READ instructions D. C. 20 MHz
tCH (1) tCLH Cloc k High time 18 ns
tCL (1) tCLL Clock Low time 18 ns
Clock Slew rate (peak-to-peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relat i ve to C) 10 ns
tCHSL S Not Active Hold time (relative to C) 10 ns
tDVCH tDSU Data In Setup time 5 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 10 ns
tSHCH S Not Active Setup time (relative to C) 10 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ (2) tDIS Output Disable time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO Output Hold time 0 ns
tTHSL Top Sector Lock Setup time 50 ns
tSHTL Top Sector Lock Hold time 100 ns
tDP (2) S to Deep Power-down 3 µs
tRDP (2) S High to Standby Power mode 30 µs
tPW (3) Page Write cycle time (256 bytes) 11 25 ms
Page Write cycle time (n bytes) 10.2+
n*0.8/256
tPP (3) Page Program cycle time (256 bytes) 1.2 5ms
Page Program cycle time (n bytes) 0.4+
n*0.8/256
tPE Page Erase cycle time 10 20 ms
tSE Sector Erase cycle time 1 5 s
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
M25PE40 DC and AC parameters
49/62
Table 20. AC characteristics (33 MHz operation)
33 MHz only available for products marked since week 40 of 2005(1)
Test conditions specified in Table 14 and Table 15
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP, WREN,
WRDI, RDSR D.C. 33 MHz
fRClock frequency for READ instructions D.C. 20 MHz
tCH (2) tCLH Clock High time 13 ns
tCL (2) tCLL Clock Low time 13 ns
Clock Slew Rate (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 10 ns
tCHSL S Not Active Hold time (relative to C) 10 ns
tDVCH tDSU Data In Setup time 3 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 5 ns
tSHCH S Not Active Setup time (relative to C) 5 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ (3) tDIS Output Disable time 12 ns
tCLQV tVClock Low to Output Valid 12 ns
tCLQX tHO Output Hold time 0 ns
tTHSL Top Sector Lock Setup time 50 ns
tSHTL Top Sector Lock Hold time 100 ns
tDP (3) S to Deep Power-down 3 µs
tRDP (3) S High to Standby Power mode 30 µs
tPW (4) Page Write cycle time (256 bytes) 11 25 ms
Page Write cycle time (n bytes) 10.2+
n*0.8/256
tPP (4) Page Program cycle time (256 bytes) 1.2 5ms
Page Program cycle time (n bytes) 0.4+
n*0.8/256
tPE Page Erase cycle time 10 20 ms
tSE Sector Erase cycle time 1 5 s
1. Details of how to find the date of marking are given in application note, AN1995.
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
4. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
DC and AC parameters M25PE40
50/62
Table 21. AC characteristics (50 MHz operation, T9HX (0.11µm) process(1))(2)
Test conditions speci f ied in Table 14 and Table 15
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR D.C. 50 MHz
fRClock frequency for READ instr uctions D.C. 33 MHz
tCH(3) tCLH Clock High time 9 ns
tCL(3) tCLL Clock Lo w time 9 ns
Clock Sle w Rate (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 5 ns
tCHSL S Not Active Hold time (relative to C) 5 ns
tDVCH tDSU Data In Setup time 2 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 5 ns
tSHCH S Not Active Setup time (relative to C) 5 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(4) tDIS Output Disable time 8 ns
tCLQV tVClock Low to Output Valid under 30 pF/10 pF 8/6 ns
tCLQX tHO Output Hold time 0 ns
tWHSL(5) Write Protect Setup time 50 ns
tSHWL(5) Write Protect Hold time 100 ns
tDP(4) S to Deep Power-down 3 µs
tRDP(4) S High to Standby mode 30 µs
tWWrite Status Register cycle time 3 15 ms
tPW(6) Page Write cycle time (256 bytes) 11 23 ms
tPP(6) Page Program cycle time (256 bytes) 0.8 3ms
Page Program cycle time (n bytes) int(n/8) × 0.025(7)
tPE Page Erase cycle time 10 20 ms
tSE Sector Erase cycle time 1.5 5 s
tSSE Subsector Erase cycle time 80 150 ms
tBE Bulk Erase cycle time 8 10 s
1. See Important note on page 6.
2. Details of how to find the technology process in the marking are given in AN1995, see also Section 13: Ordering
information.
3. tCH + tCL must be greater than or equal to 1/ fC.
4. Value guaranteed by characterization, not 100% tested in production.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
6. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
7. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
M25PE40 DC and AC parameters
51/62
Table 22. AC characteristics (75 MHz operation, T9HX (0.11µm) process(1))(2)(3)(4)
Test conditions specified in Table 14 and Table 15
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency f or the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR D.C. 75 MHz
fRClock frequency f or READ instructions D.C . 33 MHz
tCH(5) tCLH Clock High time 6 ns
tCL(5) tCLL Clock Low time 6 ns
Clock Slew Rate (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 5 ns
tCHSL S Not Active Hold time (relative to C) 5 ns
tDVCH tDSU Data In Setup time 2 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Activ e Hold time (relative to C) 5 ns
tSHCH S Not Active Setup time (relative to C) 5 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(6) tDIS Output Disable time 8 ns
tCLQV tVClock Low to Output Valid 8/6 ns
tCLQX tHO Output Hold time 0 ns
tWHSL(7) Write Protect Setup time 20 ns
tSHWL(7) Write Protect Hold time 100 ns
tDP(6) S to Deep Power-down 3 µs
tRDP(6) S High to Standby mode 30 µs
tWWrite Status Register cycle time 3 15 ms
tPW(8) Page Write cycle time (256 bytes) 11 23 ms
tPP(8) Page Program cycle time (256 bytes) 0.8 3ms
Page Program cycle time (n bytes) int(n/8) ×
0.025(9)
tPE Page Erase cycle time 10 20 ms
tSE Sector Erase cycle time 1.5 5 s
tSSE Subsector Erase cycle time 80 150 ms
tBE Bulk Erase cycle time 8 10 s
1. See Important note on page 6.
2. Details of how to find the technology process in the marking are given in AN1995, see also Section 13: Ordering
information.
3. Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
4. Preliminary data.
5. tCH + tCL must be greater than or equal to 1/ fC.
6. Value guaranteed by characterization, not 100% tested in production.
7. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
DC and AC parameters M25PE40
52/62
Figure 26. Serial input timing
Figure 27. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold
timing
1. For the differences between devices produced in the tw o processes, see Important note on page 6.
8. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
9. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
TSL
tTHSL tSHTL
AI3559
tWHSL tSHWL
Wor
M25PE40 DC and AC parameters
53/62
Figure 28. Output timing
C
Q
AI01449e
S
LSB OUT
D
ADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
DC and AC parameters M25PE40
54/62
Figure 29. Reset AC waveforms
Table 23. Reset conditions
Test conditions specified in Table 14 and Table 15
Symbol Alt. Parameter Conditions Min. Typ. Max. Unit
tRLRH(1)
1. Value guaranteed by characterization, not 100% tested in production.
tRST Reset pulse width 10 µs
tSHRH Chip Select High to
Reset High
Chip should have been
deselected before Reset is
de-asserted 10 ns
Table 24. Timings after a Res et Low pulse(1)(2)
1. All the values are guaranteed by characterization, and not 100% tested in production.
2. See Table 12 for a description of the device status after a Reset Low pulse.
Test conditions specified in Table 14 and Table 15
Symbol Alt. Parameter Conditions: Reset pulse occurred Max. Unit
tRHSL tREC Reset
recovery time
While decoding an instruction(3): WREN,
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
3. S remains Low while Reset is Low.
30 µs
Under completion of an Erase or Program
cycle of a PW, PP, PE, SE, BE operation 300 µs
Under completion of an Erase cycle of an
SSE operation 3ms
Under completion of a WRSR operation tW (see
Table 21)ms
Device deselected (S High) and in Standby
mode 0µs
AI06808
Reset tRLRH
S
tRHSLtSHRH
M25PE40 Package mechanical
55/62
12 Package mechanical
In order to mee t en viron mental requir ements , Numo nyx o ff er s these devices in ECOPACK®
packages. ECOPACK® packages are lead- free. The category of second level interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum r atings related t o soldering conditions are also marked on the inner
box label.
Figure 30. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 25. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 0.80 1.00 0.033 0.031 0.039
A1 0.00 0.05 0.000 0.002
A2 0.65 0.026
A3 0.20 0.008
b 0.40 0.35 0.48 0.016 0.014 0.019
D6.00 0.236
D1 5.75 0.226
D2 3.40 3.20 3.60 0.134 0.126 0.142
E5.00 0.197
E1 4.75 0.187
E2 4.00 3.80 4.30 0.157 0.150 0.169
e1.27– –0.050– –
R1 0.10 0.00 0.004 0.000
D
E
70-ME
A2
AA3
A1
E1
D1
eE2
D2
L
b
θ
R1
ddd
bbb
C
CAB
aaa CAA
B
aaa CB
M
0.10 CA
0.10 CB
2x
Package mechanical M25PE40
56/62
L 0.60 0.50 0.75 0.024 0.020 0.029
Θ12° 12°
aaa 0.15 0.006
bbb 0.10 0.004
ddd 0.05 0.002
Table 25. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package mechanical data (continued)
Symbol millimeters inches
Typ Min Max Typ Min Max
M25PE40 Package mechanical
57/62
Figure 31. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 26. SO8N – 8 lead plastic small outline, 150 mils body wi dth, pac kage
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– –0.050– –
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Package mechanical M25PE40
58/62
Figure 32. SO8W – 8 lead plastic smal l outline, 208 mils bo dy width, package out line
1. Drawing is not to scale.
Table 27. SO8W – 8 lead plastic small outline, 208 mi ls body width, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A2.500.098
A1 0.00 0.25 0.000 0.010
A2 1.51 2.00 0.059 0.079
b 0.40 0.35 0.51 0.016 0.014 0.020
c 0.20 0.10 0.35 0.008 0.004 0.014
CP 0.10 0.004
D6.050.238
E 5.02 6.22 0.198 0.245
E1 7.62 8.89 0.300 0.350
e1.27– –0.050– –
k 0° 10° 0° 10°
L 0.50 0.80 0.020 0.031
N8 8
6L_ME
E
N
CP
be
A2
D
c
LA1 k
E1
A
1
M25PE40 Ordering information
59/62
13 Ordering information
Note: F or a list of a vailable optio ns (speed, pac ka ge , etc.), for further inf ormation on any aspect of
this device or when ordering parts operating at 75 MHz (0.11 µm, process digit ‘4’), please
contact your nearest Numonyx Sales Office.
Table 28. Ordering information scheme
Example: M25PE40 V MP 6 T G
Device type
M25PE = page-erasable serial Flash memory
Device function
40 = 4 Mbit (512Kbit × 8)
Operatin g voltage
V = VCC = 2.7 to 3.6 V
Package
MW = SO8W (208 mils width)
MP = VFQFPN8 6 × 5 mm (MLP8)
MN = SO8N (150 mils width)(1)
1. Package only available for products in the T9HX process.
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPA CK® (RoHS compliant)
Revision history M25PE40
60/62
14 Revision history
Table 29. Document revision history
Date Revision Changes
01-Apr-2004 0.1 Initial release.
09-Nov-2004 1
Write Protect (W) pin replaced by Top Block Lock (TBL).
Section 2.5: Reset (Reset) descr iption modified. JEDEC signature
modified. Reset timings tRLRH, tRHSL and tSHRH removed from
Table 20: AC characteristics (33 MHz operation) and inserted in
Table 21: Reset timings (tRHSL modified). Document status
promoted from target specification to preliminary data.
01-Dec-2004 2 Top Block Lock (TBL) renamed as Top Sector Lock (TSL). Small te xt
changes. Deep Power-down mode clarified in Section 4.6: Active
Power, Standby Power and Deep Power-down modes.
11-Jan-2005 3 Notes removed from Table 28: Ordering information scheme.
Wording changes. SO16 package removed, SO8 wide package
added.
4-Oct-2005 4
Added Table 20: AC characteristics (33 MHz operation). Document
status promoted from preliminar y data to full datasheet. Table 19:
AC characteristics (25 MHz operation) updated. Section 4.2: An
easy way to modify data, Section 4.3: A fast way to modify data,
Section 6.9: P age Write (PW) and Section 6.10: P age Program (PP)
updated to explain optimal use of Page Write and Page Program
instructions. Clock slew r a te changed from 0.03 to 0.1 V/ns.
Updated Table 28: Ordering information scheme. Added
ECOPACK® info rmation.
11-Aug 2006 5
Changed document to new template; amended figure in Feature
summary; replaced Figure 4: Bus master and memory devices on
the SPI bus; amended data in Table 19 and Table 20; amended title
of Figure 30: VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat
package no lead 6 × 5 mm, package outline and added a footnote;
amended name of the MP package in Table 28: Ordering
information scheme.
M25PE40 Revision history
61/62
15-Jan-2007 6
50 MHz frequency added. SO8N package added, VFQFPN and
SO8W package specifications updated (see Section 12: Package
mechanical).
The sectors are further divided up into subsectors (see Table 4:
Memory organization). Important note on page 6 ad ded. Figure 4:
Bus master and memory devices on the SPI bus updated and
explanatory paragraph added. VCC supply voltage and VSS ground
added. Section 4.8: Protection modes modifi ed. Section 8: Reset
added, reset timings table split into Table 23: Reset conditions and
Table 24: Timings after a Reset Low pulse.
At power-up the WIP bit is reset (see Section 7: Power-up and
power-down).
VIO max changed in Table 13: Absolute maximum ratings. End
timing line of tSHQZ moved in Figure 28: Output timing.
Products processed in T9HX process added to datasheet:
–WP
pin replaces TSL (T7X technology), see Section 2.6: Write
Protect (W) or Top Sector Lock (TSL)
–Write Status Register (WRSR) and Subsector Erase (SSE)
instructions added for T9HX process
– subsector protection granularity removed in T9HX process, still
e xists in T7X process
–Table 4: Memory organization updated to show subsectors
– Status Register BP2, BP1, BP0 bits and SRWD bit added.
Small text changes.
23-Jan-2007 7
T7X process name corrected.
Write Enable Latch (WEL) bit is reset also on completion of the
Subsector Erase, Bulk Erase, Write to Lock Register and Write
Status Register instructions (see Section 6.2: Write Disable
(WRDI)).
Address bit A20 is not Don’t care (Note 1 modified) in the Sector
Erase (SE) instruction sequence. SO8N package is only av ailable in
products manufactured in the T9HX process.
10-Dec-2007 8
Removed ‘low voltage’ from the title.
Table 18: DC character istics (75 MHz operation, T9HX (0.11 µm)
process) and Table 22: AC characteristics (75 MHz operation, T9HX
(0.11µm) process) added.
Added ECOPAC K® text in Section 12: Package mechanical.
Updated the value for the maximum clock frequency (from 50 to
75 MHz) throug h the document.
Minor text changes.
03-Jan-2007 9 A pplied Numonyx branding.
Table 29. Document revision history (continued)
Date Revision Changes
M25PE40
62/62
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