71M6531D/F, 71M6532D/F
Energy Meter IC
Simplifying System IntegrationTM DATA SHEET
June 2010
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporati on 1
GENERAL DESCRIPTION
The Teridian 71M6531D/F and 71M6532D/F are highly
integrated SOCs with an MPU core, RTC, FLASH and LCD
driver. Teridian’s patented Singl e Converter Technol ogy®
with a 22-bit delta-sigma ADC , four analog inputs, digital
temperature compens ation, pre cision volt age refere nce, batt ery
voltage monitor and 32-bit computation engine (CE) supports
a wide range of residential metering applications with very few
low-cost external components.
A 32-kHz crystal time base for the entire system and internal
battery backup support for RAM and RTC further reduce system
cost. The IC su pports 2-wire, and 3-wir e singl e -p hase and
dual-phase resident i al m etering along with tamper-detection
mechanisms. The 71M6531D/F offers single-ended inputs for
two curren t c h annels an d two single-ended voltage inputs.
The 71M6532D/F has two differential current inputs and three
single-ended voltage inputs.
Maximum design flexibility is provided by multiple UARTs, I2C,
μWire, up to 21 DIO pins and in-system programmabl e FLASH
memory, which can be updated with data or applicati on code
in operation.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification o f TOU, AMR and Prepay m eters that comply with
worldwide electricity metering st an dards.
FEATURES
• Wh accuracy < 0.1% over 2000:1 current
range
• Exceeds IEC62053/ANSI C12.20 standards
• Four sensor inputs
• Low-jitter Wh and V ARh plus two additional
pulse test outputs (4 total, 10 kHz maximum)
with pulse count
• Four-quadrant metering
• Tamper detect i on (Neutral c urrent wit h CT,
Rogowski or shunt, magnetic tamper input)
• Line frequency count for RTC
• Digital temperature compensation
• Sag detection f or phase A and B
• Independent 32-bit compute engin e
• 46-64 Hz line frequency range with same
calibration. Phase compensation (± 7°)
• Three battery m odes with wake-up on timer
or push-button:
Brownout mode (52 µA typ.)
LCD mode (21 µA typ., DAC active)
Sleep mode (0. 7 µA typ.)
• Energy display during mains power failure
• 39 mW typical consumption @ 3.3 V, M P U
clock frequency 614 kHz
• 22-bit delta-sigma ADC with 3360 Hz or
2520 Hz sample rate
• 8-bit MPU (80515),1 clo ck cycle per instruction,
10 MHz maximum, with integrated ICE for
debug
• RTC for TOU functions with clock-rat e adjust
register
• Hardware watchdog timer, power fail monitor
• LCD driver wit h 4 comm on segment driv ers:
Up to 156 (71M6531 D/ F ) or 268 pixels
(71M6532D/F)
• Up to 22 (71M6531D/F) or 43 (71M6532D/F)
general-purpose I/O pins. Digital I/O pins
compatible with 5 V inputs
• 32 kHz time base
• High-speed slave S PI interf ace to data RAM
• Two UARTs for IR and A MR, IR driver with
modulation
• FLASH memory with security and in-system
program update:
128 KB (71M6531D/32D)
256 KB (71M6531F/32F)
• 4 KB MPU XRAM
• Industrial temperature range
• 68-pin QFN package for 71M6531D/F pin-
compatible with 71M 6521, 100-pin LQFP
package for 71M6532D/F, lead free
MPU
TIMERS
IAP*
VA
IBP*
XIN
XOUT
VREF
RX/DIO1
TX/DIO2
V1
TX
RX
COM0..3
V3.3A V3.3
SYS
VBAT
V2.5
VBIAS
GNDA GNDD
SEG/DIO
ICE I/F
LOAD
88.88.8888
I2C or µWire
EEPROM
POWER
FAULT
AMR
TEST PULSES
COMPARATOR
SENSE
DRIVE/MOD
SERIAL PORTS
OSC/PLL
ADC
LCD & DIO
COMPUTE
ENGINE
FLASH
MEMORY
RAM
VOLTAGE REF
REGULATOR
POWER SUPPLY
TERIDIAN
71M6531
71M6532
TEMP
SENSOR
32 kHz
A
NEUTRAL
CT/SHUNT
02/18/2009
VB
BLOAD
IR
PWR MODE
CONTROL
WAKE-UP
BATTERY
ICE_E GNDD
V3P3D
IAN*
IBN*
CT
SPI HOST
SPI
LCD SEG
RTC
*
Differential
pins only on 6532D/F
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
2 © 2005-2010 TE RIDIAN Semiconductor Corporation v1.3
Table of Contents
1 Hardware Description ....................................................................................................................... 10
1.1 Hardware Overview ................................................................................................................... 10
1.2 Analog Front End (AFE) ............................................................................................................. 10
1.2.1 Signal Input Pins ............................................................................................................ 10
1.2.2 Input Multiplexer ............................................................................................................ 11
1.2.3 A/D Converte r (ADC) ..................................................................................................... 12
1.2.4 FIR Filter ........................................................................................................................ 12
1.2.5 Voltage References ....................................................................................................... 12
1.2.6 Temperature Sensor ...................................................................................................... 14
1.2.7 Battery Monitor............................................................................................................... 14
1.2.8 AFE Functional Descripti on ........................................................................................... 14
1.2.9 Digital Computation E ngine (CE) ................................................................................... 15
1.2.10 Meter Equat ions ............................................................................................................. 16
1.2.11 Real-Time Monitor ......................................................................................................... 16
1.2.12 Pulse Generators ........................................................................................................... 16
1.2.13 Data RAM (XRAM) ........................................................................................................ 17
1.2.14 Delay Compensation ..................................................................................................... 17
1.2.15 CE Funct ional Overview ................................................................................................ 17
1.3 80515 MPU Core ....................................................................................................................... 19
1.3.1 Memory Organization and Addressing .......................................................................... 19
1.3.2 Special Function Registers (SFRs) ............................................................................... 21
1.3.3 Generic 80515 Special Function Register s ................................................................... 22
1.3.4 Special Function Registers (SFRs) Specific to the 71M6531 D/ F and 71M6532D/F ..... 24
1.3.5 Instruction Set ................................................................................................................ 26
1.3.6 UARTs ........................................................................................................................... 26
1.3.7 Timers and Counters ..................................................................................................... 28
1.3.8 WD Timer (Software Watchdog Timer ) ......................................................................... 30
1.3.9 Interrupts ........................................................................................................................ 30
1.4 On-Chip Resources ................................................................................................................... 36
1.4.1 Oscillator ........................................................................................................................ 36
1.4.2 Internal Clocks ............................................................................................................... 36
1.4.3 Real-Time Clock (RTC) ................................................................................................. 37
1.4.4 Temperature Sensor ...................................................................................................... 38
1.4.5 Physical Memory............................................................................................................ 38
1.4.6 Optical Interface ............................................................................................................. 40
1.4.7 Digital I/O – 71M6531D/F .............................................................................................. 41
1.4.8 Digital I/O – 71M6532D/F .............................................................................................. 43
1.4.9 Digital IO – Common Characterist i cs for 71M6531D/F and 71M 6532D/F .................... 44
1.4.10 LCD Drivers – 71M6531D/F .......................................................................................... 45
1.4.11 LCD Drivers – 71M6532D/F .......................................................................................... 46
1.4.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71 M6532D/F ............... 46
1.4.13 Battery Monitor............................................................................................................... 46
1.4.14 EEPROM Interface ........................................................................................................ 46
1.4.15 SPI Slave Port................................................................................................................ 49
1.4.16 Hardwar e Watchdog Timer ............................................................................................ 52
1.4.17 Test P orts (TMUXO UT p i n) ........................................................................................... 53
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 3
2 Functional Description ..................................................................................................................... 54
2.1 Theory of Operation ................................................................................................................... 54
2.2 System Timing Summary ........................................................................................................... 55
2.3 Battery Modes ............................................................................................................................ 56
2.3.1 BROWNOUT Mode ....................................................................................................... 57
2.3.2 LCD Mode ...................................................................................................................... 58
2.3.3 SLEEP Mode ................................................................................................................. 58
2.4 Fault and Reset Behavior .......................................................................................................... 60
2.4.1 Reset Mode .................................................................................................................... 60
2.4.2 Power Fault Circuit ........................................................................................................ 60
2.5 Wake-Up Behavior ..................................................................................................................... 61
2.5.1 Wake on PB ................................................................................................................... 61
2.5.2 Wake on Timer............................................................................................................... 61
2.6 Data Flow ................................................................................................................................... 61
2.7 CE/MPU Communication ........................................................................................................... 62
3 Application Information .................................................................................................................... 63
3.1 Connection of Sensor s ............................................................................................................... 63
3.2 Connecting 5-V Devices ............................................................................................................ 63
3.3 Temperature Measurem ent ....................................................................................................... 64
3.4 Temperature Compensat io n ...................................................................................................... 64
3.4.1 Temperature Coefficient s: ............................................................................................. 64
3.4.2 Temperature Compensation for VREF .......................................................................... 65
3.4.3 System Temperature Compen sati on ............................................................................. 65
3.4.4 Temperature Compensation for the RTC ...................................................................... 65
3.5 Connecting LCDs ....................................................................................................................... 66
3.6 Connecting I2C EEPROMs ........................................................................................................ 66
3.7 Connecting Three-Wire EEPROMs ........................................................................................... 67
3.8 UART0 (TX/RX ) ......................................................................................................................... 67
3.9 Optical Interface (UART1) .......................................................................................................... 67
3.10 Connecting the V1 Pin ............................................................................................................... 68
3.11 Connecting the Reset Pin .......................................................................................................... 69
3.12 Connecting the Emulator Port Pins ............................................................................................ 69
3.13 Connecting a Battery ................................................................................................................. 69
3.14 Flash Programming .................................................................................................................... 70
3.15 MPU Firmware ........................................................................................................................... 70
3.16 Crystal Oscill at or ........................................................................................................................ 70
3.17 Meter Calibration ........................................................................................................................ 71
4 Firmware Interface ............................................................................................................................ 72
4.1 I/O RAM and SFR Map – Functi onal Order ............................................................................... 72
4.2 I/O RAM Description – Alphabetical Order ................................................................................ 77
4.3 CE Interface Description ............................................................................................................ 88
4.3.1 CE Program ................................................................................................................... 88
4.3.2 CE Data Format ............................................................................................................. 88
4.3.3 Constants ....................................................................................................................... 88
4.3.4 Environment ................................................................................................................... 88
4.3.5 CE Calculations ............................................................................................................. 89
4.3.6 CE Status and Control ................................................................................................... 89
4.3.7 CE Transfer Variables ................................................................................................... 92
4.3.8 Pulse Generation ........................................................................................................... 93
4.3.9 CE Calibration Parameters ............................................................................................ 94
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
4 © 2005-2010 TE RIDIAN Semiconductor Corporation v1.3
4.3.10 Other CE Param eter s .................................................................................................... 95
4.3.11 CE Flow Diag ram s ......................................................................................................... 95
5 Electrical Specifications ................................................................................................................... 98
5.1 Absolute Maximum Ratings ....................................................................................................... 98
5.2 Recommended Ext ernal Components ....................................................................................... 99
5.3 Recommended Operating Con dition s ........................................................................................ 99
5.4 Performance Specificat ion s ..................................................................................................... 100
5.4.1 Input Logic Levels ........................................................................................................ 100
5.4.2 Output Logic Levels ..................................................................................................... 100
5.4.3 Power-Fault Comparator ............................................................................................. 100
5.4.4 Battery Monitor............................................................................................................. 100
5.4.5 Supply Current ............................................................................................................. 101
5.4.6 V3P3D Switch .............................................................................................................. 101
5.4.7 2.5 V Voltage Regulator ............................................................................................... 101
5.4.8 Low-Power Voltage R egulator ..................................................................................... 101
5.4.9 Crystal Oscillator .......................................................................................................... 102
5.4.10 LCD DAC ..................................................................................................................... 102
5.4.11 LCD Drivers ................................................................................................................. 102
5.4.12 Optical I nterface ........................................................................................................... 102
5.4.13 Temperat ure S ensor .................................................................................................... 103
5.4.14 VREF ........................................................................................................................... 103
5.4.15 ADC Converter, V3P3A Referenced ........................................................................... 104
5.5 Timing Specifications ............................................................................................................... 105
5.5.1 Flash Memory .............................................................................................................. 105
5.5.2 EEPROM Interface ...................................................................................................... 105
5.5.3 RESET ......................................................................................................................... 105
5.5.4 RTC .............................................................................................................................. 105
5.5.5 SPI Slave Port (MISSION Mode) ................................................................................. 106
5.6 Typical Performance Data ....................................................................................................... 107
5.6.1 Accuracy over Current ................................................................................................. 107
5.6.2 Accuracy over Temperature ........................................................................................ 107
5.7 71M6531D/F Package ............................................................................................................. 108
5.7.1 Package Outline .......................................................................................................... 108
5.7.2 71M6531D/F Pinout (QFN-68) ..................................................................................... 109
5.7.3 Recommended PCB Land Pattern for the Q FN-68 P ackage ...................................... 110
5.8 71M6532D/F Package ............................................................................................................. 111
5.8.1 71M6532D/F Pinout (LQ F P -100) ................................................................................. 111
5.8.2 LQFP-100 Mechanical Drawing ................................................................................... 112
5.9 Pin Descriptions ....................................................................................................................... 113
5.9.1 Power and Ground Pins ............................................................................................... 113
5.9.2 Analog Pins .................................................................................................................. 113
5.9.3 Digital Pins ................................................................................................................... 114
5.9.4 I/O Equivalent Circuit s ................................................................................................. 115
6 Ordering Information ...................................................................................................................... 116
7 Related Information ........................................................................................................................ 116
8 Contact In formation ........................................................................................................................ 116
Appendix A: Acronyms .......................................................................................................................... 117
Appendix B: Revisi on History ............................................................................................................... 118
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 5
Figures
Figure 1: 71M6531D/F IC Function al B l ock Diagram ................................................................................... 8
Figure 2: 71M6532D/F IC Function al B l ock Diagram ................................................................................... 9
Figure 3: General Topology of a Chopp ed Amplifier .................................................................................. 13
Figure 4: CROSS S i gnal with CHOP_E[1:0] = 00 ....................................................................................... 13
Figure 5: AFE B lock Diagram (Shown for the 71M6532D/F) ...................................................................... 14
Figure 6: Samples from Multiplexer Cycle .................................................................................................. 18
Figure 7: Accumulat i on Interval .................................................................................................................. 18
Figure 8: Interru pt Structure ........................................................................................................................ 35
Figure 9: Optical Interface ........................................................................................................................... 41
Figure 10: Conne ct i ng an External Load t o DIO Pins ................................................................................. 45
Figure 11: 3-Wire Int erface. Write Com m and, HiZ=0 ................................................................................ 48
Figure 12: 3-Wire Int erface. Write Com m and, HiZ=1 ................................................................................ 48
Figure 13: 3-Wire Int erface. Read Co m m and. ........................................................................................... 49
Figure 14: 3-Wire Int erface. Write Com m and when CNT=0 ...................................................................... 49
Figure 15: 3-Wire Int erface. Write Com m and when HiZ=1 and W F R=1 ................................................... 49
Figure 16: SPI S l ave Port: Typical Read and Write operations .................................................................. 51
Figure 17: Functi ons defined by V1 ............................................................................................................ 52
Figure 18: Voltage, Cur rent, Momentary and Accumulat ed Energy ........................................................... 54
Figure 19: Timing Relationship between ADC MUX, Compute Engine ...................................................... 55
Figure 20: RTM Output Format ................................................................................................................... 55
Figure 21: Operati on Modes State Diagram ............................................................................................... 56
Figure 22: Transition from BRO WNOUT to MISS ION Mode when System P ower Returns ...................... 59
Figure 23: Power-Up Ti m ing with V3P3SYS and VBAT tied together ........................................................ 59
Figure 24: Power-Up Timing with VBAT only .............................................................................................. 60
Figure 25: Wake Up T im i ng ........................................................................................................................ 61
Figure 26: MPU/CE Data Flow .................................................................................................................... 62
Figure 27: MPU/CE Communication ........................................................................................................... 62
Figure 28: Resistiv e V ol tage Divider ........................................................................................................... 63
Figure 29: CT wit h S i ngl e E nded (Left) and Differential Input (Right) Connectio n ..................................... 63
Figure 30: Resistiv e S hunt (Left) and Rogowski Sensor (Right ) Connection ............................................. 63
Figure 31: Conne ct i ng LCDs ....................................................................................................................... 66
Figure 32: I2C EEPROM Connection .......................................................................................................... 66
Figure 33: Three -Wi re EEPROM Connec ti on ............................................................................................. 67
Figure 34: Conne ct i ons for UART0 ............................................................................................................. 67
Figure 35: Conne ct i on for Optical Comp onents .......................................................................................... 68
Figure 36: Voltage Divider for V1 ................................................................................................................ 68
Figure 37: Ext ernal Components for the RESET Pin: Push-button (Left), Production Circuit (Right) ........ 69
Figure 38: Ext ernal Components for the Emulator Interface ...................................................................... 69
Figure 39: Conne ct i ng a B attery ................................................................................................................. 70
Figure 40: CE Dat a Fl ow: Multiplexer a nd ADC.......................................................................................... 96
Figure 41: CE Dat a Fl ow: Scaling, Gain Control, Intermedi ate Variables .................................................. 96
Figure 42: CE Dat a Fl ow: Squaring and S um m ation Stages ...................................................................... 97
Figure 43: SPI Slave Port (MISSION Mode) Timing ................................................................................. 106
Figure 44: Wh Accu racy, 0.1 A to 200 A at 240 V /50 Hz and Room Temperature .................................. 107
Figure 45: QFN-68 Package Outline, Top and Side View ........................................................................ 108
Figure 46: QFN-68 Package Outline, B ottom View .................................................................................. 108
Figure 47: Pinout for QFN-68 Package ..................................................................................................... 109
Figure 48: PCB Land Pattern for QFN 68 Package .................................................................................. 110
Figure 49: PCB Land Pattern for LQFP-100 Package .............................................................................. 111
Figure 50: LQFP-100 P ackage, Mechanical Drawing ............................................................................... 112
Figure 51: I/O Equivalent Circuits ............................................................................................................. 115
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
6 © 2005-2010 TE RIDIAN Semiconductor Corporation v1.3
Tables
Table 1: Inputs Sel ect ed in Regular and A l ternate Multiplexer Cy cles ....................................................... 11
Table 2: ADC Resol ution ............................................................................................................................. 12
Table 3: ADC RAM Locations ..................................................................................................................... 12
Table 4: XRAM Locati ons for ADC Results ................................................................................................ 15
Table 5: Meter Equations ............................................................................................................................ 16
Table 6: CKMPU Clock Frequencies .......................................................................................................... 19
Table 7: Memory Map ................................................................................................................................. 20
Table 8: Internal Dat a M emory Map ........................................................................................................... 21
Table 9: Special Fun ct i on Register Map ..................................................................................................... 21
Table 10: Generic 80515 SFRs - Location and Reset Values .................................................................... 22
Table 11: PSW Bit Functions (SFR 0xD0) ..................................................................................................... 23
Table 12: Port Registers ............................................................................................................................. 24
Table 13: Stretch M emory Cycle Width ...................................................................................................... 24
Table 14: 71M6531D/ F and 71M6532D/F Specific SFRs ........................................................................... 24
Table 15: Baud Rate Generation ................................................................................................................ 26
Table 16: UART Modes ............................................................................................................................... 26
Table 17: The S0CON (UART0) Register (SFR 0x98) ................................................................................. 27
Table 18: The S1CON (UART1) register (SFR 0x9B) .................................................................................. 27
Table 19: PCON Register Bit Description (S F R 0x87) ................................................................................ 28
Table 20: Timers/ Counters Mode Description ............................................................................................ 28
Table 21: Allowed Timer/Counter Mode Combinations .............................................................................. 29
Table 22: TMOD Register Bit Descriptio n (S F R 0x89) ................................................................................ 29
Table 23: The TCON Register Bit Functions (SFR 0x88) ............................................................................ 29
Table 24: The IEN0 Bit Functions (SFR 0xA8) ............................................................................................ 30
Table 25: The IEN1 Bit Functions (SFR 0xB8) ............................................................................................ 31
Table 26: The IEN2 Bit Functions (SFR 0x9A) ............................................................................................ 31
Table 27: TCON Bit Functions (SFR 0x8 8) ................................................................................................. 31
Table 28: The T2CON Bit Functions (SFR 0xC8) ........................................................................................ 31
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 31
Table 30: External MPU Interrupts .............................................................................................................. 32
Table 31: Interru pt Enable and Flag Bit s .................................................................................................... 32
Table 32: Interru pt Priority Level Groups .................................................................................................... 33
Table 33: Interru pt Priority Levels ............................................................................................................... 33
Table 34: Interru pt Priority Regist ers (IP0 and IP1) .................................................................................... 34
Table 35: Interru pt Polling Sequence .......................................................................................................... 34
Table 36: Interru pt Vectors .......................................................................................................................... 34
Table 37: Clock Syst em Summary .............................................................................................................. 36
Table 38: Bank Switching with FL_BANK[2:0] ............................................................................................ 40
Table 39: Data/Dire ct i on Registers and Internal Resources f or DIO 1-15 (71M6 531D/F) ......................... 42
Table 40: Data/Dire ct i on Registers and Internal Resources f or DIO 17-29 (71M6 531D/ F) ....................... 42
Table 41: Data/Dire ct i on Registers and Internal Resources f or DIO 43-46 (71M6 531D/ F) ....................... 42
Table 42: Data/Dire ct i on Registers and Internal Resources f or DIO 1-15 (71M6 532D/F) ......................... 43
Table 43: Data/Dire ct i on Registers and Internal Resources for DIO 16-30 (71M6 532D/ F) ....................... 43
Table 44: Data/Dire ct i on Registers and Internal Resources f or DIO 40-51 (71M6 532D/ F) ....................... 44
Table 45: DIO_DIR Control Bit .................................................................................................................... 44
Table 46: Selectable Control using DIO_DIR Bits ......................................................................................... 44
Table 47: EECTRL Bits for 2-pin Interface ................................................................................................... 47
Table 48: EECTRL Bits for the 3-Wire Interfac e .......................................................................................... 48
Table 49: SPI Command Description .......................................................................................................... 50
Table 50: I/O RAM Registers Accessible via SPI ....................................................................................... 50
Table 51: TMUX[4:0] Selections ................................................................................................................. 53
Table 52: Available Circuit Function s .......................................................................................................... 57
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 7
Table 53: I/O RAM Map in Functional O rder ............................................................................................... 72
Table 54: I/O RAM Description - Alphabetical ............................................................................................ 77
Table 55: CE EQU[2:0] Equation s and Element Input M appi ng ................................................................. 89
Table 56: CESTATUS (CE RAM 0x80) B i t Definitions .................................................................................. 90
Table 57: CECONFIG Bit Definitions ........................................................................................................... 91
Table 58: Sag Threshold Control ................................................................................................................ 91
Table 59: Gain Adjust Control ..................................................................................................................... 91
Table 60: CE Transfe r Variable s ................................................................................................................. 92
Table 61: CE Energy M easurement Variables ............................................................................................ 92
Table 62: Useful CE M easurement Para m eters ......................................................................................... 93
Table 63: CE Pulse Generation Parameters ............................................................................................... 94
Table 64: CE Calibrat i on Parameters ......................................................................................................... 94
Table 65: CE Parameters for Noise Su ppression and Code V ersion ......................................................... 95
Table 66: Absolute Maximum Ratings ........................................................................................................ 98
Table 67: Recomm ended External Components ........................................................................................ 99
Table 68: Recomm ended Operating Conditions ......................................................................................... 99
Table 69: Input Logi c Levels ..................................................................................................................... 100
Table 70: Output Logic Levels .................................................................................................................. 100
Table 71: Power-Fault Comparator P erformance Specifications ............................................................. 100
Table 72: Batt ery M onitor Performan ce Specification s (BME= 1) ............................................................. 100
Table 73: Supply Current Performance Specificati ons ............................................................................. 101
Table 74: V3P3D Swit ch Performance Specifications .............................................................................. 101
Table 75: 2.5 V V ol tage Regulator Performance Specificati ons ............................................................... 101
Table 76: Low-Power Voltage Regulator Performan ce Specificatio ns ..................................................... 101
Table 77: Crystal Oscillator Perf orm ance Specificati ons .......................................................................... 102
Table 78: LCD DAC Performance Spe cifications ..................................................................................... 102
Table 79: LCD Driver Performance S pecifications ................................................................................... 102
Table 80: Optical Interface Performance Specifications ........................................................................... 102
Table 81: Temperat ure Sensor Performance Specifications .................................................................... 103
Table 82: VREF Perf orm ance Specifica tions ............................................................................................ 103
Table 83: ADC Converter Performan ce Specifications ............................................................................. 104
Table 84: Flash Mem ory Timing Specific ations ........................................................................................ 105
Table 85: EEPROM Interface Timing ........................................................................................................ 105
Table 86: RESET Ti m i ng .......................................................................................................................... 105
Table 87: SPI Slave Port (MISSION M ode) Ti m ing .................................................................................. 106
Table 88: Recomm ended PCB Land Pa ttern Dimensions ........................................................................ 110
Table 89: Power and Ground Pins ............................................................................................................ 113
Table 90: Analog Pi ns ............................................................................................................................... 113
Table 91: Digit al P i ns ................................................................................................................................ 114
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
8 © 2005-2010 TE RIDIAN Semiconductor Corporation v1.3
Figure 1: 71M6531D/F IC Functional Block Diagra m
∆Σ ADC
CONVERTER
VREF
ADC_E
MUX
XIN
XOUT
VREF
DIO1/OPT_RX
RESET
V1
UART2--OPTICAL
UART1
TX
RX
4
COM0...3
LCD DISPLAY
DRIVER
DIGITAL I/O
RTCLK (32KHz)
CE_E
RTM_E
POWER FAULT
LCD_E
LCD_CLK
LCD_MODE
DIO
GNDD V3P3A
V3P3D
VBAT
VOLT
REG
2.5V to logic
V2P5
SUM_CYCLES
PRE_SAMPS
EQU
TMUXOUT
FAULTZ
TMUX[4:0]
GNDA
VBIAS
OSC
(32KHz)
MCK
PLL
VREF
VREF_DIS
TEST
TEST
MODE
DIO_R
DIO_DIR
E_RXTX
OPT_TXE
RTC
VBIAS
ICE_E
VREF_CAL
RTM_0..3
CE_LCTN
PLS_MAXWIDTH
PLS_INTERVAL
PLS_INV
OPT_TXINV
OPT_TXMOD
OPT_FDC
OPT_RXINV
OPT_RXDIS
LCD_BLKMAP
LCD_SEG
LCD_Y
SLEEP
LCD_ONLY
V3P3SYS
TEST
MUX
VBAT
CE_PROG
CK_CE
CK_MPU
VADC
CE
MULTI-
PURPOSE
IO
MUX_DIV
MUX_ALT
EQU
RTM
RPULSE
WPULSE
COM0..3
SEG...
DIO...
to TMUX
SPI SLAVE
PCMD
EEPROM
EECTRL
FLASH
128KB/
256KB
XRAM
4kB
CE_DATA
PCSZ
PCLK
PSI
PSO
SDATA
SCLK
EEDATA
OPT_TX
OPT_RX
PB
PB
IRAM
256B
MPU
EMULATOR
(ICE) E_TCLK
E_RSTZ
DIO2/OPT_TX/WPULSE/RPULSE
SEG7/MUX_SYNC
SEG8
SEG9/E_RXTX
SEG10/E_TCLK
SEG11/E_RST
SEG12
SEG13
SEG14
SEG16
SEG15
SEG17
DIO4/SEG24/SDCK
DIO5/SEG25/SDATA
DIO6/SEG26/WPULSE
DIO7/SEG27/RPULSE
DIO10/SEG30
RPULSE
WPULSE
4
XRAM BUS
8
IRAM BUS
16 32
22
CKTEST
DIO_PV
DIO_PW
CKOUT_E
MUX_SYNC_E
SPE
DIO_EEX
OPT_TXE
ICE_E
CKOUT_E
SEG0
SEG1
SEG2
SEG3/PCLK
SEG4/PSDO
SEG5/PCSZ
SEG6/PSDI
FIR
FIR_LEN
VA
IB
VB
IA
DIO12/SEG32
DIO11/SEG31
XPULSE
YPULSE
XPULSE
YPULSE
DIO_PX
DIO_PY
DIO8/SEG28/XPULSE
DIO9/SEG29/YPULSE
SEG18
SEG19/CKTEST
DIO44/SEG64
DIO43/SEG63
DIO29/SEG49
DIO28/SEG48
DIO13/SEG33
DIO14/SEG34
DIO15/SEG35
DIO46/SEG66
DIO45/SEG65
DIO17/SEG37
LCD_DAC
RTCA_ADJ
PREG
QREG
RST_SUBSEC
RTC_SEC
RTC_MIN
RTC_HR
RTC_DAY RTC_DATE
RTC_MO
RTC_YR
05/26/2010
NVRAM
GP0-GP7 2.5V_NV
2.5V_NV
2.5V_NV
2.5V_NV
TEMP
SENSOR
8
8
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 9
Figure 2: 71M6532D/F IC Functional Block Diagra m
∆Σ ADC
CONVERTER
VREF
ADC_E
MUX
XIN
XOUT
VREF
DIO1/OPT_RX
RESET
V1
UART2--OPTICAL
UART1
TX
RX
4
COM0...3
LCD DISPLAY
DRIVER
DIGITAL I/O
RTCLK (32KHz)
CE_E
RTM_E
POWER FAULT
LCD_E
LCD_CLK
LCD_MODE
DIO
GNDD V3P3A
V3P3D
VBAT
VOLT
REG
2.5V to logic
V2P5
SUM_CYCLES
PRE_SAMPS
EQU
TMUXOUT
FAULTZ
TMUX[4:0]
GNDA
VBIAS
TEMP
SENSOR
OSC
(32KHz)
MCK
PLL
VREF
VREF_DIS
TEST
TEST
MODE
DIO_R
DIO_DIR
E_RXTX
OPT_TXE
RTC
VBIAS
ICE_E
VREF_CAL
RTM_0..3
CE_LCTN
PLS_MAXWIDTH
PLS_INTERVAL
PLS_INV
OPT_TXINV
OPT_TXMOD
OPT_FDC
OPT_RXINV
OPT_RXDIS
LCD_BLKMAP
LCD_SEG
LCD_Y
SLEEP
LCD_ONLY
V3P3SYS
TEST
MUX
VBAT
CE_PROG
CK_CE
CK_MPU
VADC
CE
MULTI-
PURPOSE
IO
MUX_DIV
MUX_ALT
EQU
RTM
RPULSE
WPULSE
COM0..3
SEG...
DIO...
to TMUX
SPI SLAVE
PCMD
EEPROM
EECTRL
FLASH
128KB/
256KB
XRAM
4kB
CE_DATA
PCSZ
PCLK
PSI
PSO
SDATA
SCLK
EEDATA
OPT_TX
OPT_RX
PB
PB
IRAM
256B
MPU
EMULATOR E_TCLK
E_RSTZ
DIO2/OPT_TX/WPULSE/RPULSE
SEG7/MUX_SYNC
SEG8
SEG9/E_RXTX
SEG10/E_TCLK
SEG11/E_RST
SEG12...SEG18
DIO4/SEG24/SDCK
DIO5/SEG25/SDATA
DIO6/SEG26/WPULSE
DIO7/SEG27/RPULSE
RPULSE
WPULSE
4
XRAM BUS
8
IRAM BUS
8
16 32
22
CKTEST
DIO_PV
DIO_PW
CKOUT_E
MUX_SYNC_E
SPE
DIO_EEX
OPT_TXE
ICE_E
CKOUT_E
SEG0...SEG2
SEG3/PCLK
SEG4/PSDO
SEG5/PCSZ
SEG6/PSDI
FIR
FIR_LEN
VA
IBP
VB
IAP
XPULSE
YPULSE
XPULSE
YPULSE
DIO_PX
DIO_PY
DIO8/SEG28/XPULSE
DIO9/SEG29/YPULSE
SEG19/CKTEST
LCD_DAC
RTCA_ADJ
PREG
QREG
RST_SUBSEC
RTC_SEC
RTC_MIN
RTC_HR
RTC_DAY RTC_DATE
RTC_MO
RTC_YR
05/26/2010
NVRAM
GP0-GP7 2.5V_NV
2.5V_NV
2.5V_NV
2.5V_NV
IAN
IBN
SEG20...SEG23
DIO10/SEG30...DIO27/SEG47
DIO29/SEG59
DIO30/SEG50
DIO40/SEG60...DIO45/SEG65
DIO47/SEG67...DIO51/SEG71
DIO56...DIO58
DIO3
4
7
3
3
18
6
5
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
10 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
1 Hardware Description
1.1 Hardware Overview
The Teridian 71M6531D/F and 71M6532D/F single-chi p energy meters integrates all primary functional
blocks required t o i m pl ement a solid-stat e el ect ricity meter. Included on the chips are:
• An analog front end (AFE )
• An Independent digit al computation engine (CE)
• An 8051-compatible m icroprocessor (MPU) which executes one instruction per clo ck cycle (80515 )
• A voltage reference
• A temperatur e sensor
• LCD drivers
• RAM and Flash mem ory
• A real time clock (R T C)
• A variety of I/O pins
Various current sensor technolo gi es are supported including Current Transformers (CT), Resistive Shunts
and Rogowski coils.
In a typical applicat i on, the 32-bit comp ute engine (CE) of the 71M6531D/F and 71M6532D/F sequentially
process the samples from the voltage in puts on pins IA, V A, IB, VB and performs calculations t o m easure
active energy (Wh) and reactive ener gy (VARh), as well as A2h and V2h for four-quadrant metering.
These measureme nts are then accesse d by the MPU, processed further and ou tput using the peripheral
devices available to the MPU.
In addition to advanced measurement functions, the real time clock function all ows the 71M6531D/F and
71M6532D/F to record time of use (TOU) metering information for multi-rate applications and to time-stamp
tamper events. Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature
environments. Flexible mapping of LCD display segments facilitate i ntegration of exist i ng custom LCDs.
Design trade-off between the number of LCD segments and DIO pins can be implemented in software to
accommodate various requirements.
In addition to the temperature-trimmed ultra-precisio n voltage reference, the on-chip digital t em perature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted
temperature ef fects on measurement and RTC accuracy, e.g. to meet the requirements of ANSI and IEC
standards. Temperature-dependent external components such as a crystal oscillator, current transformers
(CTs) and their corresponding signal conditioning circuits can be characterized and their correction factors
can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature
range.
One of the two internal UARTs is adap ted to suppor t an Infrared L ED wi th internal drive and sens e
configuration and can also function as a st andard UART. The optical output can be modulated at 38 kHz.
This flexibility makes it possible to implement AMR met ers with an IR interface. A block diagram of the
71M6531D/F IC is shown i n Figure 1. A bloc k diagram of the 71M6532D/F IC is shown in Figure 2.
1.2 Analog Front End (AFE)
The AFE consists of an i nput multiplexer, a delta-sigma A/D converter and a v oltage reference.
1.2.1 Signal Input Pins
All analog signal input pins are sensitive to voltage. In the 71M6531D/F, the VA and VB pins, as well as the
IA and IB pins are single-ended. In the 71M6532D/F, the IAP/IAN and IBP/IBN pins can be programmed
individually to be differential (see I/O RAM bit SEL_IAN and SEL_IBN) or single-ended. The differential signal
is applied betwee n the IAP and IAN inpu t pins and between the IBP and IBN input pins. Single-ended
signals are applied to the IAP and IBP input pins whereas the common signal, return, is t he V3P3A pin.
When using the differential mode, inputs can be chopped, i.e. a connection from V3P3A to IAP or IAN (or
IBP an IBN, respectively) alternates in each multiplexer cycle.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 11
1.2.2 Input Multiplexer
The input multi pl exer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB
(IBP/IBN), and VB of the device. Additionally, usin g the alternate multi plexer selection, it has the ability to
select temper ature and the battery voltage. The mult i pl exer can be operated i n two modes:
• During a normal mul tiplexer cycle, t he signals from the IA (IAP/IAN), IB (IBP/IBN), VA and VB pins
are selected.
• During the alternat e multiplexer cycle, the temperature signal (TE M P ) and the battery monitor are
selected, along wit h some of the vol tage and/or current signal sources shown in Table 1. To prevent
unnecessary drainage on the battery , the battery mon i tor is only active when enabled with the BME
bit (0x2020[6]) i n the I/O RAM.
The alternate m ul tiplexer cycles are u sually performe d i nfrequently (every second or so) by the M P U. In
order to prevent di sr uption of the vol tage tracking PLL and voltage allpass networks, VA is not replaced in
the ALT selecti ons. Table 1 details the regular and alternative multiplexer sequence s. The computation
engine (CE) fil ls in m issing samples due to an ALT multi pl exer sequence.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cy cl es
Time
Slot
Regular Slot
Alternate Slot
Register Typical Selections Register Typical Selections
RAM
Address
Signal for
ADC
RAM
Signal for
ADC
0
SLOT0_SEL[3:0]
0 IA
SLOT0_ALTSEL[3:0]
A
TEMP
1 SLOT1_SEL[3:0] 1 VB SLOT1_ALTSEL[3:0] 1 VB
2 SLOT2_SEL[3:0] 2 IB SLOT2_ALTSEL[3:0] B VBAT
3 SLOT3_SEL[3:0] 3 VA SLOT3_ALTSEL[3:0] 3 VA
–
SLOT4_SEL[3:0]
– –
SLOT4_ALTSEL[3:0]
– –
– SLOT5_SEL[3:0] – – SLOT5_ALTSEL[3:0] – –
– SLOT6_SEL[3:0] – – SLOT6_ALTSEL[3:0] – –
– SLOT7_SEL[3:0] – – SLOT7_ALTSEL[3:0] – –
–
SLOT8_SEL[3:0]
– –
SLOT8_ALTSEL[3:0]
– –
– SLOT9_SEL[3:0] – – SLOT9_ALTSEL[3:0] – –
The sequenc e of sampled c h annels is fu l l y programmable us i ng I/O RAM regist ers. SLOTn_SEL[3:0]
selects the input f or the nth state in a st andard multiplexer frame, while SLOTn_ALTSEL[3:0] selects the
input for the nth state in an alternate multiplexer frame. The states shown in Table 1 are exa mples for
possible multiplexer state sequences.
In a typical applicat i on, IA (IAN/IAP) and IB (IBN/IBP) are connected to current transfo rm ers that sense
the current on each phase of the line v ol tage. VA and VB are typically connected to voltage sensors
through resistor dividers.
The multiplexer control circuit (MUX_CTRL signal ) controls multipl exer advance, FI R i ni tiation and VREF
chopping. Addit i onal ly, MUX_CTRL launches each pass through the CE pro gram. Conceptually,
MUX_CTRL is clocked by CK32, the 32768 Hz clock from the P LL block. The behavi or of MUX_CTRL is
governed by MUX_ALT, EQU[2:0], CHOP_E[1:0] and MUX_DIV[3:0].
The MUX_ALT bit requests an al ternative multiplexer frame. The bi t may be asserted on any MPU cycle
and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT
will cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate multiplexer
frame.
Another control i nput to the MUX is MUX_DIV[3:0]. These four bits can request from 1 to 10 mul tiplexer
states per frame. The multiplexer always start s at the beginning of its list and proceeds unt i l the number
of states defined by MUX_DIV[3:0] have been converted.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
12 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
The duration of each mul tiplexer state depends on the number of ADC samples processed by the FIR,
which is set by FIR_LEN[1:0]. Each multiplexer state will start on the rising edge of CK32. The MUX_CTRL
signal sends an FIR_S T ART command to begin the calculation of a sample value from t he ADC bit
stream by the FIR. Upon receipt of the FIR_DONE signal from the FI R, the multiplexer will wait until the
next CK32 rising edge to increment it s state and initiate the next FIR co nversion. FIR convers i ons require
1, 2, or 3 CK32 cycles. The number of CK 32 cycles is determined by FIR_LEN[1:0], as shown in Table 2.
1.2.3 A/D Converter (ADC)
A single delta-sigm a A/D converter digitizes the volt age and current inputs t o the 71M6531D/F and
71M6532D/F. T he resolution of the A DC is programmable using the I/O RAM M40MHZ and M26MHZ bits
(see Table 2). The CE code must be tailored for use with the sel ected ADC resolution.
Table 2: ADC Resolutio n
Setting for
[M40MHZ, M26MHZ] FIR_LEN[1:0] CK32
Cycles FIR CE Cycles Resolution
[00], [10] or [11] 0
1
2
1
2
3
138
288
384
18 bits
21 bits
22 bits
[01] 0
1
2
1
2
3
186
384
588
19 bits
22 bits
24 bits
Initiation of each ADC conversion is controlled by MUX _CTRL as described above. At the end of each
ADC conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX
selection.
1.2.4 FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.
The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each
ADC conversion, the output data is stored into the fi xed CE RAM location d etermined by the mul tiplexer
selection as shown in Table 3. FIR data is stored LSB justified, but shifted left by ei ght bits.
Table 3: ADC RAM L o cations
Address (HEX)
Name
Address (HEX)
Name
0x00 IA 0x09 AUX
0x01 VB 0x0A TEMP
0x02 IB 0x0B VBAT
0x03 VA
1.2.5 Voltage References
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques.
The reference is t rim m ed to minimize er rors caused by compon ent mismatch and drift. The result is a
voltage output with a predictable temp erature coeffici ent.
The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU using
CHOP_E[1:0] (IORAM 0x2002[5:4]). The CHOP_E[1:0] field enables the MP U to operate the chopper circuit
in regular or inverted opera tion, or in toggling mode. W hen the chopper circuit is toggled in between
multiplexer cycles, DC offsets on the m easured signals will automatically be averaged out.
The general topology of a chopped amplifier is shown in Figure 3.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 13
Figure 3: General Topolo gy of a Chopped Amplifier
It is assumed that an offset voltage Vof f appears at the positive amplifier input. W i th all s witches , as
controlled by CROSS, in the A position, the output voltage is:
Voutp – Voutn = G (Vinp + Voff – Vi nn) = G (V i np – Vinn) + G Voff
With all switches set to the B position by appl ying the inverted CROSS signal, the output voltage is:
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G V off, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
Thus, when CROSS i s toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the
output as positive and negative, whi ch results in the offset effectively being eliminated, regardless of i ts
polarity or magnit ude.
When CROSS is high, the connection of the amplifier input devices is reversed. This preserves the overall
polarit y o f that amp lif ier gain; it in ver ts i ts inp u t o ffse t. By altern ately r eversing the connection, the
amplifier’s of fset is averaged t o zero. This removes the m ost significant long-term drift mechanism in the
voltage reference. The CHOP_E[1:0] field controls the behavior of CROSS. The CROSS signal will reverse
the amplifier connection in the voltage reference in order to neg ate the effects of i ts offset. On the first
CK32 rising edge after the last multiplexer state of i ts sequence, the m ultiplexer will wai t one additional
CK32 cycle before beginning a new frame. At the beginning of this cycle, the val ue of CROSS will be
updated according to the CHOP_E[1:0] field. The extra CK32 cycle allows ti m e for the chopped V RE F to
settle. During this cycle, MUXSYNC is held high. The leading edge of MUXS Y NC ini tiates a pass
through the CE program sequence. The beginning of t he sequence is the serial readout of the four RTM
words.
CHOP_E[1:0] has four stat es: positive, reverse and two toggle states. In the positive state, CHOP_E[1:0]
= 01, CROSS and C HOP_CLK are held low. In the reverse state, CHOP_E[1:0] = 10, CROSS and
CHOP_CLK are held hi gh. In the first toggle state, CHOP_E[1:0] = 00, CROSS is automatically toggled
near the end of each multiplexer frame and an ALT frame is forced during the last multiplexer frame in each
SUM cycle. It is desirable that CROSS take on alternate v al ues during each ALT frame. For this reason,
if CHOP_E[1:0] = 00, CROSS will not toggle at the end of the m ul tiplexer frame immedi ately preceding
the ALT frame in each accumulation interval.
Figure 4: CROSS Signal with CHOP_E[1:0] = 00
Figure 4 shows CROSS over two accu m ul ation interval when CHOP_E[1:0] = 00: At the end of the first
interval, CRO S S is low, at the end of the second interval, CROSS is high. The offset error for the two
temperature measurements taken during the ALT multiplexer fram es will be averaged to zero. Note that
G
-
+Vinp Voutp
Voutn
Vinn
CROSS
A
B
A
B
A
B
A
B
Multiplexer frames
Accumulation interval n Accumulation interval n+1
2 43 251925201 2 43 251925201
Alternative MUX cycle
Multiplexer frames
Alternative MUX cycle
CROSS CROSS
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
14 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
the number of m ul tiplexer frames in an accumulation int erv al i s always even. Operation with
CHOP_E[1:0] = 00 does not require control of the cho pping m echanism by the MPU while eli m i nating the
offset for temperature measurement.
In the second toggl e state, CHOP_E[1:0] = 11, no ALT frame is f orced during the l ast multiplexer cycle i n
an accumulati on i nterval and CROSS always toggles near t he end of each multiplexer frame.
The internal bias v ol tage, VBIAS (typically 1.6 V), is used by the ADC when measuring the temperature
and battery monitor signals.
1.2.6 Temperature Sensor
The 71M6531D/F and 71M6532D/F include an on-chip temperature sensor implemented as a bandgap
reference. I t is used to determine t he die temperature. The MPU may request an alternate mult i pl exer
cycle containi ng the temperature se nsor output by as serti ng MUX_ALT.
The primary use of the temperature data is to determine the magnitude of compensation required to offset
the thermal drift in the system (see Section 3.4 Temperature Compensat i on).
1.2.7 Battery Monitor
The battery voltage i s measured by the A DC during alternati ve multiplexer f rames if the BME (Battery
Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45 kΩ load resistor is applied to
the battery and a sc al ed fraction of the b attery voltage is applied to the ADC input. After each alternative
MUX frame, the result of the ADC conversion is available at XRAM address 0x0B . BME is ignored and
assumed zero whe n sy st em power is not av ai l abl e (V1 < VBIAS). See Section 5.4.4 Battery Monitor.
1.2.8 AFE Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB and
VB) are sampled, and the ADC counts obtained are stored in XRAM where they can be ac cessed by the
CE and, if necessary, by the MPU. Alternate multiplexer cycles are initi ated less frequent l y by the MPU to
gather access t o the slow temperature and battery sig nals.
Figure 5 shows the block diagram of the AFE, with current i nputs shown only as different ial pair of pins
(for the 71M6531D/F, the current input for phase A is a single pin [IA] ).
Figure 5: AFE Block Diagram (Shown for the 71M 6532D/F)
∆Σ ADC
CONVERTER
VREF
ADC_E
MUX
VREF
VBIAS
VREF
VREF_DIS
VBIAS
VREF_CAL
VBAT
VADC
MUX_DIV
MUX_ALT
EQU
22
FIR
FIR_LEN
VA
IBP
VB
IAP
IAN
IBN
TEMP
SENSOR
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 15
1.3 Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately
measure energy. The CE calculations a nd processes includ e:
• Multiplication of each current sample with its associated voltage sample t o obtain the energy per
sample (when multiplied with the con st ant sample time).
• Frequency-insensitive delay cancellation on all four channels (to compen sat e for the delay bet ween
samples caused by the multiplexing scheme).
• 90° phase shifter (for VAR calculati ons).
• Pulse generati on.
• Monitoring of t he i nput signal frequency (for frequency and phase informatio n).
• Monitoring of t he i nput signal amplitude (for sag detection).
• Scaling of the processed samples ba sed on calibration co efficients.
• Scaling of all samples based on temperature compensat ion information (71M6532D/F only).
The CE program resides in flash memory. Common access to flash memory by CE and MPU is controlled
by a memory share circuit. Each CE instruction word is two bytes long. A l l ocat ed flash space for the CE
program cannot ex ceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the
CE code each ti m e m ul tiplexer state 0 begins. The code pass ends when a HALT instruction is executed.
For proper operation, the code pass must be completed before the multiplexer c ycle ends (see Section
2.2 System Timing Summary).
The CE program must begin on a 1-KB boundary of the flash address. The I/O RAM register CE_LCTN[7:0]
defines which 1-KB boundary contains the CE code. Thus, the first CE instr uct ion is located at
1024*CE_LCTN[7:0].
The CE can access up t o 4 KB of data RAM (XRAM), or 1024 32-bit data words, st arting at RAM address
0x0000.
The XRAM can be accessed by the FIR filter block, the RTM circuit, t he CE, and the MPU. Assigned time
slots are reserved for FIR, and MPU, respectively, to prevent bus content i on for XRAM data a ccess.
The MPU can read and write the XRAM as the primary means of data comm unication between the two
processors. Table 4 s hows the CE addr esses in XRAM allocated to analog inputs from the AFE.
Table 4: XRAM Locations for ADC Results
Address (HEX)
Name
Description
0x00 IA Phase A cur rent
0x01 VA Phase A voltage
0x02 IB Phase B cur rent
0x03 VB Phase B voltage
0x04...0x09 – Not used
0x0A TEMP Temperature
0x0B VBAT Battery Voltage
The CE is aide d by suppor t hardwar e to facili tate imple mentation o f equa tions, pulse co unters and
accumulators. This hardware is controlled through I/O RAM l ocations EQU[2:0] (equation assist ), the
DIO_PV and DIO_PW (pulse count assist) bits and PRE_SAMPS[1:0] and SUM_CYCLES[5:0] (accumulation
assist).
PRE_SAMPS[1:0] and SUM_CYCLES[5:0] support a dua l leve l accum ulation sche me where the first
accumulator accumulates results from PRE_SAMPS[1:0] samples and the second accumulator accumulates
up to SUM_CYCLES[5:0] of the first accumulator results. The integration time for each energy out put is
PRE_SAMPS[1:0] * SUM_CYCLES[5:0]/2520.6 (with MUX_DIV[3:0] = 1). The CE hardware issues the
XFER_BUSY int errupt when the accumulation is complet e.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
16 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
1.3.1 Meter Equations
The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE i n order to support various
meter equations. This assistance is controlled through I/O RAM locat i on EQU[2:0] (equation assist). The
Compute Engine (CE) firmware f or residential configu rations implement s t he equations listed in Table 5.
EQU[2:0] specifies the equation to be used based on the number of phases used for met eri ng.
Table 5: Meter Equations
EQU[2:0] Description Watt and VAR Formula Mux
Sequence ALT Mux
Sequence
Element
0
Element
1
Element
2
0
1 element, 2 W,
1φ with neutral
current sense
VA · IA VA · IB N/A Sequence is
programmable
with
SLOTn_SEL[3:0]
Sequence is
programmable wit h
SLOTn_ALTSEL[3:0]
1
1 element, 3 W,
1φ VA(IA-
IB)/2 N/A N/A
2
2 element, 3 W,
3
φ
Delta
VA · IA VB · IB N/A
Not all CE codes support all equations.
1.3.2 Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled
with the RTM_E bit. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output
enabled by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag
bit. See Figure 20 f or the RTM output format. RTM is low when not in use.
1.3.3 Pulse Generators
The 71M6531D/F and 71M6532D/F provide four pulse generators, RPULSE, WPULSE, XPULSE and
YPULSE, as well as increased hardware support for the two origi nal pulse generat ors (RPULSE and
WPULSE). The pulse generators can be used to output CE status indicators, SAG for exam ple, t o DIO pins.
The polarity of the pulses may be inverted with the PLS_INV bit. When this bit is set , the pulses are acti ve
high, rather than t he m ore usual active low. PLS_INV inverts all the pulse out puts.
XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse out puts. Pins DIO8
and DIO9 are used for these pulses. Ge nerall y, the XPULSE and YPULSE outputs ar e updated once on
each pass of the CE code, resulting in a pul se frequency up t o a m aximum of 1260Hz (assuming a MUX
frame is 13 CK32 cycles).
The YPULSE pin can be used by the CE code t o generate interrupts based on sag eve nts. This method
is faster than checking the sag bits by the MPU at every CE_BUSY interrupt. See Section 4.3.6 CE Status
and Control for details.
RPULSE and WPULSE
During each CE code pass, the hardware st ores exported WP ULSE AND RPULSE sign bits in an 8-bit
FIFO and outputs t hem at a specified interval. This permits t he CE code to calc ulate the RPULSE and
WPULSE output s at the beginning of its code pass and to rel y on hardware to spread them over the MUX
frame. The FIFO is reset a t the beginning of each MUX frame. The PLS_INTERVAL register co ntrols the
delay to the first pulse update and the interval between subsequent updates. Its LSB is 4 CK_FIR cycles.
If zero, the FIFO i s deactivated and t he DFFs are updat ed i m m ediately. Thus, NINTERVAL is
4 * PLS_INTERVAL.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 17
Since the FIFO resets at the begin ni ng of each MUX frame, the user must specify PLS_INTERVAL so that
all of the pulse updat es are output before
Hardware also provides a maximum pulse width feature. The PLS_MAXWIDTH register selects a maximum
negative pulse widt h to be Nmax updates according to t he formula: Nmax = (2*PLS_MAXWIDTH+1). If
PLS_MAXWIDTH = 255, no width checki ng is performed.
the MUX frame completes. For inst ance, if the CE code outputs
5 updates per MUX interval and if t he M UX i nterval is 1950 cycle s long, the ideal value for the interval is
1950/5/4 = 97.5. If PLS_INTERVAL = 98, the fifth output wil l occur too late and be l ost . In this case, the
proper value for PLS_INTERVAL is 97.
The WPULSE and RPULSE pulse gen erator outputs are avai lable on DIO6 and DIO7, respectively. They
can also be output on OPT_TX (see OPT_TXE[1:0] for details).
1.3.4 Data RAM (XRAM)
The CE and MPU use a single general-purpose Data RAM (also referred to as XRAM). The Data RAM i s
1024 32-bit words, shared between the CE and the MPU using a time-multiplex method. This reduces
MPU wait states wh en accessing CE da ta. When the MPU and CE are clocking at maxi m um frequency
(10 MHz), the DRA M wil l make up to four acc esses during each 100 ns interval. These consist of two
MPU accesses, one CE access and on e SPI access.
The Data RAM i s 32 bits wide and uses an external multiplexer so as to appear by te-wide to the MPU.
The Data RAM hardware will convert an MPU byte write op eration into a read-modify-write operation t hat
requires two Data RA M accesses. The se cond access is guaranteed to be available because the MPU
cannot access the XRAM on two consecutive instructions unless it is usi ng the same address.
In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE
data memory. Li kewise, the amount of memory the CE uses is not limited by the size of a dedicated CE
data RAM.
1.3.5 Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the vol tage and current f or that
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
o
delay
o
delay
ft
T
t360360 ⋅⋅=⋅=
φ
Where f is the f requency of the input signal and tdelay is the sampling delay between voltage and current.
In traditional meter ICs, sampling is accomplished by using two A/D converters per phase (one f or voltage
and the other one for current) cont roll ed to sample simul taneously. Teridian’ s patented Single-Converter
Technology®, however, exploits the 32-bit signal proce ssi ng capability of i ts CE to implement “con st ant
delay” all-pass filters. These all-pass filters correct for the conversio n time difference b etween the voltage
and the correspondi ng current samples that are obtained with a single m ultiplexed A/D convert er.
The “constant del ay” all-pass filters provide a broad-band delay β, that is precisely matched to the differ-
ence in sample time between the vol tage and the current of a given phase. This digital filter does not af-
fect the amplitude of the signal, but provides a precisely controlled phase response. The delay compen-
sation implemented in the CE aligns the voltage samples with their correspon di ng current samples by
routing the volt age samples through the all-pass filter, thus delaying the voltage samples by β, resulting in
the residual phase error β – Ф. The resi dual phase error is negli gi ble, and is typically less than ±1.5 milli-
degrees at 100H z, thus it does not contribut e to errors in the energy measuremen ts.
1.3.6 CE Functional Overview
The ADC processes o ne sample per channel per multiplexer cycle. Figure 6 sho ws t he timing of the
samples taken during one multiplexer cycle.
The number of sampl es processed d uring one accumulat i on cycle is controlled by PRE_SAMPS[1:0]
(IORAM 0x2001[7:6]) and SUM_CYCLES[5:0] (IORAM 0x2001[5:0]). The integration time for each energy
output is:
PRE_SAMPS[1:0] * SUM_CYCLES[5:0] / 2520.6, where 2520.6 is the sample rate [ Hz]
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
18 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
For exampl e, PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] = 50 will e stablish 2100 sampl es per accumulati on
cycle. PRE_SAMPS[1:0] = 100 and SUM_CYCLES[5:0] = 21 will result in the exact same accumulation
cycle of 2100 samples or 833 ms. Aft er an accumulation cycle is completed, the XFER_BUSY i nterrupt
signals to the M P U that accumulated data are available.
Figure 6: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle status information, such as sag data and the digitized input signal, is available to the MPU.
Figure 7: Accumulation Interval
Figure 7 shows the accumulation int erval resulting from PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] =
50, consisting of 2100 samples of 397 µs each, followed by the X F E R_B USY interrupt. The sampling in
this example is applied to a 50 Hz signal.
There is no correlat i on between the line signal frequency and the choice of PRE_SAMPS[1:0] or
SUM_CYCLES[5:0] (even though when SUM_CYCLES[5:0] = 42 one set of SUM_CYCLES[5:0] happens to
sample a period of 16.6 ms). Furthermore, sampling does not have to start when the line v ol tage crosses
the zero line and the length of the accumulation interval need not be an integer multiple of the signal cycles.
VA
IA
1/32768Hz =
30.518µs
13/327 68Hz = 397µs
per mux cycle
IB
VB
XFER_BUSY
Interrupt to MPU
20ms
833ms
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 19
1.4 80515 MPU Core
The 71M6531D/F and 71M6532D/F include an 80515 MPU (8-bit, 8051-compatible) t hat processes most
instructions in one clock cycle. Using a 10-MHz clock results in a processing throughput of 10 MIPS. The
80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution
phases. Normally, a machine cycl e is alig ned w ith a memory fetch, therefore, most of the 1-by te instructions
are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average performance
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Table 6 shows the CKMPU frequency as a function of the allowed combinations of the MPU cl ock divider
MPU_DIV[2:0] and the MCK divider bits M40MHZ and M26MHZ. Actual processor clocking speed can be
adjusted to the total processing demand of the application (metering calculations, AMR management, memo-
ry management, LCD driver management and I/O managem ent) using the I/O RAM field MPU_DIV[2:0]
and the MCK divider bits M40MHZ and M26MHZ, as shown in Table 6.
Table 6: CKMPU Clock Frequencies
MPU_DIV [2:0] [
M40MHZ, M26MHZ
] Values
[1,0] [0,1] [0,0]
000 9.8304 MHz 6.5536 MHz 4.9152 MHz
001 4.9152 MHz 3.2768 MHz 2.4576 MHz
010 2.4576 MHz 1.6384 MHz 1.2288 MHz
011 1.2288 MHz 819.2 kHz 614.4 kHz
100 614.4 kHz 409.6 kHz 307.2 kHz
101 307.2 kHz 204.8 kHz 153.6 kHz
110 153.6 kHz 102.4 kHz 76.80 kHz
111 153.6 kHz 102.4 kHz 76.8 kHz
Typical measurement and metering functions based on the results provided by the internal 32-bit compute
engine (CE) are available for the MPU as part of Teridian’s standard library. Teridian provides demonstration
source code to help re duce the design cycle.
1.4.1 Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory
organization in the 80515 is similar to that of the industry st andard 8051. There are fou r m emory areas:
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data mem ory (Internal RAM). Table 7 shows the memory map.
Program Memory
The 80515 can address up to 64 KB of program memory space from 0x0000 to 0xFFFF. Program memory
is read when the M PU fetches instru ct ions or performs a M O V C operation. Ac cess to program mem ory
above 0x7FFF is controlled by the FL_BANK[2:0] regist er (S FR 0xB6).
After reset, the MPU starts prog ram execution from program memory locat i on 0x0000. The lower p art of
the progra m m em ory includes reset and int errupt vectors. The inter r up t vectors are sp ac ed at 8-byte
intervals, starting from 0x0003.
MPU External Da ta Memory (XRAM)
Both internal and ex ternal memory is physically located on the 71M6531 device. The external memory
referred to in t hi s documentation is only external to the 80515 M P U core.
4 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 3 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limi t.
If the MP U ov erwrit es th e CE’s worki ng RA M, the CE’ s outp ut may b e co rrupte d. If t he CE is di sabled,
the fir st 0x40 byt es of RAM ar e still unu sable while MUX_DIV[3:0] ≠ 0 because the 71M6531 ADC
writes to these locations. Setting MUX_DIV[3:0] = 0 dis ables t he AD C outp ut prev enti ng the CE fr om
writing t he fir st 0x4 0 byte s of RAM.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
20 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A inst ruction. The MPU reads external data m em ory by executing a MOVX A,@Ri or MO V X
A,@DPTR instruction (SFR PDATA provides t he upper 8 bytes for the MOVX A,@Ri instr uct ion).
Internal and External Memory Map
Table 7 shows the address, type, use and size of the vari ous memory components.
Only the memory ranges shown in Table 7 contain physic al m em ory.
Table 7: Memory Map
Address
(hex)
Memory
Technology
Memory
Type
Name Typical Usage Memory Size
(bytes)
00000-1FFFF/
00000-3FFFF Flash
Memory Non-volatile Program me m ory
for MPU and CE
MPU Program and
non-volatile d ata 128 KB/
256 KB†
CE program (on 1
KB boundary)
8 KB max.
0000-0FFF Static RAM Volatile External RAM
(XRAM) Shared by CE and
MPU 4 KB
2000-20BF,
20C8-20FF Static RAM Volatile Configuration RAM,
I/O RAM Hardware control 256
20C0-20C7 Static RAM Non-volatile
(battery) Configuration RAM,
I/O RAM Battery-buffered
memory 8
0000-00FF Static RAM Volatile Internal RAM Part of 80515 Core 256
† Memory size depends on the IC. See Section1.5.5 Physical Memory for details.
MOVX Addressing
There are two ty pes of instructions differing in whether they provide an 8-bit or 16-bit indirect addres s to
the external data RA M .
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current regi st er bank provide the ei ght
lower-ordered bits of address. The eight hi gh-ordered bits of the address are specified with the PDATA
SFR. This method allows the user paged acce ss (256 pages of 256 bytes each) to all ranges of the
external data RAM.
In the second type of MOVX instruction, MOVX A,@DPTR, the dat a pointer generates a 16-bit address.
This form is faster a nd m ore efficient when accessing very large data arrays (up to 64 KB), since no
additional instructi ons are needed to set up the eight high order ed bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access a nd two with paged a cc ess, to the entire 64 KB of external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit regist er that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is cal led
DPTR, the second dat a pointer is called DPTR1. The data pointer select bi t, located in the LSB of the DPS
register (DPS[0]), chooses the act ive pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is selected
when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers
are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected
DPTR for any activity.
The second data pointer may not be support ed by certain compil ers.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster
compared to the reloading of DPTR from regist ers. Any interrupt routine using DPTR1 must save
and restore DPS, DPTR and DPTR1, which increase s stack usage and slows do wn interrupt latency.
By selecting the E vatronics R80515 core in the Keil compiler project settings and by using the
compiler directive “MODC2” , dual data p ointer s are enabled in certain library routines.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 21
An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometim es ref erred
to as USR2). It d ef in es t he hi gh byt e of a 16-bit address when reading or writing XDATA with the instruction
MOVX A,@Ri or MOVX @Ri,A.
Internal Data Memory Map an d Access
The Internal data mem ory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory
address is always 1 byte wide. Table 8 sho ws the internal data m em ory m ap.
The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory
is available only by direct addressing
Table 8: Internal Data Mem ory Map
. Indirect addressing of this area accesses the upper 128 bytes of
Internal RAM. The l ower 128 bytes contain working registers and bit addressable memory. The lower 32
bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select
which bank is i n use. The next 16 bytes form a block of bit addressable m emory space at bit addresses
0x00-0x7F. All of the bytes in the low er 128 bytes are accessible through direct or indirect addressi ng.
Address Range Direct addressing Indirect addressing
0x80 0xFF Special Function Registers (SFRs) RAM
0x30 0x7F Byt e addressable area
0x20 0x2F Bit addressable area
0x00 0x1F Register ban ks R0…R7
1.4.2 Special Function Registers (SFRs)
A map of the Special Function Registers is shown in Table 9.
Only a few address es in the SFR memory space are occupied, the others are not i mplem ented. A read
access to unimplemented addresses will return undefined data, while a write access will have no effect.
SFRs specific t o the 71M6531D/F and 71M6532D/F are shown i n bold print on a gray field. The registe rs
at 0x80, 0x88, 0x90, etc., are bit addressable, all others are byte addressable. See the restrictions for the
INTBITS regis ter in Table 14.
Table 9: Special Function Regis ter Map
Hex/
Bin
Bit
Addressable
Byte Addressable Bin/
Hex
X000
X001
X010
X011
X100
X101
X110
X111
F8
INTBITS
FF
F0
B
F7
E8 IFLAGS EF
E0 A E7
D8
WDCON
DF
D0
PSW
D7
C8 T2CON CF
C0 IRCON C7
B8
IEN1
IP1
S0RELH
S1RELH
PDATA
BF
B0
P3 FLSHCTL FL_BANK PGADR
B7
A8 IEN0 IP0 S0RELL AF
A0 P2 DIR2 DIR0 A7
98
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
EEDATA
EECTRL
9F
90
P1 DIR1 DPS ERASE
97
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 8F
80 P0 SP DPL DPH DPL1 DPH1 PCON 87
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
22 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
1.4.3 Generic 80515 Special Function Registers
Table 10 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional
descriptions of the registers can be f ound at the page numbers listed in the table.
Table 10: Generic 80515 SFRs - Location and Reset V alues
Name Address
(Hex) Reset value
(Hex) Description Page
P0 0x80 0xFF Port 0 24
SP 0x81 0x07 Stack Pointer 23
DPL 0x82 0x00 Data Pointer Low 0 23
DPH 0x83 0x00 Data P oi nter High 0 23
DPL1 0x84 0x00 Data Pointer Low 1 23
DPH1 0x85 0x00 Data Pointer High 1 23
PCON 0x87 0x00 UART Speed Control, Idle and Stop mode C ontrol 28
TCON 0x88 0x00 Tim er/ Counter Control 31
TMOD 0x89 0x00 Timer Mod e Cont rol 29
TL0 0x8A 0x00 Ti m er 0, low byte 28
TL1 0x8B 0x00 Ti m er 1, high byte 28
TH0 0x8C 0x00 Timer 0, l ow byte 28
TH1 0x8D 0x00 Timer 1, hi gh byte 28
CKCON 0x8E 0x01 Clock Control (Stretch=1) 24
P1 0x90 0xFF Port 1 23
DPS 0x92 0x00 Data Pointer select Register 20
S0CON 0x98 0x00 Serial P ort 0, Control Regist er 27
S0BUF 0x99 0x00 Serial Port 0, Data Buffer 26
IEN2 0x9A 0x00 Interrupt E nable Register 2 31
S1CON 0x9B 0x00 Serial Port 1, Control Regist er 27
S1BUF 0x9C 0x00 Serial Port 1, Data Buffer 26
S1RELL 0x9D 0x00 Serial Port 1, Reload Register, low byte 26
P2 0xA0 0xFF Port 2 23
IEN0 0xA8 0x00 Interrupt Enable Regist er 0 30
IP0 0xA9 0x00 Interrupt Priority Register 0 33
S0RELL 0xAA 0xD9 Serial P ort 0, Reload Register, l ow byte 26
P3 0xB0 0xFF Port 3 23
IEN1 0xB8 0x00 Interrupt Enable Re gist er 1 31
IP1 0xB9 0x00 Interrupt Priority Register 1 33
S0RELH 0xBA 0x03 Serial Port 0, Reload Register, high byte 26
S1RELH 0xBB 0x03 Serial Port 1, Reload Register, high byte 26
PDATA 0xBF 0x00 High address byte for MOVX@Ri - also called USR2 20
IRCON 0xC0 0x00 Interrupt Request Cont rol Register 31
T2CON 0xC8 0x00 Polarity for INT2 an d INT3 31
PSW 0xD0 0x00 Program Status Word 23
WDCON 0xD8 0x00 Baud Rat e Control Register (o nly WDCON[7] bit used) 26
A 0xE0 0x00 Accumulator 23
B 0xF0 0x00 B Register 23
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 23
Accumulator (ACC, A, SFR 0xE0):
ACC is the accumulator reg ister . Most ins tructions use the accum ulator to hol d the operand . The
mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC.
B Register (SFR 0xF0):
The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register
to hold temporary dat a.
Program Status Word (PSW, SFR 0xD0):
This register contains various flags and control bits f or the selection of t he register banks (see Table 11).
Table 11: PSW Bit Functions (SFR 0xD0)
PSW Bit Symbol Function
7 CV Car ry flag.
6 AC Auxiliary Carry flag for BCD operations.
5 F0 General-purpose Flag 0 available for user.
F0 is not to be confused with the F0 fl ag i n the CESTATUS register.
4 RS1
Register bank select control bits. The contents of RS1 and RS0 select the
working regist er bank:
RS1/RS0 Bank selected Location
00 Bank 0 0x00 – 0x07
01 Bank 1 0x08 – 0x0F
10 Bank 2 0x10 – 0x17
11 Bank 3 0x18 – 0x1F
3 RS0
2 OV Overflow flag.
1 - User defined flag.
0 P Parity flag, affected by hardware t o i ndicate odd or even numb er of one bits in
the Accumulator, i.e. even parity .
Stack Pointer (SP, SFR 0x81):
The stack point er is a 1-byte register init ialized to 0x07 after reset. This register is incremente d before
PUSH and CALL inst ructions, causing t he st ack to begin at location 0x08.
Data Pointer:
The data point ers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL(SFR 0x82) and DPL1
(SFR0x84) and the highest is DPH (SFR0x83) and DPH1 ( SFR 0x85). The data poi nters can be loaded as
two registers (e.g. MOV DPL,#data8). They are generally used to access ext ernal code or data space
(e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter:
The program cou nter (PC) is 2 bytes wide and initialized to 0x0000 after re set. The PC is incremented
when fetching oper ation code or when operating on data from program memory.
Port Registers:
The I/O ports are controlled by Special Function Registers P0, P1 and P2 as shown in Table 12. The contents
of the SFR can be ob serv ed on corresponding pins on the chip. Writ i ng a 1 to any of the ports causes the
corresponding pin to be at high level (V3P3). Writing a 0 causes the corresponding pin to be held at a low
level (GND). The data direction registers DIR0, DIR1 and DIR2 define individual pins a s input or output
pins (see Sections 1.5.7 Digital I/O – 71M6531D/F or 1.5.8 Digital I/O – 71M6532D/F).
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
24 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 12: Port Registers
Register SFR
Address
R/W Description
P0
0x80 R/W Register fo r port 0 read and write operations.
DIR0
0xA2 R/W Data direction register for port 0. Setting a bit to 1 indicates that t he
corresponding pin is an output.
P1 0x90 R/W Register for p ort 1 read and write oper ations.
DIR1 0x91 R/W Data di rection register f or port 1.
P2 0xA0 R/W Register for port 2 read and writ e operations.
DIR2 0xA1 R/W Data direction register for port 2.
All DIO ports on t he chip are bi-directional. Each of them consists of a Latch (SFR P0 to P2), an output
driver and an input buffer, therefore t he MPU can output or read data through any of these ports. Even if
a DIO pin is configured as an output, t he state of the pin can still be read by the MPU, for example when
counting pulses issued via DIO pins that are under CE cont rol.
The technique of reading the status of or generating interrupts based on DIO pins configured as
outputs can be use d to implement pulse counting.
Clock Stretching (CKCON[2:0], SFR 0x8E)
The CKCON[2:0] field defines the stretc h m em ory cycles that could be used for MOVX inst ructions when
accessing slow external peripherals. The practical value of this register for t he 71M653x is to guarantee
access to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should not be
changed.Table 13 shows how the si gnals of the External M em ory Interface ch ange when stretch val ues
are set from 0 t o 7. The widths of the signals are counted in MP U clock cycles. The post-reset state of
the CKCON[2:0] field (001), which is shown in bold in the table, performs the MO V X instructions with a
stretch value equal to 1.
Table 13: Stretch Memory Cycle Width
CKCON[2:0] Stretch
Value Read signal width Write signal width
memaddr memrd memaddr memwr
000
0
1
1
2
1
001
1
2
2
3
1
010
2
3
3
4
2
011 3 4 4 5 3
100
4
5
5
6
4
101 5 6 6 7 5
110
6
7
7
8
6
111 7 8 8 9 7
1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
Table 14 shows the location and description of the SFRs spe cif i c to the 71M6531D/F and 71M6532D/F.
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs
Register
(Alternate Name)
SFR
Address
Bit Field
Name R/W Description
EEDATA 0x9E R/W I
2
C EEPROM interface d ata register.
EECTRL 0x9F R/W
I
2
C EEPR OM i nte r fac e co ntr ol register. See
Section 1.5.14 EEPROM Inter face for a
description of the command and status bits
available for EECTRL.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 25
Register
(Alternate Name) SFR
Address Bit Field
Name R/W Description
ERASE
(FLSH_ERASE) 0x94 W This register is used to initiate either the Flash
Mass Erase cycle or the Flash P age E rase cy cle.
See the Flash Memory section for details.
FL_BANK
0xB6[2:0]
R/W
Flash Bank Selection.
PGADDR
(FLSH_PGADR[5:0]) 0xB7 R/W
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase
cycle.
FLSHCRL
0xB2[0] FLSH_PWE R/W
Program Writ e E nabl e:
0: MOVX commands refer to XRAM
Space, normal operation (default).
1: MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
0xB2[1] FLSH_MEEN W
Mass Erase Enable:
0: Mass Erase disabled (default).
1: Mass Erase enabled.
Must be re-written for each new Mass Erase
cycle.
0xB2[6] SECURE R/W Enables security provisions that prevent external
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be
set. Attempt s t o writ e zero are ignored.
0xB2[7] PREBOOT R Indicates that the preboot sequence i s active.
IFLAGS
0xE8[0] IE_XFER R/W Th is flag m o
nitors the XFER_BUSY interrupt.
It is set by hardware a nd must be cleared by
the interrupt handler.
0xE8[1] IE_RTC R/W This flag monitors the RTC_1SEC int errupt. It
is set by the hardware and must be cleared by
the interrupt handl er.
0xE8[2] FWCOL1 R/W This flag indicates that a f l ash w rite was in
progress while t he CE was busy.
0xE8[3] FWCOL0 R/W This flag indicates that a flash write was
attempted when the C E was attempting to
begin a code pas s.
0xE8[4] IE_PB R/W This flag indicates that the wake-up pushbutton
was pressed.
0xE8[5] IE_WAKE R/W
This flag indicates that the MPU was awakened
by the autowake tim er.
0xE8[6] PLL_RISE R/W PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
0xE8[7] PLL_FALL R/W PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt f lag.
INTBITS
(INT0 … INT6)
0xF8[6:0] INT6 … INT0 R
Interrupt inputs. The MPU may read these bits
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug u se.
0xF8[7] WD_RST W The WDT is reset when a 1 is written to this
bit.
Only byte operation s on the entire INTBITS register should be used when
writing. The byte must ha ve all bits set except the bi ts that are to b e
cleared.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
26 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
1.4.5 Instruction Set
All instructions of the generic 8051 m i crocontroller are supported. A complete list of the instru ction set
and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG).
1.4.6 UARTs
The 71M6531D/F and 71M6532D/F include a UART (UART0 ) that can be programm ed to communicate
with a variety of A M R modules. A second UART (UART1) is connect ed to the optical port, as described
in Section 1.5.6 Optical Int erface.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows:
• UART0 RX: Serial input data are applie d at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
• UART0 TX: This pin is used to output the serial data. The byt es are output LSB first.
The 71M6531D/F and 71M6532D/F have several UART-related r egi st ers for the control and buffering of
serial data.
A single SFR register serves as both the t ransmit buffer and rec ei ve buffer (S0BUF, SFR 0x99 for UART0
and S1BUF, SF R 0x 9C for UART1). When written by the MPU, S0BUF and S1BUF act as transmit buffers for
their respective channels, and when read by the MPU, they act as re ceive buffers. Writing data to the
transmit buffer st arts the transmi ssion by the associated UART. Received data are avail abl e by reading
from the receiv e buffer. Both UARTs ca n sim ultaneously tran smi t and receive data.
WDCON[7] (SFR 0xD8) selects whet her timer 1 or the internal baud rate gen erator is used. All UART
transfers are programmable for parity enable, parity, 2 stop bits/ 1 sto p bit a nd XON /XOFF optio ns fo r varia ble
communication baud rates from 300 to 38400 bps. Table 15 shows how the b aud rates are calculat ed.
Table 16 shows the selectable UART operation modes.
Table 15: Baud Rate Generation
Using Timer 1
(
WDCON[7]
= 0)
Using Internal Baud Rate Genera tor
(
WDCON[7]
= 1)
UART0
2smod * f
CKMPU
/ (384 * (256-TH1))
2smod * f
CKMPU
/(64 * (210-S0REL))
UART1
N/A
f
CKMPU
/(32 * (210-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload regist ers
(S0RELL, S0RELH, S1RELL, S1RELH). SMOD is the SMOD bit in the SFR PCON register. TH1 is the high
byte of timer 1.
Table 16: UART Modes
UART 0
UART 1
Mode 0 N/A
Start bit, 8 data bits, parity, st op bi t, variable
baud rate (internal baud rate generator)
Mode 1 Start bit, 8 data bits, stop b i t, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, stop bit , variable baud
rate (internal baud rate generator)
Mode 2 Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/ 32 or 1/64 of fCKMPU
N/A
Mode 3 Start bit, 8 data bits, parity, stop bit, va-
riable baud rate (internal baud rat e ge-
nerator or timer 1)
N/A
Parity of serial data is available thro ugh the P flag of the ac cumulator. 7-bit serial modes with
parity, such as t hose used by the FLAG protocol, can be simulated by sett ing and reading bit 7 of
8-bit out put data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant 1.
8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control
bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B) SFRs
for transmit a nd RB81 (S1CON[2]) for receive operat ions.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 27
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-proces sor communicatio n in m ulti-processor sy st ems. In this case, t he slave processors hav e bi t
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave
processors compare the received by te with their addres s. If there is a match, the addressed slave will
clear SM20 or SM21 and receive the re st of the message. All other slaves will ign ore the message. After
addressing the slave, the host outputs the rest of the m essage with the 9th bit set to 0, so no additional
serial port receiv e i nterrupts will be generated.
UART Control Registers:
The functions of UART0 and UART1 dep end on the setting of the Serial Port Con trol Registers S0CON
and S1CON shown in Table 17 and Table 18, respectively and the PCON register shown in Table 19.
Since the TI0, RI 0, TI1 and RI1 bits are in an SFR bit addressable byte, common pract ice
would be to clear them with a bit operation, but this must be avoided
The proper way t o clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
. The hardware implements
bit operations as a byte wide read-modify-write hardware ma cro. I f an interrupt occ urs after
the read, but before the write, its flag will be cleared unintentionally.
Table 17: The S0CON (UART0) Register (SFR 0x98)
Bit
Symbol
Function
S0CON[7] SM0
The SM0 and SM1 bits set the UART0 mode:
Mode Description SM0 SM1
0 N/A 0 0
1 8-bit UART 0 1
2 9-bit UART 1 0
3 9-bit UART 1 1
S0CON[6] SM1
S0CON[5] SM20 Enable s t he inter-processor communication feature.
S0CON[4] REN0 If set, enable s serial reception. Cleared by software to disable reception.
S0CON[3] TB80 The 9th transmi tted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it perf orms (parity check, multiproce ss or
communicati on etc.)
S0CON[2] RB80 In Modes 2 and 3 it is t he 9
th
data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit i s not used. Must be cleared by
software.
S0CON[1] TI0 Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software.
S0CON[0] RI0 Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software.
Table 18: The S1CON (UART1) register (SFR 0x9B)
Bit
Symbol
Function
S1CON[7] SM
Sets the baud rate and mode for UART1.
SM Mode Description Baud Rate
0
A
9-bit UART
variable
1
B
8-bit UART
variable
S1CON[5] SM21 Enable s t he inter-processor communication feature.
S1CON[4] REN1 If set, enable s serial reception. Cleared by software to disable reception.
S1CON[3] TB81 The 9
th
transmitted data bit in Mode A. Set or clear ed by the MPU,
depending on the function it performs (parity check, m ul tiprocessor
communicati on etc.)
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
28 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Bit
Symbol
Function
S1CON[2] RB81 In Modes A and B, it is the 9
th
data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. M ust be cleared by software
S1CON[1] TI1 Transmit interrupt flag, set by hardware aft er completion of a serial transfer.
Must be cleared by software.
S1CON[0] RI1 Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Table 19: PCON Registe r Bi t Descri p tio n (S F R 0x87)
Bit
Symbol
Function
PCON[7] SMOD The SMOD bit doubles the baud rat e when set
PCON[6:2] – Not us ed.
PCON[1] STOP Stops MPU flash access and M P U peripherals including timers and
UARTs when set unt i l an external interru pt is received.
PCON[0] IDLE Stops MPU flash access when set until an int ernal interrupt is received.
1.4.7 Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every 12 MPU clock cycles. In count er mode, the register is
incremented when the falling edge is observed at the corresponding input sig nal T0 or T1 (T0 and T1 a re
the timer gating inputs derived from certain DIO pins, see Section 1.5.7 Digital I/O). Since it takes 2 machine
cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU).
There are no restrictions on the duty cycle, however to ensu re proper recognition of the 0 or 1 state, an
input should be stable for at least 1 ma chine cycle.
Four operating m odes can be selected f or T im er 0 and Timer 1, a s shown in Table 20 and Table 21. The
TMOD Register, shown in Table 22, is used to select the appropriate m ode. The timer/counter operation
is controlled by the TCON Regi st er, which is shown in Table 23. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in
the TCON register start their associated timers when set.
Table 20: Timers/Counters Mode Description
M1
M0
Mode
Function
0 0 Mode 0
13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register
and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer
1, respectively). The 3 high order bits of TL0 and TL1 are held at zero.
0 1 Mode 1 16-bit Counter/Timer mode.
1 0 Mode 2 8-bit auto-reload Counter/ T im er. T he reload value is kept i n TH0 or
TH1, while TL0 or TL1 is incremented every machine cycle. When TL(x)
overflows, a va lue from TH(x) is copied to TL(x) (where x = 0 for
counter/timer 0 or 1 for counter/timer 1.
1 1 Mode 3 If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Count ers.
In Mode 3, TL0 is affected by TR0 and g ate control bits and sets the TF0 flag on overflow, while TH0
is affected by the TR1 bit and the TF1 flag is set on overf l ow.
Table 21 specifies the combination s of operation modes allowed for Timer 0 and Timer 1.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 29
Table 21: Allowed Timer/Counter Mode Combina tions
Timer 1
Mode 0 Mode 1 Mode 2
Timer 0 - mode 0 Yes Yes Yes
Timer 0 - mode 1 Yes Yes Yes
Timer 0 - mode 2 Not allowed Not allowed Yes
Table 22: TMOD Register Bit Descri ption (SFR 0x89)
Bit
Symbol
Function
Timer/Counter 1:
TMOD[7] Gate
If TMOD[7] is set, external i nput signal control is enabled for Counter 0.
external gate control. The TR1 bit in the TCON regi st er (SFR 0x88) must
also be set in orde r for Counter 1 to increm ent.
With these settings Counter 1 is incremented on every falling edge of the
logic signal applied to one or more of the interrupt sources controll ed by
the DI_RBP, DIO_R1, … DIO_RXX registers.
TMOD[6] C/T Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as a
timer.
TMOD[5:4] M1:M0 Selects the mode for Timer/Counter 1 as shown in Table 20.
Timer/Counter 0:
TMOD[3] Gate
If TMOD[3] is set, external input signal control is enabled for Co unter 0.
external gate control. The TR0 bit in the TCON register (SFR 0x88) must
also be set in order for Counter 0 to incr em ent.
With these settings Counter 0 is incremented on every falling edge of the
logic signal applied t o one or more of the interr upt sources controlled by
the DI_RBP, DIO_R1, … DIO_RXX registers.
TMOD[2] C/T Selects timer or counter operation. When set t o 1, a counter operation i s
performed. When cleared to 0, the corresponding register will fun ction as
a timer.
TMOD[1:0] M1:M0 Selects the mode for Timer/Counter 0, as sh own in Table 20.
Table 23: The TCON Register Bit Functions (SFR 0x88)
Bit Symbol Function
TCON[7] TF1 The Timer 1 ov erflow flag is set by hardware when Ti m er 1 overflows.
This flag can be cle ared by software and i s automatically cleared when an
interrupt is proce ssed.
TCON[6] TR1 Timer 1 run control bit. If cleared, Timer 1 stops.
TCON[5] TF0 Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag
can be cleared by sof tware and is automatically cleared when an i nterrupt
is processed.
TCON[4] TR0 Timer 0 Run cont rol bit. If cleared, Timer 0 stops.
TCON[3] IE1 Interrupt 1 edge flag i s s et by hardware when the falling edge on external
pin int1 is observed. Cleared when an interrupt is processed.
TCON[2] IT1 Interrupt 1 type control bit. Selects eit her the falling edge or low level on
input pin to cause an i nterrupt.
TCON[1] IE0 Interru pt 0 edge flag is set by hardware when the falling edge on external
pin int0 is observed. Cleared when an interrupt is processed.
TCON[0] IT0 Interrupt 0 type control bit. Selects eit her the falling edge or low level on
input pin to cause interrupt.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
30 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
1.4.8 WD Timer (Software Watchdog Timer)
There is no internal s oftware watchdog timer. Use the standard watchdog timer instead (see 1.5.16
Hardware Watchdog Timer).
1.4.9 Interrupts
The 80515 MPU provides 11 inter rupt sources with four priority levels. Each source has its own request
flag(s) located i n a special function register (TCON, IRCON and SCON). Each interrupt requested by the
corresponding fl ag can be individually e nabl ed or disabled by the enable bits in SFRs IEN0 (SF R 0x A8),
IEN1 (SFR 0xB8), and IEN2 (SFR 0x 9A ). Figure 8 sh ows the device interrupt structure.
Referring to Figure 8, interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) o r can originate from o ther parts of the 71M653x SoC (referred to as External Source s).
There are seven ex ternal interrupt sources, as seen in the leftmost part of Figure 8 , and in Table 24 and
Table 25 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from instruction, RETI. When an RETI is perform ed, the processor wil l return to
the instruction that would have been next when the interr upt occurred.
When the interrupt condition occurs, the processor will also indicate this by se tting a flag bit. This bit is
set regardless of whether the int errupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, after that, samples are polled by the hardware. If the sample indi cat es a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt
will be acknowled ged by hardware forcing an LCALL t o the appropriate vector address, if the following
conditions are met:
• No interrupt of equal or hi gher priority is al ready in progress.
• An instruction i s currently being executed and is not c om pl eted.
• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt f unct ions:
• The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26.
• The Timer/Counter control register s, TCON and T2CON (see Table 27 and Table 28).
• The interrupt request register, IRCON (see Table 29).
• The interrupt priority registers: IP0 and IP1 (see Table 34).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Bit
Symbol
Function
IEN0[7]
EAL
EAL
= 0 disables all interrupts.
IEN0[6] WDT Not used for interr upt control.
IEN0[5] – Not Used.
IEN0[4] ES0 ES0 = 0 disables serial channel 0 interrupt.
IEN0[3] ET1 ET1 = 0 disables timer 1 overflow interr upt.
IEN0[2] EX1 EX1 = 0 disables external interrupt 1.
IEN0[1] ET0 ET0 = 0 disables timer 0 overf low interrupt.
IEN0[0] EX0 EX0 = 0 disables external int errupt 0.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 31
Table 25: The IEN1 Bit Functions (SFR 0xB8)
Bit Symbol Function
IEN1[7]
–
Not used.
IEN1[6]
–
Not used.
IEN1[5] EX6 EX6 = 0 disables ext ernal interrupt 6: XFER_BUSY, RTC_1SEC, WD_NROVF
IEN1[4] EX5 EX5 = 0 disables external int errupt 5: EEPROM_BUSY
IEN1[3] EX4 EX4 = 0 disables external int errupt 4: PLL_OK (rise ), PLL_OK (fall)
IEN1[2] EX3 EX3 = 0 disables external int errupt 3: CE_BUSY
IEN1[1]
EX2
EX2 = 0 disables ext ernal interrupt 2: FWCOL0, FWCOL1, SPI
IEN1[0] – Not Used.
Table 26: The IEN2 Bit Functions (SFR 0x9 A)
Bit
Symbol
Function
IEN2[0] ES1 ES1 = 0 disables the serial channel 1 interrupt.
Table 27: TCON Bit Functi ons (SFR 0x88)
Bit
Symbol
Function
TCON[7]
TF1
Timer 1 overflow f lag.
TCON[6] TR1 Not used for interrupt cont rol.
TCON[5]
TF0
Timer 0 overflow f lag.
TCON[4]
TR0
Not used for int errupt control.
TCON[3] IE1 External interrupt 1 fl ag.
TCON[2] IT1
External interrupt 1 type control bit:
0 = interrupt on low l evel.
1 = interrupt on f al l i ng edge.
TCON[1]
IE0
External interrupt 0 flag
TCON[0] IT0
External interrupt 0 type control bit:
0 = interrupt on low l evel.
1 = interrupt on f al l i ng edge.
Table 28: The T2CON Bit Functions (S F R 0xC8)
Bit
Symbol
Function
T2CON[7]
–
Not used.
T2CON[6] I3FR Polarity control for external interrupt 3: CE_BUSY
0 = falling edge.
1 = rising edge.
T2CON[5] I2FR Polarity control for external interrupt 2: FWCOL0, FWCOL1, SPI
0 = falling edge.
1 = rising edge.
T2CON[4:0] – Not used.
Table 29: The IRCON Bit Functions (SFR 0xC0 )
Bit
Symbol Function
IRCON[7]
–
Not used
IRCON[6]
–
Not used
IRCON[5]
IEX6
1 = External interr upt 6 occurred and has not been cleared.
IRCON[4] IEX5 1 = External interrupt 5 occurred and has not been cl eared.
IRCON[3]
IEX4
1 = External interrupt 4 occurred an d has not been cleared.
IRCON[2]
IEX3
1 = External interrupt 3 occurred an d has not been cleared.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
32 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
IRCON[1]
IEX2
1 = External interrupt 2 occurred an d has not been cleared.
IRCON[0] – Not used.
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) will be automatically cleared by hardware when
the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
External MPU Interrupts
The seven external int errupts are the int errupts external to the 80515 core, i.e. signals that ori ginate in
other parts of the 71M6531D/F or 71M6532D/F, for ex am pl e the CE, DIO, RTC or EEPROM interface.
The external in terrupts are c onnected as described in Table 30. The polarity of interrupts 2 and 3 is
programmable in the M PU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be
programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts
4 through 6 are defined as rising-edge s ensitive. Thus, t he hardware signals attached to interrupt s 5 and
6 are inverted t o achieve the edge polarity shown in Table 30.
Table 30: External MPU Interrupts
External
Interrupt
Connection Polarity Flag Reset
0 Digital I/O High Priority see Section 1.5.7 automatic
1 Digital I/O Low Priority see Section 1.5.7 automatic
2 FWCOL0, F WCOL1, SPI falling automatic
3 CE_BUSY falling automatic
4 PLL_OK (risi ng), P LL_OK (falling) rising automatic
5 EEPROM busy falling automatic
6 XFER_BUSY, RTC_1SEC or WD_NROVF falling manual
External interrupt 0 and 1 can be mapped to pins on the dev i ce using DIO resource maps. See Section
1.5.7 Digital I/O for more information.
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the Flash Write description
in the Flash Memory section for mo re detail.
SFR enable bits must be set to permit any of these interru pts to occur. Likewise, each int errupt has its
own flag bit, which is set by the int errupt hardware, an d reset by the MPU interrupt handler.
XFER_BUSY, RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRIS E and PLLFALL have their
own enable and f l ag bi ts in addition to t he interrupt 6, 4 and enable and flag bits (see Table 31).
IE0 through IE X 6 are cleared automati cally when the hardware vectors to the interrupt handler. The other
flags, IE_XFER t hrough IE_PB, are clea red by writing a zero to them.
Since these bits are i n an SFR bit addressable byte, common pract ice would be to clear them
with a bit operation, but this must be avoided
The proper way t o clear the flag bits is to writ e a byte mask consisting of all ones exce pt for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware t o i gnore
ones written to them.
. The hardware implements bit operations as a
byte-wide read-modify-write hardware macro. If an interrupt occurs after the read , but before
the write, its flag wil l be cleared unintentionally.
Table 31: Interrupt Enable and Flag Bits
Interrupt Enable
Interrupt Flag
Interrupt Description
Name
Location
Name
Location
EX0 SFR A8[0] IE0 SFR 88[1] External interrupt 0
EX1 SFR A8[2] IE1 SFR 88[3] External interrupt 1
EX2 SFR B8[1] IEX2 SFR C0[1] External interrupt 2
EX3 SFR B8[2] IEX3 SFR C0[2] External interrupt 3
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 33
Interrupt Enable
Interrupt Flag
Interrupt Description
Name
Location
Name
Location
EX4 SFR B8[3] IEX4 SFR C0[3] External interrupt 4
EX5
SFR B8[4]
IEX5
SFR C0[4] External interrupt 5
EX6
SFR B8[5]
IEX6
SFR C0[5] External interrupt 6
EX_XFER 2002[0] IE_XFER SFR E8[0] XFER_BUSY interrupt (INT 6)
EX_RTC
2002[1]
IE_RTC
SFR E8[1] RTC_1SEC interrupt (INT 6)
IEN_WD_NROVF
20B0[0]
WD_NROVF_FLAG
20B1[0] WDT near overflow (INT 6)
IEN_SPI 20B0[4] SPI_FLAG 20B1[4] SPI Interface (INT2)
EX_FWCOL 2007[4]
IE_FWCOL0
SFR E8[3] FWCOL0 interrupt (INT 2 )
IE_FWCOL1
SFR E8[2] FWCOL1 interrupt (INT 2 )
EX_PLL 2007[5]
IE_PLLRISE
SFR E8[6] PLL_OK rise interrupt (INT 4)
IE_PLLFALL
SFR E8[7] PLL_OK fall interrupt (I NT 4)
IE_WAKE
SFR E8[5] AUTOWAKE flag
†
IE_PB
SFR E8[4] PB flag
†
† The AUTOWAKE and PB f l ag bi ts are shown in Table 31 because they behave similarly t o i nterrupt flags,
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push b utton or wake timeout. T he bi ts are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even i f the part is already awake.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32:
Table 32: Interrupt Priori ty Level Groups
Group
Group Members
0 External interrupt 0, Seri al channel 1 interrupt
1 Timer 0 interrupt, Ex ternal interrupt 2
2 External interrupt 1, External interrupt 3
3 Timer 1 interrupt, Ex ternal interrupt 4
4 Serial channel 0 interrupt , External inter rupt 5
5 External interrupt 6
Each group of i nterrupt sources can be programmed indi vidually to one of four priority lev el s (as show n i n
Table 33) by sett i ng or clearing one bit in the SFR interrupt priority register IP0 and one in IP1 (Table 34).
If requests of the same priority lev el are received simultaneously, an internal pol ling sequence as shown
in Table 35 determines which request i s serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priorit y Levels
IP1[x] IP0[x] Priority Level
0 0 Level 0 (lowest)
0 1 Level 1
1 0 Level 2
1 1 Level 3 (highest)
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
34 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 34: Interrupt Priorit y Registers (IP0 and IP1)
Register Address Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
(LSB)
IP0 SFR 0xA9
–
–
IP0[5] IP0[4] IP0[3] IP0[2] IP0[1] IP0[0]
IP1 SFR 0xB9
–
–
IP1[5] IP1[4] IP1[3] IP1[2] IP1[1] IP1[0]
Table 35: Interrupt Polling Sequence
External interrupt 0
Polling sequence
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 2
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
Interrupt Sources and Vectors
Table 36 shows the interrupts wit h their associated f lags and vector addre sses.
Table 36: Interrupt Vectors
Interrupt
Request Flag
Description Interrupt Vector
Address
IE0
External interrupt 0 0x0003
TF0 Timer 0 interrupt 0x000B
IE1 External interrupt 1 0x0013
TF1
Timer 1 interrupt 0x001B
RI0/TI0 Serial channe l 0 i nterrupt 0x0023
RI1/TI1 Serial channe l 1 i nterrupt 0x0083
IEX2
External interrupt 2 0x004B
IEX3 External interrupt 3 0x0053
IEX4 External interrupt 4 0x005B
IEX5
External interrupt 5 0x0063
IEX6
External interrupt 6 0x006B
FDS 6531/6532 005 Data Sheet 71M653 1D/ F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 35
Figure 8: Interrupt Structure
TCON.1 (IE0)
Individual
Enable Bits
S1CON.0 (RI1)
S1CON.1 (TI1)
Individual Flags
Internal
Source
>=1
TCON.5 (TF0)
TCON.3 (IE1)
TCON.7 (TF1)
S0CON.0 (RI0)
S0CON.0 (TI0) >=1
IRCON.1
(IEX2)
I2FR
IRCON.2
(IEX3)
I3FR
IRCON.3
(IEX4)
IRCON.4
(IEX5)
IRCON.5
(IEX6)
IEN0.7
(EAL)
IP1.0/
IP0.0
IP1.1/
IP0.1
IP1.2/
IP0.2
IP1.3/
IP0.3
IP1.4/
IP0.4
IP1.5/
IP0.5
Interrupt
Flags Priority
Assignment
Interrupt
Vector
Polling Sequence
Interrupt Enable
Logic and Polarity
Selection
DIO
Timer 0
Timer 1
CE_BUSY
UART0
EEPROM
XFER_BUSY
RTC_1S EX_RTC
PLL OK
External
Source
DIO_Rn
DIO_Rn
I2C
>=1
Flash
Write
Collision
>=1
IEN2.0
(ES1)
IEN0.1
(ET0)
IEN0.0
(EX0)
IEN1.1
(EX2)
IEN0.2
(EX1)
IEN1.2
(EX3)
IEN0.3
(ET1)
IEN1.3
(EX4)
IEN0.4
(ES0)
IEN1.4
(EX5)
IEN1.5
(EX6)
IE_XFER
IE_RTC
EX_XFER
>=1
EX_EEX
EX_SPI
IE_EEX
IE_SPI
IT0
IE_FWCOL1
SPI_FLAG
UART1
(optical)
0
2
1
3
4
5
6
No.
Flag=1 means
that an inter-
rupt has oc-
curred and
has not been
cleared
EX0 – EX6 are cleared
automatically when the
hardware vectors to the
interrupt handler
byte received
byte transmitted
overflow occurred
overflow occurred
byte received
byte transmitted
accumulation
cycle completed
PLL status
changed
CE completed code run and
has new status information
DIO status
changed
DIO status
changed
every second
BUSY fell
command
received
SPI I/F
Write attempt, CE
busy
2/2/2009
IE_FWCOL0
DIO
NR_OVF
EX_FWCOL
EX_PLL IE_PLLRISE
IE_PLLFALL
IEN_SPI
IEN_NR_
WDOVF WD_NROVF_FLAG
CE code start,
flash write busy
WDT near
overflow
>=1
MPU-external
sources MPU-internal
sources
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
36 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
1.5 On-Chip Resources
1.5.1 Oscillator
The oscillator of the 71M6531D/F and 71M6532D/F drives a standard 32.768 kHz watch crystal. These
crystals are accurat e and do not require a high-current oscillator circuit. The oscil l ator of the 71M6531D/F
and 71M6532D/F has been designed specifically t o handl e these crystals and is compatible with their
high impedance and l im i ted power handling ca pabi l ity.
Oscillator calibration can improve t he accuracy of both the RTC and meteri ng. Refer to Section 1.5.3
Real-Time Clock (RTC) for more information.
The oscillator is powered directly and only from VBAT, which therefore must be connected to a DC voltage
source. The oscillator requires approximately 100 nA, which is negligible compared to the internal leakage
of a battery.
The oscillator ma y appear to work when VBAT is not connec ted, but this m ode o f oper ation is not
recommended.
If VBAT is connect ed to a drained battery or disconnected, a battery test t hat sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unex pected reset during a battery test shoul d be interpreted as a battery failure.
1.5.2 Internal Clocks
Timing for the devi ce i s derived from the 32.768 kHz crystal oscillator output. On-chip timing f unct i ons
include:
• The MPU clock (CKMP U)
• The emulator cloc k (2 x CKMPU)
• The clock for the CE (CKCE)
• The clock driving the delta-sigma AD C al ong with the FIR (CKADC, CKFIR)
• A real time clock (RTC).
The two general-pur pose counter/time rs contained in the M P U are controlled by CK M P U (see Section
1.4.7 Timers and Counters). Table 37 provides a summary of the available cloc k f unct i ons.
Table 37: Clock System Summary
Clock Derived
From MCK Divider / [
M40MHZ, M26MHZ
] Brownout
Mode
÷2 / [1,0]
÷3 / [0,1]
÷4
**
/ [0,0]
CKPLL Crystal 78.6432 MHz 78.6432
MHz
78.6432
MHz
off
MCK CKPLL 39.3216 MHz 26.2144
MHz 19.6608
MHz 112 kHz
CKCE MCK 4.9152
MHz † 9.8304
MHz † 6.5536MHz 4.9152 MHz off
CKADC / CKFIR MCK 4.9152 MHz 6.5536 MHz 4.9152 MHz 28 kHz
CKMPU maximum MCK 9.8304 MHz*** 6.5536 MHz
*** 4.9152 MHz
*** 28 kHz
CK32 MCK 32.768 kHz 32.768 kHz 32.768 kHz
** Default state at power-up
*** The maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV[2:0].
† CKCE = 9.8304 MHz when CE10MHZ is set, 4.9152 MHz otherwise.
The master clock, MCK, is generated by an on-chip PLL that m ultiplies the oscillator output frequency
(CK32) by 2400 to provide approximately 80 MHz (78.6432 MHz). A di vider controlled by the I /O RAM
bits M40MHZ and M26MHZ permits scaling of M CK by ½, ⅓ and ¼. All other cloc ks are derived from this
scaled MCK output (making them multi ples of 32768 Hz), and the clock skew is m atched so that the rising
edges of CKADC, CKCE, CK32 and CKMPU are al igned.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 37
The PLL generates a 2x emulator clo ck which is controlled by the ECK_DIS bit. Since cloc k noise from
this feature may dist urb the ADC, it is recom m ended that thi s opt i on be avoided when possible.
The MPU clock fr equency CKMPU is determined by another di vider controlled by the I/O RAM field
MPU_DIV[2:0] and can be set to MCK/2(MPU_DIV+2) Hz where MPU_DIV[2:0] varies f rom 0 to 6. The circuit
also generates t he 2 x CKMPU clock for use by the emulator. The emulator clock i s not generated when
ECK_DIS is asserted.
During a power-on re set , [M40MHZ, M26MHZ] defaul ts to [0,0] and the MCK div i der i s set to divide by 4.
When [M40MHZ, M26MHZ] = [1,0], the CE clock frequency m ay be set to ~5 MHz (4.9152 MHz) or ~10
MHz (9.8304 MHz), using the I/O RAM register CE10MHZ. In this mode, the ADC and FIR clock fr equen-
cies remain at ~ 5 M Hz. When [M40MHZ, M26MHZ] = [0,1], the CE, ADC, FIR and MPU clock frequen-
cies are shifted to ~ 6.6 MHz (6.5536 MHz). This increases the ADC sample rate by 33%.
CE codes are tailore d to par ticular clock frequenc ies . Ch anging the c loc k frequency for a
particular CE code m ay render it unusable.
In sleep mode, the M40MHZ and M26MHZ inputs to the clock generator are forced low. In brownout
mode, the clocks a re derived from the cry st al oscillator and the clock freque nci es are scaled by 7/8.
1.5.3 Real-Time Clock (RTC)
The RTC is driven dir ect l y by the crystal oscillator. It is powered by the net RTC_NV (batt ery-backed up
supply). The RTC consists of a counter chain and output registers. The counter chain consists of registers
for seconds, minutes, hours, day of week, day of m onth, month and year. The RTC is capable of
processing leap y ears. Each counter has its own output register. Whenever the MPU reads the seconds
register, all other output registers are automatically updated. Since the RTC clock (RTCLK) is not coherent
to the MPU cloc k, the MPU must read the seconds register until two consecuti ve reads are the same (this
requires either 2 or 3 reads). At this point, all RTC output registers will have the correct tim e. Regardless
of the MPU cloc k sp eed, RTC reads requi re one wait state.
RTC time is set by writing to the registers RTC_SEC[5:0] through RTC_YR. Each write operation m ust be
preceded by a write o perati on to the WE register in I/O RA M. The value written to the WE register is
unimportant.
Time adjustments ar e written to the RTCA_ADJ[6:0], PREG[16:0] and QREG[1:0] registers. Updates t o
PREG[16:0] and QREG[1:0] must occur after the one second interrupt and must be finished before reaching
the next one second boundary. The new val ues are loaded into t he counters at the next one second
boundary.
PREG[16:0] and QREG[1:0] are separate registers in the device hardware, but the bits are 16-bit contiguous
so the MPU fi rm ware can treat them as a single register. A single binary number can be calculated and
then loaded into them at the same time.
The 71M6531D/F and 71M6532D/F have two rate adjustment m echanisms. The first is an analog rate
adjustment, using RTCA_ADJ[6:0], which trims t he crystal load capacitance. Setting RTCA_ADJ[6:0] to 00
minimizes the load capacitance, max i m izing the oscillator frequency. Setting RTCA_ADJ[6:0] to 0x3F
maximizes the lo ad c a pacitance, mi ni miz ing t he os cillator frequency. The adjustable cap ac ita nc e is
approximately:
pF
ADJRTCA
C
ADJ
5.16
128
_⋅=
The maximum adjustment range is approximately-12 ppm to +22ppm. The precise amount of adjust m ent
will dep end on the crys tal properties . The adjustment may occur at any time and the resulting clock
frequency can be measu red over a one-second i nterval.
The second rate adjustment is a digit al rat e adj ust using PREG[16:0] and QREG[1:0], which c an be used
to adjust the clo ck r ate up to ± 988 ppm, with a resolution of 3.8 ppm. Updates must occur after a one
second interru p t and must finish before the next one second boundar y. The rate adjustment will be
implemented start i ng at the next one second boundary. S i nce the LSB results in an adju st m ent every
four seconds, t he frequency should be m easured over an interval that is a mult i pl e of four seconds.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
38 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
To adjust the clock r ate using the digital rate adjust, the appr opriate values must be written to PREG[16:0]
and QREG[1:0]. The default frequency is 32, 768 RTCLK cycles per second. To shift the clo ck frequency
by ∆ ppm, calculate PREG[16:0] and QREG[1:0] using the following equatio n:
+
⋅∆+
⋅
=+⋅ −5.0
101 832768
46
floorQREGPREG
For example, for a shift of -988 ppm, 4⋅PREG + QREG = 262403 = 0x40103. PREG[16:0] = 0x10040 and
QREG[1:0] = 0x03. The default values of PREG[16:0] and QREG[1:0], corresponding to zero adjustment,
are 0x10000 and 0x0, respect i vely.
The RTC timing m ay be observed on the TMUXOUT pin by set ting TMUX[4:0] to 0x10 or 0x11.
Default values for RTCA_ADJ, PREG[16:0] and QREG[1:0] should be nominal values, at the center of
the adjustment range. Extreme values (zer o for example) can cause incorrect op erat i on.
If the crystal tem perature coeffi cient is known, t he M PU can integrat e temperature and correct the RTC
time as necessary.
The sub-second regi st er of the RTC, SUBSEC, can be r ead by the MPU after the one s econd interrupt and
before reaching t he next one second boundary. SUBSEC contains the count remaining, in 1/ 256 second
nominal clock periods, until the next one second boundary. When the RST_SUBSEC bit is written, the
SUBSEC counter is restarted. Reading and resetting the sub-second counter can be used as part of an
algorithm to accurat ely set the RTC.
When setting the RTC_SEC register, it is important to take into acco unt that the associated write operation
will be performed onl y in the next seco nd boundary.
1.5.4 Temperature Sensor
The device inc ludes an on-ch ip temperature sensor for determining the tempera ture of the bandgap
reference. If automatic temperature m easurement is not performed by select i ng CHOP_E[1:0] = 00, the
MPU may request an alt ernate multiplexer frame containing the temperature sensor output by asse rt i ng
MUX_ALT. The pr imary use o f the t emperature data is to determ ine the magn itude o f compens ation
required to off set the ther mal drif t in t he sy stem (see Section 3.4 Temperature Compensation).
1.5.5 Physical Memory
Flash Memory
The 71M6531D and 71M 6532D include 128 KB of on-chip flash memory. The 71M6531F and 71M6532F
offer 256 KB of flash memory. T he flash memory pri m aril y contains MPU and CE program cod e. It also
contains images of t he CE and MPU data in RA M , as well as of I/O RAM. On power-up, before enabl ing
the CE, the MPU copies these images t o their respectiv e l ocat i ons.
The flash memory i s segmented into indi vidually erasable pages that contain 1024 bytes.
Flash space allocated for t he CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash a ddress space. The CE_LCTN[7:0] word def i nes which 1-KB
boundary cont ai ns the CE code. Thus, the first CE instruction i s l ocated at 1024*CE_LCTN[7:0].
The MPU may write to the flash memory. This is one of the non-volatile storage options avail able to the
user in addition to external EEPROM.
Flash Write Procedures
FLSH_PWE (flash program write enabl e) differentiat es 80515 data store instructions (M O V X@DPTR,A)
between Flash and XRAM write oper ations. This bit m ust be cleared by the M P U after each byte write
operation. Write operations to this bit are inhibited when interrupts are enabled.
The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of collisions
between the MP U firmware and the CE timing. If a flash write operation is att empted while the CE i s
busy, the flash writ e will not execute and the FWCOL0 interrupt wil l be i ssued. If a flash write is still in
progress when the CE would otherwis e begi n a code pass, the co de pass is skipped, the write operation
is completed, and the FWCOL1 interrupt is issued.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 39
The simplest flash write procedure disables the CE during the write operation and interpolates the metering
measurements. How ever, this results in the loss of at least on e second of data, b ecause the CE has to
resynchronize with the mains volt age.
There is a brief guara nteed interval (ty pically 1/32768 s) between CE executi ons which occur s 2520 times
per second. The start of the interval ca n be detected with t he CE _BUSY interrupt which occurs on the
falling edge of CE_BUSY (an internal signal measurable from TMUXOUT ). However, this guarantee d i dle
time (30.5 µs) i s t oo short to write a byte which takes 42 µ s or t o erase a page of flash memory which
takes at least 20 ms. So me C E code has s ubstantially lo nge r idle times , bu t in those cases , fi rmware
interrupt latencies can easily cons um e the available write time. If a flash write fails in thi s s cheme, the
failure can be detect ed with the FWCOL 0 or F WCOL1 interrupt and the write can be retried.
It is practical to pre -erase pages, disa bl e interrupts and poll the CE_BUSY interr upt flag, IRCON[2]. This
method avoids problems with interrupt latency, but can still result in a writ e failure if t he CE code takes to
much time. As menti oned above, polling FWCOL0 and FWCOL1 can detect write failures. However, the
speed in a polling write is only 2520 bytes per second and the firmware cannot respond to interrupt s.
As an alternative to using flash, a small EEPROM can store data without compromises. EEPROM interfaces
are included in the device.
The original st ate of a flash byte is 0x F F (all ones). Once a valu e other than 0xFF is writ ten to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Si nce c el l s
cannot be erased individually, the page has to be copied to RAM , followed by a page erase. After t hi s,
the page can be updated in RAM and then written back to the flash memory.
Updating Individual Bytes in Flash Memory
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These sp ecial patte rn/se quence requi reme nts pr event i nadve rtent eras ure of t he fla sh mem ory.
Flash Erase Procedures
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).
2. Write pattern 0xAA to FLSH_ERASE (SFR 0x94).
The mass erase cy cle can only be i nitiated when the ICE port is enabled.
The page erase sequence is:
1. Write the pag e address to FLSH_PGADR[5:0] (SFR 0xB7[7:1]).
2. Write pattern 0x55 to FLSH_ERASE (SFR 0x94).
The program mem ory of the 71M6531 c onsists of a fixed lower ba nk of 32 KB addressable at 0x0000 to
0x7FFF plus an upper bank area of 32 KB, addressable at 0x8000 to 0xFFFF. The upper 32 KB space is
banked using the I/O RAM FL_BANK register as follows:
Bank-Switching:
• The 71M6531D provides 4 banks of 32 KB each selected by FL_BANK[1:0]. Note that when
FL_BANK[1:0] = 00, the upper bank is the same as the lower bank.
• The 71M6531F and 71M6532D/F provide 8 banks of 32 KB each selected by FL_BANK[2:0].
Table 38 illustrates the bank switching mechani sm.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
40 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 38: Bank S witching with FL_BANK[2:0]
71M6531D
FL_BANK [1:0] 71M653XF
FL_BANK [2:0] Address Range for Lower
Bank (0x000-0x7FFF)
Address Range for Upper
Bank (0x8000-0xFFFF)
000 000
0x0000-0x7FFF
0x0000-0x7FFF
001 001 0x8000-0xFFFF
010 010 0x10000-0x17FFF
011 011 0x18000-0x1FFFF
100 0x20000-0x217FF
101 0x28000-0x2FFFF
110 0x30000-0x37FFF
111 0x38000-0x3FFFF
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE
operations ar e blocked. This guarantees the security of the user’s MP U and CE program code. Security
should be enabled by MPU code that i s executed during the pre-boot int erval (60 CKMPU cycles before
the primary boot seq uence begins). Once s ecurity is enabled, the only way to disabl e it is to perform a
global erase of the flash, followed by a chip reset.
Program Security
The first 60 cy cles of the MPU boot code are called the pre-bo ot phase because during this phase t he
ICE is inhibited. A read-only status bit, PREBOOT, identifies these c ycles to the MPU. Upon completion
of pre-boot, the I CE can be enabled and is perm i tted to take control of the MPU.
The security enabl e bi t, SECURE, is reset whenever the chip is reset. Hardware associated with the bi t
permits only ones t o be written to it. Thus, pre-b oot code may set SECURE to enable the security feature
but may not reset it . Once SECURE is set, t he pre-boot code is protected and no ext ernal read of program
code is possible
Specifically, when SECURE is set, the following applies:
• The ICE is limit ed to bulk flash erase only.
• Page zero of fl ash memory, the preferred location f or the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page ze ro m ay only be erased with global flash erase.
• Write operations t o page zero, whethe r by MPU or ICE are inhibit ed.
MPU/CE RAM:
The 71M6531D/F and 71M6532D/F include 4 KB of static RAM memory on -chip (XRAM) p l us 256-bytes
of internal RAM in the MPU core. The 4 KB of static RAM are used for data storage for MPU and CE
operations.
1.5.6 Optical Interface
The device includes an interface to im plement an IR/ optical port. The pin OP T_TX is designed t o di rectly
drive an external LE D for transmitting data on an optical li nk. T he pin OPT_RX has the same threshold
as the RX pin, but can also be used to sense the input from an external photo detector used as the receiver
for the optical link. OP T _TX and OPT_RX are connected to a dedicated UART port (UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV,
respectively. Additionally, the OPT_TX output may be modulated at 38 kHz. Modulation is available when
system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation. Duty
cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5% and 6.25% duty cycle. 6. 25% duty
cycle means OPT_TX is low for 6.25% of the period. Figure 9 illustrates the OPT_TX generator.
When not needed for t he optical UART, the OPT_TX pin can alternatively be configured as DI O2,
WPULSE, or VARPULSE. The configuration bit s are OPT_TXE[1:0]. Likewise, OPT_RX can alternately
be configured as DI O1. It s control is OPT_RXDIS.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 41
B
A
OPT_TXMOD = 0 OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
B
A
1/38kHz
OPT_TXINV
from
OPT_TX UART MOD
EN DUTY
OPT_TX
OPT_TXMOD
OPT_FDC
OPT_TXE[1:0]
1
2
V3P3
Internal
AB0
2
3
DIO2
WPULSE
VARPULSE
Figure 9: Optical Interface
1.5.7 Digital I/O – 71M6531D/F
The 71M6531D/F includes up to 22 pins of general-purpose digital I/O. These pins are compatible with 5 V
inputs (no current lim i ting resistors are needed). The Digit al I/O pins can be categorized as foll ows:
• Dedicated DIO pi ns (1 pin): PB
• DIO/LCD segment pins (a total of 19 pins):
o DIO4/SEG24 - DIO15/SEG35 (12 pins)
o DIO17/SEG37 (1 pin)
o DIO28/SEG48 – DIO29/SEG49 (2 pins)
o DIO43/SEG63 - DIO46/SEG66 (4 pins)
• DIO pins combined with other functions (2 pins): DIO2/O P T _TX, DIO1/OPT_RX
The pins DIO4/S E G 24 through DIO46/SEG66 are configured by the LCD_BITMAP registers to be DIO or
segment pins. A one in LCD_BITMAP defines t he pi n as a LCD segment output, a zero makes the pin a
DIO pin. Pins configured as LCD pi ns are controlled with the LCD_SEGnn registers. Pins conf igured as
DIO can be defined i ndependently as an input or output with the DIO_DIR bit s (see Table 45).
Write operations to a disabled DIO are not ignored. Write operations are registered, but do not affect
the pin, or the result of a read operation on the pin, until it becomes a DIO output.
DIO2/OPT_T X will be an active TX output pin at power up (OPT_TXE[1:0] = 00).
A 3-bit configuration word, I/O RAM field DIO_Rx[2:0] (0x2009[2:0] through 0x20 0E[6:4]), can be used for
certain pins (whe n configured as DIO ) t o i ndi vidually assign an internal resource such a s an interrupt or a
timer control (see Table 46 for DIO pins available for this option). This w ay, DIO pins can be t racked
even if they are co nfigured as output s.
Table 39 to Table 41 lists the direction registers and configurability associated with each group of DIO pins.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
42 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 39: Data/Direction Registers and Internal Resource s for DIO 1-15 (71M6531D/F)
DIO PB 1 2 – 4 5 6 7 8 9 10 11 12 13 14 15
LCD Segment – – – – 24 25 26 27 28 29 30 31 32 33 34 35
Pin number 65 60 3 – 39 40 41 42 43 44 45 46 68 30 21 22
Configuration (DIO
or LCD segment) – – – – 0 1 2 3 4 5 6 7 0 1 2 3
LCD_BITMAP[31:24] LCD_BITMAP[39:32]
Data Register 0 1 2 – 4 5 6 7 0 1 2 3 4 5 6 7
DIO0 = P0 (SFR 0x80) DIO1 = P1 (SFR 0x 90)
Direction Register – 1 2 – 4 5 6 7 0 1 2 3 4 5 6 7
DIO_DIR0 (SFR 0xA2) DIO_DIR1 (SF R 0x91)
Internal Resources
Configurable – – – – Y Y Y Y Y Y Y Y – – – –
Table 40: Data/Direction Registers and Internal Resources for DIO 17-29 (71M6531D/F)
DIO – 17 – – – – – – – – – – 28 29 – –
LCD Segment – 37 – – – – – – – – – – 48 49 – –
Pin number – 13 – – – – – – – – – – 47 24 – –
Configuration (DIO
or LCD segment) – 5 – – – – – – – – – – 0 1 – –
LCD_BITMAP[39:32]
LCD_BITMAP[55:48]
Data Register – 1 – – – – – – – – – – 4 5 – –
DIO2 = P2 (SFR 0xA0) DIO3 = P3 (SFR 0xB0)
Direction Register
0 = input,
1 = output
– 1 – – – – – –
LCD_SEG48[3]
LCD_SEG49[3]
DIO_DIR2 (SFR 0xA1)
Table 41: Data/Direction Registers and Internal Resource s for DIO 43-46 (71M6531D/F)
DIO – – – 43 44 45 46 –
LCD Segment – – – 63 64 65 66 –
Pin number – – – 29 23 28 5 –
Configuration (DIO or
LCD segment) – – – 7 0 1 2 –
LCD_BITMAP[63:56] LCD_BITMAP[64:71]
Data Register – – –
LCD_SEG63[0]
LCD_SEG64[0]
LCD_SEG65[0]
LCD_SEG66[0]
–
Direction Register
0 = input, 1 = output – – –
LCD_SEG63[3]
LCD_SEG64[3]
LCD_SEG65[3]
LCD_SEG66[3]
–
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 43
1.5.8 Digital I/O – 71M6532D/F
The 71M6532D/F includes up to 43 pins of general-purpose digital I/O. These pins are compatible with 5 V
inputs (no current lim i ting resistors are needed). The Digital I/O pins can be categorized as follows:
• Dedicated DI O pins (4 pins):
o DIO3
o DIO56 – DIO58 (3 pi ns)
• DIO/LCD segment pins (a total of 37 pins):
o DIO4/SEG24 – DIO27/SEG47 (24 pins)
o DIO29/SEG49, DIO30/SEG50 (2 pins)
o DIO40/SEG60 – DIO45/SEG65 (6 pins)
o DIO47/SEG67 – DIO51/SEG71 (5 pins)
• DIO pins combined with other funct ions (2 pins): DIO2/ OPT_TX, DIO1/O P T _RX
On reset or power-up, all DIO pins are inputs until they are co nfigured for the desired direction under
MPU control. T he pi n function can be configured by the I /O RAM bits LCD_BITMAPn. Setting
LCD_BITMAPn = 1 co nfigures the pin for LCD, setting LCD_BITMAPn = 0 configures it f or DI O . Once a
pin is configured a s DIO , it can be configured independently as an input or outp ut with the DIO_DIR bits
or the LCD_SEGn registers. Input and out put data are written to or read from the pins u sing SFR registers
P0, P1, and P2. Table 42 to Table 44 shows the DIO pins with t hei r configuration, direction control and
data registers.
Table 42: Data/Direction Registers and Internal Resource s for DIO 1-15 (71M6532D/F)
DIO PB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LCD Segment – – – – 24 25 26 27 28 29 30 31 32 33 34 35
Pin number 92 87 3 17 60 61 62 63 67 68 69 70 100 44 29 30
Configuration (DIO
or LCD segment) Always DIO 0 1 2 3 4 5 6 7 0 1 2 3
LCD_BITMAP[31:24] LCD_BITMAP[39:32]
Data Register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
DIO0 = P0 (SFR 0x80) DIO1 = P1 (S FR 0x90)
Direction Register
0 = input,
1 = output
– 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
DIO_DIR0 (SFR 0xA2) DIO_DIR1 (SF R 0x91)
Internal Resources
Configurable Y Y Y Y Y Y Y Y Y Y Y Y – – – –
Table 43: Data/Direction Registers and Internal Resource s for DIO 16-30 (71M6532D/F)
DIO 16 17 18 19 20 21 22 23 24 25 26 27 – 29 30 –
LCD Segment 36 37 18 39 40 41 42 43 44 45 46 47 – 49 50 –
Pin number 33 12 13 64 65 66 93 54 46 43 42 41 – 32 35
Configuration (DIO
or LCD segment) 4 5 6 7 0 1 2 3 – – – – – 1 2 –
LCD_BITMAP[39:32] LCD_BITMAP[47:40] LCD_BITMAP[55:48]
Data Register 0 1 2 3 4 5 6 7 0 1 2 3 – 5 6 –
DIO2 = P2 (SFR 0xA0) DIO3 = P3 (SFR 0xB0)
Direction Register
0 = input,
1 = output
– 1 – 3 4 5 – –
– – – – –
LCD_SEG49[3]
LCD_SEG50[3]
–
DIO_DIR2 (SFR 0xA1)
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
44 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 44: Data/Direction Registers and Internal Resource s for DIO 40-51 (7 1M 6532D/F)
DIO 40 41 42 43 44 45 – 47 48 49 50 51
LCD Segment 60 61 62 63 64 65 – 67 68 69 70 71
Pin number 95 97 98 40 31 38 – 22 23 24 25 50
Configuration (DIO
or LCD segment) 4 5 6 7 0 1 – 3 4 5 6 7
LCD_BITMAP[63:56] LCD_BITMAP[71:64]
Data Register
LCD_SEG60[0]
LCD_SEG61[0]
LCD_SEG62[0]
LCD_SEG63[0]
LCD_SEG64[0]
LCD_SEG65[0]
–
LCD_SEG67[0]
LCD_SEG68[0]
LCD_SEG69[0]
LCD_SEG70[0]
LCD_SEG71[0]
Direction Register
0 = input,
1 = output
LCD_SEG60[0]
LCD_SEG61[0]
LCD_SEG62[0]
LCD_SEG63[0]
LCD_SEG64[3]
LCD_SEG65[3]
–
LCD_SEG67[3]
LCD_SEG68[3]
LCD_SEG69[3]
LCD_SEG70[3]
LCD_SEG71[3]
DIO24 and higher do not have SFR registers for direction control. DIO40 and higher do not have SFR
registers f or data access. The direct i on control of these pin s is achieved with the LCD_SEGn[3] bits and
data access is cont rol led with the LCD_SEGn[0] bits in I/O RAM.
DIO56 through DIO 58 are dedicated DIO pins. They are controlled with DIO_DIR56[7] through
DIO_DIR58[7] and with DIO_56[4] through DIO_58[4] in I/O RAM.
1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
On reset or power-up, al l DIO pins are inputs until they are configured for the desired direction und er
MPU control. T he pi n function can be configured by the I /O RAM bits LCD_BITMAPn. Setting
LCD_BITMAPn = 1 co nfigures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a
pin is configured a s DIO , it can be configured independently as an input or outp ut with the DIO_DIR bits
or the LCD_SEGn registers. Input and out put data are written to or read from the pins u sing SFR registers
P0, P1, and P2.
DIO24 and higher d o not have SFR regist ers for directi on cont rol. DIO40 and higher do not have SFR
registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with t he LCD_SEGn[0] registers in I/O RAM.
Since the control for DIO24 thro ugh DIO5 1 is shared with the control for LCD segments, the firmw are
must take care not to disturb the DIO pins when ac cessi ng the LCD se gment s and v ice v ersa. Usu ally,
this requires reading the I/O RAM register, applying a mask and writing back the modif ied byte.
Table 45: DIO_DIR Control Bit
DIO_DIR
[n]
0
1
DIO Pin n Function Input Output
Table 46: Selectable Control using DIO_DIR Bits
DIO_R
Value Resource Selected for DIO Pin
0 None
1 Reserved
2 T0 (counter 0 cloc k)
3 T1 (counter 1 cloc k)
4 High priority I/O interrupt (INT0 rising)
5 Low priority I /O interrupt (INT1 ri sing)
6 High priority I/O interru pt (INT0 falling)
7 Low priority I/O interr upt (INT1 falling )
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 45
Additionally, if D IO6 and DIO7 are con figur ed as D IO and defined as ou tputs, they can be used as
dedicated pulse output s (WPULSE = DIO6, VARPULSE = DIO7) using the DIO_PW and DIO_PV bits. In
this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implem ent the
EEPROM Interface.
The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and OPT_RX
can be configured as dedicated DIO pins, DIO1 and DIO2, respectively (see Section 1.5.6 Optical Interface).
The internal control resources sele ctabl e for the DIO pins are listed in Table 46. If more than one input i s
connected to the same resource, the resources are com bi ned using a logical OR.
Tracking DIO pins c onfigured as output s is useful for pulse count i ng without external hardware.
Either the interrupts or the counter/timer clocks can be used to count pulses on the pulse outputs
or interrupts on the CE ’ s power failure o utput.
When driving LEDs, relay coils etc., the DIO pins should sink
Figure 10 the current into GNDD (as shown in
, right), not Figure 10 source it from V3P3D (as shown in , left). This is due to the resis-
tance of the internal switch that connects V3P3D to either V3P3SYS or VBAT.
Sourcing current into or out of DIO pins other than the PB pin, for e xample with pull-up or pull-
down resistors, should be avoided. V i olating this rule wil l l ead to increased qui escent current in
sleep and LCD mode s.
Figure 10: Connecting an Extern al Load to DIO Pins
1.5.10 LCD Drivers – 71M6531D/F
The 71M6531 contai ns a total of 39 ded i cat ed and multiplex ed LCD drivers which are grouped as f ol l ows:
• 11 dedicated LCD se gm ent drivers – alway s av ai l abl e
• 3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX) – available in normal operation
mode (when not emulating )
• 2 driver multiplex ed with auxiliary sign als MUX_SYNC and CKTEST (SEG7, SEG19) – available
when not used f or test
• 4 drivers multiplexed with the SPI port (PCLK, PSDO, PCSZ, PSDI)
• 19 multi-use pins described in Section 1.5.7 Digital I/O – 71M6531D/F.
• 4 common drivers for multiplexing (2 5%, 33%, 50%, or 100% duty cycle) – always available
With a m inimu m of 1 6 driv er pin s alway s av ailable and a total of 39 d river pins i n the maxim um co nfiguration,
the device is capable of driving between 64 to 156 pixels of LCD display with 25% duty cycle. At eight pixels
per digit, this corresponds to 8 to 19 digits. At 33% duty cycle, 48 to 117 pixels can be driven.
For each multi-use pin, the corresponding LCD_BITMAP[] bit (see Section 1.5.7 Digital I/O – 71M6531D/F),
is used to select the pi n for DIO or LCD oper ation. The mapping of the LCD_BITMAP[] bits is specified in
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
46 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Section 4.1 I/O RAM and SFR Map – Functional Order. The LCD drivers are supported by the four common
pins (COM0 – COM3).
1.5.11 LCD Drivers – 71M6532D/F
The 71M6532D/F contains a total of 67 dedicated and multiplex ed LCD drivers, which are grouped as
follows:
• 15 dedicated LCD segment drivers (SEG0 to SEG2, SEG8, SEG12 - SEG18, SEG20 – SEG23)
• 4 drivers multipl exed with the SPI port (SEG3 to SEG6)
• 2 drivers multi plexed with M UX_SY NC (SE G7) or CKTEST (SEG19)
• 3 drivers multipl exed with the ICE interface (SEG9 t o S EG11)
• 43 multi-use LCD/DIO pin s described in Section 1.5.8 Digital I/O – 71M6532D/F.
With a minimum of 15 driver pins always avail able a nd a tota l of 67 driver pins in the maximum configuration,
the device is capable of driving between 60 to 268 pixels of an L CD display with 25% duty cycle. At eight
pixels per digit, this corresponds to 7.5 to 33.5 digits.
For ea ch mul ti-use pin, the corresponding LCD_BITMAP[ ] bit (see Section 1.5.8 Digita l I/O – 71M6532D/F),
is used to sel ect the pin for DIO or L CD operation. The mapping of the LCD_BITMAP[ ] bits is specified in
Section 4.1 I/O RAM and SFR Map – Functional Order. The LCD drivers are supported by the four common
pins (COM0 – COM3).
1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
The LCD interface is flexible and can dri ve 7-segment digit s, 14-segment digits or enunciator symbol s.
The LCD bias may be compensated for t em perature using the LCD_DAC[2:0] bits in I/O RAM. The bias
may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in mission mode and br ownout modes,
VBAT in LCD mode). When the LCD_DAC[2:0] bits are set to 000, the DAC is bypassed and powered
down. This can be u sed t o reduce current in LCD mode.
Segment drivers SEG18 a nd S EG19 can be configured to blink at eit her 0.5 Hz or 1 Hz. The blink rat e i s
controlled by LCD_Y. There can b e up to four pixels/segments connected t o each of these driv ers.
LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] i dentify which pixels, if an y, are to bl ink. The most
significant bit cor responds to COM3, the least significant to COM0.
1.5.13 Battery Monitor
The battery voltage i s measured by the A DC during alternati ve MUX frames if t he BME (Battery Measure
Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled
fraction of the battery vol tage is applied to the ADC input. After each alternative MUX frame, the result of
the ADC conversio n i s available at RAM address 0x0B. BME is ignored and assumed zero when system
power is not availabl e.
If VBAT is connected to a drained battery or disconnected, a battery test t hat sets BME may drain
VBAT’s supply and cause the oscillator to stop. A st opped oscillator may force the dev i ce to reset.
Therefore, an unex pected reset during a battery test shoul d be interpreted as a battery failure.
Battery measurement is not very li near but is very reproducible if properly calibrated. The best way to
perform the calibrat i on is to set the batt ery i nput to the desired failure voltage and then have the MPU
firmware reco rd that measurement . After this, the battery measurement logic may use the recorded value
as the battery f ai l ure li m i t. The same value ca n al so be a calibration offset for any battery voltage display.
See Section 5.4.4 Battery Monitor for details regardi ng the ADC LSB size and t he conversion accuracy.
1.5.14 EEPROM Interface
The 71M6531D/F and 71M6532D/F provide hardware support for either a two-pin or a t hree-wire (µ-wire)
type of EEPROM interface. The interfaces use the EECTRL and EEDATA registers f or communication.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 47
Two-Pin EEPROM Interface
The dedicated 2-p in ser ial i nterface c ommunicat es with e xternal EEPROM dev ices . The inter face is
multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setti ng DIO_EEX[1:0] = 01.
The MPU communicates with the int erface through the SFR registers EEDATA and EECTRL. If the MPU
wishes to write a byte of data to the EEPROM, it places t he data in EEDATA and then writ es the Transmit
code to EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also
asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged
the transmission.
A byte is read by writing the Receive comm and to EECTRL and wait i ng for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission and then holds in a high state until the next transmission. The EECTRL bits when the two-pin
interface is selected are shown in Table 47.
Table 47: EECTRL Bits for 2-pin Interface
Status
Bit Name
Read/
Write
Reset
State Polarity Description
7 ERROR R 0 Positive 1 when an illegal command is received.
6 BUSY R 0 Positive 1 when serial data bus is busy .
5 RX_ACK R 1 Negative 0 indicates that the EEPROM sent an ACK bit.
4 TX_ACK R 1 Negative 0 indicates when an ACK bit has been sent to the
EEPROM.
3:0 CMD[3:0] W 0000 Positive CMD[3:0] Operation
0000 No-op comm and. Stops the I
2
C
clock (SCK, DIO4). If not issued,
SCK keeps toggling.
0010 Receive a byte from the EEPROM
and send ACK.
0011 Transmit a byte to the EEPROM.
0101 Issue a STO P sequence.
0110 Receive the last byte f rom the
EEPROM and do not send ACK.
1001 Issue a START s equence.
Others No operation, set the ERROR bit.
The EEPROM int erf ace can also be operated by controlling t he DIO4 and DIO5 pi ns directly. In
this case, a resist or has to be used in s eries with SDA to avoid data collisions due to limits in the
speed at which the SDA pi n can be sw itched from outpu t to input. Co ntrollin g DIO4 and DIO5
directly is discouraged, because it may tie up the M P U to the point where i t may become too busy
to process interr upts.
Three-Wire (µ-Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA , SCK and a DIO pin for CS is available. The int erf ace is
selected by setting DIO_EEX[1:0] = 2 (b10). The EECTRL bit s when the three-wire interface is selected
are shown in Table 48. When EECTRL is w ri tten, up to 8 bits from EEDATA are either writt en to the
EEPROM or read from the EEPROM, depending on the values of the EECTRL bits.
The µ-Wire EE PROM interface is only functional wh en MPU_DIV[2:0] = 000.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
48 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 48: EECTRL Bits for the 3-Wire I nterface
Control
Bit
Name Read/
Write
Description
7 WFR W Wait for Ready. If this bit is set, the trailing edge of BUS Y will be delayed
until a rising edge i s se en on the data line. This bit can be used during
the last byte of a Writ e command to ca use the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ = 0.
6 BUSY R Asserted while the serial d ata bus is busy. When the B US Y bit falls, an
INT5 interrupt occ urs.
5 HiZ W Indicates that the SD signal is to be floated to high impedance immediately
after the last SCK rising edge.
4 RD W Indicates that EEDATA is to be filled with data from EEPROM.
3:0 CNT[3:0] W Specifies the number of clocks to be issued. All owed values are 0
through 8. If RD=1 , CNT bi ts of data will be read MSB first and right
justified int o the low order bits of EEDATA. If RD=0, CNT bits will be sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
The timing diagram s in Figure 11 through Figure 15 describe the 3-wire EEPROM interface behavior. All
commands begin w hen the EECTRL register is written. Transactions start by fi rst raising the DIO pin t hat
is connected to CS. Multiple 8-bit or l ess commands such as those shown in Figure 11 through Figure 15
are then sent via EECTRL and EEDATA.
When the transact i on is finished, CS must be lowered. At t he end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take cont rol of SDATA and force it to
a low-Z state.
Figure 11: 3-Wire Interfac e. Write Co m mand, HiZ=0
Figure 12: 3-Wire Interfac e. Write Co m mand, HiZ=1
SCLK (output )
BUSY (bit)
CNT Cycles (6 s hown)
SDATA (output)
Wr ite -- No HiZ
D2D3D4D5D6D7
EECTRL Byt e Written INT5
SDATA output Z
(LoZ)
CNT Cycles (6 s hown)
Wr ite -- W ith HiZ
INT5
EECTRL Byt e Written
SCLK (output )
BUSY (bit)
SDATA (output)
D2D3D4D5D6D7
(HiZ)(LoZ)
SDATA output Z
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 49
Figure 13: 3-Wire Interfac e. Read Com m and.
Figure 14: 3-Wire Interfac e. Wr ite Command when CNT=0
Figure 15: 3-Wire Interfac e. Write Co m mand when HiZ=1 and WFR=1
1.5.15 SPI Slave Port
The slave SPI port communicates di rectly with t he M PU data bus and is abl e to read and write Data RAM
locations. It is also able to send comma nds to the MPU. The interface to the slave port consists of the
PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed wit h the LCD segment driver pins SEG3
to SEG6. The port pins default to LCD driver pins. The port i s enabled by setting the SPE bit.
A typical SPI transaction is as follow s. While PCSZ is high, the port is held in an initial i zed/reset state.
During this state, P SDO is held in HiZ state and all transitions on P CLK and PSDI are ignor ed. When
PCSZ falls, the port wil l begin the transact i on on the first rising edg e of PCLK. A transaction consists of
an 8-bit command, a 16-bit address and then one or more bytes of data. The t ransaction ends when
PCSZ is raised. Some transactions may consi st of a command only.
The last SPI command and addres s (if part of the command) are avai l able to the MPU in registers
SP_CMD and SP_ADDR.
The SPI port supports data transfer s at 1 Mb/s in mission mode and 16 kb/s in brownout m ode. The SPI
commands are described in Table 49 and in Figure 16 ill ust rate the SPI Interface read and write timing.
CNT Cycles (8 s hown)
READ
D0D1D2D3D4D5
INT5
D6D7
EECTRL Byt e Written
SCLK (output )
BUSY (bit)
SDATA (i nput)
SDATA output Z
(HiZ)
CNT Cycles (0 s hown)
Wr ite -- No HiZ
D7
INT5 not issued CNT Cycles (0 s hown)
Wr ite -- HiZ
INT5 not issued
EECTRL Byt e Written EECTRL Byt e Written
SCLK (output )
BUSY (bit)
SDATA (output)
SCLK (output )
BUSY (bit)
SDATA (output)
(HiZ)
SDATA output ZSDATA output Z
(LoZ)
CNT Cycles (6 s hown)
Write -- Wi th HiZ and WFR
EECTRL Byt e Written
SCLK (output )
BUSY (bit)
SDATA (out/in) D2D3D4D5D6D7 BUSY READY
(From EEPROM)
INT5
(From 6520)
SDATA output Z (HiZ)(LoZ)
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
50 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 49: SPI Command Description
Command
Description
11xx xxxx ADDR Byte0 ... ByteN Read data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP__CMD=11xx xxxx , SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1100 0000. Otherwise,
an SPI interrupt is generated.
10xx xxxx ADDR Byte0 ... ByteN Write data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP_CMD=10xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1000 0000. Otherwise,
an SPI interrupt is generated.
Certain I/O R A M regist ers can be written and read using the SP I port (see Table 50). However, the MPU
takes priority ov er the I/O RAM bus, and SPI operation may fail without notice. To avoid this situation, the
SPI host should se nd a command other than 11xxxxxx or 10xx xxxx (read or write) before the actual read
or write command. The SPI slave interface will load the command register a nd generate an INT2 inter-
rupt upon receiving the command. The MPU should service the interrupt and halt any external data memory
operations to effectively grant the bus t o the SPI. When the S PI host finishes, it should send another
command so the M P U can release the bus. There are no issues with Data RAM access; SPI and the
MPU will share the bus with no conflicts for Data RAM access.
Table 50: I/O RAM Reg isters Accessible via SPI
Name Address (hex) Bit Range Read/Write
CE0 2000 7:3 RW
CE1 2001 7:0 RW
CE2 2002 5:3, 1:0 RW
CONFIG0 2004 7:6, 3:0 RW
CONFIG1 2005 5:2, 0 RW
VERSION 2006 7:0 R
CONFIG2 2007 7:0 RW
DIO0 2008 7:6, 4:0 RW
DIO1 to DIO6 2009 to 200E 6:4, 2:0 RW
− 200F 7:6, 3:2 RW
RTM0H 2060 1:0 RW
RTM0L 2061 7:0 RW
RTM1H 2062 1:0 RW
RTM1L 2063 7:0 RW
RTM2H 2064 1:0 RW
RTM2L 2065 7:0 RW
RTM3H 2066 1:0 RW
RTM3L 2067 7:0 RW
PLS_W 2080 7:0 RW
PLS_I 2081 7:0 RW
SLOT0 to SLOT9 2090 to 209A 7:0 RW
CE3 209D 3:0 RW
CE4 20A7 7:0 RW
CE5 20A8 7:0 RW
WAKE 20A9 7:5, 3:0 R
CONFIG3 20AC 5:4, 1:0 RW
CONFIG4 20AD 5:4, 1:0 RW
− 20AF 2:0 RW
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 51
Name Address (hex) Bit Range Read/Write
SPI0 20B0 4, 0 RW
SPI1 20B1 4, 0 R
VERSION
20C8
7:0
R
CHIP_ID 20C9 7:0 R
TRIMSEL 20FD 4:0 RW
TRIMX
20FE
0
RW
TRIM 20FF 7:0 RW
A15 A14 A1 A0C0
031
x
D7 D6 D1 D0 D7 D6 D1 D0
C5C6C7
x
PCSZ
PSCK
PSDI
PSDO
8 bit CMD 16 bit Address DATA[ADDR] DATA[ADDR+1]
7 8 23 24 32 39
Extended Read . . .
SERIAL READ
A15 A14 A1 A0C0
031
C5C6C7
x
PCSZ
PSCK
PSDI
PSDO
8 bit CMD 16 bit Address DATA[ADDR] DATA[ADDR+1]
7 8 23 24 32 39
Extended Write . . .
SERIAL WRITE
D7 D6 D1 D0 D7 D6 D1 D0 x
HI Z
HI Z
(From Host)
(From 6531)
(From Host)
(From 6531)
Figure 16: SPI Slave Port: Typical Read and Write operations
Possible applicat ions for the SPI interface are:
1) An external host reads data from CE locations to obtai n m etering informat ion. This can be used in
applications whe re the 71M6531D/F or 71M6532D/F function as smart front-ends with preprocessing
capability. S ince the addresses are in 16-bit format, any type of XRAM dat a can be accesse d: CE,
MPU, I/O RAM, but not SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory locations,
the external host can initiate and control processes in t he MPU of the 71M6531D/F or 71M6532D/F.
Writing to a CE or M PU location normally generates an int errupt, a function that can be used to signal
to the MPU that the byte that had just be en writ ten by the ext ernal host must be read and processed.
Data can also be inse rted by the ext ernal host without generating an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation u ses the
71M6531D/F or 71M6532D/F as an analog f ront-end (AFE).
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
52 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
V3P3
V3P3 -
400mV
V3P3 - 10mV
VBIAS
0V
Battery
modes
Normal
operation,
WDT
enabled
WDT dis-
abled
V1
1.5.16 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included
in the 71M6531D/F an d 71M6532D/F. It uses the RTC crystal oscill ator as
its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not ref reshed on time, t he WDT overflows and the part
is reset as if the RES E T pin were pulled high, except that the I/O RAM bits
will be in the same st ate as after a wake-up from SLEEP or LCD modes
(see the I/O RAM description in Section 4.2 for a list of I/O RAM bit states
after RESET and wak e-up). 4100 oscil lator cycles (or 125 ms) after the
WDT overflow, t he M P U wil l be launched from prog ram address 0x0000.
A status bit, WD_OVF, is set when the WDT ov e rflow occurs. Th is bit is
powered by the nonvolatile supply and can be read by the MPU when
WAKE rises to determine if the part is initializing after a WDT overflow
event or after a power-up. After it is read, the MPU firmware must clear
WD_OVF. The WD_OVF bit is al so cleared by the RE S ET pin.
There is no internal digi tal state that deactivates the WDT.
Figure 17: Functions defined by V1
The WDT can be dis abl ed by tying the V1 pin to V3P3 (see Figure 17). Of course, this also d eact ivates
V1 power fault detection. Since there is no m ethod in firmware to disable the cryst al oscillator or the
WDT, it is guarante ed that whatever st ate the part might find itself in, upon w atchdog overflow, the part
will be reset to a known state.
Asserting ICE_E wil l also deactivate the WD T. T hi s is the only method that will work in BROWNOUT
mode. In normal ope rat i on, the WDT is reset by periodically writ i ng a one to the WDT_RST bit. The
watchdog timer is also reset when the internal signal WAKE = 0 (see Section 2.5 Wake-Up Behavior).
If enabled with the IEN_WD_NROVF bit in I/O RAM, an interrupt occurs roughly 1 ms before the WDT resets
the chip. This can be u sed to determine the cause of a WDT reset since it allows the code to log its state
(e.g. the current PC value, loop counters, flags, etc.) before a WDT reset occurs.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 53
1.5.17 Test Ports (TMUXOUT pin)
One of the digit al or analog signals li st ed in Table 51 can be selected to be output on the TMUXOUT pin.
The function of t he m ul tiplexer is controlled with the I/O RA M field TMUX[4:0] (0x20AA[4: 0]), as shown in
Table 51.
Table 51: TMUX[4:0] Selections
TMUX[4:0] Mode Function
0 Analog GNDD
1 Analog Reserved
2 Analog GNDD
3 Analog Reserved
4 Analog PLL_2P5
5 Analog Output of the 2.5 V low-po wer regulat or
6 Analog Internal VBIAS voltage (nominally 1.6V)
7 Analog Not used
8 - 0x0F – Reserved
0x10 Digital RTC 1-se cond output
0x11 Digital RTC 4-se cond output
0x12 – Not used
0x13 Digital V1_OK comparator output
0x14 Digital Real-time output (RTM) from the CE
0x15 Digital WDTR_EN (Com parator 1 Output AND V1LT3)
0x16 – 0x17 – Not used
0x18 Digital RXD (from Optical interfac e, w/ optional inversion)
0x19 Digital MUX_SYNC
0x1A – Not used
0x1B Digital CKMPU (MPU clock)
0x1C Digital Pulse output
0X1D Digital RTCLK (output of the oscillator circuit, nominally
32,786Hz)
0X1E Digital CE_BUSY (busy i nterrupt generat ed by CE, 396µs)
0X1F Digital XFER_BUSY (transfer busy interrupt generate d by the
CE, nominally every 999.7ms)
The TMUXOUT pin m ay be used for dia gnosis purposes or in production test. The RTC 1-second output
may be used to calibrate the crystal oscillator. The RTC 4-second output provides ev en hi gher precision.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
54 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
2 Functional Description
2.1 Theory of Operation
The energy deliv ered by a power sourc e into a load can be expressed as:
∫
=
tdttItVE
0
)()(
Assuming phase a ngl es are constant, t he following formulae apply:
P = Real Energy [Wh] = V * A * cos φ* t
Q = Reactiv e Energy [VARh] = V * A * sin φ * t
S = Apparent Energy [VAh] =
22 QP +
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content
may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state
electricity met er IC such as the Teridian 71M6531 functions by emulating the integral ope rat i on above, i.e.
it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC
resolution is high enough and the sample frequency is beyond the harm onic range of interest , the current
and voltage sampl es, multiplied with t he time period of sampl ing will yield an accurate quantity for the
momentary energy. S umming up the momentary energy quant i ties over time will result in accumulated
energy.
Figure 18: Voltage, Current, Momentary and Acc um ulated Energy
Figure 18 shows t he shapes of V(t), I(t), the momentar y power and the accumulated power, res ul ting from
50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and 100 A
results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the accumulated
power curve. The described sampling method works reliably, even in the presence of dynamic phase shift
and harmonic distortion.
-500
-400
-300
-200
-100
0
100
200
300
400
500
0 5 10 15 20
Current [A]
Voltage [V]
Energy per I nterval [Ws]
Accumulated Energy [Ws]
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 55
2.2 System Timing Summary
Figure 19 summ arizes the timi ng relationships betwe en the input MUX states, the CE_BUSY signal and
the two serial output streams. In thi s example, MUX_DIV[3:0] = 4 and FIR_LEN[1:0] = 2 (384 CE cycles,
3 CK32 cycles per conversion), result i ng in 13 CK32 cycles per multiplexer fram e. G enerall y, the duration
of each MUX frame is:
• 1 + MUX_DIV * 1, if FIR_LEN[1:0] = 0 (138 CE cycles)
• 1 + MUX_DIV * 2, if FIR_LEN[1:0] = 1 (288 CE cycles)
• 1 + MUX_DIV * 3, if FIR_LEN[1:0] = 2 (384 CE cycles).
An ADC conversion wil l always consume an integer number of CK 32 clocks. Following this is a single
CK32 cycle where the bandgap voltage i s all owed to recover from the change in CROSS.
Figure 19: Timing Relatio nshi p between ADC MUX, Compute Engine
Each CE program pass begins when the A DC0 conversion (for IA) begins. Dep ending on the length of
the CE program, it may continue running until the end of the last conversion (ADC3). CE opcodes are
constructed to ensure that all CE cod e passes consum e exactly the same number of cycles. The re sult of
each ADC conversion i s inserted into the RAM when the conversi on is complete. The CE code is written
to tolerate sudden changes in ADC data. The ex act clock count when each ADC value is loaded into
RAM is shown in Figure 19.
Figure 20 shows t hat the serial data st ream, RTM, begins transmitting at the beginning of state S. RTM,
consisting of 140 CK cycles, will alway s finish before the nex t code pass starts.
FLAG
RTM DATA 0 (32 bits)
0 1 0 1 0 1 0 1
FLAG FLAG FLAG
CK32
MUX_SYNC
CKTEST
TMUXOUT/RTM
LSB
LSB
SIGN
SIGN
LSB
SIGN
30 31 30 31 30 31 30 31
LSB
SIGN
RTM DATA 1 (32 bits)
RTM DATA 2 (32 bits)
RTM DATA 3 (32 bits)
Figure 20: RTM Output Format
CK32
MUX STATE 0
MUX_DIV=4 (4 conversions) is shown Settle
ADC MUX Frame
ADC EXECUTION
S
MUX_SYNC
S
CE_EXECUTION MAX CK COUNT
0 450
150
900 1350 1800
ADC0 ADC1 ADC2 ADC3
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRE_SAMPS * SUM_CYCLES) CODE PASSES.
CE_BUSY
XFER_BUSY INITIATED BY A CE OPCODE AT END OF SUMMATION INTERVAL
ADC TIMING
CE TIMING
1 2 3
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
56 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
2.3 Battery Modes
Shortly after syst em power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode
means that the part is operating with sy stem power and that the internal PLL is stable. This mode is the
normal operat i on m ode where the part is capable of measurin g energy.
When system power is not available (i. e. when V1<VBIAS), the 71M6531 will be i n one of three battery
modes: BROWNOUT, LCD, or SLEEP mode. Figure 21 shows a state diagram of the various operat i on
modes, with the possible transitio ns between modes. For information on the timing of mode transitions
refer to Figure 22 through Figure 24.
Figure 21: Operation Modes State Diagram
When V1 falls below V B IAS or the part wakes up under battery power, the part wil l automatically ent er
BROWNOUT mode (see Section 2.5 Wake-Up Beha vior). From BROWNOUT mode, the part m ay enter
either LCD mode or SLE EP mode, as controll ed by the MPU via the I/O RAM bits LCD_ONLY and SLEEP.
The transition from MISSION mode t o BROWNOUT m ode i s signaled by the IE_PLLFALL interrupt flag
(SFR 0xE8[7]). The transition in the other direction is signal ed by the IE_PLLRISE interr upt flag (SFR
0xE8[6]), when the PLL becomes stabl e.
Meters that do not require functionali ty in the battery m odes, e.g. meter s that only use the SLEEP
mode to maintain the RTC, still need t o contain code that brings the chip from BROWNOUT
mode to SLEEP mode. Otherwise, t he chip remains in BROWNOUT mode onc e the system
power is missi ng and consumes more current than intended.
Similarly, met ers equipped with batteries need to cont ai n code that transitio ns t he chip to SLEE P
mode as soon as the battery is attached in production. Otherwise, remaining in BROWNOUT
mode would unnecessarily drain the batt ery .
V3P3SYS
rises
V3P3SYS
falls
MISSION
BROWNOUT
LCD
SLEEP or
V1 > VBIAS
V1 <= VBIAS
LCD_ONLY
RESET &
VBAT_OK
RESET
IE_PLLRISE IE_PLLFALL
IE_PB
IE_WAKE
PB
timer
timer
PB
RESET &
V3P3SYS
rises
V3P3SYS
rises
VBAT_OK
VBAT_OK
VBAT_OK
VBAT_OK
SLEEP
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 57
To facilitate transition to sleep m ode, which is useful when an unprogrammed IC is mounted on a PCB
with a battery i nst al l ed, the Teridian production test programs the foll owing six-byte seque nce into the
flash location starting at address 0x0 0000: 0x74 - 0x40 - 0x90 - 0x20 - 0xA9 - 0xF0. This sequence de-
codes to the followin g assembler code:
0000: 7440 MOV A,#40 ; set bit 6 in accumulator
0002: 9020A9 MOV DPTR,#20A9 ; point to I/O RAM address 0x20A9
0005: F0 MOVX @DPTR,A ; set bit 6 (sleep) in 0x20A9
Transitions from both LCD and SLEEP m ode are initiated by the wake-up timer timeout conditions or
pushbutton events. When the PB pin is pulled high (pushbutton is pre ss ed), the IE_PB interrupt flag (SFR
0xE8[4]) is set, and when the wake-up timer times out, the IE_WAKE interrupt flag (SFR 0xE8[5]) is set.
In the absence of sy st em power, if the volt age m argin for the LDO regul ator providing 2.5 V to the internal
circuitry becomes too low to be safe, the part automatically enters sleep mode (BAT_OK false). The battery
voltage must stay above 3 V to ensur e that BAT_OK remains true. Under this condit i on, the 71M6531
stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK true). Table 52 shows
the circuit funct i ons available in each operating mode.
Table 52: Available Circuit Functions
Circuit Function System Power Battery Po wer (Nonvolatile Supply)
MISSION BROWNOUT LCD SLEEP
CE
Yes
–
–
–
CE Data RAM Yes Yes – –
FIR Yes – – –
Analog circuit s Yes – – –
MPU clock rate From PLL, as
defined by
MPU_DIV[2:0]
28.672 kHz
(7/8 of 3276 8 Hz) – –
MPU_DIV[2:0] Yes – – –
ICE Yes Yes – –
DIO Pins Yes Yes – –
Watchdog Timer Yes Yes – –
LCD Yes Yes Yes –
EEPROM Interface (2-wire) Yes Yes (8 kb/s) – –
EEPROM Interface (3-wire) Yes Yes (16 kb/s) – –
UART Yes 300 bd – –
Optical TX modulat i on Yes – – –
Flash Read Yes Yes – –
Flash Page Erase Yes Yes – –
Flash Write Yes – – –
RAM Read and Write Yes Yes – –
Wakeup Timer Yes Yes Yes Yes
OSC and RTC
Yes
Yes
Yes
Yes
XRAM data preservation Yes Yes – –
V3P3D voltage out put pin Yes Yes – –
GPO – GP7 registers Yes Yes Yes Yes
– indicates not active
2.3.1 BROWNOUT Mode
In BROWNOUT mod e, most non-meteri ng di gital functions are active (as shown in Table 52), including
ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a l ow bias current regulat or will provide
2.5 Volts to V2P5 and V2P5NV. The regulator has an output called BAT_OK to indicate that it has sufficient
overhead. When BAT_O K = 0, the part will enter SLEEP mode. From B ROWNOUT mode, t he processor
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
58 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically
transition from any of the battery m odes to MISSION mode, once the PLL has s ettled.
The MPU will run at 7/ 8 of the crystal clo ck ra te. T hi s permits the UA RTs to be operated at 300 bd. In
this mode, the MPU clock has substantial short-term jitter.
The value of MPU_DIV[2:0] will be reme m bered (not changed) as the part enter s and exits BROWNOU T.
MPU_DIV[2:0] will be ignored during B ROWNOUT.
While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in the zero state disabling both the ADC and
the CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts.
2.3.2 LCD Mode
In LCD mode, the data contained in the LCD_SEGn[3:0] fields is displayed. Up to four LCD segments,
each connected to pins SEG18 and SE G 19, can be made to bli nk without the inv ol vement of the M P U,
which is disabled in LCD mode. To minim ize power, only segments that might be used should be
enabled.
LCD mode can be exited only by system power up, a timeout of the wake-up timer, or a push button.
When the IC exits LCD mode, the MPU can discover the event that caused the exit by reading the interrupt
flags and interpret them as follows:
• IE_WAKE = 1 indicates t hat the wake timer has expired.
• IE_PB =1 indicate s that the pushbutton input (PB) wa s acti vated.
• COMPSTAT = 0 indicates that a reset occurred but that m ai n power is not yet available.
• If none of the above conditions applie s, system power (V3P3SYS) must have been restored
After the transition from LCD mode to MISSION or BROWNOUT mode, the PC will be at 0x0000, the
XRAM is in an undefined state and the I/O RAM is only partially preserved (see the description of I/O RAM
states in Section 4.2). The GP0[7:0] through GP7[7:0] registers are preserved unless RESET goes high.
2.3.3 SLEEP Mode
In SLEEP mode, the battery current i s minimized and onl y the Oscillator and RTC functions are active.
This mode can be exited only by system power-up, a timeout of t he wake-up t imer, or a push button event.
When the IC exits SLEEP mode, th e MPU can discover the e vent tha t caused the exit by read ing the
interrupt flags and interpret them as follows:
• IE_WAKE = 1 indicates t hat the wake timer has expired.
• IE_PB =1 indicates that the pushbutt on input (PB) was acti vated.
• COMPSTAT = 0 indicates that a reset occurred but that m ain power is not yet av ai l able.
• If none of the above conditions applie s, system power (V3P3SYS) must have been restored
After the transition from SLEE P m ode to MISSION or BRO WNOUT mode the PC will be at 0x0000, the
XRAM is in an undefined state and the I/O RAM is only partially preserved (see the description of I/O RAM
states in Section 4.2). The GP0[7:0] through GP7[7:0] registers are preserved unless RESET goes high.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 59
Figure 22: Tran sition from BROWNOUT to MISSI O N M o de when System Power Returns
Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together
time
System
Power
(V3P3SYS)
MPU Mod e
Battery
Current
Transition
MPU Clock
Source Xtal PLL
(4.2MHz/MUX_DIV)
PLL_OK
MISSION
2048...4096
CK32 cycles
300nA
13..14 CK
cycles
WAKE
BROWNOUT
V1_OK
time
V3P3SYS
and VBAT
MPU Mod e
Battery
Current
MPU Clock
Source Xtal PLL
(4.2MHz)
PLL_OK
MISSION
300nA
WAKE
Internal
RESETZ
BROWN-
OUT
1024 CK32
cycles
14.5 CK32
cycles
4096 CK32
cycles
V1_OK
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
60 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Figure 24: Power-Up Timing with VBAT only
2.4 Fault and Reset Behavior
2.4.1 Reset Mode
When the RESE T pi n i s pulled high, all digital activity stops. The oscillator and RTC m odule continue to
run. Additionally, al l I/O RAM bits are set to their default states. As long as V 1, the input voltage at the
power fault block, is greater than V BIAS, the internal 2 .5 V regulator will continue to provide po wer t o the
digital section.
Once initiated , the reset mode will persi st until the reset timer times out, signifi ed by WAKE rising. This
will occur in 4100 cycles of the real ti m e clock after RE SET goes low, at which time the MPU will begi n
executing it’s pre-boot and boot sequences from addres s 00. See the Program Security description in the
Flash Memory section for additional descriptions of pre-boot and boot.
If system power is not present, the res et timer duration will be 2 cy cles of the crystal clock at which time
the MPU will begin ex ecuting in BROWNOUT mode, starting at address 00.
2.4.2 Power Fault Circuit
The 71M6531D/F and 71M6532D/F include a comparato r to monitor system power fault condit ions.
When the output of the comparator f al ls (V1<VBIAS), the I/O RAM bits PLL_OK are zeroed and the part
switches to BROWNOUT mode if a battery is present. Once system power ret urns, the MPU remains in
reset and does not transition to MISSION mode until 2048 to 4096 CK32 clock cycles later, when PLL_OK
rises. If a battery i s not present, as indicated by B AT_OK=0, WAKE will fall and the part will enter SLEEP
mode.
There are several conditions the device could be in as system power returns. If the part is in BROWNOUT
mode, it will automatically switch to MISSION mode when PLL_OK rises. It will receive an interrupt indicating
this. No configuration bits wil l be re set or reconfigured during this transition.
If the part is in LC D or S LEEP mode when system power returns, it will also switch to MISSION mode
when PLL_OK rises. In this case, all conf i gurat i on bits will be in th e reset state due to WA KE having
been zero. The RTC clock will not be disturb ed, but the MPU RAM m ust be re-initialized. The hardware
watchdog timer will become active when the part enters MI S SION mode.
If there is no bat tery when system power returns, the part wil l switch to MISSION mode when PLL_OK
rises. All configuration bi ts will be in re set state and RTC a nd M PU RAM data will be unknown and must
be initialized by the M PU.
time
VBAT
MPU Mod e
Battery
Current
MPU Clock
Source Xtal
PLL_OK
WAKE
Internal
RESETZ 1024 CK32
cycles
BROWNOUT
14.5 CK32
cycles
VBAT_OK
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 61
2.5 Wake-Up Behavior
As described above, the part will always wake up in MISSION mode when system power is restored.
Additionally, the part wil l wake up in BRO WNOUT mode when PB rises (push b utton is pressed) or when
a timeout of the wake-up timer occurs.
2.5.1 Wake on PB
If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally
pulled to GND and can be pulled high by a push button depression. Before the PB signal rises, the MPU
is in reset due to WA KE being low. When PB rises, WAKE rises and within three crystal cycles, the MPU
begins to execute. The MPU can determi ne whether the P B signal woke it up by chec king the IE_PB flag.
Figure 25 shows the Wa ke Up timing.
For debouncing, the PB pin is monito red by a state machine operating from a 32 Hz clock. This circuit
will reject between 31 ms and 62 ms of noise. Detection hardware will i gnore all transitio ns after the initial
rising edge. This will cont inue until the MPU clears the IE_PB bit.
Figure 25: Wake Up Timi ng
2.5.2 Wake on Timer
If the part is in SLE EP or LCD mode, it c an be awakened by the w ake-up timer. Until this timer times out,
the MPU is in reset d ue to WAKE being low. When the wake-up timer times out, the WAKE signal rises
and within three crystal cycles, the MPU begins to execute. The MPU can det ermine whether the timer
woke it by checking the AUTOWAKE interrupt flag (IE_WAKE).
The wake-up t i m er begins timing when the part enters LCD or SLEEP mode. Its durati on is controlled by
WAKE_PRD[2:0] and WAKE_RES. WAKE_RES select s a timer LSB of either 1 minute (WAKE_RES = 1) o r
2.5 seconds (WAKE_RES = 0). WAKE_PRD[2:0] sele cts a duration of from 1 to 7 LSBs.
The timer is arme d by WAKE_ARM = 1. It m ust be armed at least three RTC cycles before SLEEP or
LCD_ONLY is initiated. Setting WAKE_ARM presets the timer with the values in WAKE_RES and WAKE_PRD
and readies the tim er to start when the proce ssor wri tes to SLEEP or LCD_ONLY. The timer is reset and
disarmed whenever the processor i s awake. Thus, if it is desired to wake the MPU periodical l y (every 5
seconds, for ex am pl e) the timer must be rearmed every time the MPU is awakened.
2.6 Data Flow
The data flow be tween the Co mp u te En gine (CE) and the MPU is s hown in
Figure 26. In a typic al
application, the 32-bit CE sequentially processes the samples from the voltage inputs on pin s IA, VA, IB
and VB, performi ng calculations to m easure active power (Wh), reactive power (VARh), A2h and V2h for
four-quadrant metering. These measu rements are then accessed by the M PU, processed further and
output using the peri pheral devices available to the MPU.
Figure 26 illustrates the CE/MPU data flow.
time
System
Power
(V3P3SYS)
MPU Mod e
PLL_OK
15 CK32
cycles
WAKE
LCD
PB or wake-
up tim er
BROWNOUT
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
62 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Figure 26: MPU/CE Data Flow
2.7 CE/MPU Communicati on
Figure 27 shows t he functional relationships between the CE and the MPU. The CE is controlled by the
MPU via shared registers in the I /O RAM and in RAM.
The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to
the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. Thi s signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE
is updating data to the output region of the RAM. This will occur whenever the CE has finished generating
a sum by completing an accumulation interval determined by SUM_CYCLES[5:0] * PRE_SAMPS[1:0] samples.
Interrupts to the M P U occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Refer to Section 4.3 CE Interfac e Description for additional information on setting up the device using the
MPU firmware.
VARSUM
WSUM
APULSEW
APULSER
EXT PULSE
SAG CONTROL
DATA
DIO
XFER BUSY
SAMPLES
CE
MPU
INTERRUPTS
I/O RAM (Configuration RAM)
Mux Control
ADC
DISPLAY (Memory
mapped LCD
segments)
SERIAL
(UART0/1)
EEPROM
(I2C)
VAR
(DIO7) PULSES
W (DIO6)
CE BUSY
Figure 27: MPU/CE Communication
CE
MPU
Pre
-
Processor
Post
-
Processor
IRQ
Processed
Metering
Data
Pulses
I/O RAM (Configuration RAM)
Samples
Data
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 63
3 Application Information
3.1 Connection of Sensors
Figure 28 through Figure 30 show how resistive dividers, current transformers, Rogowski coils and resistive
shunts are connect ed to the voltage and current inputs of the 71M6531.
The analog input pi ns of the 71M65XX are designed for sensor s with low source im pedance. RC
filters with resi st ance values higher than those implem ented in the Teridian Demo Boards should be
avoided.
Figure 28: Resistive Voltage Divider
Figure 29: CT with Single Ended (Left) and Differential I nput (Right) Connection
Figure 30: Resistive Shunt (Left) and Rogowski Sensor (Right ) Connection
3.2 Connecting 5-V Devices
All digital input pi ns of the 71M6531D/F and 71M6532D/F are compatible with external 5-V devices. I/O
pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V
devices.
VA = Vin * R
out
/(R
out
+ R
in
)
V
in
R
in
R
out
VA
V
out
R
1/N
I
in
I
out
Filter
V3P3
IA
InP
InN
V3P3A
V
OUT
I
OUT
I
IN
R
1/N
V
DIFF
Vout
R
Iin IA
V3P3
Vout = c*dIin /dt
Vout
1/N
Iin
IAN
IAP
V3P3A
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
64 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
3.3 Temperature Measurement
Measurement of absolute temperature uses the on-chi p temperature senso r and applying the f oll owing
formula:
n
n
n
T
SNTN
T+
−
=))((
In the above formula, T is the tempe rat ure in °C, N(T) i s t he A DC count at temper ature T, Nn is the ADC
count at 25°C, Sn is the sensitivity in LSB/°C as stated in t he Electrical Specifi cations and Tn is +25 °C.
It is recommended that temperatu re m easurements be based on TEMP_RAW_X which is the sum of two
consecutive temperature readings, thus being higher by a factor of two than the raw sensor readings.
3.4 Temperature Compensation
3.4.1 Temperature Coefficients:
The internal volt age reference VREF is calibrated duri ng device manufacture.
The temperature c oefficient TC2 is giv en as a constant that represents typical component behavior (in
µV/°C2). TC1 (µV/°C) can be calculated for t he i ndi vidual chip from the contents of the TRIMT[7:0] I/O
RAM register. TC1 and TC2 allow compensati on for variations of t he reference voltage to within ± 40
PPM/°C.
Since TC1 and TC2 are gi ven in µV/°C a nd µ V/°C2, respectively , the value of the V RE F voltage
(1.195V) has to be taken into account when transitioning to P PM/°C and PPM/° C2. This means
that PPMC = 26.84*TC1/1.195 and PP M C2 = 1374*TC2/1.195).
Close examination of the electrical specification (see Table 53) reveals that the achievable deviation is
not strictly ±40 PPM/°C over the whole temperature range: Only for temperat ures for which T-22 > 40 (i.e.
T > 62°C) or for which T-22 < -40 (i.e. T < -18°C), the dat a sheet states ±40 PPM/°C. For temperatures
between -18°C and +62°C, the erro r should be considered constant at ±1, 600 P PM, or ±0.16%.
Parameter Condition Min Typ
VREF(T) deviation from VN OM (T)
)40,22max( 10
)( )()( 6
−
−
TTVNOM TVNOMTVREF
-40 +40 PPM/ºC
Table 53: VREF Definition for 6513H
Figure 31 shows t his concept graphically. The “box” f rom -18°C to +62°C r eflects the fact t hat it is imprac-
tical to measure the t em perature coeffi cient of high-quality ref erences at small temperature excur sions.
For example, at +25°C, the expected error would be ±3°C * 40 PPM/°C, or just 0.012%.
The maximum dev i ation of ±2520 PPM (or 0.252%) i s reached at the temperature extreme s. If the refer-
ence voltage is us ed to measure both voltage and current , the identical errors of ±0.252% add up to a
maximum Wh registration error of ±0.504%.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 65
Figure 31: Error Band for VREF over Temperature
3.4.2 Temperature Compensation for VREF
The bandgap temperature is used to digitally compensate the power outputs for the temperature dependence
of VREF, using t he CE register GAIN_ADJ. Since the band gap amplifier is chopper-stabilized, the most
significant long-term drift mechanism in the voltage reference is remov ed.
The following f orm ul a is used to determine the GAIN_ADJ value of the CE. I n this formula, TEMP_X is the
deviation from nom i nal or calibration te m perature expressed i n multiples of 0.1 °C:
23
2
14 22_
2
_
16385_ PPMCXTEMPPPMCXTEMP
ADJGAIN ⋅
+
⋅
+=
3.4.3 System Temperature Compensation
In a production elect ricity meter, t he 71M6531 or 71M6532D/F is not the only compone nt contributing to
temperature dependen cy . A whole range of components (e.g. current transformers, resistor dividers,
power sources, filter capacitors) wil l contribute temperature effect s.
Since the output of the on-chip temperature sensor is ac ce ssible to the MPU, t em perat ure compensation
mechanisms with great flexibility are possible. MPU access to GAIN_ADJ permits a system-wide temperature
correction over t he entire meter rather than local to the chip.
3.4.4 Temperature Compensation for the RTC
In order to obt ai n accurate readings from the RTC, the following procedure is recommended:
1. At the time of meter calibration, the crystal oscillator is calibrated using the RTCA_ADJ register in I/O
RAM to be as close t o 32768 Hz as possible. The recommended procedure is to connect a hi gh-
precision freq uency counter to the TMUXOUT pin and select 0x11 for TMUX[4:0]. This will generate
a 4-second pulse at TMUXOUT that c an be used to trim RTCA_ADJ to the best value.
2. When the meter is in service, the MPU takes frequent temp erature readi ngs. If the temper ature
characteristics of t he crystal are known, the temperature r eadings can be used to m odify the settings
for the I/O RAM registers PREG[16:0] and QREG[1:0] in order to keep the crystal frequency close to
32768 Hz.
3. After periods of operation under battery power, the temperature for the time the meter was not powered
can be estimated by averaging the temperatures before and after battery operation. Based on this, the
overall correc tion for the RTC time can be calculated and applied to the RTC af ter main power returns
to the meter.
-2800
-2400
-2000
-1600
-1200
-800
-400
0
400
800
1200
1600
2000
2400
2800
-40 -20 020 40 60 80
Error Band (PPM) over Temperature (°C)
±40 PPM/°C
±40 PPM/°C
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
66 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
3.5 Connecting LCDs
The 71M6531D/F and 71M6532D/F have an on-chip LCD controller cap able o f control ling s tatic or
multiplexed LCDs. Figure 32 shows the basic connecti on for an LCD.
The following dedicated and multi-u se pins can be assign ed as LCD segment pins f or the 71M6531D/ F:
• 12 dedicated LCD segment pins: SEG 0 to SEG2, SEG7, SE G 8, SEG12 to SEG18.
• 7 dual-function pins: SEG3/PCLK, SEG4/PSDO, SEG5/PCSZ, SEG6/PSDI, E_RXTX/SEG9,
E_TCLK/SEG10, and E_RST/SEG11.
• 14 combined DIO and segment pins: SEG24/DIO4 to SEG35/DIO15, SE G 37/DIO17, SEG48/DIO28,
SEG49/DIO29 and S EG63/DIO43 to SEG66/DIO46.
The following dedicated and multi-use pins can be assigned as LCD segm ents for the 71M6532D/F:
• 15 dedicated LCD segment pins: SEG0 to SEG2, SEG8, SEG12 - SEG18, SEG20 - SEG23.
• 9 dual-function pins: MUX_SYNC/SEG7, E_RXTX/SEG9, E_TCLK/SEG10, E_RST/SEG11,
SEG3/PCLK, SEG4/PSDO, SEG5/PCSZ, SEG6/PSDI.
• 43 combined DIO and segment pins, as described in section 1.5.8.
.
Figure 32: Connecting L CDs
3.6 Connecting I2C EEP ROMs
I2C EEPROMs or other I2C compatible devices should be connected to the DI O pi ns DIO4 and DIO5, as
shown in Figure 33.
Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation i n B ROWNOUT mode) should be used
for both SCL and SDA signals. The DIO_EEX[1:0] register in I/O RAM must be set to 01 in order to convert
the DIO pins DIO4 and DIO5 to I2C pins SCL and S DA .
Figure 33: I2C EEPROM Connection
DIO4
DIO5
71M6531D/F
71M6532D/F
EEPROM
SCL
SDA
V3P3D
10 k
Ω
10 k
Ω
segments
71M6531D/F or 71M 6532D/F
LCD
commons
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 67
3.7 Connecting Three-Wi re EEPROMs
µWire EEPROMs and other compatibl e devices should be connected to t he DIO pins DIO4 an d DIO5, as
shown in Figure 34 and described belo w:
• DIO5 connects t o both the DI and DO pins of the three-wire device.
• The CS pin must be connected to a vacant DI O pi n of the 71M6531.
• In order to prevent bus contention, a 10 kΩ to resistor is used t o separate the DI and DO signals.
• The CS and CLK pins should be pulled down with resistors to prevent operation of the three-wire device
on power-up, bef ore t he 71M6531 can est abl ish a stable signal f or CS and CLK.
• The DIO_EEX[1:0] register i n I/O RAM must be set to 2 (b10) in order to convert the DIO pins DIO4
and DIO5 to µWire pins.
The µ-Wire EEPROM i nterface is only f unct ional when MPU_DIV[2:0] = 000.
Figure 34: Three-Wire EEPROM Connection
3.8 UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and addit ionally pro tected by a 100 pF
ceramic capacitor, a s shown in Figure 35.
Figure 35: Connections for UA RT0
3.9 Optical Interface (UART1)
The OPT_TX and OPT_RX pins can be used for a reg ular ser ial in terface (by connec ting a RS-232
transceiver for example ), or they can be used to directly operate optical components (for example, an
infrared diode and phototransistor implementing a FLAG interface). Figure 36 shows the basic connections
for UART1. The OPT _TX pin becomes active when the I/O RAM register OPT_TXE is set to 00.
TX
RX
71M6531D/F, 71M6532D/F
10 k
Ω
100 pF
RX
TX
71M653X
EEPROM
100 kΩ
DIO4
DIO5
CLK
DI
V3P3D
100 kΩ
CS
DIOn
DO
10 k
Ω
VCC
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
68 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV
and OPT_RXINV, respectively.
The OPT_TX out put may be modulated at 38 kHz when system power is present. Modulation is not
available in BROWNOUT mode. The OPT_TXMOD bit enables modulation. The duty cy cle i s controlled
by OPT_FDC[1:0], which can select 50%, 25% , 12.5% and 6.25% duty cycle. A 6.25% dut y cycle means
OPT_TX is low for 6.25% of the period. The OPT_ RX pin uses digital signal thresholds. It may need an
analog filter when receiving modulated optical signals.
With modulation, an optical emitt er can be operated at hi gher current than nominal, enabling it to
increase the distance along the opti cal path.
If operation in B ROWNOUT mode is desired, the external components should be connected to V3P3D.
Figure 36: Connection for Optical Components
3.10 Connecting the V1 Pin
A voltage divider should be used to establish that V1 is in a safe range when the meter is in MISSION
mode (see Figure 37). V1 must be lower than 2.9 V in al l cases in order to keep the hardware watchdog
timer enabled. The resistor divider ratio must be chosen so t hat V1 crosses t he VBIAS threshold when
V3P3 is near the minimum supply voltage (3.0 VDC). A series resistor (R3) provides additional hysteresis,
and a capacitor t o ground (C1) is added for enhanced EMC immunity.
The amount of hyst eresis depends on the choice of R1 and R3: If V1 < VBIAS, approximately 1 µA will
flow into the on-chip V1 comparator causing a voltage drop. If V1 ≥ VBIAS, almost no current will flow
into the comparator. The voltage drop will require V3P3 to be slightly higher f or V1 to cross the V BIAS
threshold when V 3P 3 is rising as compared to when V3P3 is falling. Maintaining suf ficient hysteresis
helps to eliminate rapid mode changes which may occur in cases where the power suppl y is unstable with
V1 close to the VB IAS threshold point.
Figure 37: Voltage Divider for V1
V3P3
R2V1
R1R3
C1
100pF
GND
16.9kΩ20kΩ
OPT_TX
R
2
R
1
OPT_RX
71M6531D/F or 71M6532D/F
V3P3SYS
Phototransistor
LED
10 kΩ
100 pF
V3P3SYS
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 69
R
1
RESET
71M6533
DGND
100Ω
R
1
RESET
71M6533
DGND
100Ω
3.11 Connecting the Reset Pin
Even though a funct i onal meter will not nece ssarily need a reset s witch, it is useful t o have a reset push-
button for prototyping as shown in Figure 38, left side. The RESET signal may be sourced from V3P 3SYS
(functional in M ISSION mode only), V 3P3D (MISSION and BRO WNOUT modes), or VBAT (all mode s, i f
a battery is present ), or from a combination of these s ources, depending on the application.
For a production m eter, the RESET pi n should be protected by the by the ext ernal components shown in
Figure 38, right side. R1 should be in the rang e of 100 Ω and mount ed as closely as possible to the IC.
Figure 38: External Components for the RESET Pin: Push-button (Left), Production Circuit ( Right)
Since the 71M6531 generates its own power-on res et, a reset b utton or circuit ry, a s show n in Figure 38,
is only required for test units and prototypes.
3.12 Connecting the Emulator Por t Pins
Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection
from EMI as illustrated in Figure 39. Productio n boards should have the ICE_E pin connect ed to ground.
Figure 39: External Components for the Emulator Interface
3.13 Connecting a Battery
It is important that a valid voltage is connected to the VB AT pin at all times. For m eters without a battery,
VBAT should be connected directly to V3P 3S YS. Designs for meters with batteries need to ensure that
the meter functi ons even when the battery voltage decreases below the sp ecif i ed voltage for VBAT. This
can be achieved by connecting a diode from V3P3SYS to VBAT. However, the battery test will yield
inaccurate results if that techni que is used, since the voltage at V3P3S Y S will feed current t o the VBAT
pin. A better soluti on is shown in Figure 40: During the battery test, a DIO pin is acti vated as an output
and applies a low voltage to the anode of the diode. This prevents the voltage at the power supply to in-
fluence the volt age at the VBAT pin.
E_RST
71M6531D/F
71M6532D/F
E_TCLK
62
Ω
62 Ω
62 Ω
22 pF
22 pF
22 pF
LCD
Segments
ICE_E
V3P3D
E_RXT
(optional)
R
1
RESET
GNDD
V3P3D
R
2
VBAT/
V3P3D
Reset
Switch
1k
Ω
0.1µF
10k
Ω
71M6531D/F
71M6532D/F
71M6531D/F
71M6532D/F
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
70 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Figure 40: Connecting a Bat tery
As mentioned in section 2.3, meters equipped with batteries need to contain code that transitions
the chip to SLEE P m ode as soon as the batt ery is attached in production. Otherwise, rem aining
in BROWNOUT mode would add unnece ss ary drain to the battery.
3.14 Flash Programming
Operational or test code can be programmed into the fl ash memory using either an in-circuit emulator or
the Flash Programmer M odule (TFP2) avai l able from Teridian. The flash programming procedure uses
the E_RST, E_RXTX and E_TCLK pins. The FL_BANK[2:0] register must be set to the value corresponding
to the bank that i s being programmed.
3.15 MPU Firmw a r e
All application-specific MPU functions mentioned in the Application Information section are f eatured in the
demonstratio n source code supplied by Teridian. The cod e i s available as part of the Demonstration K i t
for the 71M6531D/F and 71M6532D/F. The Demonstration Kits come with the 71M6531D/F or 71M6532D/F
preprogramm ed wi th demo firmwar e and mounted on a functional sample meter Demo B oard. The Demo
Boards allow f or qui ck and efficient ev aluation of the IC without having to writ e firmware or hav i ng to
supply an in-circuit em ulator (ICE).
3.16 Crystal Oscillator
The oscillator dri ves a standard 32.768 kHz watch crystal. The oscillator has been design ed specifically
to handle these crystals and is compatible with their high impedance and limited power handling capability.
The oscillator power dissipation is very low to maximize the li fetime of any battery backup device attached
to VBAT.
Board layouts with minimum capacit ance from XIN to X O UT wil l require less battery current. Good
layouts will have X IN and XOUT shielded f rom each other.
For best rejection of electromagnetic interference, connect the crystal body and the ground
terminals of the two crystal capacitors to GNDD through a ferrite bead. No external resistor
should be connected across the crystal, since the oscillator is self-biasing.
71M6531/71M6532
V3P3A
DIO
Power
Supply V3P3SYS
VBAT
Battery or
Super-Cap
+
-
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semi conductor Corporation 71
3.17 Meter Calibration
Once the Teridian 71M6531D/F or 71M6532D/F energy meter device has been installed in a meter system,
it must be calibrated. A complete calibrat i on i ncludes the foll owing:
• Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers
and signal conditi oni ng components a s well as of the internal reference voltage (V RE F).
• Establishment of the reference temperature (Section 3.3) for temperature measurement and temperature
compensation (Section 3.4).
• Calibration of the battery voltage m easurement (Section 1.5.13).
• Calibration of the oscillator frequency (Section 1.5.3) and tempe rature compensation for the RTC
(Section 3.4.4).
The metrology secti on can be calibrate d using the gain and ph ase adjustment factors accessible t o the
CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning,
especially the resist ive com ponents . Phase adjus tment is provided to compensa te for phase shifts
introduced by the current sensors or by the effects of react ive power supplie s.
Due to the flex ibi l i ty of the MPU firmware, any calibrat i on m ethod, such as calibr ation based on energy , or
current and vo ltage can be i mple ment ed. It is also po ssibl e to implement segment -wise calibration (depending
on current range).
The 71M6531D/F and 71M6532D/F support common industry standard calibration techniques, such as single-
point (ene rgy-only), multi-point (energy, Vrms, Irms) and auto-calibration.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
72 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
4 Firmware Interface
4.1 I/O RAM and SFR Map – Functional Order
In Table 54, unimplemented (U) and r eserved (R) bits are shaded in light gray. Unimplemented bits have no memory st orage, writing them has no
effect, and reading them always retur ns zero. Reserved bits m ay be in use and sho uld not be changed from the values given in par entheses.
Writing values other than those sh own in parenthesis to reserved bits may have undesirable side effects and must be avoided.
Non-volatile b i ts are shaded in dark gray. Non-volatile bi ts are backed-up during power failures if the system i ncludes a battery con nected to the
VBAT pin.
This table lists only the SFR registers th at are not generic 8051 S FR registers. B its marked wit h † apply to the 71M6531D/F only , bits marked with
‡ apply to the 71M6532D/F only and sh ould be 0 for the other dev ice.
Table 54: I/O RAM Map in Functional Order
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration:
CE0 2000 EQU[2:0] CE_E CE10MHZ U
CE1
2001
PRE_SAMPS[1:0]
SUM_CYCLES[5:0]
CE2 2002 U CHOP_E[1:0] RTM_E WD_OVF EX_RTC EX_XFR
COMP0
2003
U
PLL_OK
U
U
U
U
U
COMP_STAT
CONFIG0
2004
VREF_CAL
PLS_INV
U
CKOUT_E
VREF_DIS
MPU_DIV[2:0]
CONFIG1 2005 U U ECK_DIS M26MHZ ADC_E MUX_ALT U M40MHZ
VERSION
2006
VERSION[7:0]
CONFIG2 2007 OPT_TXE[1:0] EX_PLL EX_FWCOL FIR_LEN[1:0] OPT_FDC[1:0]
CE3
209D
U
MUX_DIV[3:0]
CE4 20A7 BOOT_SIZE[7:0]
CE5
20A8
CE_LCTN[7:0]
WAKE
20A9
WAKE_ARM
SLEEP
LCD_ONLY
U
WAKE_RES
WAKE_PRD[2:0]
TMUX 20AA U TMUX[4:0]
ANACTRL
20AB
R (0000)
LCD_DAC[2:0]
CHOP_I_EN‡
CONFIG3 20AC U SEL_IBN‡ CHOP_IB‡ U SEL_IAN‡ CHOP_IA‡
CONFIG4
20AD
U
R (0)
R (0)
U
R (0)
R (0)
Interrupts and WD Timer
:
INTBITS
SFR F8
WD_RST
INT6
INT5
INT4
INT3
INT2
INT1
INT0
IFLAGS
SFR E8
IE_PLLFALL
IE_PLLRISE
IE_WAKE
IE_PB
IE_FWCOL1
IE_FWCOL0
IE_RTC
IE_XFER
Flash Memory:
ERASE
SFR 94
FLSH_ERASE[7:0]
FLSHCTL SFR B2 PREBOOT SECURE WRPROT_BT WRPROT_CE U FLSH_MEEN FLSH_PWE
FL_BANK
SFR B6
U
FLBANK[2:0]
PGADR SFR B7 FLSH_PGADR[5:0] U
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 73
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Digital I/O:
20AF U DIO_RRX[2:0]
DIO0 2008 DIO_EEX[1:0] OPT_RXDIS OPT_RXINV DIO_PW DIO_PV OPT_TXMOD OPT_TXINV
DIO1 2009 U DIO_R1[2:0]† U DI_RPB[2:0]
DIO2 200A U U U DIO_R2[2:0]
DIO3
200B U
DIO_R5[2:0]
U
DIO_R4[2:0]
DIO4 200C U DIO_R7[2:0] U DIO_R6[2:0]
DIO5
200D U
DIO_R9[2:0]
U
DIO_R8[2:0]
DIO6
200E U
DIO_R11[2:0]
U
DIO_R10[2:0]
200F R(0) R (0) U
DIO_PX
DIO_PY
U
DIO7
SFR 80
DIO_0[7:1]
DIO_0[0]†
DIO8
SFR A2
DIO_DIR0[7:1]
DIO_DIR0[0]†
DIO9
SFR 90
DIO_1[7:0] (Port 1)
DIO10
SFR 91
DIO_DIR1[7:0]
DIO11
SFR A0
DIO_2[7]‡
DIO_2[6]‡
DIO_2[5]‡
DIO_2[4] ‡
DIO_2[3] ‡
DIO_2[2] ‡
DIO_2[1]
DIO_2[0]‡
DIO12 SFR A1 DIO_DIR2[7] ‡ DIO_DIR2[6] ‡ DIO_DIR2[5] ‡ DIO_DIR2[4] ‡ DIO_DIR2[3] ‡ DIO_DIR2[2] ‡ DIO_DIR2[1] DIO_DIR2[0] ‡
DIO13 SFR B0 R(0) DIO_3[6]‡ DIO_3[5] DIO_3[4]† DIO_3[3] ‡ DIO_3[2] ‡ DIO_3[1] ‡ DIO_3[0] ‡
Real Time Clock:
RTCCTRL
2010 U
RST_SUBSEC
RTCA_ADJ 2011 U RTCA_ADJ[6:0]
SUBSEC1
2014
SUBSEC[7:0]
RTC0
2015 U
RTC_SEC[5:0]
RTC1 2016 U RTC_MIN[5:0]
RTC2
2017 U
RTC_HR[4:0]
RTC3 2018 U RTC_DAY[2:0]
RTC4 2019 U RTC_DATE[2:0]
RTC5
201A U
RTC_MO[3:0]
RTC6
201B
RTC_YR[7:0]
RTCADJ_H 201C U PREG[16:14]
RTCADJ_M
201D
PREG[13:6]
RTCADJ_L
201E
PREG[5:0]
QREG[1:0]
WE 201F RTC write protect register
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
74 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD Display Inte rfa ce:
LCDX
2020
MUX_SYNC_E
BME
R (0) R (0) U
LCDY
2021 U
LCD_Y
LCD_E
LCD_MODE[2:0]
LCD_CLK[1:0]
LCD_MAP0
2023
LCD_BITMAP[31:24]
LCD_MAP1 2024
LCD_BITMAP
[39]‡
LCD_BITMAP
[38]‡
LCD_BITMAP
[37]
LCD_BITMAP
[36]‡
LCD_BITMAP
[35]
LCD_BITMAP
[34]
LCD_BITMAP
[33]
LCD_BITMAP
[32]
LCD_MAP2 2025 LCD_BITMAP[47:40]‡
LCD_MAP3 2026 U LCD_BITMAP
[50]‡ LCD_BITMAP
[49] LCD_BITMAP
[48]†
LCD_MAP4 2027
LCD_BITMAP
[63] LCD_BITMAP
[62]‡ LCD_BITMAP
[61]‡ LCD_BITMAP
[60]‡ U
LCD_MAP5 2028
LCD_BITMAP
[71]‡ LCD_BITMAP
[70]‡ LCD_BITMAP
[69]‡ LCD_BITMAP
[68]‡ LCD_BITMAP
[67]‡ LCD_BITMAP
[66]† LCD_BITMAP
[65] LCD_BITMAP
[64]
LCD_MAP6
2029 U
LCD0
2030
LCD_SEG42[3:0]‡
LCD_SEG0[3:0]
LCD1
2031
LCD_SEG43[3:0]‡
LCD_SEG1[3:0]
LCD2
2032
U
LCD_SEG2[3:0]
LCD3 2033 LCD_SEG45[3:0]‡ LCD_SEG3[3:0]
LCD4
2034
LCD_SEG46[3:0]‡
LCD_SEG4[3:0]
LCD5 2035 LCD_SEG47[3:0]‡ LCD_SEG5[3:0]
LCD6 2036 LCD_SEG48[3:0]† LCD_SEG6[3:0]†
LCD7
2037
LCD_SEG49[3:0]
LCD_SEG7[3:0]
LCD8
2038
LCD_SEG50[3:0]‡
LCD_SEG8[3:0]
LCD9
2039 U LCD_SEG9[3:0]
…
…
…
…
LCD17 2041 U LCD_SEG17[3:0]
LCD18
2042
LCD_SEG60[3:0]‡
LCD_SEG18[3:0]
LCD19
2043
LCD_SEG61[3:0]‡
LCD_SEG19[3:0]
LCD20 2044 LCD_SEG62[3:0]‡ LCD_SEG20[3:0]‡
LCD21
2045
LCD_SEG63[3:0]
LCD_SEG21[3:0]‡
LCD22 2046 LCD_SEG64[3:0] LCD_SEG22[3:0]‡
LCD23 2047 LCD_SEG65[3:0] LCD_SEG23[3:0]‡
LCD24
2048
LCD_SEG66[3:0]†
LCD_SEG24[3:0]
LCD25
2049
LCD_SEG67[3:0]‡
LCD_SEG25[3:0]
LCD26
204A LCD_SEG68[3:0]‡ LCD_SEG26[3:0]
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 75
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD27
204B
LCD_SEG69[3:0]‡ LCD_SEG27[3:0]†
LCD28
204C
LCD_SEG70[3:0]‡
LCD_SEG28[3:0]
LCD29
204D
LCD_SEG71[3:0]‡ LCD_SEG29[3:0]
LCD30
204E
U LCD_SEG30[3:0]
…
…
…
…
LCD33
2053
U
LCD_SEG35[3:0]
LCD36 2054 U LCD_SEG36[3:0]‡
LCD37
2055 U
LCD_SEG37[3:0]
LCD38 2056 U LCD_SEG38[3:0]‡
…
…
…
…
LCD41
2059 U
LCD_SEG41[3:0]‡
LCD_BLNK
205A
LCD_BLKMAP19[3:0] LCD_BLKMAP18[3:0]
RTM:
RTM0H
2060 U
RTM0[9:8]
RTM0L
2061
RTM0[7:0]
RTM1H 2062 U RTM1[9:8]
RTM1L
2063
RTM1[7:0]
RTM2H
2064
U
RTM2[9:8]
RTM2L 2065 RTM2[7:0]
RTM3H
2066
U
RTM3[9:8]
RTM3L
2067
RTM3[7:0]
SPI Interface:
SPI…
2070
SPE
U
SP_CMD 2071 SP_CMD[7:0]
SP_ADH 2072 SP_ADDR[15:8]
SP_ADL
2073
SP_ADDR[7:0]
Pulse Generator :
PLS_W 2080 PLS_MAXWIDTH[7:0]
PLS_I
2081
PLS_INTERVAL[7:0]
ADC MUX:
SLOT0 2090 SLOT1_SEL SLOT0_SEL
SLOT1
2091
SLOT3_SEL
SLOT2_SEL
SLOT2 2092 R R
SLOT3 2093 R R
SLOT4
2094
R
R
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
76 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLOT5 2096 SLOT1_ALTSEL SLOT0_ALTSEL
SLOT6 2097
SLOT3_ALTSEL SLOT2_ALTSEL
SLOT7 2098 R R
SLOT8 2099 R R
SLOT9 209A R R
SPI Interrupt:
SPI0 20B0 U IEN_SPI U IEN_WD_NROVF
SPI1 20B1 U SPI_FLAG U WD_NROVF_FLAG
General-Purpose Nonvolatile Registers:
GP0 20C0 GPO[7:0]
… … …
GP7 20C7 GP7[7:0]
VERSION 20C8 VERSION[7:0]
Serial EEPROM:
EEDATA SFR 9E EEDATA[7:0]
EECTRL SFR 9F EECTRL[7:0]
† 71M6531D/F only
‡ 71M6532D/F only
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 77
4.2 I/O RAM Description – Alphabetical Order
The following conventions apply to the descriptions in this table:
• Bits with a W (write) direction are writ ten by the MPU into configuration RAM. Typically, they are initial ly stored in flash memory and copied to
the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining
bits are mapped to 2xxx.
• Bits with a R (read) direction can be read by the M PU.
• Columns labeled Reset and Wake describe the bit values upon reset and wake, respectively. “NV” in the Wake column means the bit is powered
by the nonvolat i l e supply and is not initialized. LCD-related registers labeled “L” retain dat a upon transition from LCD mode to BROWNOUT
mode and vice v ersa, but do not retain data in SLEEP mode. “–“ means that the v al ue is undefined.
• Write-only bits will return zero when they are rea d.
Table 55: I/O RAM Description - Alphabetical
Name
Location
Reset
Wake
Dir
Description
ADC_E 2005[3] 0 0 R/W Enables ADC and VREF. When disable d, removes bias cur rent.
BME 2020[6] 0 – R/W Battery Measure Enable. When set, a load current is immediately applied to the battery
and it is connected t o the ADC to be measured on Alternat i ve Mux Cycles. See the
MUX_ALT bit.
BOOT_SIZE[7:0] 20A7[7:0] 01 01 R/W End of space reserved for boot program . T he endi ng address of the boot region is
1024*BOOT_SIZE.
CE10MHZ 2000[3] 0 0 R/W CE clock select . When set, the CE is clocked at 10 MHz. Otherwise, the CE clock
frequency is 5 MHz.
CE_E 2000[4] 0 0 R/W CE enable.
CE_LCTN[7:0] 20A8[4:0] 31 31 R/W CE program locat i on. The starting address for the CE program is 1024*CE_LCTN.
CHOP_E[1:0] 2002[5:4] 0 0 R/W
Chop enable f or the reference band gap circuit. The value of CHOP will change on the
rising edge of MUXS YNC according to the value in CHOP_E[1:0]:
00 = toggle, except at the mux sync edge at the end of SUMCYCLE, an alternative
MUX frame is automatically inserted at the end of each acc um ulation interval.
01 = positive.
10 = reversed.
11 = toggle, no alternat i ve MUX frame i s inserted
CHOP_IA 20AC[0] 0 0 R/W This bit enables chop mode for the IA current channel (71M6532D/F only). CHOP_I_E
must be set also.
CHOP_IB 20AC[4] 0 0 R/W This bit enables chop mode for the IB current channel (71M6532D/F only). CHOP_I_E
must be set also.
CHOP_I_E 20AB[0] 0 0 R/W This bit must be set to enabl e chop mode for the current channels (71M6532D/F only).
CKOUT_E 2004[4] 0 0 R/W Control bit for the SEG19/CKOUT pin:
0: The pin is the SE G 19 LCD driver
1: The pin is the CK_FIR output (5 MHz in mission mode, 32 kHz in brownout m ode)
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
78 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
Name
Location
Reset
Wake
Dir
Description
COMP_STAT[0] 2003[0] – – R Status bit for the V1 comparator (same as V1_OK, see TMUXOUT)
DI_RPB[2:0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RRX[2:0]
2009[2:0]
2009[6:4]
200A[2:0]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
20AF[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W Connects dedicate d I/O pins DIO2 and DI O 4 through DIO11 as well as input pins PB,
DIO1 and RX t o i nternal resources. If m ore than one input is c onnected to the same
resource, the Multiple column in the table below specifies how they are combined.
DIO_Rx[2:0] Resource Multiple
000 NONE –
001 Reserved OR
010 T0 (Counter /Timer 0 clock or gate) OR
011 T1 (Counter /Timer 1 clock or gate) OR
100 High priority IO interrupt (int0 rising) OR
101 Low priority IO int errupt (int1 rising) OR
110 High priority IO interrupt (int0 fall-
ing) OR
111 Low priority IO i nterrupt (int1 fal l i ng) OR
DIO_DIR0[7:1] SFR A2 [7:1] 0 – R/W Program s t he direction of DIO pins 7 through 1. 1 indicat es an output. The bits are
ignored if the pin is not configu red as DIO. See DIO_PV and DIO_PW f or speci al option s
for DIO6 and DIO 7. See DIO_EEX[1:0] for special options for DI O 4 and DIO5.
DIO_DIR1[7:0] SFR 91 0 – R/W Programs the direction of DIO pins 15 through 8. 1 indicates an output. The bits are
ignored if the pin is not configured as I/O. See DIO_PX and DIO_PW for special options
for the DIO8 and DIO9 outputs.
DIO_DIR2[1] SFR A1[1] 0 – R/W Programs the di rect ion of DIO17.
DIO_0[7:0]
DIO_1[7:0]
DIO_2[1]
DIO_3[5:4]
SFR 80
SFR 90
SFR A0[1]
SFR B0[5:4]
0
0
0
0
−
–
–
–
R/W
R/W
R/W
R/W
The value on t he DIO pins. Pins config ured as LC D will read zer o. When writt en, chan ges
data on pins configured as outputs. Pins configured as LCD or input will ignore writes.
DIO_0[7:1] corresponds to DI O 7 through DIO1. PB is read on DIO_0[0].
DIO_1[7:0] corresponds to DI O 15 through DIO8.
DIO_2[1] corresponds to D IO17.
DIO_3[5:4] corresponds to DI O 28 and DIO29.
DIO_EEX[1:0] 2008[7:6] 0 0 R/W
When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes
SDCK and DIO5 becomes bi-directional SDATA.
DIO_EEX[1:0]
Function
00 Disable EEPROM i nterface
01 2-Wire EEPROM interface
10 3-Wire EEPROM interface
11 not used
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 79
Name
Location
Reset
Wake
Dir
Description
DIO_PV 2008[2] 0 0 R/W Causes VARP ULS E to be output on DIO7.
DIO_PW 2008[3] 0 0 R/W Causes WPULS E to be output on DIO6.
DIO_PX
200F[3]
0
0
R/W
Causes XPULSE to be output on DIO8.
DIO_PY
200F[2]
0
0
R/W
Causes YPULSE to be output on DIO9.
EEDATA[7:0] SFR 9E 0 0 R/W Serial EEPROM i nterface data.
EECTRL[7:0] SFR 9F 0 0 R/W Serial EEPROM interface control.
ECK_DIS 2005[5] 0 0 R/W Emulator clock disable. When ECK_DIS = 1, the em ulator clock is disabled.
If ECK_DIS is set, the emulator and programming devices will be unable to
erase or program the device.
EQU[2:0] 2000[7:5] 0 0 R/W Specifies the power equation to be used by the CE.
EX_XFR
EX_RTC
EX_FWCOL
EX_PLL
2002[0]
2002[1]
2007[4]
2007[5]
0
0
0
0
0
0
0
0
R/W
Interrupt enabl e bi ts. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-
WareCollision (FWCOL) and PLL interrupt s. Not e that if one of these interrupts is to
be enabled, its corr esponding MPU EX enabl e m ust also be set. S ee Section 1.4.9
Interrupts for details.
FIR_LEN[1:0] 2007[3:2] 1 1 R/W
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore controls
the time taken for each conversion.
[M40MHZ, M26MHZ] FIR_LEN[1:0] Resulting FIR
Filter Cycles Resulting
CK32 Cycles Resulting
DC Gain
[00], [10], or [11] 00 138 1 0.110017
01 288 2 1.000
10 384 3 2.37037
[01] 00 186 1 0.113644
01 384 2 1.000
10 588 3 3.590363
FL_BANK[2:0] SFR B6[2:0] 1 1 R/W Flash bank. Memory abov e 32 KB is mapped to the MPU address space from 0x8000
to 0xFFFF in 32 KB banks. When M PU address[15] = 1, the address in flash is
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
80 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
Name
Location
Reset
Wake
Dir
Description
FLSH_ERASE
[7:0] SFR 94[7:0] 0 0 W
Flash Erase Initi ate. (Default = 0x00). FLSH_ERASE is used to initiat e either the Flash
Mass Erase cy cle or the Flash Page Erase cycle. Specific p atterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
0x55 = Initiate Flash P age E rase cycle. Must b e proceeded by a write to
FLSH_PGADR[5:0] @ SFR 0xB7.
0xAA = Initiate Flash Mas s E rase cycle. Must be proceeded by a writ e to
FLSH_MEEN @ SFR 0xB2 and the debug (C C) port must be enabl ed.
Any other patt ern written to FLSH_ERASE will have no eff ect . The erase cycle is not
completed unti l 0x00 is written to FLSH_ERASE.
FLSH_MEEN SFR B2[1] 0 0 W
Mass Erase Enable.
0 = Mass Erase disabled (default).
1 = Mass Erase enabl ed.
Must be re-written for each new Mass Erase cycle.
FLSH_PGADR
[5:0] SFR B7 [7:2] 0 0 W
Flash Page Erase Address. (Default = 0 x00)
FLSH_PGADR[5:0] with FL_BANK[2:0], set s t he Fl ash Page Address (page 0 through
127) that will be era sed during the Page Erase cycle.
Must be re-written for each new Page Erase cycle.
FLSH_PWE SFR B2[0] 0 0 R/W
Program Writ e E nabl e. This bit must be cleared by the MPU aft er each byte write op-
eration. Write operations to this bit are inhibited when i nterrupts are enabled.
0 = MOVX commands refer to XRAM S pace, normal operation (default) .
1 = MOVX @DPTR, A m oves A to Program Space (Flash) @ DPTR.
GP0
…
GP7
20C0
…
20C7
0
…
0
NV
…
NV
R/W Non-volatile general-purpose registers powered by the RTC supply. These registers
maintain their value in all power modes, but will be cleared on reset. The values of
GP0…GP7 will be undefined if VBAT drops below the minimum value.
IE_FWCOL0
IE_FWCOL1 SFR E8[2]
SFR E8[3] 0
0 0
0 R/W
R/W Interrup t flags for Firmw are Col lisi on Int errup t. See the Flash Memory section for
details.
IE_PB SFR E8[4] 0 – R/W
PB flag. Indicate s that a rising edge o ccurred on PB. Firmware must write a zero to
this bit to clear it. The bit is also cleared when the MPU requests SLEEP or LCD
mode. On bootup, the MPU can read this bit to determine if t he part was woken with
the PB (DIO0[0]).
IE_PLLRISE SFR E8[6] 0 0 R/W Indicate s t hat the MPU was woken or interrupted (INT4) by system power becoming
available, or more precisely, by PLL_OK rising. The firmware must write a zero to this
bit to clear it.
IE_PLLFALL SFR E8[7] 0 0 R/W
Indicates that the MPU has entered BRO WNOUT mode because system power has
become unavailable (INT4), or more precisely, because PLL_OK fell. This bit will not
be set if the part wakes into BROWNO UT m ode because of P B or the WAKE timer.
The firmware must write a zero to this bit to clear it.
IEN_SPI 20B0[4] 0 – R/W SPI i nterrupt enable.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 81
Name
Location
Reset
Wake
Dir
Description
IEN_WD_NROVF 20B0[0] 0 0 R/W Active high watchdog near ov erflow interrupt enable.
IE_XFER
IE_RTC SFR E8[0]
SFR E8[1] 0
0 0
0 R/W Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC
interrupt. The f l ags are set by hardware and clear automatically.
IE_WAKE SFR E8[5] 0 – R/W Indicates that the MPU was awakened by the autowake time r. This bit is typica ll y read
by the MPU on bootup. The firmware m ust write a zero to this bit to clear it.
INTBITS SFR F 8[6:0] – – R/W Interrupt inputs. The MPU may read these bits to see the status of external interrupts
INT0, INT1 up to INT6. These bits do n ot have any memory an d are primarily intended
for debug use.
LCD_BITMAP
[31:24] 2023 0 L R/W Confi guratio n for DIO1 1/SEG3 1 through DI O4/SEG 24. Unuse d bits shoul d be set to zer o.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[39:32] 2024 0 L R/W Bitmap of DIO19/SEG39 throu gh DI O12/SEG32. Unused bit s should be s et to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[55:48] 2026 0 L R/W Bitmap of DI O 28/SEG48 through DIO35/SEG55. Unuse d bits shoul d be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[63:56] 2027 0 L R/W Bitmap of DIO36/SE G56 through DIO43/SEG63. Unu sed bits sho uld be set to zer o.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[71:64] 2028 0 L R/W Bitmap of DIO44/SEG64 through DI O51/SEG71. U nused bit s should be s et to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BLKMAP19
[3:0]
LCD_BLKMAP18
[3:0]
205A[7:4]
205A[3:0]
0 L R/W Identifies which segments connected to SEG18 and S EG19 should blink. 1 means
blink. The most significant bit corr esponds to COM3, t he least significant bit t o COM 0.
LCD_CLK[1:0] 2021[1:0] 0 L R/W
Sets the LCD clock frequency for COM/SEG pins (not
00 = fw/29
frame rate) accord ing to the
following (fw = 32768 Hz):
01 = fw/28
10 = fw/27
11 = f
w
/26
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
82 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
Name
Location
Reset
Wake
Dir
Description
LCD_DAC[2:0] 20AB[3:1] 0 L R/W
LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS
(mission mode) or VBAT (brownout/LCD modes).
LCD_DAC[2:0] Resulting LCD Voltage
000 V3P3 or VBAT
001 V3P3 or VBAT – 0.2V
010 V3P3 or VBAT – 0.4V
011 V3P3 or VBAT – 0.6V
100 V3P3 or VBAT – 0.8V
101 V3P3 or VBAT – 1.0V
110 V3P3 or VBAT – 1.2V
111 V3P3 or VBAT – 1.4V
LCD_E 2021[5] 0 L R/W Enables the LCD display. When disabl ed, VLC2, VLC1 and V LC0 are ground as are
the COM and SEG outputs.
LCD_MODE[2:0] 2021[4:2] 0 L R/W
The LCD bias mode. Use the LCD DAC in ANACTRL to reduce saturation. The number
of states is the number of commons whi ch are driven to mult i pl ex the LCD.
LCD_MODE[2:0] Function Notes
000 4 states, ⅓ bias ⅓ bias modes can drive 3.3 V LCDs.
001 3 states, ⅓ bias
010 2 states, ½ bias ½ bias and static modes c an drive
both 3.3 V and 5 V LCDs.
011 3 states, ½ bias
100 static display
LCD_ONLY 20A9[5] 0 0 W
Puts the part to sleep, but wit h the LCD display stil l act i ve. LCD_ONLY is ignored if
system power is pres ent. While in SLEEP mode, the device will wake up on reset,
when the autowa ke timer times out, when the push butt on i s pushed, or when syst em
power returns.
LCD_SEG0[3:0]
…
LCD_SEG19[3:0]
2030[3:0]
…
2043[3:0]
0
…
0
L
…
L
R/W
…
R/W
LCD Segment Data. Each word contains information for 1 to 4 time divisions of each
segment. Some addresses are used to address two segm ents.
In each word, bit 0 corr esponds to COM 0, bit 1 to COM1, bit 2 t o COM 2 and bit 3 to
COM3 of the fi rst segment. Bits 4 through 7 correspond to COM0 to COM3, respec-
tively, of the second segment.
Care should be take n when writing to LCD_SEG locations since some of them control
DIO pins.
LCD_SEG24[3:0]
…
LCD_SEG31[3:0]
2048[3:0]
…
204F[3:0]
0
…
0
L
…
L
R/W
…
R/W
LCD_SEG32[3:0] 2050[3:0] 0 L R/W
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 83
Name
Location
Reset
Wake
Dir
Description
LCD_SEG33[3:0]
…
LCD_SEG35[3:0]
2051[3:0]
…
2053[3:0]
0
…
0
L
…
L
R/W
…
R/W
LCD_SEG37[3:0] 2055[3:0] 0 L R/W
LCD_SEG39[3:0]
…
LCD_SEG41[3:0]
2057[3:0]
…
2059[3:0]
0
…
0
L
…
L
R/W
…
R/W
LCD_SEG48[7:4]
…
LCD_SEG49[7:4]
2036[7:4]
…
2037[7:4]
0
…
0
L
…
L
R/W
…
R/W
LCD_SEG63[7:4]
…
LCD_SEG66[7:4]
2045[7:4]
…
2048[7:4]
0
…
0
L
…
L
R/W
…
R/W
LCD_SEG71[7:4]
…
LCD_SEG73[7:4]
204D[7:4]
…
204F[7:4]
0
…
0
L
…
L
R/W
…
R/W
LCD_Y 2021[6] 0 L R/W LCD Blink Frequency (i gnored if blink is disabled or if the segment is off).
0 = 1 Hz (500 ms ON, 500 ms OFF)
1 = 0.5 Hz (1 s ON, 1 s OFF)
M26MHZ
M40MHZ 2005[4]
2005[0] 0
0 0
0 R/W
R/W
M26MHZ and M40MHZ set the master clock (MCK ) frequency. These bit s are reset on
chip reset and may only be set. Attempts to write zeroes t o M40MHZ and M26MHZ.are
ignored.
MPU_DIV[2:0] 2004[2:0] 0 0 R/W
The MPU clock divider (from MCK). These bits may be pro grammed by MPU w i thout
risk of losing control .
MPU_DIV[2:0]
Resulting Clock Frequency
000
MCK/22
001 MCK/2
3
010 MCK/2
4
011
MCK/25
100
MCK/26
101 MCK/2
7
110 MCK/2
8
111
MCK/28
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
84 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
Name
Location
Reset
Wake
Dir
Description
MUX_ALT 2005[2] 0 0 R/W
The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of i nputs.
If CHOP_E[1:0] is 00, MUX_ALT is automat icall y asserted once per sumcycle, w hen
XFER_BUSY falls.
MUX_DIV[3:0] 209D[3:0] 0 0 R/W The number of states in t he input multip l exer.
MUX_SYNC_E 2020[7] 0 0 R/W When set, SEG7 output s MUX_SYNC. Ot herwise, SEG7 is an L CD pin.
OPT_FDC[1:0] 2007[1:0] 0 0 R/W
Selects the modulation duty cycle for OPT_TX.
OPT_FDC[1:0] Function
00 50% Low
01 25% Low
10 12.5% Low
11 6.25% Low
OPT_RXDIS 2008[5] 0 0 R/W Configures OPT_RX to an analog input to the optical UART comparat or or as a digital
input/output, DIO1: 0 = OPT_RX, 1 = DIO1.
OPT_RXINV 2008[4] 0 0 R/W Inverts the result from the OPT_RX co m parator when 1. Affects only the UART input.
Has no effect when OP T_RX is used as a DI O input.
OPT_TXE[1:0] 2007[7:6] 00 00 R/W
Configures the OPT_TX output pin.
OPT_TXE[1:0] Function
00 OPT_TX
01 DIO2
10 WPULSE
11 RPULSE
OPT_TXINV 2008[0] 0 0 R/W Inverts OPT_TX when 1. This inversion occurs before modulation.
OPT_TXMOD 2008[1] 0 0 R/W Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is m odul ated
when it would otherwise have been zero. The modulation is applied after any inversion
caused by OPT_TXINV.
PLL_OK 2003[6] 0 0 R Indicates that system power is pr esent and the clock generation PLL is settled.
PLS_MAXWIDTH
[7:0] 2080[7:0] FF FF R/W
Determines the maximum width of the pulse (low going pulse).
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL
.
If PLS_INTERVAL = 0, TI is the sample time (397 µs). If set to 255, pulse width control
is disabled and puls es are output with a 50% duty cycle.
PLS_INTERVAL
[7:0] 2081[7:0] 0 0 R/W For PULSE_W and PULS E_V only: If the FIFO i s used, PLS_INTERVAL must be set to
81. If PLS_INTERVAL = 0, the FIFO is not used and pu l ses are output as soon as the
CE issues them.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 85
Name
Location
Reset
Wake
Dir
Description
PLS_INV 2004[6] 0 0 R/W Inverts the polarity of the pulse outputs. Normally, t hese pulses are active low. When
inverted, they become active high.
PREBOOT
SFRB2[7]
–
–
R Indicate s that the preboot sequence is activ e.
PREG[16:0] 201C[2:0]
201D[7:0]
201E[7:2]
4
0
0
4
0
0
R/W
R/W
R/W
RTC adjust. See Section 1.5.3 Real-Time Clock (RT C) for additional details.
0x0FFBF ≤ PREG[16:0] ≤ 0x10040
PREG[16:0] and QREG[1:0] are separate i n hardware but can be programmed wit h a
single number calculated by the MPU.
PRE_SAMPS[1:0] 2001[7:6] 0 0 R/W
The duration of the pre-summer, in samples.
PRE_SAMPS[1:0] Pre-summer Duration
00 42
01 50
10 84
11 100
QREG[1:0] 201E[1:0] 0 0 R/W RTC adjust. See Section 1.5.3 Real-Time Clo ck (RT C) for additional details.
RST_SUBSEC 2010[0] 0 0 R/W The sub-second counter is restarted when a 1 is writt en to this bit.
RTCA_ADJ[6:0] 2011[6:0] 40 – R/W Analog RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
RTC_SEC[5:0
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2015
2016
2017
2018
2019
201A
201B
*
*
*
*
*
*
*
NV
NV
NV
NV
NV
NV
NV
R/W
These are the year, m onth, day, hour, m i nute and second parameters of the RT C.
Writing to these re gi st ers sets the time. Each write operation to one of these regist ers
must be preceded by a write to 0x201F (WE). Vali d values for each para m eter are:
SEC: 00 to 59, MIN: 00 to 59, HR: 00 to 23 (00 = Midnight)
DAY: 01 to 07 (01 = Sunday), DATE: 01 to 31, MO: 01 to 12
YR: 00 to 99 (00 and all other s di visible by 4 are leap years)
Values in the RTC registers are undefined wh en the IC powers up wit hout a battery but
are maintained through mission and battery modes when a sufficient voltage is maintained
at the VBAT pin.
* no change of val ue at reset.
RTM_E 2002[3] 0 0 R/W Real Time Monit or (RTM) enable. When 0, the RTM output is low.
RTM0[9:0]
RTM1[9:0]
RTM2[9:0]
RTM3[9:0]
2060[9:8]
2061[7:0]
2062[9:8]
2063[7:0]
2064[9:8]
2064[7:0]
2065[9:8]
2066[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W The four RTM probes. B efore each CE code pa ss, the values of these registers are
serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
86 © 2005-2010 TERIDIAN Semiconductor Corpo ration v1.3
Name
Location
Reset
Wake
Dir
Description
SECURE SFRB2[6] 0 – R/W
When set, enables security provisions that prevent external reading of the flash memory
(zeros will be retur ned if the flash is read). SECURE should be set during the preboot
phase, i.e. while PREBOOT is set. SECURE is cleared when the flash is mass-erased
and when the chip is reset. The bit may only be set, attempts to write zero are ignored.
SEL_IAN 20AC[1] 0 0 R/W When set to 1, selects differential mode for the current input (IAP, IA N). When 0, the
input remains singl e-ended (71M6532D/F only).
SEL_IBN 20AC[5] 0 0 R/W When set to 1, selects differential mode for the current input (IBP, IBN). When 0, the
input remains singl e-ended (71M6532D/F only).
SLEEP 20A9[6] 0 0 W Puts the 71M6531 into SLEEP mode. This bit is ignored if syste m power is present.
The 71M6531 will wake when the auto wake timer times out, when the push button is
pushed, when syst em power returns, or when RESET goes high.
SLOT0_SEL[3:0]
SLOT1_SEL[3:0]
SLOT2_SEL[3:0]
SLOT3_SEL[3:0]
2090[3:0]
2090[7:4]
2091[3:0]
2091[7:4]
0
1
2
3
0
1
2
3
R/W
Primary multipl exer frame analog input selection. These bits map the select ed input,
0-3 to the multipl exer state. The ADC output is always writ ten to the memory l ocation
corresponding to the input, regardless of which multiplexer state an input is mapped to
(see Section 1.2 Analog Front E nd (A FE)).
SLOT0_ALTSEL
[3:0]
SLOT1_ALTSEL
[3:0]
SLOT2_ALTSEL
[3:0]
SLOT3_ALTSEL
[3:0]
2096[3:0]
2096[7:4]
2097[3:0]
2097[7:4]
A
1
2
3
A
1
B
3
R/W
Alternate multiplexer frame analog input selection. Maps the selected input to the
multiplexer state.
The additional inputs, 10 and 11 in the alternate frame are:
10 = TEMP
11 = VBAT
SP_ADDR[15:8]
SP_ADDR[7:0] 2072[7:0]
2073[7:0] 0
0 0
0 R
R SPI Address. 16-bit address from t he bus master.
SP_CMD 2071 0 0 R SPI command. 8-bit command from the bus master.
SPE 2070[7] 0 0 R/W SPI port enable. Enabl es the SPI interface on pins SEG3 through SEG5.
SPI_FLAG 20B1[4] 1 1 R/W SPI interrupt flag. The flag is set by the hardware and is cleared by the firmware writing
a 0. Firmware usin g this interrupt sho uld clear the spurious interrupt indication during
initialization.
SUBSEC[7:0] 2014[7:0] – – R The remaining count, in terms of 1/256 RTC cycles, to the next one second boundary.
SUBSEC may be read by the MPU after the one second interrupt and before reaching
the next one second boundary. Setting RST_SUBSEC will clear SUBSEC.
SUM_CYCLES
[5:0] 2001[5:0] 0 0 R/W The number of pre-summer outputs summed i n the final summing st age of the CE.
TMUX[4:0] 20AA[4:0] 2 – R/W Selects one of 32 signals for TMUXOUT. For detai ls, see Section 1.5.17 Test Ports
(TMUXOUT pin).
TRIM[7:0] 20FF 0 0 R/W Contains fuse information, depe ndi ng on the value wri tten to TRIMSEL[3:0].
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 87
Name
Location
Reset
Wake
Dir
Description
TRIMSEL[3:0] 20FD[3:0] 0 0 R/W Selects the trim fuse to be read with the TRIM register:
TRIMSEL[3:0]
Trim Fuse
Purpose
1 TRIMT[7:0] Trim for the magnitude of VREF
VERSION[7:0] 2006
20C8
–
–
–
– R
R The device version index. This word may be read by the firmware to determine t he
silicon version.
VERSION[7:0]
Silicon Version
0001 0101 A05
VREF_CAL 2004[7] 0 0 R/W Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.
VREF_DIS 2004[3] 0 0 R/W Disables the i nternal voltage refer ence.
WAKE_ARM 20A9[7] 0 – W A rm the autowake timer. Writing a 1 to this bit arms the autowake timer and presets it
with t he val ues pr ese ntl y i n WAKE_PRD and WAKE_RES. The autowake timer is reset and
disarmed whenever the IC is in MISSION or BROWNOUT mode. The timer must be
armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded.
WAKE_PRD 20A9[2:0] 001 – R/W Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. Default = 001. Maxi m um value is 7.
WAKE_RES 20A9[3] 0 – R/W Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.
WD_NROVF_
FLAG 20B1[0] – 0 R/W This flag is set approximately 1 ms before the watc hdog timer overf lows. It is cleared
by writing a 0 or on the falling edge of WA K E.
WD_RST SFR F8[7] 0 0 W WD timer bit. This bit must
WD_OVF
be accessed with byte operations. Operat i ons possible for
this bit are: Write 0xFF: Re sets the WDT.
2002[2] 0 0 R/W The WD overflow status bit. T hi s bit is set when the WD tim er overflows. It is powered
by the nonvolat i l e supply and at bootup wil l i ndicate if the part is recovering from a WD
overflow or a power fault. This bit s hould be cleared by the MPU on bootup. It is also
automatically cleared when RESET is high.
WE 201F[7:0] – – W An 8-bit value has to be written to this address prior to accessing the RTC registers.
WRPROT_BT SFR B2[5] 0 0 When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from fl ash page
erase.
WRPROT_CE SFR B2[4] 0 0 When set, this bit protects flash addresses from CE_LCTN*1024 to t he end of memory
from flash page erase.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
88 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
4.3 CE Interface Descrip t ion
4.3.1 CE Program
The CE performs the precision comp utations necessary to accurately m easure energy. Different code
variations are used for EQU[2:0] = 0 and EQU[2:0] = 1 or 2. The computations include offset cancellation,
products, product smoothing, product summation, frequency detecti on, VAR calculation, sag detection,
peak detection and voltage phase measurement. All data computed by the CE is dependent on the
selected meter equation as given by EQU[2:0]. Although EQU[2:0] = 0 and EQU[2:0] = 2 have the same
element mappi ng, the MPU code can use the value of EQU[2:0] to decide if element 2 is used f or tamper
detection (typically done by connectin g V B to VA) or as a second independent element .
The CE program i s supplied by Teridian as a data image that can b e m erged with the MPU operational
code for meter applications. Typically, the CE program covers most applications and does not need to be
modified. Other variations of CE code may be available from TERIDIAN. The description in t hi s section
applies to CE code r evision CE31A04 (for EQU[2:0] = 0). Deviati ons for code rev ision CE31 A03 (for
EQU[2:0] = 1 or 2) are noted where appli cable.
4.3.2 CE Data Format
All CE words are 4 bytes. Unless specif i ed otherwise, t hey are in 32-bit two’s compl em ent format
(-1 = 0xFFFFFFFF). Calibration parameters are defined in flash memory (or external EEP ROM) and
must be copied to CE data memory by t he M PU before enabling the CE. Internal variables are used in
internal CE calculation s. Input variables allow the MPU to control t he behavior of the CE code. Output
variables are out puts of the CE calculations. The corresp onding MPU addre ss for the most si gnificant
byte is given by 0x0000 + 4 x CE_address and by 0x 0003 + 4 x CE_address fo r the least significant byte.
4.3.3 Constants
Constants used in the CE Data Memory tables are:
• FS = 32768 Hz/13 = 2520.62 Hz.
• F0 is the fundamental frequency.
• IMAX is the external rms current corresponding to 250 mV pk at the inputs IA and I B.
• VMAX is the external rms voltage corre sponding to 250 mV pk at the VA and VB inputs.
• NACC, the accumulation count for energy m easurements is PRE_SAMPS[1:0]*SUM_CYCLES[5:0].
• The duration of the accumulation interval for energy meas urements is
PRE_SAMPS[1:0]*SUM_CYCLES[5:0]/FS
• ln_8 is a gain constant of the current channel, n. Its val ue i s 8 or 1 and is controll ed by In_SHUNT.
• X is a ga in con stant of the puls e gene rator s. Its v alue is det ermin ed by PULSE_FAST and PULSE_SLOW.
• V oltage LSB f or sag dete ction = VMAX * 7.8798*1 0-6 V.
The system constants IMAX and VMAX are used by the MPU to convert internal quantities (as used by
the CE) to external, i .e. metering quantities. Their values are det ermined by the off-chip scaling of the
voltage and curr ent sensors used in an actual meter. The LSB values use d i n this document rel ate digital
quantities at the CE or M PU interface to external meter input quantiti es. For example, if a SAG threshold
of 80 V peak is desire d at the meter inpu t, the digital value that should be programmed into SAG_THR
would be 80/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR.
The parameters EQU[2:0], CE_E, PRE_SAMPS[1:0] and SUM_CYCLES[5:0] essential t o the function of the
CE are stored in I/O RAM (see Section 4.2 I/O RAM Description – Alphabetical Order).
4.3.4 Environment
Before startin g the CE using the CE_E bit , the MPU has to establi sh the proper environment for the CE by
implementing the following steps (for CE 31A04 code ):
• Load the CE data into RAM.
• Establish the equation to be applied in EQU[2:0]. The CE code ha s t o m atch the selected e quation.
• Establish the accumulation period and number of samples in PRE_SAMPS[1:0] = 0 (multiplier = 42) and
SUM_CYCLES[5:0] = 0x3C (60).
• Set PLS_INTERVAL[7:0] to 81.
• Select the values for FIR_LEN[1:0] = 2 and MUX_DIV[3:0] = 4.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 89
• Select the values for SLOT0_SEL[3:0] = 0, SLOT1_SEL[3:0] = 1, SLOT2_SEL[3:0] = 2, SLOT3_SEL[3:0]
= 3
• Select the values for SLOT0_ALTSEL[3:0] = 0x0A, SLOT1_ALTSEL[3:0] = 1, SLOT2_ALTSEL[3:0] =
0x0B, SLOT3_ALTSEL[3:0] = 3.
• Set CHOP_E[1:0] = 00.
• Initialize any M P U i nterrupts, such as CE_BUSY, XFER_B US Y , or a power failure detection int errupt.
When different CE codes are used, a different set of environment param eters needs to be es tablished.
The exact values for these parameters are stated in the Application Notes and other documentation
accompanying the CE codes.
CE codes should only
be used with environment parameters specified in this document or in the
applicable CE code description. Changing environment parameters at random will lead to unpre-
dictable results.
Typically, there are thirteen 3276 8 Hz cycles per ADC mul tiplexer frame ( see Figure 19). This means that
the product of the number of cycles per frame and the number of conversions per frame must be 12 (allowing
for one settling cycle).
During operation, CHOP_E[1:0] = 00 enables the automatic chopp ing m ode an d forces an a lterna te
multiplexer sequence at regular inte rv als. This enables accurate temperat ure measurement .
4.3.5 CE Calculations
Table 56: CE EQU[2:0] Equations and Element Input Mapping
EQU[2:0] Watt & VAR Fo r mula
(WSUM/VARSUM)
Element Input Mapping
W0SUM/
VAR0SUM W1SUM/
VAR1SUM I0SQSUM I1SQSUM
0 VA IA (1 element, 2W 1φ)
with tamper detection VA*IA VA*IB IA IB
1 VA*(IA-IB)/2
(1 element, 3W 1φ) VA*(IA-IB)/2 (VA * IB)/2 IA-IB IB
2 VA*IA + VB*IB
(2 element, 4W 2φ) VA*IA VB*IB IA IB
4.3.6 CE Status and Control
The CESTATUS register provides information about t he st atus of voltage and input AC signal frequency,
which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It contains
sag warning flags for VA and VB as we ll as F0, the der i ved clock operat ing a t the fundamen tal inp ut
frequency. CESTATUS represents the status f l ags for the preceding CE code pass (CE busy i nterrupt).
Sag alarms are not remembered from one code pass t o the next. The CE Status word is refreshed at
every CE_BUSY i nterrupt. The significa nce of the bits in CESTATUS is shown in Table 57.
CE Address Name Description
0x80
CESTATUS
See description of
CESTATUS
bits in Table 57.
Since the CE_BUSY interrupt typically occ urs at 2520.6 Hz, it i s desirable to mini m i ze t he computation
required in the interrupt handler of t he MPU. Rather t han reading the CE stat us word at every CE_BUSY
interrupt and interpret the sag bits, it is recommended that the MPU activate the YPULSE output to generate
interrupts when a sag occurs (see the description of the CECONFIG register)
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
90 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Table 57: CESTATUS (CE RAM 0x80 ) Bit Definitions
CESTATUS [bit] Name Description
31:29
Not Used
These unused bits will always be zero.
28 F0 F0 is a square wave at the exact fundam ental frequency for t he
phase selected with the FREQSELn bits in CECONFIG.
27 Reserved
26 SAG_B Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VB rises above
SAG_THR.
25 SAG_A Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VA rises above
SAG_THR.
24:0 Not Used These unused bits will always be zero.
The CE is initialized and its functions are cont rolled by the MP U using CECONFIG. This register contains
in packed form SAG_CNT, FREQSEL, E XT _PULSE, I0_SHUNT, I1_SHUNT, PULSE_SLOW and PULSE_FAST.
The CECONFIG bit definitions ar e gi ven in Table 58.
CE Address
Name
Data
Description
0x20 CECONFIG 0x5020 See des cription of the CECONFIG bits in Table 58.
IA_SHUNT and/or IB_SHUNT can configure their respective current inputs to accept shunt resistor sensors.
In this case the CE pr ovides an additional gain of 8 to the selected current input. WRATE may need to be
adjusted based on the values of IA_SHUNT and IB_SHUNT. When ever IA_SHUNT or IB_SHUNT are set to
1, In_8 (in the equation for Kh) i s assigned a value of 8.
The CE pulse generat or can be controlle d by either the MPU (external) or CE (internal) variables. Cont rol
is by the MPU if EXT_PULSE = 1. In this case, the MP U controls the pulse rate by placing values into
APULSEW, APULSER, APULSE2 and APULSE3. By setting EXT_PULSE = 0, the CE controls the pulse rate
based on W0SUM_X and VAR0SUM_X (EQU[2:0] = 0) or WSUM_X (EQU[2:0] = 2).
If EXT_PULSE = 0 and EQU[2:0] = 2, the pulse inputs are W0SUM_X + W1SUM_X and VAR0SUM_X +
VAR1SUM_X. In this case, creep cannot be controlled since creep is an MPU functi on.
If EXT_PULSE = 0 and EQU[2:0] = 0, the pulse inputs are W0SUM_X if I0SQSUM_X > I1SQSUM_X and
W1SUM_X, if I1SQSUM_X > I0SQSUM_X.
The 71M6531 Demo Code creep function hal ts both internal and external pulse generation.
The EXT_TEMP bit controls the tempe rature compensat ion m ode:
• When EXT_TEMP = 0 (inter nal compe nsation ), the CE will control th e gain usin g GAIN_ADJ (see Table 60)
based on PPMC, PPMC2 and TEMP_X, the difference between die tem perature and the ref erence /
calibration temper atur e TEMP_NOM. Since PPMC and PPMC2 reflect the typical behavior of the
reference voltage over temperature, the internal tem perature compensat i on el im inates the effe ct s of
temperature-rel ated errors of VREF onl y.
• When EXT_TEMP = 1 (external compensat i on), the MPU is allo wed to control the CE gai n using
GAIN_ADJ, based on any algorithm implemented in MPU code.
The FREQSEL1 and FREQSEL0 bits sele ct the phase used to control the CE-internal PLL. CE acc uracy
depends on the channel selected by the FREQSEL1 and FREQSEL0 bits receiv ing a clean voltage sig nal.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 91
Table 58: CECONFIG Bit Defini ti ons
CECONFG
[bit] Name Default Description
[19]
[18] SAG_MASK1
SAG_MASK0 0
0 Sets the sag cont rol of phase B.
Sets the sag control of phase A.
If more than one sag mask is set, a sag int errupt will only be
generated when all phases enabled for the interrupt sag.
[17] SAG_INT 0 Whe n set , enables the sag interrupt to be output on the
YPULSE/DIO9 pin.
[16] EXT_TEMP 0 When set, enables the control of GAIN_ADJ by the MPU.
When 0, enables the control of GAIN_ADJ by the CE.
[15:8] SAG_CNT 80
(0x50)
The number of con secutive voltage sam ples below SAG_THR
before a sag alarm is declared. The m aximum value is 255.
SAG_THR is at address 0x24.
[7] FREQSEL1 0 The combination of FREQSEL1 and FREQSEL0 selects the phase
to be used for the frequenc y monitor, the phase-to-phase lag
calculation, the zero-crossing counter MAINEDGE_X and t he
F0 bit (CESTATUS[28]).
FREQSEL1/FREQSEL0 = 0/0: Phase A
FREQSEL1/FREQSEL0 = 0/1: Phase B
[6] FREQSEL0 0
[5] EXT_PULSE 1
When zero, causes t he pulse generators to respond to i nternal
data (PULSE0 = WSUM_X, PULSE1 = VARSUM_X., PULSE2 =
VASUM_X). Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER.
[4] – 0 Unused.
[3] IB_SHUNT 0 When 1, the current gain of channel B is increased by 8. The
gain factor controll ed by In_SHUNT is referred to as In_8
throughout thi s document.
[2] IA_SHUNT 0 When 1, the current gain of channel A is increased by 8.
[1] PULSE_FAST 0
When PULSE_FAST = 1, the pulse gener ator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input i s
reduced by a factor of 64. These two bits control the pulse
gain factor X (see table below). Default is 0 for both (X = 6).
PULSE_SLOW PULSE_FAST X
0 0 1.5 * 2
2
= 6
0 1 1.5 * 2
6
= 96
1 0 1.5 * 2
-4
= 0.09375
1 1 Do not use
[0] PULSE_SLOW 0
Table 59: Sag Threshold Control
CE
Address Name Default Description
0x24 SAG_THR 443000 The threshold for sag war nings. The default value is
equivalent to 80 V RMS if VMAX = 600 V. The LSB value
is VMAX * 4.255*10-7 V (peak).
Table 60: Gain Adjust Co ntrol
CE
Address Name Default Description
0x40 GAIN_ADJ 16384 Thi s register scales al l voltage and current channels. The
default value is equi valent unity gai n (1.000).
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
92 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
4.3.7 CE Transfer Variables
When the MPU receives the XFER_BUSY i nterrupt, it knows that fresh data is av ai l able i n the transfer
variables. CE transfer variables are modified during the CE code pass that ends with an X FER_BUSY
interrupt. They remai n constant throughout each accumulation interval . In this data sheet, the names of
CE transfer vari ables always end with _X.
The transfer variabl es can be categorized as:
1. Fundamental energy measurem ent variables
2. Instantaneou s (RMS) values
3. Other measur em ent parameters
Fundamental Energy Measureme nt Variables
Table 61 describes each transfer variable for f undamental energy meas urement. All variabl es are signed
32-bit integers. A ccumulated variables such as WSUM are i nternally scaled so they have at least 2x
margin before overflow when the integration time is one second. Additionally, the hardware will not permit
output values to fold back upon overf low.
Table 61: CE Transfer Variables
CE
Address
Name Description
0x85 WSUM_X
For EQU[2:0] = 2, this register holds the calculated sum of Wh samples
from each wat tmeter element (In_8 is the gain of 1 or 8 configured by
IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 Wh.
0x86
W0SUM_X
The sum of Wh samples from each wattmeter element (In_8 is the gain
of 1 or 8 configured by IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 Wh.
0x87 W1SUM_X
0x8A VARSUM_X
For EQU[2:0] = 2, this register hol ds the calc ulated sum of VA Rh
samples from each el em ent (In_8 is the gain of 1 or 8 config ured by
IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 VARh.
0x8B
VAR0SUM_X
The sum of VARh samples from each elem ent (In_8 is the gain 1 or 8
configured by IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 VARh.
0x8C VAR1SUM_X
WxSUM_X is the Wh value accumulated for element X in the last accumulation interval and can be computed
based on the specif i ed LSB value.
For example, with VMAX = 600 V and IMAX = 208 A, the LSB for WxSUM_X is 0.08356 µWh.
Instantaneous Measurement V ariables
Table 62 contains various measurem ent results. The F requency measurement is computed for the phase
selected with FREQSELn bits in the CECONFIG register.
IxSQSUM_X and VxSQSUM are the squa red curre nt and volta ge sampl es acquired during the last accumulation
interval. They can be used to calculate RMS voltages and currents. INSQSUM_X can be used for computing
the neutral current.
Table 62: CE Energy Measurement Variables
CE
Address Name Description
0x82 FREQ_X
Fundamental freque ncy.
LSB
6
32
10587.0
2
−
⋅≈≡
S
F
Hz
0x8F I0SQSUM_X The sum of squared current samples from each element.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 93
0x90 I1SQSUM_X
LSB
I
= 6.6952*10-13 IMAX2 / In_82 A2h
0x93 V0SQSUM_X The sum of squared voltag e samples from each element.
LSBV= 6.6952*10-13 VMAX2 V2h
0x94 V1SQSUM_X
0x45 WSUM_ACCUM These registers contain roll-over accumulators for WPULSE and
VPULSE respectively.
0x46 VSUM_ACCUM
0x47 SUM3_ACCUM These re giste rs contain roll-ov er accumulators fo r pulse outputs
XPULSE and YPULSE respectively.
0x48 SUM4_ACCUM
0x99 I0SQRES_X These registers hold residual current measurements with double-
precision accuracy . The exact current ISQn is:
ISQn = InSQSUM_X + 232 * InSQRES_X
0x9A I1SQRES_X
The RMS values can be computed by the MP U from the squared current and voltage s am ples as follows:
ACC
SI
RMS NFLSBIxSQSUM
Ix ⋅⋅⋅
=3600
Other Measur ement Parameters
Table 63 describes the CE measurem ent parameters l ist ed below:
• MAINEDGE_X: Useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X
is the number of hal f-cy cles accounted for i n the last accumulated interval for the AC signal.
• TEMP_RAW: May be used by the MPU to monitor the chip temperature or to implement temperature
compensation.
• GAIN_ADJ: A scaling factor for measurements based on the temperature. GAIN_ADJ can be controlled
by the MPU for tem perature compensation.
• VBAT_SUM_X: This result can be used to calculate the measu red battery vol tage (VBAT).
Table 63: Useful CE M easurement Par ameters
CE
Address
Name Default Description
0x83 MAINEDGE_X N/A The number of zero crossings of t he voltage selected with
FREQSELn in the previous accumulation interval. Zero crossings
are either direction a nd are debounced.
0x81 TEMP_RAW_X N/A The filtered, un-scaled reading from the temperature sensor.
0x9D TEMP_X N/A
This regi ster contai ns the difference between the d ie tem peratu re
and the reference/calibration temperature as established in the
TEMP_NOM register, measured in 0.1°C.
0x40 GAIN_ADJ 16384
Scales a ll volt age an d curr ent i nputs. A v alue of 163 84 provide s
unity gain. This register is used by the CE or by the MPU t o
implement temperature compensation.
0x84 VBAT_SUM_X N/A Output of the batt ery measurement. This value is equi valent to
twice the measured ADC value.
4.3.8 Pulse Generation
Table 64 describes the CE pulse generation parameters WRATE, APULSEW, APULSER, APULSE2 and
APULSE3.
WRATE controls the number of pulses that are generated per measured Wh and VARh quantities. The lower
WRATE is the slower the pulse rate for measured energy quantity. The metering constant Kh is derived from
WRATE as the amount of energy measured for each pulse. That is, if Kh = 1 Wh/pulse, a power applied
to the meter of 120 V and 30 A (3,600 W) results in one pulse per second. If the load is 240 V at 150 A
(36,000 W), ten pulses per second will be generated.
The maximum pulse rate is 7.5 kHz for APULSEW and APULSER and 1.2 kHz for APULSE2 and APULSE3.
ACC
SV
RMS
NFLSBVxSQSUM
Vx ⋅⋅⋅
=3600
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
94 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
The maximu m time jitt er is 67 µs and i s independ ent of the n umber of pul ses meas ured. Thus, if the pulse
generat or is m onitor ed fo r one secon d, th e pea k jitte r is 67 ppm. Af ter 10 se conds, t he p eak jitt er i s 6.7 p pm.
The average jitter is always zero. If it is attempted to drive either pulse g enerator faster than its maximum
rate, it will simply output at its maxim um rate without ex hi biting any rollover characteristics. The act ual
pulse rate, using WSUM as an exampl e, is:
Hz
XFWSUMWRATE
RATE
S
46
2
⋅⋅⋅
=
,
where FS = sampling fr equency (2520.6 Hz ) and X = Pulse speed f act or (as defined in t he CECONFIG
register with the PULSE_FAST and PULSE_SLOW bits).
Table 64: CE Pulse Generation Parameters
CE
Address Name Default Description
0x21 WRATE 827
Kh = VMAX*IMAX*47.1132 / (In_8*WRATE*NACC*X) Wh/pulse. The
default value res ul ts in a Kh of 1.0 Wh/pulse when 2520 samples
are taken in each ac cumulation interval (and VMAX=600,
IMAX = 442 [for 400µΩ shunt], In_8 = 1, X = 6).
Maximum value = 215 -1.
0x41 APULSEW 0 Watt pulse generato r i nput (see DIO_PW bit). The output pulse
rate is: APULSEW * FS * 2-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computatio n i nterval. The change will
take effect at the begi nning of the next interval.
0x42 APULSER 0 VAR pulse generator inp ut (see DIO_PV bit). The output pulse rate
is: APULSER * FS*2-32 * WRATE * X * 2-14. This input is buffered and
can be loaded during a computation interval. The change will take
effect at the beginning of the next i nterval.
0x43 APULSE2 0 Third pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE2 * FS*2-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computatio n i nterval. The change will
take effect at the begi nning of the next interval.
0x44 APULSE3 0 Fourth pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE3 * FS*2-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computatio n i nterval. The change wil l
take effect at the begi nning of the next interval.
0x38 PULSE
WIDTH 12 Register for pulse width control of XPULSE and YPULSE. The max-
imum pulse width is (2*PULSEWIDTH+1)*(1/FS). The default value
will generate pulses of 10 ms width at FS = 2520.62 Hz.
4.3.9 CE Calibration Parameters
Table 65 lists the parameters that a re typically entered to effect calibration of meter accuracy.
Table 65: CE Cal i bration Paramet ers
CE
Address Name Default Description
0x10 CAL_IA 16384
These constants co ntrol the gain of t heir respective chann els. The
nominal value for each parameter is 214 = 16384. The gain of each
channel is directly proportional t o i ts gain constant. Thus, if the
gain of the IA channel i s 1% slow, CAL_IA should be scaled by
1/(1 – 0.01) and the resulting v al ue is 16549.
0x11 CAL_VA 16384
0x12 CAL_IB 16384
0x13 CAL_VB 16384
0x18 PHADJ_A 0
These two cons tants con trol the CT phase c ompensa tion . No
compensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introdu ced. Range: ± 215 – 1. If it is
desired to delay the current by the angle Φ, the equations are:
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 95
CE
Address Name Default Description
0x19 PHADJ_B 0
Φ⋅−
Φ⋅
=TAN
TAN
XPHADJ 0131.01487.0 02229.0
2_
20
at 60Hz
Φ⋅−
Φ⋅
=TAN
TAN
XPHADJ 009695.01241.0 0155.0
2_ 20
at 50Hz
0x1F TEMP_NOM 0
This register contains the reference point for the temp erat ure
measurement. At calibration temperatu re, the value read at
TEMP_RAW_X shoul d be wri tte n to TEMP_NOM. The CE will calculate
the chip temperature TEMP_X relative t o the reference tem perature.
0x39 DEGSCALE 9174
The scale factor for the temperature calculation. It is not necessary
to use values other than the default value.
4.3.10 Other CE Parameters
Table 66 shows the CE parameters used for suppression of noise due to scaling and truncat ion effects.
The table also includes the parameter which indicates the CE Code version.
Table 66: CE Parameters for Noise Suppression and Code Version
CE Ad-
dress Name Default Description
0x22 KVAR 6448 This is the scale factor f or the VAR calculation. No value
other than the def ault value should be applied.
0x26 QUANT_A 0 These parameters are added to the Watt calculati on for
element 0 and 1 t o com pens ate fo r input no ise and trun cation.
LSB = (VMAX*IMAX / In_8) *7.4162*10-10 W
0x27 QUANT_B 0
0x2A QUANT_VARA 0 These paramet ers are added to the VAR calculation for
element A a nd B t o compe nsate f or in put no ise a nd tru ncatio n.
LSB = (VMAX*IMAX / In_8) * 7.4162*10-10 W
0x2B QUANT_VARB 0
0x2E QUANT_IA 0 These parameters are added to compensate for input noi se
and truncation in their respective channels in the squaring
calculations f or I 2 and V2.
LSB = VMAX2*7.4162*10-10 V2 and
LSB = (IMAX2/In_82)*7.4162*10-10 A2
0x2F QUANT_IB 0
0x35 0x63653331 Text strings hol ding the CE version information as supplied
by the CE data asso ciated with the CE code. For example,
the words 0x63653331 and 0x61303463 form the text st ring
“ce31a04c”.
These locations are overwritten i n operation.
0x36 0x61303463
0x37 0x00000000
4.3.11 CE Flow Diagrams
Figure 41 through Figure 43 show the data flow through the CE in simplified form. Functions not shown
include delay comp ensation, sample interpolation, s caling and processi ng of meter equation s.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
96 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Figure 41: CE Data Flow: Multiplexer and ADC
Figure 42: CE Data Flow: Scaling, Gain Control, Intermediate Variables
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 97
Figure 43: CE Data F low: Squaring and Summation Stages
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
98 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5 Electrical Specifications
5.1 Absolute Maximum Ratings
Table 67 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings
may cause permanent damage to the d evice. These are str ess ratings only and functional operation at
these or any other conditions beyond those indicated under recommended operating conditions (Section
5.3) is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability. Al l voltages are with respe ct to GNDA.
Table 67: Absolute Maxim u m Ratings
Voltage and Current
Supplies and Ground Pins
V3P3SYS, V3P3A −0.5 V to 4.6 V
VBAT -0.5 V to 4.6 V
GNDD -0.5 V to +0.5 V
Analog Output Pins
V3P3D -10 mA to 10 mA,
-0.5 V to 4.6 V
VREF -10 mA to +10 mA,
-0.5 V to V3P3A+0.5 V
V2P5 -10 mA to +10 mA,
-0.5 V to 3.0 V
Analog Input Pins
IA, VA, IB, VB, V1 -10 mA to +10 mA
-0.5 V to V3P3A+0.5 V
XIN, XOUT -10 mA to +10 mA
-0.5 V to 3.0 V
All Other Pins
Configured as SEG or COM drivers -1 mA to +1 mA,
-0.5 to V3P3D+0.5
Configured as Digital Inputs -10 mA to +10 mA,
-0.5 to 6 V
Configured as Digital Outputs -15 mA to +15 mA,
-0.5 V to V3P3D+0.5 V
All other pins −0.5 V to V3P3D+0.5 V
Temperature and ESD Stress
Operating junction temperature (peak, 100ms) 140 °C
Operating junction temperature (cont inuous) 125 °C
Storage temperature −45 °C to +165 °C
Solder temperat ure – 10 second duration 250 °C
ESD stress on all pi ns 4 kV
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 99
5.2 Recommended External Components
Table 68: Recommended External Components
Name
From
To Function Value Unit
C1 V3P3A AGND Bypass capacitor for 3.3 V supply ≥0.1 ±20% † µF
C2 V3P3D GNDD Bypass capacitor for 3.3 V output ≥0.1 ±20% † µF
CSYS V3P3SYS GNDD Bypass capacitor for V3P3SYS ≥1.0 ±30% µF
C2P5 V2P5 GNDD Bypass capacitor for V2P5 0.1 ±20% µF
XTAL XIN XOUT 32.768 kHz crystal – electrically similar to
ECS .327-12.5-17X or Vishay XT26T,
load capacitance 12.5 pF 32.768 kHz
CXS XIN AGND Load capacitor for crystal (depends on
crystal specs and board parasiti cs ). 33 ±10% pF
CXL XOUT AGND Load capacitor for cryst al (depends on
crystal specs and board parasiti cs ). 15 ±10% pF
Notes:
1. AGND and GNDD should be connected together.
2. V3P3SYS and V3P3A should be connected together.
† For accuracy and E M I rejection, C1 + C2 s hould be 470 µF or higher.
5.3 Recommended Operating Conditions
Table 69: Recommended Opera ti ng Conditions
Parameter
Condition
Min
Typ
Max
Unit
V3P3SYS, V3P3A: 3.3 V Supply Voltage
V3P3A and V3P3SYS m ust be at the
same voltage
Normal Operat ion 3.0 3.3 3.6 V
Battery Backup 0 3.6 V
VBAT
No Battery Externally Connect to V3P3SYS
Battery Backup:
BRN and LCD modes
SLEEP mode
3.0
2.0
3.8
3.8
V
V
Operating Temper ature -40 +85 ºC
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
100 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5.4 Performance Specifications
5.4.1 Input Logic Levels Table 70: Input Logic Levels
Parameter
Condition
Min
Typ
Max
Unit
Digital high-level input voltagea, VIH
2
V
Digital low-level input voltagea, VIL
0.8
V
Input pull-up current, IIL
E_RXTX,
E_RST, CKTEST
Other digital inputs
VIN=0 V, ICE_E=1
10
10
-1
0
100
100
1
µA
µA
µA
Input pull down current, IIH
ICE_E
RESET
PB
Other digital inputs
VIN = V3P3D
10
10
-1
-1
0
0
100
100
1
1
µA
µA
µA
µA
a In battery powered modes, digital inputs should be below 0.3 V or above 2.5 V to minimize battery current.
5.4.2 Output Logic Levels Table 71: Output Logic L evels
Parameter
Condition
Min
Typ
Max
Unit
Digital high-level output volt age V OH
ILOAD = 1 mA
V3P3D–0.4
V
ILOAD = 15 mA
V3P3D-0.6
V
Digital low-level output volt age V OL
ILOAD = 1 mA
0
0.4
V
ILOAD = 15 mA
0.8
V
OPT_TX V
OH
(V3P3D-OPT_TX)
I
SOURCE
=1 mA
0.4
V
OPT_TX V
OL
I
SINK
=20 mA
0.7
V
5.4.3 Power-Fault Comparator
Table 72: Power-Fault Comparator Performance Specifications
Parameter Condition Min Typ Max Unit
Offset Voltage: V1-VBIAS -20 +15 mV
Hysteresis Current: V1 Vin = VBIAS – 100 mV 0.8 1.2 μA
Response Time: V1 +100 mV overdrive
Voltage at V1 rising
Voltage at V1 fall i ng
10
8
37
100
100
µs
μs
WDT Disable Threshold: V1-V3P3A -400 -10 mV
5.4.4 Battery Monitor
Table 73: Battery Monitor Performance Speci fications (BME= 1)
Parameter Condition Min Typ Max Unit
Load Resistor
27
45
63
kΩ
LSB Value
[M40MHZ, M26MHZ]
= [00], [10], or [11]
FIR_LEN[1:0]=0 (L=138)
FIR_LEN[1:0]=1 (L=288)
FIR_LEN[1:0]=2 (L=384)
(-10%)
-48.7
-5.35
-2.26
(+10%)
μV
μV
μV
[M40MHZ, M26MHZ]
= [01]
FIR_LEN[1:0]=0 (L=186)
FIR_LEN[1:0]=1 (L=384)
FIR_LEN[1:0]=2 (L=588)
(-10%)
-19.8
-2.26
-0.63
(+10%)
μV
μV
μV
Offset Error -200 0 +100 mV
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 101
5.4.5 Supply Current
Table 74: Supply Current Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
V3P3SYS current (CE off) Normal Operation,
V3P3A = V3P3SYS = 3.3 V
CKMPU = 614 kHz
No Flash Memory write
RTM_E=0, ECK_DIS=1,
ADC_E=1, ICE_E=0
4.2 6.35 mA
V3P3SYS current (CE on) 8.4 9.6 mA
V3P3A current 3.3 3.8 mA
VBAT current -400 +400 nA
V3P3SYS current,
Write Flash
Normal Operation as a bove, exce pt
write Flash at m aximum rate,
CE_E = 0, ADC_ E = 0
9.1 12 mA
VBAT current
VBAT=3.6V
BROWNOUT mode
71M6531D/F
71M6532D/F
LCD Mode
LCD DAC off
LCD DAC on
SLEEP Mode
52
82
11
21
0.7
250
250
40
46
1.5
µA
µA
µA
µA
µA
5.4.6 V3P3D Switch
Table 75: V3P3D Switch Performance Sp ecifications
Parameter
Condition
Min
Typ
Max
Unit
On resistance – V3P3SYS to V3P3D | IV3P3D | ≤ 1 mA 9 15 Ω
On resistance – VBAT to V3P3D | IV3P3D | ≤ 1 mA 32 50 Ω
5.4.7 2.5 V Voltage Regulator
Table 76: 2.5 V Voltage Regulator Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
V2P5 Iload = 0 2.3 2.5 2.7 V
V2P5 load regulation Iload = 0 mA to 5 mA 40 mV
Voltage overhead V3P 3-V2P5 Iload = 5 mA, reduce V3P3
until V2P5 drops 2 00 mV 470 mV
PSSR ∆V2P5/∆V3P3 RESET=0, iload=0 -2 +2 mV/V
5.4.8 Low-Power Voltage Regulator
Unless otherwise specified, V3P3SYS = V3P3A = 0, PB =GND (BROWN O UT).
Table 77: Low-Power Voltage Regulator Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
V2P5 ILOAD = 0 2.3 2.5 2.7 V
V2P5 load regulation ILOAD = 0 mA to 1 mA 30 mV
VBAT voltage requirement ILOAD = 1 mA, reduce VBAT
until REG_LP_OK = 0 3.0 V
PSRR ΔV2P5/ΔVBAT ILOAD = 0 -50 50 mV/V
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
102 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5.4.9 Crystal Oscillator
Table 78: Crystal Oscillator Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
Maximum Output Power to Crystal
4
Crystal connected 1 μW
XIN to XOUT Capacitance
1
3 pF
Capacitance to GNDD
1
XIN
XOUT RTCA_ADJ[6:0] = 0
5
5
pF
pF
5.4.10 LCD DAC
Table 79: LCD DAC Performance Specifications
Parameter Condition Min Typ Max Unit
VLCD Voltage
V019.0LCD_DAC)059.01(3P3VVLCD −⋅−⋅=
1 ≤ LCD_DAC[2:0] ≤ 7 -10 +10 %
5.4.11 LCD Drivers
The information in Table 80 applies to all COM and SEG pins with LCD_DAC[2:0] = 000.
Table 80: LCD Driver Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
VLC2 Voltage With respect to VLCD
1
-0.1 +0.1 V
VLC1 Voltage
†
,
⅓ bias
½ bias
½ bias, minimum output level
With respect to 2*VLC2/3
With respect to VLC2/2
-3
-3
+2
+2
1.0
% VLC2
% VLC2
V
VLC0 Voltage,
⅓ bias
With respect to VLC2/3
-4
+1
%
VLC1 Impedance ∆ILOAD = 100 µA (Isink) 9 15 kΩ
∆ILOAD = -100 µA (Isource) 9 15
VLC0 Impedance ∆ILOAD = 100 µA (Isink) 9 15 kΩ
∆ILOAD = -100 µA (Isource) 9 15
1VLCD is V3P3SYS i n M ISSION mode and VBAT in B ROWNOUT and LCD modes.
† Specified as percentage of V LC2, the maximum LCD voltage.
5.4.12 Optical Interface
Table 81: Optical Interface Performance Specificat ions
Parameter Condition Min Typ Max Unit
OPT_TX VOH (V3P3D-OPT_TX) ISOURCE =1 mA 0.4 V
OPT_TX VOL ISINK = 20 mA 0.7 V
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 103
5.4.13 Temperature Sensor
Table 82 shows the performance f or t he temperat u re senso r. The LSB values do not include the 8-bit left
shift at CE input.
Table 82: Temperature Sensor Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
Nominal relationship: N(T) = Sn*(T-Tn) + Nn, Tn = 25ºC
Nominal Sensi-
tivity (Sn)4
3
3
00109.0
⋅−= L
Sn
[M40MHZ, M26MH] =
[00], [10], or [11]
FIR_LEN[1:0]=0
(L=138)
FIR_LEN[1:0]=1
(L=288)
FIR_LEN[1:0]=2
(L=384)
-106
-964
-2286
LSB/ºC
[M40MHZ, M26MHZ] =
[01]
FIR_LEN[1:0]=0
(L=186)
FIR_LEN[1:0]=1
(L=384)
FIR_LEN[1:0]=2
(L=588)
-260
-2286
-8207
NominalOffset
(Nn) 4
3
3
508.0
⋅= L
N
n
[M40MHZ, M26MHZ] =
[00], [10], or [11]
FIR_LEN[1:0]=0
(L=138)
FIR_LEN[1:0]=1
(L=288)
FIR_LEN[1:0]=2
(L=384)
49447
449446
1065353
LSB
[M40MHZ, M26MHZ] =
[01]
FIR_LEN[1:0]=0
(L=186)
FIR_LEN[1:0]=1
(L=384)
FIR_LEN[1:0]=2
(L=588)
121071
1065353
3825004
Temperature Erro r
1
−
−=
n
n
SNTN
TERR ))((
Tn = 25°C,
T = -40ºC to +85ºC -10 10 ºC
Nn is measured at Tn during meter calibration and is stored in MP U or CE for use in t em perat ure calcula-
tions.
5.4.14 VREF
Table 83 shows the performance sp ecifications for VREF. Unless otherwise specified, VREF_DIS = 0.
Table 83: VREF Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
VREF output voltage, VREF(22) Ta = 22ºC 1.193 1.195 1.197 V
VREF chop step 40 mV
VREF power supply sensitivity
ΔVREF / ΔV3P3A V3P3A = 3.0 to 3.6 V -1.5 1.5 mV/V
VREF input impedance VREF_DIS = 1,
VREF = 1.3 to 1.7 V 100 kΩ
VREF output impedance CAL =1,
ILOAD = 10 µA, -10 µA 2.5 kΩ
VNOM definitiona
626 102)22(101)22()22()( −− ⋅−+⋅−+= TCTTCTVREFTVNOM
V
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
104 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Parameter
Condition
Min
Typ
Max
Unit
VNOM temperature co efficients:
TC1
TC2
3.18·(52.46-TRIMT)
-0.444
µV/ºC
µV/°C2
VREF(T) deviation from VN OM (T)
)40,22max( 10
)( )()( 6
−
−
TTVNOM TVNOMTVREF
-40 +40 PPM/ºC
VREF aging ±25 PPM/
year
a This relationship d escribes the nomin al behavior of VRE F at different tempe ratures.
5.4.15 ADC Converter, V3P3A Referenced
Table 84 shows the performance sp ecifications for t he ADC converter, V3P3A reference d. For this data,
FIR_LEN[1:0]=0, VREF_DIS=0 and LSB values d o not include the 8 -bit left shift at the CE input.
Table 84: ADC Converter P erformance Specifications
Parameter Condition Min Typ Max Unit
Recommended Input Range
(Vin-V3P3A) -250 250 mV
peak
Voltage to Current Crosstalk
)cos(
*10
6
VcrosstalkVin
Vin
Vcrosstalk ∠−∠
Vin = 200 mV peak,
65 Hz, on VA.
Vcrosstalk = largest
measurement on IA or IB
-10 10
μV/V
THD (First 10 harmonics)
1
:
250 mV-pk
20 mV-pk
Vin=65 Hz,
64 kpts FFT, Blackman-
Harris window
CKCE = 5 MHz
-75
-90
dB
dB
Input Impedance Vin = 65 Hz 40 90 kΩ
Temperature coef ficient of Input Im-
pedance Vin = 65 Hz 1.7 Ω/°C
LSB size
3
3
75.4 25.1
⋅⋅= L
VV REFLSB
L = FIR length
[M40MHZ,
M26MHZ] =
[00], [10], or [11]
FIR_LEN[1:0]=0
FIR_LEN[1:0]=1
FIR_LEN[1:0]=2
3231
355
150
nV/
LSB
[M40MHZ,
M26MHZ] =
[01]
FIR_LEN[1:0]=0
FIR_LEN[1:0]=1
FIR_LEN[1:0]=2
1319
150
42
nV/
LSB
Digital Full Scale
3
3
L
L = FIR length
[M40MHZ,
M26MHZ] =
[00], [10], or [11]
FIR_LEN[1:0]=0
FIR_LEN[1:0]=1
FIR_LEN[1:0]=2
±97336
±884736
±2097152
LSB
[M40MHZ,
M26MHZ] =
[01]
FIR_LEN[1:0]=0
FIR_LEN[1:0]=1
FIR_LEN[1:0]=2
±238328
±2097152
±7529536
LSB
ADC Gain Error versus
%Power Supply Variation
3.3/33100 /357106
APV VnVNout INPK
∆
∆
Vin=200 mV pk, 65 Hz
V3P3A=3.0 V, 3.6 V
50 ppm/%
Input Offset (Vin-V3P3A) -10 10 mV
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 105
5.5 Timing Specifications
5.5.1 Flash Memory
Table 85: Flash Memory Timing Specifications
Parameter
Condition
Min
Typ
Max
Unit
Flash Read Pulse Width V3P3A = V3P3SYS = 0
(BROWNOUT Mode) 30 100 ns
Flash write cycles -40°C to +85°C 20,000 Cycles
Flash data retent i on 25°C 100 Years
Flash data retent i on 85°C 10 Years
Flash byte write operat i ons between
page or mass erase operations 2 Cycles
Write Time per Byte 42 µs
Page Erase (1024 byt es) 20 ms
Mass Erase 200 ms
5.5.2 EEPROM Interface
Table 86: EEPROM Interface Timing
Parameter
Condition
Min
Typ
Max
Unit
Write Clock frequency (I2C)
CKMPU = 4.9 MHz,
Using interrupt s 78 kHz
CKMPU = 4.9 MHz,
bit-banging DIO4/5 150 kHz
Write Clock frequency (3-wire) CKMPU=4.9 MHz 500 kHz
5.5.3 RESET
Table 87: RESET Timing
Parameter Condition Min Typ Max Unit
Reset pulse width 5 µs
Reset pulse fall time 1 µs
5.5.4 RTC
Parameter
Condition
Min
Typ
Max
Unit
Range for date 2000 2255 year
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
106 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5.5.5 SPI Slave Port (MISSION Mode)
Table 88: SPI Slave Port (MISSION Mode) Timing
Parameter
Condition
Min
Typ
Max
Unit
t
SPIcyc
PCLK cycle time 1 µs
t
SPILead
Enable lead time 15 ns
t
SPILag
Enable lag time 0 ns
tSPIW PCLK pulse width:
High
Low
40
40
ns
ns
tSPISCK PCSZ to first PCLK fall Ignore if PCLK is low
when PCSZ falls. 2 ns
tSPIDIS Disable time 0 ns
tSPIEV PCLK to Data Out 15 ns
tSPISU Data input setup time 10 ns
tSPIH Data input hold time 5 ns
MSB OUT LSB OUT
MSB IN LSB IN
t
SPIcyc
t
SPILead
t
SPILag
t
SPISCK
t
SPIH
t
SPIW
t
SPIEV
t
SPIW
t
SPIDIS
PCSZ
PCLK
PSDI
PSDO
Figure 44: SPI Slave Port (MISSION Mode) Timing
Electrical Specification Footnotes
1. This spec will be guaranteed and verified in production samples, but will not be measured in production.
2. This spec will be guaranteed and verified in production samples, but will be measured in production
only at DC.
3. This spec will be m easured in production at the limits of the specified operat ing temperature.
4. This spec defi nes a nominal relation ship rather than a m easured parameter. Co rrect circuit operation
will be verified wit h other specs that use this nominal relationship as a refe rence.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 107
5.6 Typical Performance Data
5.6.1 Accuracy over Current
Figure 45 shows accuracy over current for various load angles at room temperature.
Figure 45: Wh Accur acy, 0.1 A to 200 A at 240 V/50 Hz and Room Temperature
5.6.2 Accuracy over Temperature
With digital temperature com pensat ion enabled, the temperature characteristics of the reference voltage
(VREF) are compensated to within ±4 0 PPM/°C (see sect ion 3.4 for details).
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
0.1 110 100 1000
% Error
I (A rms)
6531 Wh, A ll Phases, 50 Hz, 240 V
0 Degree
60 Degree
300 Degree
180 Degree
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
108 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5.7 71M6531D/F Package
5.7.1 Package Outline
Figure 46: QFN-68 Package Outline, Top and Side View
Figure 47: QFN-68 Package Outline, Bottom Vi ew
* Pin length is nominal ly 0.4 mm (min = 0.3 mm, max = 0.4 mm).
** Exposed pad is internally connected t o G NDD.
*** Pin 1 is marked on bottom with notch or cham fered corner in the exposed pad next to pin 1.
SIDE VIEW
TOP VIEW
PIN #1 DOT
BY
MARKING
68
2
1
8.000 ±0.050
8.000 ±0.050
0.000 ±0.050 0.203 REF
0.850 ±0.050
PIN #1 ID R0.20, or
CHAMFER 0.500 x 45°
BOTTOM
VIEW
68
1
2
6.300 ±0.100
Exp. pad
6.300 ±0.100
Exp. pad
6.400 REF.
0.400 ±0.050
0.400 BSC
0.200 ±0.050
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 109
5.7.2 71M6531D/F Pinout (QFN-68)
Figure 48: Pinout for QF N-68 P ackage
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31
32
26
27
28
29
30
18
19
20
21
22
24
25
35
36
37
38
39
40
41
42
43
44
45
46
47
48
64
63
62
61
67
52
53
54
55
56
57
58
59
60
65
66
SEG9/E_RXTX
GNDD
TMUXOUT
SEG37/DIO17
TX
SEG3/PCLK
V3P3D
SEG19/CKTEST
SEG4/PSDO
SEG5/PCSZ
DIO2/OPT_TX
V3P3SYS
COM1
COM2
COM3
COM0
SEG14
SEG13
SEG12
SEG7/MUX_SYNC
SEG8
SEG6/PSDI
SEG49/DIO29
SEG35/DIO15
SEG34/DIO14
SEG2
SEG1
SEG15
SEG0
SEG65/DIO45
SEG33/DIO13
SEG63/DIO43
SEG16
SEG27/DIO7/RPULSE
SEG26/DIO6/WPULSE
SEG25/DIO5/SDATA
SEG29/DIO9/YPULSE
RX
SEG31/DIO11
RESET
V2P5
VBAT
SEG24/DIO4/SDCK
SEG28/DIO8/XPULSE
ICE_E
SEG18
SEG17
SEG30/DIO10
SEG11/E_RST
SEG32/DIO12
VA
PB
XOUT
TEST
XIN
DIO1/OPT_RX
V1
VREF
IA
IB
V3P3A
GNDA
VB
GNDD
17
SEG66/DIO46
23
SEG64/DIO44
33
34
49
50
SEG48/DIO28
51
68
SEG10/E_TCLK
TERIDIAN
71M6531D-IM
71M6531F-IM
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
110 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5.7.3 Recommended PCB Land Pattern for the QFN-68 Package
Figure 49: PCB Land P attern for QFN 68 P ackage
Table 89: Recommended P CB Land Pattern Dimensions
Symbol
Description
Typical Dimension
e Lead pit ch 0.4mm
x Pad width 0.23mm
y Pad length, see note 3 0.8mm
d See note 1 6.3mm
A 6.63mm
G 7.2mm
Notes:
1. Do not place unmasked vias in the region denoted by di m ension d.
2. Soldering of bot tom internal pad is not required for proper operation.
3. The y dimension has been elongated to allow for hand soldering and reworking. Production assembly
may allow this dimension to be reduced as long as t he G dimension is mai ntained.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 111
5.8 71M6532D/F Package
5.8.1 71M6532D/F Pinout (LQFP-100)
Figure 50: PCB Land Pattern for LQFP-100 Package
1
Teridian
71M6532D
71M6532F
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
92
93
94
95
96
97
98
99
100
26
27
28
29
30
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SEG38/DIO18/MTX
SEG9/E_RXTX
GNDD
TMUXOUT
SEG37/DIO17
TX
SEG3/PCLK
V3P3D
SEG19/CKTEST
SEG4/PSDO
SEG5/PCSZ
DIO2/OPT_TX
V3P3SYS
DIO3
COM1
COM2
COM3
COM0
DIO57
DIO58
DIO56
GNDD
SEG14
SEG13
SEG12
SEG7/MUX_SYNC
SEG8
SEG50/DIO30
SEG6/PSDI
SEG36/DIO16
SEG49/DIO29
SEG2/TEST2
SEG1/TEST1
SEG15
SEG0/TEST0
SEG65/DIO45
SEG44/DIO24
SEG45/DIO25
SEG47/DIO27
SEG46/DIO26
SEG33/DIO13
SEG63/DIO43
SEG64/DIO44
SEG16
SEG27/DIO7/RPULSE
SEG39/DIO19
SEG26/DIO6/WPULSE
SEG25/DIO5/SDATA
SEG29/DIO9/YPULSE
RX
SEG31/DIO11
GNDD
RESET
V2P5
VBAT
SEG24/DIO4/SDCK
SEG23
SEG22
SEG28/DIO8/XPULSE
SEG41/DIO21
SEG40/DIO20
ICE_E
SEG18
SEG17
SEG30/DIO10
SEG20
SEG21
SEG43/DIO23
VB
VX
V3P3A
GNDA
VA
PB
NC
XOUT
TEST
XIN
DIO1/OPT_RX
V1
VREF
IAP
IBN
GNDD
SEG11/E_RST
SEG10/E_TCLK
SEG61/DIO41
IAN
IBP
SEG35/DIO15
SEG34/DIO14
SEG67/DIO47
SEG68/DIO48
SEG69/DIO49
SEG70/DIO50
SEG71/DIO51
SEG42/DIO22/MRX
SEG60/DIO40
SEG62/DIO42
SEG32/DIO12
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
112 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5.8.2 LQFP-100 Mechanical Drawing
Figure 51: LQFP-100 P ackage, Mechanical Drawing
(Dimensions are in mm.)
1
15.7(0.618)
16.3(0.641)
15.7(0.618)
16.3(0.641)
Top View
MAX. 1.600
0.50 TYP.
14.000 +/- 0.200
0.225 +/- 0.045
0.60 TYP>
1.50 +/- 0.10
0.10 +/- 0.10
Sid e Vi ew
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 113
5.9 Pin Descriptions
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output
The circuit num ber denotes the equivalent circuit, as s pecified under S ect ion 5.9.4 I/O Equiv alent Circuits.
5.9.1 Power and Ground Pins
Table 90: Power and Ground P ins
Name Type Circuit Description
GNDA P – Analog ground: This pin should be connected directly to the ground
plane.
GNDD P
–
Digital ground: T his pi n should be conn ect ed directly to t he ground plane.
V3P3A P – Analog power supply: A 3.3 V power supply should be conn ect ed to this
pin, must be the same voltage as V3P 3SYS.
V3P3SYS P – System 3.3 V supply. This pi n should be connected to a 3.3 V power
supply.
V3P3D O 13
Auxiliary voltage output of the chip, controlled by the internal 3.3 V selection
switch. In m i ssi on m ode, this pin is int ernally connected t o V 3P3SYS. In
BROWNOUT mode, it is internally connected to VBAT. This pin is floating
in LCD and sleep mode. A bypass capacitor to ground should not exceed
0.1 µF.
VBAT P 12 Battery backup and oscillator powe r supply. A battery or super-capacitor
is to be con nected between VBAT an d GNDD. If no bat tery is used,
connect VBAT to V3P3SYS.
V2P5 O 10 Output of the internal 2.5 V regulator. A 0.1 µF capacitor to GNDA
should be conne ct ed to this pin.
5.9.2 Analog Pins
Table 91: Analog Pins
Name Type Circuit Description
IA, IB
IAP/IAN,
IBP/IBN 1) I 6 Line Current Sense Inputs: These pins are volt age i nputs to the internal
A/D converter. Typically, they are connected to the outputs of current
sensors. Unused pins must be tied to V3P3A.
VA, VB,
VX 1) I 6
Line Voltage Sense I nputs: These pins are voltage inputs t o the internal
A/D converter. Typically, they are connected to the outputs of resistor
dividers. Unused pins must be tied to V3P3A.
The VX pin is not supported by standard CE code.
V1 I 7
Comparator Input: This pin is a voltage i nput to the internal comparator.
The voltage applied t o the pin is compared to the internal B IAS voltage
(1.6 V). If the input voltage is above VBI AS, the comparator output will
be high (1). If the comparator output is low, a voltage fault will occur. A
series resis tor should be connected from V1 to the resistor d ivider to
provide hysteresis.
VREF O 9 Voltage Reference for the ADC. Normally disabled and left unconnected.
If enabled, a 0.1 µF capaci tor to V3P3A should be connected to thi s pin.
XIN
XOUT I 8
Crystal Inputs: A 32 kHz crystal should be connected across these pins.
Typically, a 33 pF ca pacit or is also connected f rom XIN to GNDA and a
15 pF capacitor is connected from XOUT to GNDA. It is impor tan t to
minimize the capacitance between these pins. See the crystal manufacturer
datasheet for details.
If an external clock is used, a 150 mV (p-p) clock signal should be applied
to XIN, and XOUT should be left unconnected.
1) Differential pin pairs IAP/IAN and IBP/IBN, as well as sin gle-ended VX pin use d on 71M6532D/F only.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
114 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
5.9.3 Digital Pins Table 92: Digital Pins
Name
Type
Circuit
Description
COM3,COM2,
COM1,COM0
O 5 LCD Common Outputs: These 4 pins provi de the select signal s f or
the LCD display .
SEG0…SEG2,
SEG7, SEG8
SEG12…SEG18 O 5 Dedicated LCD Segment Output pins.
SEG20…SEG23
O
5
Dedicated LCD Segment Output pins (71M6532D/F only ).
SEG24/DIO4…
SEG35/DIO15,
SEG37/DIO17,
SEG48/DIO28,
SEG49/DIO29,
SEG63/DIO43…
SEG66/DIO46
I/O 3, 4, 5
Multi-use pins, configurable as either LCD SEG driver or DI O.
(DIO4 = SCK, DIO5 = SDA when configured a s E E PROM interface;
WPULSE = DIO6, VARPULSE = DIO7 when configured as pulse
outputs). Unused pins must be configured as outputs or terminated
to V3P3/GNDD.1)
SEG3/PCLK
SEG4/PSDO
SEG5/PCSZ
SEG6/PSDI
I/O 3, 4, 5 Multi-use pins, configurable as either LCD SE G driver or SPI PORT.
E_RXTX/SEG9
I/O
1, 4, 5
Multi-use pins, config urable as either e m ul ator port pins (when I CE_E
pulled high) or LCD SEG drivers (when ICE_E tied to GND).
E_RST/SEG11 I/O 1, 4, 5
E_TCLK/SEG10
O
4, 5
ICE_E I 2 ICE enable. When zero, E_RST, E_TCLK and E_RXTX become
SEG32, SEG33 and SEG38 respectively. For production units, this
pin should be pull ed to GND to disable t he em ul ator port.
CKTEST/SEG19,
MUXSYNC/SEG7 O 4, 5 Multi-use pins, configurable as either multiplexer/clock out put or LCD
segment driver using the I/O RAM re gi sters CKOUT_E or
MUX_SYNC_E.
TMUXOUT
O
4
Digital output test multiplexer. Cont rolled by
TMUX[3:0].
OPT_RX/DIO1 I/O 3, 4, 7 Multi-use pin, configurable as Optical Receive Input or general DIO.
When conf igured a s OPT_RX, t his pin receiv es a sign al from an external
photo-detector used in an IR serial interface. If this pin is unused it
must be confi gured as an output or te rminated t o V3P3D or GNDD.
OPT_TX/DIO2 I/O 3, 4 Multi-use pin, configurable as either optical LED tran smit output,
WPULSE, RPULSE, or general DIO. When configured as OP T_TX,
this pin is capable of di rectly driving an LED for transmi tting data in
an IR serial interface.
RESET I 2 Chip reset: Thi s i nput pin is used to re set the chip into a known state.
For normal operatio n, this pin is pulled low. To reset the chip, this pi n
should be pulled high. This pin has an internal 30 μA (nominal) current
source pull-down. No external reset circuitry is necessary .
RX I 3 UART input. If this pin is unused it must be configured as an
output or terminated to V3P3D or GNDD.
TX
O
4
UART output.
TEST I 7
Enables Production Test. This pin must be grounded in normal
operation.
PB I 3
Push button input. T his pin must be at GNDD when not active. A
rising edge sets t he IE_PB flag. It al so cau ses the part to wake up if it
is in SLEEP or LCD mode. PB does not have an internal pull-up or
pull-down.
1) Not all pins available on the 71M6531D/F or 71M6532D/F.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 115
5.9.4 I/O Equivalent Circuits
Figure 52: I/O Equivalent Circuits
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
GNDD
110K
V3P3D
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input
Type 2:
Pin configured as DIO Input
with Internal P ull-Down
GNDD
110K
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
CMOS
Output
GNDD
V3P3D
GNDD
V3P3D
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DI O O ut put
Digital
Output
Pin
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
LCD
Driver
GNDD
LCD SEG
Output
Pin
To
MUX
GNDA
V3P3A
Analog Input Equivalent Circuit
Typ e 6:
ADC Input
Analog
Input
Pin
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
GNDA
V3P3A
To
Comparator
Comparator
Input
Pin
To
Oscillator
GNDD
Oscillator
Pin
VREF Equivalent Circuit
Type 9:
VREF
from
internal
reference
GNDA
V3P3A
VREF
Pin
V2P5 Equi valent Circuit
Type 10:
V2P5
from
internal
reference
GNDD
V3P3D
V2P5
Pin
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
LCD
Drivers
VLCD
Pin
VBAT Equivalent Circuit
Type 12:
VBAT Power
GNDD
Power
Down
Circuits
VBAT
Pin
V3P3D Eq uival ent Circu it
Type 13:
V3P3D
from
V3P3SYS
V3P3D
Pin
from
VBAT
10
40
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
116 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
6 Ordering Information
Part Part Description
(Package)
Flash
Size
Packaging Order Number Package Mark-
ing
71M6531D
68-pin QFN,
lead free
128 KB Bulk 71M6531D-IM/F 71M6531D-IM
71M6531D 128 KB Tape and reel 71M6531D-IMR/F 71M6531D-IM
71M6531F 256 KB Bulk 71M6531F-IM/F 71M6531F-IM
71M6531F 256 KB Tape and reel 71M6531F-IMR/F 71M6531F-IM
71M6532D
100-pin LQFP,
lead free
128 KB Bulk 71M6532D-IGT/F 71M6532D-IGT
71M6532D 128 KB Tape and reel 71M6532D-IGTR/F 71M6532D-IGT
71M6532F 256 KB Bulk 71M6532F-IGT/F 71M6532F-IGT
71M6532F 256 KB Tape and reel 71M6532F-IGTR/F 71M6532F-IGT
7 Related Information
The following documents applicable to the 71M6531D/F and 71M6532D/F are available from Teridia n
Semiconduct or Corporation:
• 71M653X Software User’s Guide (SUG_653X)
• Demo Board User’s Guide (DBUM_6531)
• Application Not e on Migration from the 6521 to the 6531 (AN_6531_001)
8 Contact Information
For more informat i on about Teridian Semiconductor prod ucts or to check the availability of the
71M6531D/F or 71M6532D/F, contact us at:
6440 Oak Canyon Ro ad
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 5 08-8800
FAX: (714) 508-8878
Email: meter.support@teridian.com
For a complete list of worldwide sales off i ces, go to http://www.teridian.com.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 117
Appendix A: Acronyms
AFE Analog Front End
AMR Automatic Met er Reading
ANSI American National St andards Institute
CE Compute Eng ine
DIO Digital I /O
DSP Digital Signal Processor
FIR Finite Impulse Re sponse
I2C Inter-IC Bus
ICE In-Circuit Emulator
IEC International Electrotechnical Com m ission
MPU Microprocessor Unit (CPU)
PLL Phase-locked loop
RMS Root Mean Square
SFR Special Function Register
SOC System on Chip
SPI Serial Peripheral Interface
TOU Time of Use
UART Universal Asynchronous Receiver/Transmitter
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
118 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
Appendix B: Revision History
Revision
Date
Description
1.3 June 9, 2010 1) Throughout document: Added bit ranges to all register fields where
missing (e.g. MPU_DIV[2:0]).
2) Figure 1, Figure 2: corrected name for PSDI and PSDO signals.
3) 1.4 80515 MPU Core
Added SFR regi st er addresses whe re needed.
(Page 19) Table 6: Cha nge approximate frequencies to exact
frequencies.
(P age 19) Changed providing Library to providing demonstration
source code.
(Page 20) Added not e about MUX_DIV=0 disables ADC o utput.
(Page 21) See restrictions on INTBITS register.
(Page 22) Added P1-P3 to Table 10.
(Page 23) Updated Data Pointer de scription.
(Page 24) Table 14: Updated descripti on for FWCOL0, FWCOL1.
(Page 26) 1.4.6 UARTs: Clarified SOBUF, S1BUF as Tx and Rx
buffers.
(Page 27) Added caution on proper way to clear flag bits.
(Page 30) 1.4.9 Interrupts: Clarifie d Exter nal v s Inte rnal i nterr upts.
(Page 31) Table 25: Added Interrupt sources for Ext. Interrupts 2-6.
4) 1.5.2 Internal Clocks
(Page 36) Table 37: Changed frequencies to exact freque ncies.
(Page 38) Added caution concerning frequency relationship to
specific CE code.
5) 1.5.3 Real-Time Clock (RT C): (Page 39) Added description for
observing RTC ti m i ng on TMUXOUT pin, corr ect ed values for
RTCA_ADJ, and achievable frequency st ep.
6) 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and
71M6532D/F (Page 45):
Added caution about not sourcing current in or out of DIO pins.
Updated Figure 10 : Connecting an E xternal Load to DIO Pins.
7) 1.5.13 Batt ery Monitor (Page 46): Corrected RAM address for
ADC data.
8) 1.5.15 SPI Slave Port (page 49): Clarified description of I/O RAM
access via the S PI interface. A dded Table 50.
9) 2.3 Battery M odes (page 56, 57): Added det ai ls on software pre-
cautions for switching between modes and factory programming of
the first 6 flash addresses.
10) 3.1 Connection of Sensors (page 63): Added note concerning
analog input pins requiring sensors with low source impeda nce.
11) 3.15 MPU Firmware (page 70): Modified to indicate demonstration
source code provided.
12) 3.16 Crystal Oscillator (page 70): Updated caution concerning
rejecting electromagneti c interference.
13) Table 54: I/O RA M M ap in Functional O rder (page 72): Updated
Unused and NVRAM locations.
14) 4.3.4 Environment: A dded comment con cerning importance of
parameter dependence on CE code env ironment.
15) 4.3.6 CE Status and Co ntrol (page 89):
Updated descript i on of F0 in Table 57.
Updated descript i ons in Table 58 (page 91).
16) 4.3.7 CE Transfer Va riables: Updated descri ption of
VBAT_SUM_X in Table 63 (page 93).
17) Corrected values for
EXT_PULSE
in descriptio n of internal pulse
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 119
generation (page 89).
18) Updated pin-out for QFN-68 package (Figure 48).
19) Added explanation for InSQRES_X.
20) Added explanation of delay compensation in CE (1.3.5).
21) Added explanation on temperature coefficients for VERF in Appli-
cation Section (3.4.1).
22) Corrected Figure 30 (right si de).
1.2 October 21, 2009 Updated number range for RTC_ADJ to 0 – 0x7F and tolerance for e x -
posed pad in Figure 46 to 0.1 mm. Correct ed bit range for CE_LCTN
to [7:0] and funct ional descriptio n for TMOD[7] and TMOD[3] in Table
22. Added maxim um value for WRATE and text stating that registers
RTC_SEC to RTC_YR do not change at reset. A dded V LS B entry for
sag detection i n CE Interface Description, text regardi ng hysteresis at
section 3.10, note that VX pin is not s upported by standard CE code,
and description of STOP and IDLE bits in PCON register. Changed
value for Wh accuracy percentage on title page (value stated for
room temperature).
1.1 July 27, 2009 Updated mechani cal drawing for QFN-6 8 package.
Replaced Figure 19 with single-phase example.
Corrected LQFP-100 package drawing (Figure 50).
Applied minor cor rections and enhancements to diag rams.
1.0 February 27,
2009
Initial release. Changes with respect to PDS v1.3:
1) Corrected Ti m er/Counter 0/1 label in Table 22.
2) Corrected entries for DIO29 and DIO43 in Table 39.
3) Updated unused/reserved bits in I/O RAM tables, added descrip-
tion for WE register.
4) Documented blink capability for both SEG18 and SEG19.
5) Changed package for 71M6532D/ F to LQFP-100, updat ed al l pi n
tables and I/O RAM tables accordingly .
6) Replaced graph showing system performance specification over
temperature wit h specification on accuracy of VREF compensa-
tion.
7) Added explanation for hysteresis at the V1 pin in A pplications
Section.
8) Added note on recom m ended bypass capacitors C1 and C2 in
Electrical Specification.
9) Removed access to I/O RAM from SPI Port description.
10) Updated numerous parameters in Electrical Specifi cation (tem-
perature sensor, supply current for m ission and battery modes).
11) Corrected number of pre-boot cy cles in Flash Memory Section.
12) Updated entri es in I/O RAM table under “Wake” colu m n.
Data Sheet 71M653 1D/ F-71M6532D/F FDS 6531/6532 005
120 © 2005-2010 TERIDIAN Semiconductor Corporation v1.3
© 2008-2010 T eridian Semiconductor Corporation. All rights Reserved.
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All other trademarks are the property of their respecti ve owners.
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contained in the Company’s warrant y detailed in the Teridian Semiconductor Corporation st andard Terms
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