74LVT16373MEAX - Fairchild - Product.Network

January 1999

Revised June 2005

74LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transpar ent Latch with 3-STATE Outputs

74LVT16373 • 74LVTH16373

Low Voltage 16-Bit Transparent Latch

with 3-STATE Outputs

General Descript ion

The LVT16373 and LVTH16373 contain sixteen non-invert-

ing latches with 3-STATE outputs and is intended for bus

oriented applications. The device is byte controlled. The

flip-flops appear transparent to the data when the Latch

Ena ble ( L E ) is H IGH . Wh e n L E is LO W, t h e da t a th at m e ets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

The LVTH16373 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These latches are designed for low-voltage (3.3V) VCC

applications, bu t with the capability to provide a TTL inte r-

face to a 5V envir onmen t. The LVT16373 an d LVTH16373

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Features

■Input and output interface capability to systems at

5V VCC

■Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16373),

also availabl e wit ho ut bush old feat ure (74LVT16373)

■Live insertion /extracti on per mitt ed

■Power Up/Power Down high impedance provides

glitch-fr ee bus load i ng

■Outputs source/sink



32 mA/



64 mA

■Functionally compatible with the 74 series 16373

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human-body model

2000V

Machine model

200V

Charged-device model

1000V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Prelimi nary)

Ordering Code:

Note 1: BGA package av ailable in Tape and Reel only.

Note 2: Device also av ailable in Tape and R eel. Specify by appending suffix lette r “X” to the ord ering code.

Logic Symbol

Order Num b er Packag e Num b er Packa ge Des cri pt io n

74LVT16373GX

(Note 1) BGA54A

(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74LVT16373MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16373MTD

(Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVTH16373GX

(Note 1) BGA54A

(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74LVTH16373MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVTH16373MTD

(Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2

74LVT16373 • 74LVTH16373

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA

(Top Thru Vi ew)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

HIGH Voltag e Level

LOW Voltage Le ve l

Immaterial

HIGH Im pedance

Previous output prior to HIGH-to-LOW transition of LE

Pin Names Description

OEn Output Enable Input (Active LOW)

LEn Latch Enable Input

I0–I15 Inputs

O0–O15 3-STATE Outputs

NC No Connect

123456

AO0NC OE1LE1NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE2LE2NC I15

Inputs Outputs

LE1OE1 I0–I7 O0–O7

X H X Z

H L L L

H L H H

L L X O

Inputs Outputs

LE2OE2 I8–I15 O8–O15

X H X Z

H L L L

H L H H

L L X O

3 www.fairchildsemi.com

74LVT16373 • 74LVTH16373

Functional Description

The LVT16373 and LVTH16373 contain sixteen D-type

latches with 3-STATE standa rd out puts. The devic e is byte

controlled with each byte functioning identically, but inde-

pendent of the othe r. Con trol pins ca n be shorted together

to obtain full 16-bit operation. The following description

applies to eac h byte. When the Latch E nab le (L E n) input is

HIGH, data on the Dn enters the latches. In t his condition

the latches are transparent, i.e, a latch output will change

states each time its D input changes. When LEn is LOW,

the latches store information that was present on the D

inputs a setu p time precedi ng the HIGH-to-LO W transition

of LEn. The 3-STATE standard outputs are controlled by

the Output Enable (OEn) input. When OEn is LOW, the

standard outputs are in the 2-state mode. When OEn is

HIGH, the standard outputs are in the high impedance

mode but this does not interfere with entering new data into

the latches.

Logic Diagrams

Please not e t hat these diagram s are provided only fo r t he understa nding of logic operat ions and s hould not be used to e stimate propagation delays .

www.fairchildsemi.com 4

74LVT16373 • 74LVTH16373

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions

Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyo nd those in dic ated may adver s ely affec t device rel iability. Fun c tio nal opera ti on under ab s olute maximum rated con dit ions is not implied.

Note 4: IO Absolute Maximum Rating must be observed.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



4.6 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Voltage



0.5 to



7.0 Output in 3-STATE V



0.5 to



7.0 Output in H IGH or LOW State ( Note 4)

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA

IODC Output Current 64 VO

VCC Output at HIGH State mA

128 VO

VCC Output at LOW State

ICC DC Supply Current per Supply Pin

64 mA

IGND DC Ground Current per Ground Pin

128 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage 2.7 3.6 V

VIInput Voltage 0 5.5 V

IOH HIGH Level Output Current



32 mA

IOL LOW Level Output Current 64 mA

TAFree-A ir Ope rat i ng Temperature



40 85

V Input Edge Rate, VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter VCC T A



C to



CUnits Conditions

(V) Min Max

VIK Input Clamp Diode Voltage 2.7



1.2 V II



18 mA

VIH Input HIGH Voltage 2.7–3.6 2.0 V VO

0.1V or

VIL Input LOW Voltage 2.7–3.6 0.8 V VO

VCC



0.1V

VOH Output HIGH Voltage 2.7–3.6 VCC



0.2 VIOH



100

2.7 2.4 IOH



8 mA

3.0 2.0 IOH



32 mA

VOL Output LOW Voltage 2.7 0.2

IOL

100

2.7 0.5 IOL

24 mA

3.0 0.4 IOL

16 mA

3.0 0.5 IOL

32 mA

3.0 0.55 IOL

64 mA

II(HOLD) Bushold Input Minimu m Drive 3.0 75

AVI

0.8V

(Note 5)



75 VI

2.0V

II(OD) Bushold Input Over- Dri ve 3.0 500

A(Note 6)

(Note 5) Current to Change State



500 (Note 7)

IIInput Current 3.6 10

5.5V

Control Pins 3.6

0V or VCC

Data Pins 3.6



VCC

IOFF Power Off Leakage Current 0

100

A0V

VI or VO

5.5V

IPU/PD Power Up /Down 3-STA TE 0–1.5V

100

AVO

0.5V to 3.0V

Output Current VI

GND or VCC

IOZL 3-STATE Output Leakage Current 3.6



0.5V

IOZH 3-STATE Output Leakage Current 3.6 5

3.0V

IOZH



3-STATE Output Leakage Current 3.6 10



5.5V

5 www.fairchildsemi.com

74LVT16373 • 74LVTH16373

DC Electrical Characteristics (Continued)

Note 5: Applies to bus hold versions only (74LVTH16373).

Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 7: An external driver mus t s ink at least the s pec if ied current to switc h f rom HIG H -t o-LOW.

Note 8: This is the incr eas e in sup ply c urrent for eac h input tha t is at t he specified voltage lev el rather th an VCC or GND.

Dynamic Switching Characteristics (Note 9)

Note 9: Characterized in SSOP packa ge. Guaranteed parameter, but not te sted.

Note 10: M ax number of out put s d ef ined as (n). n



1 data inp uts are driven 0V to 3V. Output under tes t held LOW.

AC Electrical Characteristics

Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to- LOW (tOSHL) or LOW- to -H I GH (t OSLH).

Capacitance (Note 12)

Note 12: C apacitanc e is m easured at fr equency f

1 MHz, per MIL-STD -883, M et hod 3012.

Symbol Parameter VCC T A



C to



CUnits Conditions

(V) Min Max

ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH

ICCL Power Supply Current 3.6 5 mA Outputs LOW

ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled

ICCZ



Power Supply Current 3.6 0.19 mA VCC

5.5V,

Outputs Disabled

ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC



0.6V

(Note 8) Other Inputs at VCC or GND

Symbol Parameter VCC TA

CUnits Conditions

(V) Min Typ Max CL

50 pF, RL

500

VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10)

VOLV Quiet Output Minimum Dynamic VOL 3.3



0.8 V (Note 10)

Symbol Parameter



C to



C, CL

50pF, RL

500

UnitsVCC

3.3V

0.3V VCC

2.7V

Min Max Min Max

tPHL Propagation Delay 1.5 3.9 1.5 4.3 ns

tPLH Dn to On1.5 3.8 1.5 4.2

tPHL Propagation Delay 1.9 4.2 1.9 4.4 ns

tPLH LE to On1.6 4.3 1.6 4.8

tPZL Output Enable Time 1.3 4.3 1.3 4.9 ns

tPZH 1.0 4.3 1.0 5.1

tPLZ Output Disable Time 1.5 4.7 1.5 4.8 ns

tPHZ 2.0 5.0 2.0 5.4

tSSetup T ime, Dn to LE 1.0 0.8 ns

tHHold Time, Dn to LE 1.0 1.1 ns

tWLE Pulse Width 3.0 3.0 ns

tOSHL Output to Output Skew (Note 11) 1.0 1.0 ns

tOSLH 1.0 1.0

Symbol Parameter Conditions Typical Units

CIN Input Capaci tance VCC

Open, VI

0V or VCC 4pF

COUT Output Capacitance VCC

3.0V, VO

0V or VCC 8pF

www.fairchildsemi.com 6

74LVT16373 • 74LVTH16373

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Packag e Num b er BGA5 4A

Preliminary

7 www.fairchildsemi.com

74LVT16373 • 74LVTH16373

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

www.fairchildsemi.com 8

74LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A cri tical compon ent in any com ponen t of a life su pport

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device or system, or to affect its safety or effectiveness.