LTC3785-1
1
37851fa
TYPICAL APPLICATION
DESCRIPTION
10V, High Effi ciency,
Buck-Boost Controller
with Power Good
The LTC
®
3785-1 is a high power synchronous buck-boost
controller that drives all N-channel power MOSFETs from
input voltages above, below and equal to the output volt-
age. With an input range of 2.7V to 10V, the LTC3785-1 is
well suited for a wide variety of single or dual cell Li-Ion
or multicell alkaline/NiMH applications.
The operating frequency can be programmed from 100kHz
to 1MHz. The soft-start time and current limit are also
programmable. The soft-start capacitor doubles as the
fault timer which can program the IC to latch off or recycle
after a determined off time. Burst Mode operation is user
controlled and can be enabled by driving the mode pin
high. The LTC3785-1 includes a power good output that
indicates when the output voltage is within 7.5% of its
designed setpoint.
Protection features include foldback current limit,
short-circuit and overvoltage protection.
Effi ciency vs Input Voltage
FEATURES
APPLICATIONS
n Palmtop Computers
n Handheld Instruments
n Wireless Modems
n Cellular Telephones
n Single Inductor Architecture Allows VIN Above,
Below or Equal to VOUT
n Power Good Output Indicator
n 2.7V to 10V Input and Output Range
n Up to 96% Effi ciency
n Up to 10A of Output Current
n All N-channel MOSFETs, No RSENSE™
n True Output Disconnect During Shutdown
n Programmable Current Limit and Soft-Start
n Optional Short-Circuit Shutdown Timer
n Output Overvoltage and Undervoltage Protection
n Programmable Frequency: 100kHz to 1MHz
n Selectable Burst Mode
®
Operation
n Available in 24-Lead (4mm × 4mm) Exposed Pad
QFN Package
L, LT, LTC ,LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
VCC
ISVIN
TG1
VSENSE
BG1
FB
VC
TG2
BG2
SW2
37851 TA01a
VBST1
SW1
ISSW1
ISVOUT
RT
VDRV
ISSW2
VBST2
PGOOD
CCM
ILSET
MODE
RUN/SS
VIN
VOUT
LTC3785-1
GND
4.7μF
0.22μF
0.22μF
VIN
2.7V
TO 10V
VOUT
3.3V
5A
22μF
4.7μH
100μF
215k
12k
49.9k
127k
215k1.3k
270pF
1nF
2.2nF 42.2k
C
D
B
A
127k
VIN (V)
2.5
EFFICIENCY (%)
95
10
37851 TA01b
90
85 45.5 78.5
100
ILOAD = 1A
VOUT = 3.3V
FOSC = 500kHz
ILOAD = 2A
LTC3785-1
2
37851fa
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN) ......................... –0.3V to 11V
ISVOUT, ISVIN .............................................. –0.3V to 11V
SW1, SW2, ISSW1, ISSW2 Voltage:
DC ............................................................. –1V to 11V
Pulsed, <1μs ............................................. –2V to 12V
RUN/SS, MODE, CCM, VDRV, VCC Voltages ..–0.3V to 6V
PGOOD Voltage ............................................ –0.3V to 6V
VBST1 Voltage ............................................. –0.3V to 16V
With Respect to SW1 ............................... –0.3V to 6V
VBST2 Voltage ............................................. –0.3V to 16V
With Respect to SW2 ............................... –0.3V to 6V
Peak Driver Output Current < 10μs
(TG1, TG2, BG1, BG2) .................................................3A
VCC Average Output Current .................................100mA
Operating Temperature Range (Note 2)....–40°C to 85°C
Junction Temperature ........................................... 125°C
Storage Temperature Range ...................–65°C to 125°C
(Note 1)
24 23 22 21 20 19
7 8 9
TOP VIEW
25
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18RUN/SS
VC
FB
VSENSE
ILSET
CCM
ISSW1
BG1
VDRV
BG2
ISSW2
SW2
VIN
VCC
ISVIN
VBST1
TG1
SW1
RT
MODE
PGOOD
ISVOUT
VBST2
TG2
TJMAX = 125°C, θJA = 37°C/W 4 LAYER BOARD
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3785EUF-1#PBF LTC3785EUF-1#TRPBF 37851 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi
cations, go to: http://www.linear.com/tapeandreel/
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Supply
Input Operating Voltage l2.7 10 V
Quiescent Current—Burst Mode Operation VC = 0V, MODE = 3.6V (Note 4) 86 200 μA
Quiescent Current—Shutdown RUN/SS = 0V, ISVOUT = 3.6V 15 25 μA
Quiescent Current—Active MODE = 0V (Note 4) 0.8 1.5 mA
Error Amp
Feedback Voltage (Note 5) l1.200 1.225 1.25 V
Feedback Input Current 1 500 nA
Error Amp Source Current –500 μA
Error Amp Sink Current 900 μA
Error Amp AVOL 90 dB
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
LTC3785-1
3
37851fa
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Regulator
VCC Maximum Regulating Voltage VIN = 5V, IVCC = –20mA l4.15 4.35 4.55 V
VCC Regulation Voltage VIN = 3.6V, IVCC = –20mA l3.3 3.5 3.6 V
VCC Regulator Sink Current ISVOUT = VCC = 5V 800 μA
Run/Soft-Start
RUN/SS Threshold When IC is Enabled
When EA is at Maximum Boost Duty Cycle
l0.35 0.7
1.9 1.1 V
V
RUN/SS Input Current RUN/SS = 0V –1 μA
RUN/SS Discharge Current During Current Limit 20 30 μA
Current Limit
Current Limit Sense Threshold ISVIN to ISSW1, RILSET = 121k
ISVIN to ISSW1, RILSET = 59k
l
l
20
55 60
105 100
155 mV
mV
Reverse Current Limit Sense Threshold ISSW2 to ISVOUT, CCM > 2V
ISSW2 to ISVOUT, CCM < 0.4V
l
l
–50 –110
–15 –170
–35 mV
mV
Input Current ISVIN
ISVOUT
ISSW1, ISSW2
80
10
0.1
150
20
5
μA
μA
μA
CCM Input Threshold (High) l2.2 V
CCM Input Threshold (Low) l0.4 V
CCM Input Current CMM = 3.6V 0.01 1 μA
Burst Mode Operation
Mode Threshold l0.8 1.5 2.2 V
Mode Input Current 0.01 1 μA
tON Time 1.4 μs
Oscillator
Frequency Accuracy l370 509 650 kHz
Switching Characteristics
Maximum Duty Cycle Boost (% Switch BG2 On)
Buck (% Switch TG1 On)
l80 90
99 %
%
TG1, TG2 Driver Impedance 2Ω
BG1, BG2 Driver Impedance 2Ω
TG1, TG2 Rise Time CLOAD = 3300pF (Note 3) 20 ns
BG1, BG2 Rise Time CLOAD = 3300pF (Note 3) 20 ns
TG1, TG2 Fall Time CLOAD = 3300pF (Note 3) 20 ns
BG1, BG2 Fall Time CLOAD = 3300pF (Note 3) 20 ns
Buck Driver Nonoverlap Time TG1 to BG1 100 ns
Boost Driver Nonoverlap Time TG2 to BG2 100 ns
Power Good
Undervoltage Threshold VSENSE Falling, % Below FB Regulation Voltage –5 –7.5 –10.5 %
Undervoltage Hysteresis 1.5 %
Overvoltage Threshold VSENSE Rising % Above FB Regulation Voltage,
MODE = 0V 5 7.5 10.5 %
Overvoltage Hysteresis –2 %
LTC3785-1
4
37851fa
TYPICAL PERFORMANCE CHARACTERISTICS
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
60
80
100
1
37851 G01
40
20
50
70
90
30
10
00.001 0.01 0.1 10
VIN = 4.2V
VIN = 3.6V
VIN = 3V
Burst Mode
OPERATION
FIXED
FREQUENCY
MOSFET Si7940
L = 4.7μH WURTH WE-PD
fOSC = 500kHz
LOAD CURRENT (A)
0.0001 0.001 0.01 0.1 1
40
EFFICIENCY (%)
50
60
70
80
10
37851 G02
30
20
10
0
90
100
VIN = 8.4V
VIN = 7.2V
VIN = 5.4V
MOSFET Si7940
L = 5.6μH MSS1260
fOSC = 430kHz
Burst Mode
OPERATION
FIXED
FREQUENCY
LOAD CURRENT (A)
0.0001 0.001 0.01 0.1 1
40
EFFICIENCY (%)
50
60
70
80
10
37851 G03
30
20
10
0
90
100
VIN = 9V
VIN = 4.2V
VIN = 3.6V
VIN = 2.7V
MOSFET Si7940
L = 5.6μH MSS1260
fOSC = 430kHz
Burst Mode
OPERATION
FIXED
FREQUENCY
VOUT
50mV/DIV
AC
COUPLED
INDUCTOR
CURRENT
1A/DIV
5μs/DIVVOUT = 3.3V
COUT = 100μF
37851 G04
VOUT
500mV/DIV
VIN
3V TO 8.5V
500μs/DIVILOAD = 300μA
VOUT =5V
37851 G05
VOUT
200mV/
DIV
ILOAD
10mA TO 2A
100μs/DIVVIN = 3.6V
VOUT = 3.3V
C 100μF
37851 G06
Burst Mode Ripple Line Transient Response VOUT Load Transient
Li-Ion to 3.3V Effi ciency
vs Load Current
Two Li-Ion to 7V Effi ciency
vs Load Current
Li-Ion/9V to 5V VOUT Effi ciency
vs Load Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3785E-1 is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: Specifi cation is guaranteed by design and not 100% tested in production.
Note 4: Current measurements are performed when the outputs are not switching.
Note 5: The IC is tested in a feedback loop to make the measurement.
PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Output Low IPGOOD = 500μA 200 500 mV
PGOOD Leakage VPGOOD = 5.5V 5 μA
VSENSE Input Current VSENSE = Measured FB Voltage 1 500 nA
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
LTC3785-1
5
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TEMPERATURE (°C)
–50
1.2255
1.2245
1.2250
1.2240
1.2235
1.2230
1.2225
1.2220
1.2215
1.2210 25 75
37851 G07
–25 0 50 100
VFB (V)
TEMPERATURE (°C)
–50
–1.0
CHANGE FROM 25°C (%)
–0.6
–0.2
0.2
–25 025 50
37851 G08
75
0.6
1.0
–0.8
–0.4
0
0.4
0.8
100
RT (kΩ)
20
0
OSCILLATOR FREQUENCY (kHz)
200
400
600
800
1000
1200
40 60 80 100
37851 G09
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–50
2.465
VIN START-UP VOLTAGE (V)
2.470
2.475
2.480
2.485
2.490
–25 02550
37851 G10
75 100
TEMPERATURE (°C)
–50
VIN CURRENT (mA)
–25 025 50
37851 G11
75
80
85
100
90
95
100
TEMPERATURE (°C)
–50
–8
THRESHOLD (%)
–4
0
4
–25 025 50
37851 G12
75
8
–6
–2
2
6
100
OV THRESHOLD
UV THRESHOLD
VIN Start-Up Voltage
vs Temperature
VIN Burst Quiescent Current
vs Temperature
OV and UV Thresholds
vs Temperature
VFB vs Temperature
Normalized Oscillator Frequency
vs Temperature Oscillator Frequency vs RT
PIN FUNCTIONS
RUN/SS (Pin 1): Run Control and Soft-Start Input. An
internal 1μA charges the soft-start capacitor and will
charge to approximately 2.5V. During a current limit fault,
the soft-start capacitor will incrementally discharge. Once
the pin drops below 1.225V the IC will enter fault mode,
turning off the outputs for 32 times the soft-start time. If
>5μA (at RUN/SS = 1.225V) is applied externally, the part
will latch off after a fault is detected. If >40μA (at RUN/SS
= 1.225V) is applied externally, current limit faults will not
discharge the SS capacitor.
VC (Pin 2): Error Amp Output. A frequency compensation
network is connected from this pin to the FB pin to compen-
sate the loop. See the section Closing the Feedback Loop
in the Applications Information section for guidelines.
FB (Pin 3): Feedback Pin. Connect resistor divider tap
here. The feedback reference voltage is typically 1.225V
The output voltage can be adjusted from 2.7V to 10V ac-
cording to the following formula:
VOUT =1.225V • R1+R2
R2
LTC3785-1
6
37851fa
PIN FUNCTIONS
VSENSE (Pin 4): Overvoltage and Undervoltage Sense.
The overvoltage threshold is internally set 7.5% above
the regulated FB voltage and the undervoltage threshold
is internally set 7.5% below the FB regulated voltage. This
pin can be tied to FB but to optimize the response time it
is recommended that a separate voltage divider from VOUT
be applied. The divider can be skewed from the feedback
value to achieve the desired UV or OV threshold.
ILSET (Pin 5): Current Limit Set. A resistor from this pin
to ground sets the current limit threshold from the ISVIN
and ISSW1 pins.
CCM (Pin 6): Continuous Conduction Mode Control Pin.
When set low, the inductor current is allowed to go slightly
negative (–15mV referenced to the ISVOUT – ISSW2 pins).
When driven high, the reverse current limit is set to the similar
value of the forward current limit set by the ILSET pin.
RT (Pin 7): Oscillator Programming Pin. A resistor from
this pin to GND sets the free-running frequency of the IC.
fOSC ≅ 2.5e10/RT.
MODE (Pin 8): Burst Mode Control Pin.
• MODE = High: Enable Burst Mode Operation. In Burst
Mode operation the operation is variable frequency,
which provides a signifi cant effi ciency improvement
at light loads. The Burst Mode operation will continue
until the pin is driven low.
• MODE = Low: Disable Burst Mode operation and maintain
low noise, constant frequency operation.
PGOOD (Pin 9): Open Drain Output. PGOOD is pulled to
ground when the voltage on VSENSE is not within ±7.5%
of its setpoint. PGOOD will also be pulled low when the
part is in shutdown or input UVLO.
ISVOUT (Pin 10): Reverse Current Limit Comparator Non-
inverting Input. This pin is normally connected to the drain
of the N-channel MOSFET D (TG2 driven).
VBST2 (Pin 11): Boosted Floating Driver Supply for Boost
Switch D. This pin will swing from a diode below VCC up
to VOUT + VCC – VDIODE.
SW2 (Pin 13): Ground Reference for Driver D. Gate drive
from TG2 will reference to the common point of output
switches C and D.
ISSW2 (Pin 14): Reverse Current Limit Comparator Invert-
ing Input. This pin is normally connected to the source of
the N-channel MOSFET D (TG2 driven).
VDRV (Pin 16): Driver Supply for Ground Referenced
Switches. Connect this pin to VCC potential.
BG1, BG2 (Pins 17, 15): Bottom gate driver pins drive
the ground referenced N-channel MOSFET switches B
and C.
ISSW1 (Pin 18): Forward Current Limit Comparator Non-
inverting Input. This pin is normally connected to the
source of the N-channel MOSFET A (TG1 driven).
SW1 (Pin 19): Ground Reference for Driver A. Gate drive
from TG1 will reference to the common point of output
switches A and B.
TG1, TG2 (Pins 20, 12): Top gate drive pins drive the
top N-channel MOSFET switches A and D with a voltage
swing equal to VCC – VDIODE superimposed on the SW1
and SW2 nodes respectively.
VBST1 (Pin 21): Boosted Floating Driver Supply for the
Buck Switch A. This pin will swing from a diode below
VCC up to VIN + VCC – VDIODE.
ISVIN (Pin 22): Forward Current Limit Comparator Invert-
ing Input. This pin is normally connected to the drain of
N-channel MOSFET A (TG1 driven).
VCC (Pin 23): Internal 4.35V LDO Regulator Output. The
driver and control circuits are powered from this voltage
to limit the maximum VGS drive voltage. Decouple this pin
to power ground with at least a 4.7μF ceramic capacitor.
For low VIN applications, VCC can be bootstrapped from
VOUT through a Schottky diode.
VIN (Pin 24): Input Supply Pin for the VCC Regulator. A
ceramic capacitor of at least 10μF is recommended close
to the VIN and GND pins.
Exposed Pad (Pin 25): The GND and PGND pins are con-
nected to the Exposed Pad which must be connected to
the PCB ground for electrical contact and rated thermal
performance.
LTC3785-1
7
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BLOCK DIAGRAM
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
2.4V
TSD 1.225V
TG1
BG1
VOUT
LOW
15mV
OR
1X ILIMIT
gm
1/25k
V = 60k/RILSET
X10
V = 90k/RILSET
UVLO
VBE
2μA
ILIM(OUT)
ILIM(OUT)
10μA MAX
1μA
RUN/SS
CSS
VSENSE
VOUT
FB
RT
MODE
1.5V
SS
ILIM COMP
IMAX COMP
VC
1.225V
RUN
VREF
–7.5%
FAULT
LOGIC
BURST
LOGIC
ILIMIT
SET
1/2 LIMIT AT VOUT < 1V
GND/PGNDPGOOD
UV
OV
SD
UVLO
1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
100% DUTY
CHARGE PUMP
100% DUTY
CHARGE PUMP
0 = 15mV
1 = ILIMIT
4.35V REG
SAMPLED
SAMPLED
PGND
1.8V
DISABLE
REVERSE
CURRENT LIMIT
(ZERO LIMIT FOR BURST)
IDEAL DIODE
BBM
SW1
DELAY
VCC
VIN
ILIMIT
VIN
2.7V TO 10V
ISVIN
VBST1
VBST2
VOUT
D1
OPT
D2
OPT
COUT
L1
TG1 MA CIN
CVCC
MB
MD
MC
CB
CASW1
SW2
SW1
SW2
BG2
VDRV
PGND
ISSW2
ISSW1
ISVOUT
VDRV
BG1
TG2
ADRV
IMAX
SW1
PULSE
SW2
PULSE
TG2
BG2
VREV
BBM
SW2
DELAY
BDRV
CCM
37851 BD
VREV
CDRV
DDRV
REVERSE
LIMIT
UV
UV
+
–
7.5%
OSC
OV
BURST
OV
1.225V
R2
R1
RT
RILSET
+
–
+
–
ILSET
+
–
VOUT
CP1
23
22
20
21
19
18
16
17
10
12
11
13
14
15
6
25
9
5
8
7
2
3
4
1
24
LTC3785-1
8
37851fa
the off time of switch A, synchronous switch B turns on for
the remainder of the switching period. Switches A and B will
alternate similar to a typical synchronous buck regulator.
As the control voltage increases, the duty cycle of switch
A increases until the max duty cycle of the converter in
buck mode reaches DMAX_BUCK, given by:
D
MAX_BUCK = 100 – D4(SW)%
where D4(SW) = duty cycle % of the four switch range.
D4(SW) = (300ns • f) • 100%
where f = operating frequency, Hz.
Beyond this point the four switch or buck-boost region
is reached.
Buck-Boost or Four Switch (VIN ~ VOUT)
When the error amp output voltage, VC, is above ap-
proximately 0.65V, switch pair AD remain on for duty
cycle DMAX_BUCK, and the switch pair AC begin to phase
in. As switch pair AC phases in, switch pair BD phases
out accordingly. When the VC voltage reaches the edge of
the buck-boost range, approximately 0.7V, the AC switch
pair completely phase out the BD pair, and the boost phase
begins at duty cycle, D4(SW).
OPERATION
MAIN CONTROL LOOP
The LTC3785-1 is a buck-boost voltage mode controller
that provides an output voltage above, equal to or below
the input voltage.
The LTC proprietary topology and control architecture also
employs drain-to-source sensing (No RSENSE) for forward
and reverse current limiting. The controller provides
all N-channel MOSFET output switch drive, facilitating
single package multiple power switch technology along
with lower RDS(ON). The error amp output voltage (VC)
determines the output duty cycle of the switches. Since
the VC pin is a fi ltered signal, it provides rejection of high
frequency noise.
The FB pin receives the voltage feedback signal, which
is compared to the internal reference voltage by the er-
ror amplifi er. The top MOSFET drivers are biased from a
fl oating bootstrap capacitor, which is normally recharged
during each off cycle through an external diode when the
top MOSFET turns off. Optional Schottky diodes can be
connected across synchronous switch B and D to provide
a lower drop during the dead time and eliminate effi ciency
loss due to body diode reverse recovery.
The main control loop is shut down by pulling the RUN/
SS pin low. An internal 1μA current source charges the
RUN/SS pin and when the pin voltage is higher than 0.7V
the IC is enabled. The VC voltage is then clamped to the
RUN/SS voltage minus 0.7V while CSS is slowly charged
during start-up. This soft-start clamping prevents inrush
current draw from the input power supply.
POWER SWITCH CONTROL
Figure 1 shows a simplifi ed diagram of how the four power
switches are connected to the inductor, VIN, VOUT and GND.
Figure 2 shows the regions of operation for the LTC3785-1
as a function of duty cycle D. The power switches are
properly controlled so that the transfer between modes
is continuous.
Buck Region (VIN > VOUT)
Switch D is always on and switch C is always off during
buck mode. When the error amp output voltage, VC, is
approximately above 0.1V, output A begins to switch. During
Figure 1. Response Time Test Circuit
SW2
BG1 C
37851 F01
SW1
B BG2
L
VOUT
VIN
TG1 D
A TG2
Figure 1. Response Time Test Circuit
BOOST REGION
BUCK/BOOST REGIONFOUR SWITCH PWM
90%
DMAX
BOOST
DMIN
BOOST
A ON, B OFF
PWM C, D SWITCHES
BUCK REGION
DMIN
BUCK 37851 F02
DMAX
BUCK
D ON, C OFF
PWM A, B SWITCHES
LTC3785-1
9
37851fa
OPERATION
The input voltage, VIN, where the four switch region begins
is given by:
VIN =VOUT
1– 300ns • f
()
V
the point at which the four switch region ends is given
by:
V
IN = VOUT(1 – D) = VOUT(1 – 300ns • f) V
Boost Region (VIN < VOUT)
Switch A is always on and switch B is always off during
boost mode. When the error amp output voltage, VC, is ap-
proximately above 0.7V, switch pair C and D will alternately
switch to provide a boosted output voltage. This operation
is typical to a synchronous boost regulator. The maximum
duty cycle of the converter is limited to 90% typical.
Burst Mode OPERATION
During Burst Mode operation, the LTC3785-1 delivers
energy to the output until it is regulated and then goes
into a sleep state where the outputs are off and the IC
is consuming only 86μA. In Burst Mode operation, the
output ripple has a variable frequency component, which
is dependent upon load current
During the period where the converter is delivering en-
ergy to the output, the inductor will reach a peak current
determined by an on time, tON, and will terminate at zero
current for each cycle. The on time is given by:
tON =2.4
VIN •f
where f is the oscillator frequency.
The peak current is given by:
IPEAK =VIN
L•t
ON
IPEAK =2.4
f•L
So the peak current is independent of VIN and inversely
proportional to the f • L product optimizing the energy
transfer for various applications.
In Burst Mode operation the maximum output current is
given by:
IOUT(MAX,BURST) ≈1.2 • VIN
f•L• V
OUT +VIN
()
A
Burst Mode operation is user-controlled by driving the
MODE pin high to enable and low to disable.
VCC REGULATOR
An internal P-channel low dropout regulator produces
4.35V at the VCC pin from the VIN supply pin. VCC powers
the drivers and internal circuitry of the LTC3785-1. The
VCC pin regulator can supply a peak current of 100mA and
must be bypassed to ground with a minimum of 4.7μF
placed directly adjacent to the VCC and GND pins. Good
bypassing is necessary to supply the high transient cur-
rent required by the MOSFET gate drivers and to prevent
interaction between channels. If desired, the VCC regulator
can be connected to VOUT through a Schottky diode to
provide higher gate drive in low input voltage applications.
The VCC regulator can also be driven with an external 5V
source directly (without a Schottky diode).
TOPSIDE MOSFET DRIVER SUPPLY (VBST1, VBST2)
The external bootstrap capacitors connected to the VBST1
and VBST2 pins supply the gate drive voltage for the top-
side MOSFET switches A and D. When the top MOSFET
switch A turns on, the switch node SW1 rises to VIN and
the VBST2 pin rises to approximately VIN + VCC. When the
bottom MOSFET switch B turns on, the switch node SW1
drops low and the boost capacitor is charged through the
diode connected to VCC. When the top MOSFET switch D
turns on, the switch node SW2 rises to VOUT and the VBST2
pin rises to approximately VOUT + VCC. When the bottom
MOSFET switch C turns on, the switch node SW2 drops
low and the boost capacitor is charged through the diode
connected to VCC. The boost capacitors need to store about
100 times the gate charge required by the top MOSFET
switch A and D. In most applications a 0.1μF to 0.47μF,
X5R or X7R dielectric capacitor is adequate.
LTC3785-1
10
37851fa
OPERATION
RUN/SOFT-START (RUN/SS)
The RUN/SS pin serves as the enable to the LTC3785-1,
soft-start function, and fault programming. A 1μA current
source charges the external capacitor. Once the RUN/SS
voltage is above a diode drop(~0.7V) the IC is enabled. Once
the IC is enabled, the RUN/SS voltage minus a diode drop
(RUN/SS – 0.7V) clamps the output of the error amp (VC)
to limit duty cycle. The range of the duty cycle clamping is
approximately 0.7V to 1.7V. The RUN/SS pin is clamped
to approximately 2.2V. If current limit is reached the pin
will begin to discharge with a current determined by the
magnitude of inductor current overcurrent limit, but not
to exceed 10μA. This function will be described in more
detail in the Forward Current Limit section.
OSCILLATOR
The frequency of operation is set through a resistor from
the RT pin to ground where f ≅ (2.5e10/RT)Hz.
ERROR AMP
The error amplifi er is a voltage mode amplifi er with a
reference voltage of 1.225V internally connected to the
non-inverting input. The loop compensation components
are confi gured around the amplifi er to provide loop com-
pensation for the converter. The RUN/SS pin will clamp the
error amp output, VC, to provide a soft-start function.
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
The LTC3785-1 incorporates overvoltage (OV) and
undervoltage (UV) functions for fault protection and
transient limitation. Both comparators are connected
to the VSENSE pin, which usually has a similar voltage
divider as the error amplifi er without the compensation.
The overvoltage threshold is 7.5% above the reference.
The undervoltage threshold is 7.5% below the reference
with both comparators having 1.5% hysteresis. During
an overvoltage fault, all output switching stops until the
fault ceases. During an undervoltage fault, the IC is com-
manded to run fi xed frequency only (disabled Burst Mode
operation). If the design requires a tightened threshold to
one of the comparator thresholds the voltage divider on
the VSENSE pin can be skewed to achieve the threshold.
Since the range is a constant, tightening the UV threshold
will loosen the OV threshold and vice versa.
POWER GOOD COMPARATOR
The PGOOD pin is an open-drain output which indicates
the status of the buck-boost converter output. The output
voltage is monitored at VSENSE via a resistor divider tap
from VOUT to GND. The values used for this resistor divider
are typically selected to be the same as those used in the
error amplifi er feedback divider. If the voltage on VSENSE
either falls 7.5% below (UV condition) or rises 7.5%
above (OV condition) the regulation voltage, the PGOOD
open-drain output will pull low signaling the output is
out of regulation. Once an out of regulation condition is
triggered, the voltage on VSENSE must rise 1.5% above
the UV threshold or fall 2% below the OV threshold before
the pull-down will turn off. In addition, there is a 15μs
deglitch delay to help prevent false trips due to voltage
transients caused by line or load steps. Depending upon
the application, this delay may be insuffi cient. A capaci-
tor can be placed from VSENSE to GND to add additional
deglitch fi ltering, ensuring PGOOD doesn’t trip during
a transient. The PGOOD output will also pull low during
shutdown and input undervoltage lockout to indicate these
fault conditions.
FORWARD CURRENT LIMIT
The LTC3785-1 is designed to sense the input current by
sampling the voltage across MOSFET A during the on time of
the switch (TG1 = High). The sense pins are ISVIN and ISSW1.
A current sense resistor can be used if increased accuracy
is required. The current limit threshold can be programmed
with a resistor on the ILSET pin. Once the desired current
limit has been chosen, RILSET can be determined by the
following formula:
RILSET =6000
RDS(ON)A •ILIMIT
Ω
where RDS(ON)A = RDS(ON) of N-channel MOSFET switch A
and ILIMIT = current limit in Amps.
Once the voltage between ISVIN and ISSW1 exceeds the
threshold, current will be sourced out of FB to take control
LTC3785-1
11
37851fa
OPERATION
of the voltage loop, resulting in a lower output voltage
to regulate the input current. This fault condition causes
the RUN/SS capacitor to begin discharging. The level of
the discharge current depends on how much the current
exceeds the programmed threshold. Figure 3 is a simpli-
fi ed diagram of the current sense and fault circuitry. If the
current limit fault duration is long enough to discharge the
RUN/SS capacitor below 1.225V, the fault latch is set and
will cycle the RUN/SS capacitor 16 times (1μA charging
and 1μA discharging of the RUN/SS capacitor) to create an
off time of 32 times the soft-start time before the outputs
are allowed to switch to restart the output voltage. If the
current limit fault level exceeds 150% of the programmed
ILIMIT level at any time, the IMAX comparator is tripped and
output switches B and D are turned on to discharge the
inductor current for the remainder of the cycle.
To have the power converter latch off on a fault, a pull-up
current between 4μA and 7μA on the RUN/SS pin will allow
the RUN/SS capacitor to discharge during an extended
fault, but will prevent cycling of the fault which will cause the
converter to stay off. One method to implement this is by
placing a diode (anode tied to VOUT) and a resistor from VOUT
to the RUN/SS pin. The current sourced into RUN/SS will be
VOUT – 0.7 divided by the resistor value. To ignore all faults
source greater than 40μA into the RUN/SS pin (At 1.225V on
the RUN/SS pin). Since the maximum fault current is limited,
this will prevent any discharging of the RUN/SS capacitor,
the soft-start capacitor will need to be sized accordingly to
accommodate the extra charging current at start-up.
During an output short-circuit or if VOUT is less than 1.8V, the
current limit folds back to 50% of the programmed level.
REVERSE CURRENT LIMIT
The LTC3785-1 can be programmed to provide full class D
operation or allowed to source and sink current equal to
the current limit set value. This is achieved by asserting a
high level on the CCM pin. To minimize the reverse output
current, the CCM pin should be driven low or strapped to
ground. During this mode only, –15mV typical is allowed
across output switch D and is sensed with the ISVOUT and
ISSW2 pins.
+
–
+
–
+
–
+
–
+
–
+
–gm
gm = 1/20k
ILIMIT COMP
IMAX COMP
TURN
SWITCHES
B AND D ON
V = 60k/RILSET
(15k/RILSET WHEN VOUT < 1.8V)
X10
V = 90k/RILSET
0.7V
2μA
2.2V
CSS
1/3 • ILIM(OUT)
10μA MAX
ILIM(OUT)
30μA MAX
1μA
RUN/SS
VOUT
FB
R1
R2
ILIM COMP
IMAX COMP
VC
CP1
1.225V
THERMAL SD
RUN
FAULT
LOGIC
ILIMIT
SET
SAMPLED
SAMPLED
REVERSE
CURRENT LIMIT
CCM = HIGH = 6k/RILSET
CCM = LOW = 15mV
ISVIN
VIN
VOUT
COUT
L1
TG1
SW1
SW2
A
B
D
C
ISSW2
ISSW1
CCM
ISVOUT
+–
TG2
37851 F03
SWITCH D
OFF
1.225V ERROR AMP
+
–
ILSET
RILSET
BG1
BG2
S
S
1
4
3
2
5
15
14
13
12
10
6
17
18
19
20
22
Figure 3. Block Diagram of Current Limit Fault Circuitry
LTC3785-1
12
37851fa
INDUCTOR SELECTION
The high frequency operation of the LTC3785-1 allows
the use of small surface mount inductors. The inductor
current ripple is typically set 20% to 40% of the maximum
inductor current. For a given ripple the inductance terms
are given as follows:
L>VIN(MIN)2•V
OUT –V
IN(MIN)
()
• 100
f•I
OUT(MAX) • %Ripple • VOUT2, (Boost Mode)
L>VOUT •V
IN(MAX) –V
OUT
()
• 100
f•I
OUT(MAX) • %Ripple • VIN(MAX)
, (Buck Mode)
where:
f = Operating frequency, Hz
%Ripple = Allowable inductor current ripple, %
VIN(MIN) = Minimum input voltage (limit to VOUT/2
minimum for worst-case), V
VIN(MAX) = Maximum input voltage, V
VOUT = Output voltage, V
IOUT(MAX) = Maximum output load current, A
For high effi ciency choose an inductor with a high frequency
core material, such as ferrite, to reduce core loses. The
inductor should have low ESR (equivalent series resistance)
to reduce the I2R losses, and must be able to handle the
peak inductor current without saturating. Molded chokes
or chip inductors usually do not have enough core to sup-
port the peak inductor currents in the 3A to 6A region. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
CIN AND COUT SELECTION
In boost mode, input current is continuous. In buck mode,
input current is discontinuous. In buck mode, the selection
of input capacitor, CIN, is driven by the need to fi lter the
input square wave current. Use a low ESR capacitor, sized
to handle the maximum RMS current. For buck operation,
the maximum RMS capacitor current is given by:
IRMS ~IOUT(MAX) •VOUT
VIN
•1–
VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
APPLICATIONS INFORMATION
This formula has a maximum at VIN = 2VOUT, where IRMS =
IOUT(MAX)/2. This simple worst-case condition is commonly
used for design because even signifi cant deviations do not
offer much relief. Note that ripple current ratings from ca-
pacitor manufacturers are often based on only 2000 hours
of life which makes it advisable to derate the capacitor.
In boost mode, the discontinuous current shifts from the
input to the output, so COUT must be capable of reducing
the output voltage ripple. The effects of ESR (equivalent
series resistance) and the bulk capacitance must be
considered when choosing the right capacitor for a given
output ripple voltage. The steady ripple due to charging
and discharging the bulk capacitance is given by:
VRIPPLE _BOOST =IOUT(MAX) •V
OUT –V
IN(MIN)
()
COUT •V
OUT •f
VRIPPLE _BUCK =VOUT •V
IN(MAX) –V
OUT
()
8•L•C
OUT •V
IN(MAX) •f
2
where COUT= output fi lter capacitor, F
The steady ripple due to the voltage drop across the ESR
is given by:
ΔVBOOST,ESR = IL(MAX,BOOST) • ESR
ΔVBUCK,ESR =VIN(MAX) –V
OUT
()
•V
OUT
L•f•V
IN
•ESR
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coeffi cient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
POWER N-CHANNEL MOSFET SELECTION AND
EFFICIENCY CONSIDERATIONS
The LTC3785-1 requires four external N-channel power
MOSFETs, two for the top switches (switches A and D,
shown in Figure 1) and two for the bottom switches
LTC3785-1
13
37851fa
(switches B and C shown in Figure 1). Important param-
eters for the power MOSFETs are the breakdown voltage
VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON),
reverse transfer capacitance CRSS and maximum current
IDS(MAX). The drive voltage is set by the 4.35V VCC supply.
Consequently, logic-level threshold MOSFETs must be used
in LTC3785-1 applications. If the input voltage is expected
to drop below 5V, then sub-logic threshold MOSFETs should
be considered. In order to select the power MOSFETs, the
power dissipated by the device must be known.
For switch A, the maximum power dissipation happens
in boost mode, when it remains on all the time. Its maxi-
mum power dissipation at maximum output current is
given by:
PA(BOOST) =VOUT
VIN
•IOUT(MAX)
⎛
⎝
⎜⎞
⎠
⎟
2
•ρT•R
DS(ON)
where ρT is a normalization factor (unity at 25°C) ac-
counting for the signifi cant variation in on-resistance with
temperature, typically about 0.4%/°C as shown in Figure 4.
For a maximum junction temperature of 125°C, using a
value ρT = 1.5 is reasonable.
Switch B operates in buck mode as the synchronous
rectifi er. Its power dissipation at maximum output current
is given by:
PB(BUCK) =VIN –V
OUT
VIN
•IOUT(MAX)2•ρT•R
DS(ON)
APPLICATIONS INFORMATION
Switch C operates in boost mode as the control switch. Its
power dissipation at maximum current is given by:
PC(BOOST) =VOUT –V
IN
()
•V
OUT
VIN2•IOUT(MAX)2•ρT
• RDS(ON) +k•V
OUT3•IOUT(MAX)
VIN
•CRSS •f
where CRSS is usually specifi ed by the MOSFET manufactur-
ers. The constant k, which accounts for the loss caused by
reverse recovery current, is inversely proportional to the
gate drive current and has an empirical value of 1.0.
For switch D, the maximum power dissipation happens in
boost mode when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
PD BOOST
()
=VOUT
VIN
•IOUT(MAX)2•ρT•R
DS(ON)
Typically, switch A has the highest power dissipation and
switch B has the lowest power dissipation unless a short
occurs at the output. From a known power dissipated
in the power MOSFET, its junction temperature can be
obtained using the following formula:
T
J = TA + P • RTH(JA)
The RTH(JA) to be used in the equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(CA)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
SCHOTTKY DIODE (D1, D2) SELECTION
Optional Schottky diodes D1 and D2 shown in the Block
Diagram conduct during the dead time between the conduc-
tion of the power MOSFET switches. They are intended to
prevent the body diode of synchronous switches B and D
from turning on and storing charge during the dead time.
In particular, D2 signifi cantly reduces reverse recovery
current between switch D turn off and switch C turn on,
which improves converter effi ciency and reduces switch C
voltage stress. In order for D2 to be effective,
it must be
located in very close proximity to SWD.
JUNCTION TEMPERATURE (°C)
–50
RT NORMALIZED ON-RESISTANCE
1.0
1.5
150
37851 F04
0.5
0050 100
2.0
Figure 4. Normalized RDS(ON) vs Temperature
LTC3785-1
14
37851fa
CLOSING THE FEEDBACK LOOP
The LTC3785-1 incorporates voltage mode control. The
control to output gain is given by:
GBuck =1.6 • VIN, Buck Mode
GBOOST =1.6 • VOUT2
VIN
, Boost Mode
The output fi lter exhibits a double-pole response and is
given by:
fFILTER_POLE=1
2•π•L•C
OUT
where COUT is the output fi lter capacitor.
The output fi lter zero is given by:
fFILTER _ ZERO=1
2•π•RESR •C
OUT
where RESR is the capacitor equivalent series resistance.
A troublesome feature in boost mode is the right half plane
zero (RHP), and is given by:
fRHPZ =VIN2
2•π•IOUT •L•V
OUT
The loop gain is typically rolled off before the RHP zero
frequency.
APPLICATIONS INFORMATION
A simple type I compensation network (Figure 5) can be
incorporated to stabilize the loop but at a cost of reduced
bandwidth and slower transient response. To ensure proper
phase margin, the loop must cross over almost a decade
before the L-C double pole.
The unity gain frequency of the error amplifi er with the
type 1 compensation is given by:
fUG=1
2•π•R1•CP1
Most applications demand an improved transient response
to allow a smaller output fi lter capacitor. To achieve a higher
bandwidth, type III compensation is required as shown
in Figure 6. Two zeros are required to compensate for the
double pole response.
fPOLE1≈1
2•π•32e3•CP1•R1
(a very low frequency)
fZERO1=1
2•π•RZ•CP1
fZERO2 =1
2•π•R1•CZ1
fPOLE2≈1
2•π•RZ•CP2
–
+
FB
ERROR
AMP
1.225V
37851 F05
R1
R2
VC
VOUT
CP1
Figure 5. Error Amplifi er with Type I Compensation
–
+
FB
ERROR
AMP
1.225V
37851 F06
R1 CZ1
R2
VCRZ
VOUT
CP1
CP2
Figure 6. Error Amplifi er with Type III Compensation
LTC3785-1
15
37851fa
EFFICIENCY CONSIDERATIONS
The percentage effi ciency of a switching regulator is equal
to the output power divided by the input power times
100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LTC3785-1 application
circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, sensing resistor (if used), inductor and PC
board traces and cause the effi ciency to drop at high
output currents.
2. Transition loss. This loss arises from the brief voltage
transition time of switch A or switch C. It depends upon
the switch voltage, inductor current, driver strength and
MOSFET capacitance, among other factors.
Transition Loss ~ VSW2 • IL • CRSS • f
where CRSS is the reverse transfer capacitance.
3. CIN and COUT loss. The input capacitor has the diffi cult
job of fi ltering the large RMS input current to the regula-
tor in buck mode. The output capacitor has the more
diffi cult job of fi ltering the large RMS output current in
boost mode. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and suffi cient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
4. Other losses. Optional Schottky diodes D1 and D2 are
responsible for conduction losses during dead time
and light load conduction periods. Core loss is the
predominant inductor loss at light loads. Turning on
switch C causes reverse recovery current loss in boost
mode. When making adjustments to improve effi ciency,
the input current is the best indicator of changes in
effi ciency. If you make a change and the input current
decreases, then the effi ciency has increased. If there
is no change in input current, then there is no change
in effi ciency.
APPLICATIONS INFORMATION
5. VCC regulator loss. In applications where the input
voltage is above 5V, such as two Li-Ion cells, the VCC
regulator will dissipate some power due the differential
voltage and the average output current to the drive the
gates of the output switches. The VCC pin can be driven
directly from a high effi ciency external 5V source if
desired to incrementally improve overall effi ciency at
lighter loads.
DESIGN EXAMPLE
As a design example, assume VIN = 2.7V to 10V (3.6V
nominal Li-Ion with 9V adapter), VOUT = 3.3V (5%),
IOUT(MAX) = 3A and f = 500kHz.
Determine the Inductor Value
Setting the Inductor Ripple to 40% and using the equations
in the Inductor Selection section gives:
L>2.7
()
2• 3.3 – 2.7
()
• 100
500 • 103• 3 • 40 • 3.3
()
2=0.67µH
L>3.3 • 10 – 3.3
()
• 100
500 • 103•3•40•10=3.7µH
So the worst-case ripple for this application is during buck
mode so a standard inductor value of 3.3μH is chosen.
Determine the Proper Inductor Type Selection
The highest inductor current is during boost mode and
is given by:
IL(MAX _ AV) =VOUT •IOUT
VIN •η
where η = estimated effi ciency in this mode (use 80%).
IL(MAX _ AV) =3.3 • 3
2.7 • 0.8 =4.6A
LTC3785-1
16
37851fa
To limit the maximum effi ciency loss of the inductor ESR
to below 5% the equation is:
ESRL(MAX) ~VOUT •IOUT • %Loss
IL(MAX _ AV)2• 100 =24mΩ
A suitable inductor for this application could be a Coiltron-
ics CD1-3R8 which has a rating DC current of 6A and ESR
of 13mΩ.
Choose a Proper MOSFET Switch
Using the same guidelines for ESR of the inductor, one
suitable MOSFET could be the Siliconix Si7940DP which
is a dual MOSFET in a surface mount package with 25mΩ
at 2.5V and a total gate charge of 12nC.
Checking the power dissipation of each switch will ensure
reliable operation since the thermal resistance of the
package is 60°C/W.
The maximum power dissipation of switch A and C oc-
curs in boost mode. Assuming a junction temperature
of TJ = 100°C with ρ100C = 1.3, the power dissipation at
VIN = 2.7, and using the equations from the Effi ciency
Considerations section:
PA(BOOST) =3.3
2.7 •3
⎛
⎝
⎜⎞
⎠
⎟
2
• 1.3 • 0.025 =0.43W
PC(BOOST) =3.3 – 2.7
()
• 3.3
2.72•3
2• 1.3 • 0.025
+ 1• 3.33•3
2.7 • 0.45 – 9 • 500 • 103
=0.09W
The maximum power dissipation of switch B and D occurs
in buck mode and is given by:
PB(BUCK) =10 – 3.3
10 •3
2• 1.3 • 0.025 =0.20W
PD(BOOST) =3.3
10 •3
2• 1.3 • 0.025 =0.10W
APPLICATIONS INFORMATION
Now to double check the TJ of the package with 50°C
ambient. Since this is a dual NMOS package we can add
switches A + B and C + D worst-case. For applications
where the MOSFETs are in separate packages each device’s
maximum TJ would have to be calculated.
T
J(PKG1) = TA + θJA(PA + PB)
= 50 + 60 • (0.43 + 0.20) = 88°C
T
J(PKG2) = TA + θJA(PC + PD)
= 50 + 60 • (0.09 + 0.10) = 60°C
Set The Maximum Current Limit
The equation for setting the maximum current limit of the
IC is given by:
RILSET =6000
RDS(ON)A •ILIMIT
Ω
The maximum current is set 25% above IL(PEAK) to account
for worst-case variation at 100°C = 6A.
RILSET =6000
0.025 • 6 =42k
Choose the Input and Output Capacitance
The input capacitance should fi lter current ripple which is
worst-case in buck mode. Since the input current could
reach 6A, a capacitor ESR of 10mΩ or less will yield an
input ripple of 60mV.
The output capacitance should fi lter current ripple which
is worst in boost mode, but is usually dictated by the loop
response, the maximum load transient and the allowable
transient response.
LTC3785-1
17
37851fa
PC BOARD LAYOUT CHECKLIST
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN, switch A, switch B and D1 in one compact
area. Place COUT, switch C, switch D and D2 in one
compact area.
• Use immediate vias to connect the components (includ-
ing the LTC3785-1’s GND/PGND pin) to the ground plane.
Use several large vias for each power component.
• Use planes for VIN and VOUT to maintain good voltage
fi ltering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(VIN or GND). When laying out the printed circuit board,
the following checklist should be used to ensure proper
operation of the LTC3785-1.
• Segregate the signal and power grounds. All small-signal
components should return to the GND pin at one point.
The sources of switch B and switch C should also con-
nect to one point at the GND of the IC.
• Place switch B and switch C as close to the controller
as possible, keeping the PGND, BG and SW traces
short.
• Keep the high dV/dT SW1, SW2, VBST1, VBST2, TG1 and
TG2 nodes away from sensitive small-signal nodes.
APPLICATIONS INFORMATION
• The path formed by switch A, switch B, D1 and the CIN
capacitor should have short leads and PC trace lengths.
The path formed by switch C, switch D, D2 and the
COUT capacitor also should have short leads and PC
trace lengths.
•
The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor.
• Connect the VCC decoupling capacitor CVCC closely to
the VCC and PGND pins.
• Connect the top driver boost capacitor CA closely to
the VBST1 and SW1 pins. Connect the top driver boost
capacitor CB closely to the VBST2 and SW2 pins.
• Connect the input capacitors CIN and output capaci-
tors COUT close to the power MOSFETs. These capaci-
tors carry the MOSFET AC current in boost and buck
mode.
• Connect FB and VSENSE pin resistive dividers to the (+)
terminals of COUT and signal ground. If a small VSENSE
decoupling capacitor is used, it should be as close as
possible to the LTC3785-1 GND pin.
• Route ISVIN and ISSW1 leads together with minimum
PC trace spacing. Ensure accurate current sensing
with Kelvin connections across MOSFET A or sense
resistor.
• Route ISVOUT and ISSW2 leads together with minimum
PC trace spacing. Ensure accurate current sensing
with Kelvin connections across MOSFET D or sense
resistor.
• Connect the feedback network close to IC, between the
VC and FB pins.
LTC3785-1
18
37851fa
TYPICAL APPLICATION
VCC
ISVIN
TG1VSENSE
BG1FB
VC
TG2
BG2
SW2
37851 TA02
VBST1
SW1
ISSW1
ISVOUT
RT
VDRV
ISSW2
VBST2
CCM
ILSET
MODE
RUN/SS
VIN
1nF
1nF
205k
270pF
1.3k
R1
205k
12k
R2
124k
RT
59k
PGOOD
VOUT
100k
RILSET
42.2k
124k
LTC3785-1
GND
CVCC
4.7μF Li-Ion
2.7V TO 4.2V
MA = MB = MC = MD = 1/2 Si7940DY
L1 = WÜRTH ELECTRONICS 744311470
D1 = D2 = PMEG2020EJ
9V REGULATED
WALL ADAPTER
VIN
2.7V TO 10V
VOUT
3.3V
3A
CIN
22μF
MA
MB D1
D2
OPTIONAL
OPTIONAL
MD
MC
CA
0.22μF
CB
0.22μF
CMDSH-3
CMDSH-3
L1
4.7μH
COUT
100μF
+
LTC3785-1
19
37851fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
LTC3785-1
20
37851fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0409 REV A • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
Li-Ion/9V Wall Adapter to 5V/2A
VCC
ISVIN
TG1VSENSE
BG1FB
VC
TG2
BG2
SW2
37851 TA03
VBST1
SW1
ISSW1
ISVOUT
RT
VDRV
ISSW2
VBST2
CCM
ILSET
MODE
RUN/SS
VIN
1nF
1nF
205k
270pF
1.3k205k
12k
59k
66.5k
42.2k
66.5k
LTC3785-1
GND
CVCC
4.7μF Li-Ion
2.7V TO 4.2V
MA = MB = MC = MD = 1/2 Si7940DY
L1 = RLF7030T-3R3M4R1
D1 = D2 = PMEG2020EJ
9V REGULATED
WALL ADAPTER
VIN
2.7V TO 10V
VOUT
5V
2A
CIN
22μF
MA
MB D1
D2
OPTIONAL
OPTIONAL
MD
MC
CA
0.22μF
CB
0.22μF
CMDSH-3
CMDSH-3
L1
3.3μH
COUT
100μF
+
PGOOD
VOUT
100k
PART NUMBER DESCRIPTION COMMENTS
LTC3443 1.2A IOUT, 600kHz, Synchronous Buck-Boost DC/DC Converter VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 28μA, ISD < 1μA,
MS Package
LTC3444 500mA IOUT, 1.5MHz Synchronous Buck-Boost DC/DC Converter VIN: 2.7V to 5.5V, VOUT: 0.5V to 5.25V, Optimized for WCDMA RF
Amplifi er Bias
LTC3531/
LTC3531-3/
LTC3531-3.3
200mA IOUT, Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 2V to 5V, IQ = 35μA, ISD < 1μA,
MS, DFN Packages
LTC3532 500mA IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 35μA, ISD < 1μA,
MS, DFN Packages
LTC3533 2A Wide Input Voltage Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40μA, ISD < 1μA,
DFN Package
LTC3780 High Effi ciency, Synchronous, 4-Switch Buck-Boost Controller VIN: 4V to 36V, VOUT: 0.8V to 30V, IQ = 1.5mA, ISD < 55μA,
SSOP-24, QFN-32 Packages
LTC3785 10V, High Effi ciency, Synchronous, No RSENSE, Buck-Boost
Controller VIN: 2.7V to 10V, VOUT: 2.7V to 10V, IQ = 86mA, ISD < 15μA,
QFN-24 Package
LTM4605 5A to 12A Buck-Boost μModule 4.5V ≤ VIN ≤ 20V, 0.8V ≤ VOUT ≤ 16V, 15mm × 15mm × 2.8mm
LGA Package
LTM4607 5A to 12A Buck-Boost μModule 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 24V, 15mm × 15mm × 2.8mm
LGA Package
