CS5467-ISZ - Cirrus Logic Inc.

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CS5467

Four-channel Power/Energy IC

Features & Description

• Energy Linearity: ±0.1% of Reading over 1000:1

Dynamic Range

• On-chip Functions:

-Voltage and Current Measurement

-Active, Reactive, and Apparent Power/Energy

-RMS Voltage and Current Calculations

-Current Fault and Voltage Sag Detection

-Calibration

-Phase Compensation

-Temperat ur e Sen s o r

-Energy Pulse Outputs

• Meets Accuracy Spec for IEC, ANSI, & JIS

• Low Power Consumption

• Voltage Tamper Correction

• Ground-referenced Inputs with Single Supply

• On-chip 2.5 V Reference (40 ppm / °C typ.)

• Power Supply Monitor Function

• Three-wire Serial Interface to Microcontroller or

E2PROM

• Power Supply Configurations

GND: 0 V, VA+: +5 V, VD+: +3.3 V to +5 V

Description

The CS5467 is a watt-hour meter on a chip. It

measures line voltage and current and calcu-

lates active, reactive, apparent power, energy,

power factor, and RMS voltage an d current.

An internal RMS voltage reference can be used

if voltage measurement is disabled by

tampering.

Four  analog-to-digital converters are used to

measure two voltages and two currents. Option-

ally, voltage2 channel can be used for

temperature measure ment.

The CS5467 is design ed to interfac e to a varie t y

of voltage and current sensors.

Additional features include system-level calibra-

tion, voltage sag and current fault detection,

peak detection, phase compensation, and ener-

gy pulse outputs.

ORDERING INFORMATION

See Page 45.

VA+ VD+

IIN1+

IIN1-

VIN2+

VIN2-

VREFIN

VREFOUT

AGND XIN XOUT CPUCLK DGND

SDO

SDI

SCLK

INT

Voltage

Reference

System

Clock /K Clock

Generator

Serial

Interface

E-to-F

Power

Monitor

PFMON

RESET

Digital

Filter Calibration

MODE

Power

Calculation

Engine

4th Order 

Modulator

2nd Order 

Modulator

Temperature

Sensor

Digital

Filter

PGA

HPF

Option

HPF

Option

x10

IIN2+

IIN2- 4th Order 

Modulator Digital

Filter

PGA HPF

Option

VIN1+

VIIN1- Digital

Filter

2nd Order 

Modulator HPF

Option

x10

JAN ‘11

DS714F3

CS5467

2DS714F3

TABLE OF CONTENTS

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Control Pins and Serial Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Analog Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Analog Inputs (All Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Analog Inputs (Current Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Analog Inputs (Voltage Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Master Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

SDI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

SDO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

E2PROM mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

E1, E2, and E3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Signal Path Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 DC Offset and Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.6 Low-Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.7 RMS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.8 Power and Energy Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.9 Peak Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.10 Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.1 Voltage1 & Voltage2 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.2 Current1 & Current2 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.3 Power Fail Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CS5467

DS714F3 3

5.1.4 Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.5 Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.6 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.1 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.2 CPU Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.3 Interrupt Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.4 Energy Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.5 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6. Setting Up the CS5467 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 CPU Clock Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 Interrupt Pin Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4 Current Input Gain Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.5 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.6 Cycle Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.7 Energy Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.8 No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.9 Energy Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.10 Energy Pulse Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.11 Voltage Sag/Current Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.12 Epsilon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.13 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7. Using the CS5467 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 Voltage Tamper Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.5 Register Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.1 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.2 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.3 Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.4 Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.5 Page 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.1.1 DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.1.2 AC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.1.2.1 AC Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.1.2.2 DC Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

CS5467

4DS714F3

9.1.3 Calibration Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.1.4 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.1.4.1 Temperature Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . 41

9.1.4.2 Temperature Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . 41

10. E2PROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.1 E2PROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.2 E2PROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.3 Which E2PROMs Can Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

14. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 45

15. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

LIST OF FIGURES

Figure 1. CS5467 Read and Write Timing Diagrams ................................................................. 12

Figure 2. Timing Diagram for E1, E2, and E3.............................................................................. 13

Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements ............................................................ 14

Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements ............................................................ 14

Figure 5. Low-rate Calculations.................................................................................................. 16

Figure 6. Two-channel Power Summation.................................................................................. 16

Figure 7. Oscillator Connections................................................................................................. 18

Figure 8. Sag and Fault Detect................................................................................................... 22

Figure 9. Fixed RMS Voltage Selection...................................................................................... 23

Figure 10. Calibration Data Flow................................................................................................40

Figure 11. System Calibration of Offset...................................................................................... 40

Figure 12. System Calibration of Gain........................................................................................ 41

Figure 13. Typical Interface of E2PROM to CS5467 .................................................................. 42

Figure 14. Typical Connection Diagram ..................................................................................... 43

LIST OF TABLES

Table 1. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 2. Current Input Gain Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 3. High-pass Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4. E2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. E3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. E1 / E2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. E3 Pin with E1MODE enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

CS5467

DS714F3 5

1. OVERVIEW

The CS5467 is a CMOS power me asurement integrate d circuit utilizing four  a nalog-to-digital convert-

ers to measure two line voltages and two currents. Optionally, voltage2 channel can be used for temper-

ature measurement. It calculates active, reactive, and apparent power as well as RMS and peak voltage

and current. It handles othe r system-related functions, such as pulse output conve rsion, voltage sag, cur-

rent fault, voltage zero crossing, line frequency, and voltage tamper correction.

The CS5467 is optimized to interface to current transformers or shunt resistors for cu rrent measurement,

and to resistive dividers or voltage transformers for voltage measurement. Two full-scale ranges are pro-

vided on the current inputs to acco mmodate both types of current sensors. The CS5467’s fo ur differential

inputs have a common-mode input range from analog ground (AGND) to the positive analog supply

(VA+).

An additional analog input (PFMON) is provided to allow the application to determine when a power failure

is in progress. By monitoring the unregulated power supply, the application can take any required action

when a power loss occurs.

An on-chip voltage reference (nominally 2.5 volts) is generated and provided at analog output, VREFOUT.

This reference can be supplied to the chip by connecting it to the reference voltage input, VREF IN. Alter-

natively, an external voltage reference can be supplied to the reference input.

Three digital outputs (E1, E2, E3) provide a variety of output signals and, de pending on the mode select-

ed, provide energy pulses, power failure indication, or other choices.

The CS5467 includes a three-wire serial host interface to an external microcontroller or serial E2PROM.

Signals include serial data input (SDI), serial data output (SDO), serial clock (SCLK), and optionally a chip

select (CS), which allows the CS5467 to share the SDO signal with other devices. A MODE input is used

to control whether an E2PROM will be used instead of a host microcontroller.

CS5467

6DS714F3

2. PIN DESCRIPTION

Clock Generator

Crystal Out

Crystal In 1,28 XOUT, XIN — Connect to an external quartz crystal. Alternatively, an external clock can be sup-

plied to the XIN pin to provide the system clock for the device.

CPU Clock Output 2CPUCLK — Logic-level output from crystal oscillator. Can be used to clock an external CPU.

Control Pins and Serial Data I/O

Serial Clock 5SCLK — Clocks serial data from the SDI pin and to the SDO pin when CS is low. SCLK is a

Schmitt-trigger input when MODE is low and a driven output when MODE is high.

Serial Data Output 6SDO — Serial data output. Data is clocked out by SCLK.

Chip Select 7CS — An input that enables the serial interface when MODE is low and a driven output when

MODE is high.

Mode Select 8MODE — High selects external E2PROM, Low selects external microcontroller . MODE includes a

weak internal pull-down and therefore selects microcontroller mode if not connected.

Energy Output 22, 25,

26 E3, E1, E2 — Primarily active-low energy pulse outputs. These can be programmed to output

other conditions.

Reset 23 RESET — An active-low Schmitt-trigger input used to reset the chip.

Interrupt 24 INT — Active-low output, indicates that an enabled condition has occurred.

Serial Data Input 27 SDI — Serial data input. Data is clocked in by SCLK.

Analog Inputs/Outputs

Differential Voltage Inputs 9,10

13, 14 VIN1+, VIN1-, VIN2+, VIN2- — Differential analog inputs for the voltage channels.

Differential Current Inputs 20,19,

16,15 IIN1+, IIN1-, IIN2+, IIN2- — Differential analog inputs for the current channels.

Voltage Reference Output 11 VREFOUT — The on-chip voltage reference output. Nominally 2.5 V, referenced to AGND.

Voltage Reference Input 12 VREFIN — The voltage reference input. Can be connected to VREFOUT or external 2.5 V refer-

ence.

Power Supply Connections

Positive Digital Supply 3VD+ — The positive digital supply.

Digital Ground 4DGND — Digital ground.

Positive Analog Supply 18 VA+ — The positive analog supply.

Analog Ground 17 AGND — Analog ground.

Power Fail Monitor 21 PFMON — Used to monitor the unregulated power supply via a resistive divider. If the PFMON

voltage drops below its low limit, the low-supply detect (LSD) bit is set in the Status register.

VREFIN 12Voltage Reference Input VREFOUT 11Voltage Reference Output VIN1- 10Differential Voltage Input VIN1+ 9Differential Voltage Input MODE 8Mode Select CS 7Chip Sele ct SDO 6Serial Data Ouput SCLK 5Serial Clock DGND 4Digital Ground VD+ 3Positive Digital Supply CPUCLK 2CPU Clock Output XOUT 1Crystal Out

AGND17 Analog Ground

VA+18 Positive Analog Supply

IIN1-19 Differential Current Input

IIN1+20 Differential Current Input

PFMON21 Power Fail Monitor

E322 Energy Output 3

RESET23 Reset

INT24 Interrupt

E125 Energy Output 1

26 SDI27 Serial Data Input

XIN28 Crystal In

E2 Energy Output 2

VIN2- 14Differential Voltage Input VIN2+ 13Differential Voltage Input IIN2-15 Differential Current Input

IIN2+16 Differential Current Input

CS5467

DS714F3 7

3. CHARACTERISTICS & SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ANALOG CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions .

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 5 V ±5 %; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.

• DCLK = 4.096 MHz.

Notes: 1. Applies when the HPF option is enabled.

2. Applies when the line frequency is equal to the prod uct of the output word rate (OWR) and th e value of

Epsilon.

Parameter Symbol Min Typ Max Unit

Positive Digital Power Supply VD+ 3.135 5.0 5.25 V

Positive Analog Power Supply VA+ 4.75 5.0 5.25 V

Voltage Reference VREFIN - 2.5 - V

Specified Temperature Rang e TA-40 - +85 °C

Parameter Symbol Min Typ Max Unit

Accuracy

Active Power All Gain Ranges

(Note 1) Input Range 0.1% - 100% PACTIVE -±0.1- %

Reactive Power All Gain Ranges

(Note 1 and 2) Input Range 0.1% - 100% QAVG -±0.2- %

Power Factor All Gain Ranges

(Note 1 and 2) Input Range 1.0% - 100%

Input Range 0.1% - 1.0% PF -

-±0.2

±0.27 -

Current RMS All Gain Ranges

(Note 1) Input Range 1.0% - 100%

Input Range 0.1% - 1.0% IRMS -

-±0.1

±0.17 -

Voltage RMS All Gain Ranges

(Note 1) Input Range 5% - 100% VRMS -±0.1- %

Analog Inputs (All Inputs)

Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB

Common Mode + Signal -0.25 - VA+ V

Analog Inputs (Current Inputs)

Differential Input Range (Gain = 10)

[(IIN+) – (IIN-)] (Gain = 50) IIN -

-500

100 -

-mVP-P

mVP-P

Total Harmonic Distortion (Gain = 50) THD 80 94 - dB

Crosstalk from Voltage input a t Full Scale (50, 60 Hz) --115-dB

Input Capacitance IC - 27 - pF

Effective Input Impedance EII 30 - - k

Noise (Referred to Input) (Gain = 10)

(Gain = 50) NI-

-22.5

4.5 µVrms

µVrms

Offset Drift (Without the High-pass Filter) OD - 4.0 - µV/°C

Gain Error (Note 3) GE - ±0.4 %

CS5467

8DS714F3

ANALOG CHARACTERISTICS (Continued)

Notes: 3. Applies before system calibration.

4. All outputs unloaded. All inputs CMOS level.

5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV

(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The

“+” and “-” in pu t p ins o f b oth inpu t ch ann els are sh or te d to AGND. The CS5 467 is then comma nded to

continuous conversion acquisition mode, and digital ou tput data is collected for the channel under test.

The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted

into the (zero-to -peak) value of the sinusoidal vo ltage (measured in mV) tha t would need to be app lied

at the channel’s inp uts, in order to cause the same di gital sinusoidal output. This voltage is then defined

as Veq. PSRR is (in dB):

6. When the voltage level on PFMON is sagging and LSD bit = 0, this is the voltage at which LSD is set to 1.

7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on

PFMON at which the LSD bit can be permanently reset back to 0.

Parameter Symbol Min Typ Max Unit

Analog Inputs (Volt age Inputs)

Differential Input Range [(VIN+) – (VIN-)] VIN - 500 - mVP-P

Total Harmonic Distortion THD 65 75 - dB

Crosstalk from Current inputs at Full Scale (50, 60 Hz) --70-dB

Input Capacitance All Gain Ranges IC - 2.0 - pF

Effective Input Impedance EII 2 - - M

Noise (Referred to Input) NV--140µV

rms

Offset Drift (Without the High-pass Filter) OD - 16.0 - µV/°C

Gain Error (Note 3) GE - ±3.0 %

Temperature

Temperature Accuracy T - ±5 - °C

Power Supplies

Power Supply Currents (Active State) IA+

ID+ (VA+ = VD+ = 5 V)

ID+ (VA+ = 5 V, VD+ = 3.3 V)

PSCA

PSCD

1.5

3.5

2.3

Power Consumption Active State (VA+ = VD+ = 5 V)

(Note 4) Active State (VA+ = 5 V, VD+ = 3.3 V )

Stand-by State

Sleep State

Power Supply Rejection Ratio (50, 60 Hz)

(Note 5) Voltage

Current (Gain = 50x)

Current (Gain = 10x)

PSRR 48

PFMON Low-volta ge Trigger Threshold (Note 6) PMLO 2.3 2.45 - V

PFMON High-voltage Power-on Trip Point (Note 7) PMHI - 2.55 2.7 V

PSRR 20 150

Veq

----------

log=

CS5467

DS714F3 9

VOLTAGE REFERENCE

Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the

following formula is used to calculate the VREFOUT temperature coefficient.

9. Specified at maximum recommended output of 1 µA, source or sink.

Parameter Symbol Min Typ Max Unit

Reference Output

Output Voltage VREFOUT +2.4 +2.5 +2.6 V

Temperature Coef ficient (Note 8) TCVREF - 40 - ppm/°C

Load Regulation (Note 9) VR-610mV

Reference Input

Input Voltage Range VREFIN +2.4 +2.5 +2.6 V

Input Capacitance - 4 - pF

Input CVF Current - 100 - nA

(VREFOUTMAX - VREFOUTMIN)

VREFOUTAVG

(

TAMAX - TAMIN

(

1.0 x 10

(

TCVREF =

CS5467

10 DS714F3

DIGITAL CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions .

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• DCLK = 4.096 MHz.

Notes: 10. All measurements performed under static conditions.

11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is

used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between

2.5 MHz - 5.0 MHz.

12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.

13. The frequency of CPUCLK is equal to MCLK.

14. The minimum FSCR is limited by the maximum allowed gain registe r value. The maximum FSCR is

limited by the full-scale signal applied to the input.

15. Configuration register (Config) bits PC[6:0] are set to “0000000”.

16. Th e MODE pin is pulled low by an internal resistor.

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

Master Clock Frequency Internal Gate Oscillator (Note 11) DCLK 2.5 4.096 20 MHz

Master Clock Duty Cycle 40 - 60 %

CPUCLK Duty Cycle (Note 12 and 13) 40 - 60 %

Filter Characteristics

Phase Compensation Range (60 Hz, OWR = 4000 Hz) -5.4 - +5.4 °

Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz

Digital Filter Output W ord Rate (Both channels) OWR - DCLK/1024 - Hz

High-pass Filter Corner Frequency -3 dB -0.5-Hz

Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR 25 - 100 %FS

Channel-to-channel Time-shift Error (Note 15) 1.0 µs

Input/Output Characteristics

High-level Input Voltage All Pins Except XIN and SCLK and RESET

XIN

SCLK and RESET

VIH 0.6 VD+

(VD+) – 0.5

0.8VD+

Low-level Input Voltage (VD = 5 V)

All Pins Except XIN and SCLK and RESET

XIN

SCLK and RESET

VIL -

0.8

1.5

0.2VD+

Low-level Input Voltage (VD = 3.3 V)

All Pins Except XIN and SCLK and RESET

XIN

SCLK and RESET

VIL -

0.48

0.3

0.2VD+

High-level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 - - V

Low-level Output Voltage Iout =-5mA(VD=+5V)

Iout = -2.5 mA (VD = +3.3V) VOL -

-0.4

0.4 V

Input Leakage Current (Note 16) Iin -±1±10µA

3-state Leakage Current IOZ --±10µA

Digital Output Pin Capacitance Cout -5-pF

CS5467

DS714F3 11

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions .

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.

Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

Parameter Symbol Min Typ Max Unit

Rise Times

(Note 17) Any Digital Output trise -

50 1.0

-µs

Fall Times

(Note 17) Any Digital Output tfall -

50 1.0

-µs

Start-up

Oscillator Start-up Time XTAL = 4.096 MHz (Note 18)tost -60-ms

Serial Port Timing

Serial Clock Frequency SCLK - - 2 MHz

Serial Clock Pulse Width High

Pulse Width Low t1

200

200 -

-ns

SDI Timing

CS Falling to SCLK Rising t350 - - ns

Data Set-up Time Prior to SCLK Rising t450 - - ns

Data Hold Time After SCLK Rising t5100 - - ns

SDO Timing

CS Falling to SDO Driving t6-2050ns

SCLK Falling to New Data Bit (hold time) t7-2050ns

CS Rising to SDO Hi-Z t8-2050ns

E2PROM mode Timing

Serial Clock Pulse Width Low

Pulse Width High t9

t10

8DCLK

DCLK

MODE setup time to RESET Rising t11 50 ns

RESET rising to CS falling t12 48 DCLK

CS falling to SCLK rising t13 100 8 DCLK

SCLK falling to CS rising t14 16 DCLK

CS rising to driving MODE low t15 50 ns

SDO setup time to SCLK rising t16 100 ns

CS5467

12 DS714F3

t1t2

t4t5

MSB

MSB-1

LSB

MSB

MSB-1

LSB

MSB

MSB-1

LSB

MSB

MSB-1

LSB

Command T im e 8 S C LKs High Byte M id Byte Low B yte

SCLK

SDI

t10 t9

RESET

SDO

SCLK

Last 8

Bits

SDI

MODE

STOP bit

D a ta from EEP ROM

t16 t4t5

t14

t15

t13

t12

t11

(INPUT)

(OUTPUT)

(INPUT)

t1t2

MSB

MSB-1

LSB

Com m and Time 8 S CLKs SYNC0 or SYNC1

Command SYNC0 or SYNC1

Command

MSB

MSB-1

LSB

MSB

MSB-1

LSB

MSB

MSB-1

LSB

H ig h B yte Mid B yte L ow B y te

SDO

SCLK

SDI

SYNC0 or SYNC1

Command

UNKNOWN

SDI Write Timing (Not to Scale)

SDO Read Timing (Not to Scale)

Figure 1. CS5467 Read and Write Timing Diagrams

E2PROM mode Sequence Timing (Not to Scale)

CS5467

DS714F3 13

SWITCHING CHARACTERISTICS (Continued)

Notes: 19. Pulse output timing is specified at DCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to

6.7 Energy Pulse Outputs on page 20 for more information on pulse output pins.

20. Timing is proportional to the frequency of DCLK.

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)]  + 6.0 V.

22. VD+ and AGND must satisfy [(VD+) - (AGND)]  + 6.0 V.

23. Applies to all pins including continuous over-volta ge conditions at the analog input pin s.

24. Transient current of up to 100 mA will not cause SCR latch-up.

25. Maximum DC input current for a power supply pin is ±50 mA.

26. Total power dissipation, including all input currents and output currents.

Parameter Symbol Min Typ Max Unit

E1, E2, and E3 Timing (Note 19 and 20)

Period tperiod 500 - - s

Pulse Width tpw 244 - - s

Rising Edge to Falling Edge t36--s

E2 Setup to E1 and/or E3 Falling Edge t41.5 - - s

E1 Falling Edge to E3 Falling Edge t5248 - - s

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 21 and 22)

Positive Digital

Positive Analog VD+

VA+ -0.3

-0.3 -

-+6.0

+6.0 V

Input Current, Any Pin Except Supplies (Notes 23, 24, 25) IIN --±10mA

Output Current, Any Pin Except VREFOUT IOUT --100mA

Power Dissipation (Note 26) PD--500mW

Analog Input Voltage All Analog Pins VINA - 0.3 - (VA+) + 0.3 V

Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V

Ambient Operating Temperature TA-40 - 85 °C

Storage Temperature Tstg -65 - 150 °C

tperiod

E1 t3

t5t3

tpw

tperiod

tpw

Figure 2. Timing Diagram for E1, E2, and E3

CS5467

14 DS714F3

4. SIGNAL PATH DESCRIPTION

The data flow for voltage and current mea surement and

the other calculations are shown in Figures 3, 4, and 5.

4.1 Analog-to-Digital Converters

Voltage1 channel and voltage2/temperature channel

use second-order delta-sigma modulators and the two

current channels use fourth-order delta-sigma modula-

tors to convert the analog inputs to single-bit digital data

streams. The converters sample at a rate of DCLK /8.

This high sampling provides a wide dynamic range and

simplifies anti-alias filter design.

4.2 Decimation Filters

The single-bit modulator output data is widened to 24

bits and down-sampled to DCLK/1024 with low-pass

decimation filters. These decimation filters are third-or-

der Sinc. Their outputs are passed through third-order

IIR “anti-sinc” filters, used to compensate for the ampli-

tude roll-off of the decimation filters.

4.3 Phase Compensation

Phase compens ati on chan ges th e ph ase of c urren t rel-

ative to voltage by changing the sampling time in the

decimation filters. The amount of phase shift is set by

bits PC[7:0] in the Configuration register (Config) for

channel 1 and bits PC[7:0] in the Control register (Ctrl)

for channel 2.

Phase compensation, PC[7:0] is a sig ned two’s comple-

ment binary value in the range of -1.0 to almost +1.0

output word r ate (OWR) s amples. For a sample rate of

4000 Hz, the delay range is ±250 uS, a phase shift of

±4.5° at 50 Hz and ±5.4° at 60 Hz. The step size would

be 0.0352° at 50 Hz and 0.0422° at 60 Hz at this sample

rate.

Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements

FGA

VHPF1 IHPF1

V1GAIN

V1OFF

I1GAIN

I1OFF

Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements

FGA

V2Q

V2GAIN

V2OFF

I2GAIN

I2OFF

Control Register

VHPF2 IHPF2

CS5467

DS714F3 15

4.4 DC Offset and Gain Correction

The system and chip inherently ha ve gain and offset er-

rors which can be removed using the gain and offset

registers. (See Section 9. System Calibration on page

40). Each measurement channel has its own registers.

For every channel, the output of the IIR filter is added to

the offset register and multiplied by the gain register.

4.5 High-pass Filters

Optional high-pass filters (HPF in Figures 3 and 4) re-

move any DC from the selected signal paths. Subse-

quently, DC will also be removed from power, and all

low-rate results. (see Figures 5).

Each energy channel has a current and voltage path. If

an HPF is enabled in only one path, a phase-matching

filter (PMF) is applied to the other path which matches

the amplitude and phase delay of the HPF in the band

of interest, but passes DC. For more information, see

6.5 High-pass Filters on page 20. The HPF filter multi-

plexers drive the I1, V1, I2, and V2 result registers.

4.6 Low-Rate Calculations

Low-rate results are derived from sample-rate results

integrated over N samples, where N is the value stored

in the Cycle Count register. The low-rate interval is the

sample interval multiplied by N.

4.7 RMS Results

The root mean square (RMS in Figure 5) calculations

are performed on N instantaneous voltage and current

samples, using the formula:

IRMS In

n0=

N1–



---------------------

CS5467

16 DS714F3

4.8 Power and Energy Results

The instantaneous voltage and current samples are

multiplied to obtain the instantaneous power (P1, P2)

(see Fig ure 3 and 4). The product is then average d over

N conversions to compute active power (P1AVG,

P2AVG).

Apparent power (S1, S2) is the prod uct of RM S voltag e

and current as shown:

Power factor (PF1, PF2) is active power divided by ap-

parent power as shown below. The sign of the power

factor is determined by the active power.

Wideband reactive power (Q1WB, Q2WB) is calculated

by doing a vector subtraction of active power from ap-

parent power.

Quadrature power (Q1, Q2) are samp le ra te results ob-

tained by multiplying instantaneous current (I1, I2) by in-

stantaneous quadrature voltage (V1Q, V2Q) which are

created by phase shifting instantaneous voltage (V1,

V2) 90 degrees using first-order integrators. (See Fig-

ure 3 and 4). The gain of these in tegrators is inversely

related to line frequency, so their gain is corrected by

the Epsilon register, which is ba sed on line frequency.

Reactive power (Q1Avg, Q2AvG) is generated by inte-

grating the instantaneous quadrature power over N

samples.

Active power (P1AVG, P2AVG), apparent power (S1, S2),

and reactive power (Q1AVG, Q2AVG) of the two channels

are summed up and then divided by 2. The calculation

results are p laced in EPULSE, SPULSE, and QPULSE reg-

isters which can be configured to drive energy pulse

outputs. (See Figure 6.)

V1ACOFF

(V2ACOFF)

I1ACOFF

(I2ACOFF)

P1OFF(P2OFF)

Figure 5. Low-rate Calculations

RMS IRMS

=

PF PActive

------------------

QWB S2PActive

–=

P1AVG

÷2

P2AVG

EPULSE EACCM

+ × +

OVF=

S1 ÷2

S2 SPULSE SACCM

+ × +

OVF=

Q1AVG

÷2

Q2AVG

QPULSE QACCM

+ × +

OVF=

PulseRate ( E1, E2, E3 )

Figure 6. Two-channel Power Summation

CS5467

DS714F3 17

4.9 Peak Voltage and Current

Peak current (I1PEAK, I2PEAK) and peak voltage

(V1PEAK, V2PEAK) are the largest current and voltage

samples detected in the previous low-rate interval.

4.10 Power Offset

The power offset regi sters, P1OFF (P2OFF) can be used

to offset erroneous power sources resident in the sys-

tem not originating from the power line. Residual powe r

offsets are usually caused by crosstalk into current

paths from voltage p aths or from ri pple on th e met er or

chip’s power supply, or from inductance from a nearby

transformer.

These offsets can be either positive or negative, indi cat-

ing crosstalk coupling either in phase or out of phase

with the applied voltage input. The power offset regis-

ters can compensate fo r either condition.

To use this feature, measure the average power at no

load using either Single or Continuous Conversion com-

mands. Take the measured result (from the P1AVG

(P2AVG) register), invert (negate) the value and write it

to the associated power offset register, P1OFF (P2OFF).

CS5467

18 DS714F3

5. PIN DESCRIPTIONS

5.1 Analog Pins

The CS5467 has four differential inputs: VIN1VIN2

IIN1, and IIN2 are the voltage1, voltage2, current1,

and current2 inputs, respectively. A single-ended power

fail monitor input, voltage reference input, and voltage

reference output are also available.

5.1.1 Voltage1 & Voltage2 Inputs

The output of the line voltage resistive divider or trans-

former is connected to the VIN1+ (VIN2+) and VIN1-

(VIN2-) input pins of the CS5467. The voltage channel

is equipped with a 10x, fixed-gain amplifier. The

full-scale signal level that can be applied to the voltage

channel is ±250 mV. If the input signal is a sine wave,

the maximum RMS voltage is

250 mVp / 2176.78 mVRMS which is approximate-

ly 70.7% of maximum peak voltage.

5.1.2 Current1 & Current2 Inputs

The output of the current-sensing resistor or transform-

er is connected to the IIN1+ (IIN2+) and IIN1- (IIN2-) in-

put pins of the CS5467. To accommodate different

current-sensin g eleme nts, the curr ent channe l incorpo-

rates a programmable g ain amplifier (PGA) with two se-

lectable input gains. The full-scale signal level for the

current channels is ±50 mV or ±250 mV. If the input sig-

nal is a sine wave, the maximum RMS voltage is

35.35 mVRMS or 176.78 mVRMS which is approxi-

mately 70.7% of maximum peak voltage.

5.1.3 Power Fail Monitor Input

An analog input (PFMON) is provided to determine

when a power loss is imminent. By connecting a resis-

tive divider from the unregulated meter power su pply to

the PFMON input, an interrup t can be gener ated, or the

Low Supply Detected (LSD) Status register bit can be

monitored to indicate low-supply conditions. The PF-

MON input has a comparator that trips around the level

of the voltage reference inp ut (VREFIN).

5.1.4 Voltage Reference Input

The CS5467 requires a stable voltage reference of

2.5 V applied to the VREFIN pin. This reference can be

supplied from an external voltage reference or from the

VREFOUT output. A bypass capacitor of at least 0.1 F

is recommended at the VREFIN pin.

5.1.5 Voltage Reference Output

The CS5467 generates a 2.5 V reference (VREFOUT).

It is suitable for driving the VREFIN pin, but has very lit-

tle fan-out capacity and is not recommended for driving

external circuit s .

5.1.6 Crystal Oscillator

An external quartz crystal can be connected to the XIN

and XOUT pins as shown in Figure 7. To reduce system

cost, each pin is supplied with an on-chip, phase-shift-

ing capacitor to ground.

Alternatively, an external clock source can be connect-

ed to the XIN pin.

5.2 Digital Pins

5.2.1 Reset Input

The active-low RESET pin, when asserted, will halt all

CS5467 operations and reset internal hardware regis-

ters and states. When de-asserted, an initialization se-

quence begins, setting default register values.

5.2.2 CPU Clock Output

A logic-level clock output (CPUCLK) is provided at the

crystal frequency to drive an external CPU or micr ocon-

troller clock. Two phase choices are available.

5.2.3 Interrupt Output

The INT pin indicates an enabled Inte rnal Status regis-

ter (Status) bit is set. Status register bits indicate condi-

tions such as data ready, modulator oscillations, low

supply, voltage sag, current fa ults, numerical overflows,

and result updates.

5.2.4 Energy Pulse Outputs

The CS5467 provides three pins (E1, E2, E3) for pulse

energy outputs. These pins can also be used to output

other conditions, such a s voltage1 sign, power fail m on-

itor, or energy sign.

Figure 7. Oscillator Connections

Oscillator

Circuit

DGND

XIN

XOUT

C1 = 22 pF

C2 =

CS5467

DS714F3 19

5.2.5 Serial Interface

The CS5467 provides 5 pins, SCLK, SDI, SDO, CS, and

MODE for communication between a host microcon-

troller or serial E2PROM and the CS5467.

MODE is an input that, when high, indicates to the

CS5467 that a serial E2PROM is being used instead of

a host microcontroller. It ha s a weak pull-do wn allowing

it to be left unconnected if micr ocontroller mode is used.

SCLK is used to shift and qualify serial data. Serial data

changes as a result of the falling edge of SCLK and is

valid during the rising edge. It is a Schmitt-trigger input

for host microcontrollers, and a driven output for serial

E2PROMs.

SDI is the serial data input to the CS5467.

SDO is the se ria l d ata o utput from the CS546 7. It’s out-

put drivers are disabled whenever CS is de-asserted, al-

lowing other devices to drive the SDO line.

CS is the chip select input for the serial bus. A high logic

level de-asserts it, tri-stating the SDO pin and clearing

the serial interface. A low logic level enables the serial

port. This pin may be tied low for systems not requiring

multiple SDO drivers. CS is a driven output when inter-

facing to serial E2PROMs.

CS5467

20 DS714F3

6. SETTING UP THE CS5467

6.1 Clock Divider

The internal clock to the CS5467 needs to operate

around 4 MHz. However, by using the internal clock di-

vider, a higher crystal frequency can be used. This is im-

portant when driving an external microcontroller

requiring a faster clock and using the CPUCLK output.

K is the divide ratio from the crystal input to the internal

clock and is selected with Configuration register (Con-

fig) bits K[3:0]. It has a range of 1 to 16 . A valu e of zero

results in a setting of 16.

6.2 CPU Clock Inversion

By default, CPUCLK is inverted from XIN . Setting Con-

figuration regist er bit iCPU re m ov es this inversion. This

can be useful when one phase adds more noise to the

system than the other.

6.3 Interrupt Pin Behavior

The behavior of the INT pin is controlled by the IMODE

and IINV bits in the Configuration registe r as shown.

If IMODE = 1, the duration of the INT pulse will be two

DCLK cycles, where DCLK = MCLK/K.

6.4 Current Input Gain Ranges

Control register bits I1gain (I2gain) select the input

range of the current inputs.

6.5 High-pass Filters

Mode Control (Modes) register bits VHPF an d IHPF ac-

tivate the HPF in the voltage and current paths, respec-

tively. Each energy channel has separate VHPF and

IHPF bits. When a high-pass filter is enable d in only one

path within a channel, a phase matching filter (PMF) is

applied to the other path within that channel. The PMF

filter matches the amplitude and phase response of the

HPF in the band of interest, but passes DC.

6.6 Cycle Count

Low-rate calculations, such as average power and RMS

voltage and current integrate over several (N) output

word rate (OWR) samples. The dura tion of this averag-

ing window is set by the Cycle Count (N) register. By de-

fault, Cycle Count is set to 4000 (1 second at output

word rate [OWR] of 4000 Hz). The minimum value for

Cycle Count is 10.

6.7 Energy Pulse Outputs

By default, E1 outputs total active energy, E3, total re-

active energy, and E2, the sign of both active and reac-

tive energy. (See Figure 2. Timing Diagram for E1, E2,

and E3 on page 13.)

Three pairs of bits in the Mod e Control (Modes) register

control the operation of these outputs. These bits are

named E1MODE[1:0], E2MODE[1:0], and

E3MODE[1:0]. Some combinations of these bits over-

ride others, so read the following paragraphs carefully.

The E2 pin can outp ut energy sign, or total apparen t en-

ergy. Table 4 lists the functions of E2 as controlled by

E2MODE[1:0 ] in the Modes register.

Note: E2MODE[1:0]=3 is a special mode.

The E3 pin can output total reactive energy, power fail

monitor status, voltage1 sign, or total apparent energy.

Table 5 lists the functions of E3 as controlled by

IMODE IINV INT Pin

0 0 Active- low Le ve l

0 1 Active-high Level

10 Low Pulse

11 High Pulse

Table 1. Interrupt Configuration

I1gain, I2gain Maximum Input Gain

0±250mV10x

1 ±50 mV 50x

Table 2. Current Input Gain Ranges

VHPF IHPF Filter Configuration

0 0 No filter on Voltage or Current

0 1 HPF on Current, PMF on Voltage

1 0 HPF on Voltage, PMF on Current

1 1 HPF on Current and V oltage

Table 3. High-pass Filter Configuration

E2MODE1 E2MODE0 E2 output

0 0 Energy Sign

0 1 Total Apparent Energy

1 0 Not Used

1 1 Enable E1MODE

Table 4. E2 Pin Configuration

CS5467

DS714F3 21

E3MODE[1:0] in the Modes register when E1MODE is

not enabled.

When both E2MODE bits are high, the E1MODE bits

are enabled, allowing active, apparent, reactive, or wide

band reactive energy for both energy channels to be

output on E1 and E2. Table 6 lists the functions of E1

and E2 with E1MODE enabled.

When E1MODE bits are enabled, the E3 pin outputs ei-

ther the power fail monitor status, or the sign of the E1

and E2 outputs. Tab le 7 lis t the function s of the E3 pin

using E3MODE[1:0] in the Modes register when

E1MODE is enabled.

6.8 No Load Threshold

The No Load Threshold register (LoadMIN) is used to

zero out the contents of EPULSE and QPULSE registers if

their magnitude is less than the LoadMIN register value.

6.9 Energy Pulse Width

Note: Energy Pulse Width (PulseWidth) only applies to

E1, E2, or E3 pins that are configured to output pulses.

When any are configured to output steady-state signals,

such as voltage1 sign, power fail monitor, or energy

sign, pulse widths and output rates do not apply.

The pulse width time (tpw) in Figure 2, is set by the value

in the PulseWidth register which is an integer multiple of

the sample or output word rate (OWR). At OWR of

4000 Hz (a period of 250 uS) tpw = PulseWidth x

250 uS. By default, PulseWidth is set to 1.

6.10 Energy Pulse Rate

The full-scale pulse frequency of enabled E1, E2, E3

pins is the value in PulseRate x output word rate

(OWR)/2. The actual pulse frequency is the full-scale

pulse frequency multiplied by the pulse register’s

(EPULSE, SPULSE, or QPULSE) value.

Example:

If the output word rate (OWR) is 4000 Hz, and the

PulseRate register is set to 0.05, the full-rate pulse fre-

quency is 0.05 x 4000 / 2 = 100 Hz. If the EPULSE regis-

ter, driving E1, is 0.4567, the pulse output rate on E1 will

be 100 Hz x 0.4567 = 45.67 Hz.

6.11 Voltage Sag/Current Fault Detection

Voltage sag detection is used to determine when aver-

aged voltage falls below a predetermined level for a

specified interval of time. Current fault detection deter-

mines when averaged current falls below a predeter-

mined level for a specified interval of time.

The specified interval of time (duration) is set by the val-

ue in the V1SagDUR (V2SagDUR) and I1FaultDUR

(I2FaultDUR) registers. Setting any of these to zero (de-

fault) disables the detect feature for the given channel.

The value is in output word rate (OWR) samples. The

predetermined level is set by the values in the

V1SagLEVEL (V2SagLEVEL) and I1FaultLEVEL

(I2FaultLEVEL) registers.

E3MODE1 E3MODE0 E3 output

0 0 Total Reactive Energy

0 1 Power Fail Monitor

1 0 Voltage1 Sign

1 1 Total Apparent Energy

Table 5. E3 Pin Configuration

E1MODE1 E1MODE0 E1 / E2 outputs

0 0 Active Energy

0 1 Apparent Energy

1 0 Reactive Energy

1 1 Wideband Reactive

Table 6. E1 / E2 Modes

E3MODE1 E3MODE0 E3 output

0 0 Power Fail Monitor

0 1 Energy Sign

1 0 not used

1 1 not used

Table 7. E3 Pin with E1MODE enabled

CS5467

22 DS714F3

For each enabled input channel, the measured value is

rectified and compared to the associated level register.

Over the duration window, the number of samples

above and below the level are counted. If the number of

samples below the level exceeds the number of sam-

ples above, a Status register bit V1SAG (V2SAG),

I1FAULT (I2FAULT) is set, indicating a sag or fault condi-

tion. (see Figure 8)..

6.12 Epsilon

The Epsilon register is used to set the gain of the 90°

phase shift used in the quadrature p ower calculation.

The value in the Epsilon register is the ratio of the line

frequency to the output word rate (OWR). It is, by de-

fault, 50/4000 (0.0125), for 50 Hz line and 4000 Hz sam-

ple (OWR) frequencie s.

For 60 Hz line frequency, it is 60/4000 (0.015). Other

output word rates (OWR) can be used.

Epsilon can also be calculated automatically by the

CS5467 by setting the AFC bit in the Mode Control

(Modes) register. The Frequency Update bit (FUP) in

the Status register is set every time the Epsilon register

has been automatically updated.

6.13 Temperature Measurement

The on-chip temperature sensor is designed to mea-

sure temperature and optionally compensate for tem-

perature drift of the voltage reference. It uses the VBE of

a transistor to determine temperature.

In the CS5467, voltage2 and temperature are multi-

plexed on one ADC channel. To initiate a temperature

measurement, write 1 to the Temperature Measure-

ment (TMEAS) register. TMEAS will go through counts 1,

2, 4, and back to 0. Wait for TMEAS to return to 0. When

done, Temperature (T) is updated. The Status register

bit TUP also indicates when the Temp erature register is

updated. The Vo ltage2 register ( V2) will not update dur-

ing the temperature measurement, but resume mea-

surement afterwards.

Temperature measurements are stored in the Temper-

ature register (T) which, by default, is configured to a

range of ±128 degrees on the Celsius (°C) sca le.

The application prog ram can change both the scale and

range of Temperatur e (T) by changing the Temperature

Gain (TGAIN) and Temperature Offset (TOFF) registers.

Two values must be known — the transistor’s VBE per

degree, and the transistor’s VBE at 0 degrees. At the

time of this publication, these values are:

VBE (per degree) = 0.276 9523 mV/°C or °K

VBE0 = 79.2604368 mV at 0°C

To determine the values to write to TGAIN and TOFF, use

the following formulae:

TGAIN = ADFS / VBE / TFS x 217

TOFF = -VBE0 / ADFS x 223

In the above equations, ADFS is the full-scale input

range of the temper ature A/D conver ter or 83 3.333 mV

and TFS is the desired full-scale range of the Tempera-

ture (T) register. The binary exponents are the bit posi-

tions of the binary point of these registers.

To use the Celsius scale (° C) and cover th e chip’s oper-

ating temperature range of -40°C to +85°C, the Temper-

ature register range needs to be ±128 degrees. TFS

should be 128 deg re es .

TGAIN = 833.333 / 0.2769523 / 128 x 131072

= 3081155 (0x2F03C3)

TOFF = -79.2604368 / 833.333 x 8388608

= -797862 (0xF3D35A)

These are the actual default values for these registers.

TGAIN and TOFF can also be used to calibrate the gain

and/or offset of the temperature sensor or A/D convert -

er. (See Section 9. System Calibration on page 40).

To use the Kelvin (°K) scale, simply add 273 times VBE

/ ADFS x 223 to TOFF since 0°C = 273°K,. You will also

need more range. Since -40°C to +85°C is 233°K to

358°K, a TFS of 512 degrees should be used in the

TGAIN calculation.

To use the Fahrenheit (°F) scale, multiply VBE by 5/9

and add 32 times the newVBE/ ADFS x 223 to TOFF

since 0°C = 32°F. You will also want to use aTFS of 256

degrees to cover the -40°C to +85°C range.

Figure 8. Sag and Fault Detect

CS5467

DS714F3 23

7. USING THE CS5467

7.1 Initialization

The CS5467 uses a power-on-reset circuit (POR) to

provide an internal re se t until the an alog volta ge r each-

es 4.0 V. The RESET input pin can also be used b y th e

application circuit to reset the part.

After RESET is removed and the oscillator is stable, an

initialization program is executed to set the default reg-

ister values.

A Software Reset command is also provided to allow

the application to run the initialization program without

removing power or asserting RESET.

The application should avoid sending commands during

initialization. The DRDY bit in the Status register indi-

cates when the initialization program has completed.

7.2 Power-down States

The CS5467 has two power-down states, stand-by and

sleep. In the stand-by state, all circuitry except the volt-

age reference and crystal oscillator is powered off. In

sleep state, all circuitry except the instruction decoder is

powered off.

To return the device to the active state, send a Wake-

up/Halt command to the device. When returning from

stand-by mode, registers will retain their contents prior

to entering the stand-by state. When returning from

sleep mode, a complete initialization occurs.

7.3 Voltage Tamper Correction

The CSS5467 provides compensation for meter tam-

pering on voltage channels.

If the application detects that the voltage in put has been

impaired it may choose to use the fixed internal RMS

voltage reference by setting the VFIX bit in the Modes

fault 0.707107 (full-scale RMS) but can be changed by

the application program. (See fig ure 9)

Figure 9. Fixed RMS Voltage Selection

CS5467

24 DS714F3

7.4 Command Interface

Commands and data are transferred most-significant bit

(MSB) first. Figure 1 on page 12, defines the serial port

timing. Commands are clocked in on SDI using SCLK.

They are a single byte (8 bits) long and fall into one of

four basic types:

1. Register Read

2. Register Write

3. Synchronizing

4. Instructions

data to be clocked out, MSB first on the SDO pin by

SCLK. During this time, other commands can be

clocked in on the SDI pin. Other commands will not in-

terrupt read data, except another register read, which

will cause the new read data to appear on SDO.

Synchronizing can be sent while read data is being

clocked out if no other commands need to be sent.

Synchronizing commands are also us ed to synchr onize

the serial port to a byte boundary. The CS and RESET

pins will also synchronize the serial port.

low, clocked in on the SDI pin, MSB first by SCLK.

Instructions are commands that will interrupt any in-

struction currently executing and begin the new instruc-

tion. These include conversions, calibrations, power

control, and soft reset.

(See Section 7.6 Commands on page 25).

7.5 Register Paging

Read and Write commands access one of 32 registers

within a specified page. The Register Page Select reg-

ister’s (Page) default value is 0. To access registers in

another page, write the desired page number to the

Page register. The Page register is always at address

31 and is accessible fro m within an y pa ge .

CS5467

DS714F3 25

7.6 Commands

All commands are 1 byte (8 bits) long. Many com mand values ar e unused and sho uld NOT be writte n by the

application program. All commands except register reads, register writes, or synchronizing commands will

abort any conversion, calibration, or any initialization sequence currently executing. This includes reset. No

commands other than reads or synchronizing should be executed until the rese t sequence completes.

7.6.1 Conversion

Executes a conversion (m ea su re m en t ) pro gr a m.

CC Continuous/Single Conversion

0 = Perform a Single Conversion (0xE0)

1 = Perform Continuous Conversion (0xE8)

7.6.2 Synchronization (SYNC0 and SYNC1)

The serial interface is bidirectional. While r eading data on the SDO output, the SDI input must be receiving

commands. If no command is needed during a read, SYNC0 or SYNC1 commands can be sent while read

data is received on SDO.

The serial port is no rmally initialized by de-asserting CS. An alternative method of initialization is to send 3 or

more SYNC1 commands followed by a SYNC0. This is useful in systems where CS is not used an d tied low.

7.6.3 Power Control (Stand-by, Sleep, Wake-up/Halt and Software Reset)

The CS5467 has two power-down states, stand- by and sleep. In stand- by, all circuitry except the voltage re f-

erence and clocks are turned off. In sleep mode, all circuitry except the command decoder is turned off. A

Wake-up/Halt command restores full-power operation after stand-by and issues a h ardware reset after sleep.

The Software Reset command is a program that emulates a pin reset and is not a power control functio n.

S[1:0] 00 = Software Reset

01 = Sleep

10 = Wake-up/Halt

11 = Stand-by

B7 B6 B5 B4 B3 B2 B1 B0

1110CC000

B7 B6 B5 B4 B3 B2 B1 B0

1111111SYNC

B7 B6 B5 B4 B3 B2 B1 B0

10S1S00000

CS5467

26 DS714F3

7.6.4 Calibration

The CS5467 can per form gain and offset calibrations using eithe r DC or AC signals. Proper input levels must

be applied to the current inputs and voltage input before performing calibrations.

CAL[5:4]* 00 = DC Offset

01 = DC Gain

10 = AC Offset

11 = AC Gain

CAL[3:0] 0001 = Current for Channel 1

0010 = Voltage for Channel 1

0100 = Current for Channel 2

1000 = Voltage for Channel 2

Note: Anywhere from 1 to all 4 channels can be calibrated simultaneously.

B7 B6 B5 B4 B3 B2 B1 B0

1 0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

CS5467

DS714F3 27

7.6.5 Register Read and Write

Read and Write comma nds provide access to on-ch ip registers. After a Read command, the addr essed data

can be clocked out the SDO pi n by SCLK. After a Write command, 24 bits of write da ta must follow. The data

is transferred to the addressed register after the 24th data bit is received. Registers are or ganized into pages

of 32 addresses each. To access a desired page, write its number to the Page register at address 31.

W/R Write/Read control

0 = Read

1 = Write

RA[4:0] Register address.

Page 0 Registers

Address RA[4:0] Name Description

0 00000 Config Configuration

1 00001 I1 Instantaneous Current Channel 1

2 00010 V1 Instantaneous Voltage Channel 1

3 00011 P1 Instantaneous Power Channel 1

4 00100 P1AVG Active Power Channel 1

5 00101 I1RMS RMS Current Channel 1

6 00110 V1RMS RMS Voltage Channel 1

7 00111 I2 Instantaneous Current Channel 2

8 01000 V2 Instantaneous Voltage Channel 2

9 01001 P2 Instantaneous Power Channel 2

10 01010 P2AVG Active Power Channel 2

11 01011 I2RMS RMS Current Channel 2

12 01100 V2RMS RMS Voltage Channel 2

13 01101 Q1AVG Reactive Power Channel 1

14 01110 Q1 Instantaneous Quadrature Power Channel 1

15 01111 Status Internal Status

16 10000 Q2AVG Reactive Power Channel 2

17 10001 Q2 Instantaneous Quadrature Power Channel 2

18 10010 I1PEAK Peak Current Channel 1

19 10011 V1PEAK Peak Voltage Channel 1

20 10100 S1 Apparent Power Channel 1

21 10101 PF1 Power Factor Channel 1

22 10110 I2PEAK Peak Current Channel 2

23 10111 V2PEAK Peak Voltage Channel 2

24 11000 S2 Apparent Power Channel 2

25 11001 PF2 Power Factor Channel 2

26 11010 Mask Interrupt Mask

27 11011 T Temperature

28 11100 Ctrl Control

29 11101 EPULSE Active Energy Pulse Output

30 11110 SPULSE Apparent Energy Pulse Output

31 R 11111 QPULSE Reactive Energy Pulse Output

31 W 11111 Page Register Page Select

Warning: Do not write to unpublished register locations.

B7 B6 B5 B4 B3 B2 B1 B0

0W/R

RA4 RA3 RA2 RA1 RA0 0

CS5467

28 DS714F3

Page1 Register s

Address RA[4:0] Name Description

0 00000 I1OFF Current DC Offset Channel 1

1 00001 I1GAIN Current Gain Channel 1

2 00010 V1OFF Voltage DC Offset Channel 1

3 00011 V1GAIN Voltage Gain Channel 1

4 00100 P1OFF Power Offset Channel 1

5 00101 I1ACOFF Current AC (RMS) Offset Channel 1

6 00110 V1ACOFF Voltage AC (RMS) Offset Channel 1

7 00111 I2OFF Current DC Offset Channel 2

8 01000 I2GAIN Current Gain Channel 2

9 01001 V2OFF Voltage DC Offset Channel 2

10 01010 V2GAIN Voltage Gain Channel 2

11 01011 P2OFF Power Offset Channel 2

12 01100 I2ACOFF Current AC (RMS) Offset Channel 2

13 01101 V2ACOFF Voltage AC (RMS) Offset Channel 2

14 01110 PulseWidth Pulse Output Width

15 01111 PulseRate Pulse Output Rate (frequency)

16 10000 Modes Mode Control

17 10001 Epsilon Ratio of Line to Sample Frequency

19 10011 N Cycle Count (Num b e r o f O WR Samples in One Low-rate Interval)

20 10100 Q1WB Wideband Reactive Power from Power Triangle Channel 1

21 10101 Q2WB Wideband Reactive Power from Power Triangle Channel 2

22 10110 TGAIN Tem p erature Senso r Ga in

23 10111 TOFF T em p erature Senso r Offset

25 11001 TSETTLE Filter Settling Time for Conversion Startup

26 11010 LoadMIN No Load Threshold

27 11011 VFRMS Voltage RMS Fixed Reference

28 11100 G System Gain

29 11101 Time System Time (in samples)

31 W 11111 Page Register Page Select

Page2 Register s

Address RA[4:0] Name Description

0 00000 V1SagDUR V Sag Duration Channel 1

1 00001 V1SagLEVEL V Sag Level Channel 1

4 00100 I1FaultDUR I Fault Duration Channel 1

5 00101 I1FaultLEVEL I Fault Level Channel 1

8 01000 V2SagDUR V Sag Duration Channel 2

9 01001 V2SagLEVEL V Sag Level Channel 2

12 01100 I2FaultDUR I Fault Duration Channel 2

13 01101 I2FaultLEVEL I Fault Level Channel 2

31 W 11111 Page Register Page Select

Page5 Register

Address RA[4:0] Name Description

26 11010 TMEAS Temp erature Mea s u re ment

31 W 11111 Page Register Page Select

Warning: Do not write to unpublished register locations.

CS5467

DS714F3 29

8. REGISTER DESCRIPTIONS

1. “Default” = bit states after power-on or reset

2. DO NOT write a “1” to any unpublished register bit.

3. DO NOT write to any unpublished register addre ss.

8.1 Page Register

8.1.1 Page – Address: 31, Write-only, can be written from ANY page.

Default = 0

is 12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each.

The Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all

pages are used,

Page is a write-only integer containing 7 bits.

8.2 Page 0 Registers

8.2.1 Configuration (Config) – Address: 0

Default = 1 (K=1)

PC[7:0] Phase compensation for channel 1. Sets a delay in voltage, relative to current. Phase is

signed and in the range of -1 .0 value1.0 sample (OWR) inte rva ls.

EWA Allows the E1 and E2 pins to be configured as open-drain outputs.

0 = Normal Outputs

1 = Open-drain Outputs

IMODE, IINV Interrupt configuration. Selects INT pin behavior.

00 = Low Logic Level When Asserted

01 = High Logic Level When Asserted

10 = Low-going Pulse on New Interrupt

11 = High-going Pulse on New Interrupt

iCPU Inverts the CPUCLK output.

0=Default

1 = Invert CPUCLK.

K[3:0] Clock divider. Divides MCLK by K to generate internal clock DCLK. (DCLK = MCLK/K). K

is unsigned and in the range of 1 to 16. When zero, K = 16. At reset, K = 1.

MSB LSB

26252423222120

23 22 21 20 19 18 17 16

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

15 14 13 12 11 10 9 8

EWA - - IMODE IINV - - -

76543210

- - -iCPUK3K2K1K0

CS5467

30 DS714F3

8.2.2 Instantaneous Current (I1, I2), Voltage (V1, V2), and Power (P1, P2)

Address: 1 (I1), 2 (V1), 3 (P2), 7 (I2), 8 (V2), 9 (P2)

I1 (I2) and V1 (V2) contain instantaneous cu rrent and vo ltage, respectively, which are multiplied to yield instan-

taneous power, P1 (P2). These are two's co mple ment valu es in the rang e of - 1.0 value1.0, with the binary

point to the right of the MSB.

8.2.3 Active Power (P1AVG , P2AVG )

Address: 4 (P1AVG ), 10 (P2AVG )

Instantaneous power is averaged over each low-rate interval (N samples) to compute active power, P1AVG

(P2AVG). These are two's complement values in the range of -1.0 value 1.0, with the binary point to the

right of the MSB.

8.2.4 RMS Current (I1RMS , I2RMS ) and Voltage (V1RMS , V2RMS )

Address: 5 (I1RMS), 6 (V1RMS), 11 (I2RMS), 12 (V2RMS)

I1RMS (I2RMS) and V1RMS (V2RMS) contain the root mean squar e ( RMS) value s o f I1 (I2) and V1 (V2), calcu-

lated each low-ra te interva l . Th es e ar e un sig ned valu es in th e ra ng e of 0 value1.0, with the binary point

to the left of the MSB.

8.2.5 Instantaneous Quadrature Power (Q1, Q2)

Address: 14 (Q1), 17 (Q2)

Instantaneous quadrature power, Q1 (Q2), the product of voltage1 (voltage2) shifted 90 degrees and current1

(current2). These are two's com plement values in the range o f -1.0 value1.0, with the binary point to the

right of the MSB.

8.2.6 Reactive Power (Q1Avg , Q2AVG )

Address: 13 (Q1AVG), 16 (Q2AVG)

Reactive power Q1AVG (Q2AVG) is Q1 (Q2) averaged over every N samples. These are two's complement

values in the range of -1.0 value1.0, with the binary point to the right of the MSB.

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

CS5467

DS714F3 31

8.2.7 Peak Current (I1PEAK, I2PEAK ) and Peak Voltage (V1PEAK, V2PEAK )

Address: 18 (I1PEAK), 19 (V1PEAK), 22 (I2PEAK), 23 (V2PEAK)

Peak current, I1PEAK (I2PEAK) and peak voltage, V1PEAK (V2PEAK) are the instantaneous current an d voltage

samples with the greatest magnitude detected during the last low-rate interval. These are two's complement

values in the range of -1.0 value1.0, with the binary point to the right of the MSB.

8.2.8 Apparent Power (S1, S2)

Address: 20 (S1), 24 (S2)

Apparent power S1 (S2) is the product of V1RMS and I1RMS (V2RMS and I2RMS), These are two' s complement

values in the range of 0 value1.0, with the binary point to the right of the MSB.

8.2.9 Power Factor (PF1, PF2)

Address: 21 (PF1), 25 (PF2)

Power factor is calculated by dividing active powe r by apparent power. The sign is determined by the active

power sign. These are two's complement values in the ra nge of -1.0 value1.0, with the binary point to the

right of the MSB.

8.2.10 Temperature (T) – Address: 27

T contains results from th e on-chip temperature measurement. By default, T uses the Celsius scale, and is a

two's complemen t value in the range of - 128.0 value128.0 (oC), with the binary point to the right of bit 16.

T can be rescaled by the application using the TGAIN and TOFF registers.

8.2.11 Active, Apparent, and Reactive Energy Pulse Outputs (EPULSE , SPULSE , QPULSE )

Address: 29 (EPULSE), 30 (SPULSE), 31 (QPULSE)

These drive the pulse outputs when configured to do so. These are two's complement values in the range of

-1.0 value1.0, with the binary point to the right of the MSB. Refer to 4.8 Power and Energy Results on

page 16.

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

-(27)2

6252423222120..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

CS5467

32 DS714F3

8.2.12 Internal Status (Status) and Interrupt Mask (Mask)

Address: 15 (Status); 26 (Mask)

Default = 1 (Status), 0 (Mask)

The Status register indicates a variety of conditions within the chip. Writing a '1' to a Status register bit will

clear that bit if the condition that set it has been removed. Writing a '0' to any bit has no effect.

The Mask register is used to control the activation of the INT pin. Writing a '1' to a Mask register bit will allow

the corresponding Status register bit to activate the INT pin when set.

DRDY Data Ready. During conversion, this bit indicates that low-rate results have been updated.

It indicates completion of other commands and the reset sequence.

I1OR (I2OR) Current Out of Range. Set when the me asured current wou ld cause the I1 (I2) register to

overflow.

V1OR (V2OR) Voltage Out of Range. Set when the meas ured vo ltage wou ld caus e the V1 (V2) re gister

to overflow.

CRDY Conversion Ready. Indicates that sample rate (ou tput word rate) results have been updat-

ed.

I1ROR (I2ROR) RMS Current Out of Range. Set when RMS current would cause the I1RMS (I2RMS) regis-

ter to overflow.

V1ROR (V2ROR) RMS Voltage Out of Range. Set when RMS volta ge would cause the V1RMS (V2RMS) reg-

ister to overflow.

E1OR (E2OR) Energy Out of Range. Set whe n average power wo uld cause P1AVG (P2AVG) to overflow.

I1FAULT (I2FAULT)Indicates when a current fault condition has occurred.

V1SAG (V2SAG) Indicates when a volt ag e sag cond itio n ha s occ ur re d .

TUP Indicates when the Temperature register (T) has been updated.

V1OD (V2OD) Modulator oscillation has been detected in the voltage1 (voltage2) A/D.

I1OD (I2OD) Modulator oscillation has been detected in the current1 (current2) A/D.

LSD Low Supply Detect. Set when th e voltage on the PFMON pin falls below the specified low

level. The LSD bit cannot be reset until the voltage rises above the specified high level.

FUP Frequency Updated. Indicates the Epsilon register has been updated.

IC Invalid Command. Normally logic 1. Set to 0 when an invalid command is received. It may

also indicate loss of serial command synchronization and the part may need to be re-ini-

tialized.

23 22 21 20 19 18 17 16

DRDY I2OR V2OR CRDY I2ROR V2ROR I1OR V1OR

15 14 13 12 11 10 9 8

E2OR I1ROR V1ROR E1OR I1FAULT V1SAG I2FAULT V2SAG

76543210

TUPV2ODI2ODV1ODI1OD LSD FUP IC

CS5467

DS714F3 33

8.2.13 Control (Ctrl) – Address: 28

Default = 0

PC[7:0] Phase compensation for channel 2. Sets a delay in voltage relative to current. Phase is

signed and in the range of -1 .0 value1.0 sample (OWR) inte rva ls.

I1gain (I2gain) Sets the gain of the current1 (current2) input.

0 = Gain is set for ±250mV range.

1 = Gain is set for ±50mV range.

STOP Terminat es E2PROM command sequence (if used).

0 = No Action

1 = Stop E2PROM Commands.

INTOD Converts INT output pin to an open drain output.

0 = Normal Output

1 = Open-drain Output

NOCPU Saves power by disabling the CPUCLK output pin.

0 = CPUCLK Enabled

1 = CPUCLK Disabled

NOOSC Disables the crystal oscillator, making XIN a logic-level input.

0 = Crystal Oscillator Enabled

1 = Crystal Oscillator Disabled

23 22 21 20 19 18 17 16

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

15 14 13 12 11 10 9 8

---I2gain---STOP

76543210

- - I1gain INTOD - NOCPU NOOSC -

CS5467

34 DS714F3

8.3 Page 1 Registers

8.3.1 DC Offset for Current (I1OFF , I2OFF ) and Voltage (V1OFF , V2OFF )

Address: 0 (I1OFF ), 2 (V1OFF ), 7 (I2OFF ), 9 (V2OFF )

Default = 0

DC offset registers I1OFF & V1OFF (I2OFF & V2OFF ) are initialized to zero on reset. During DC offset calibra-

tion, selected registers are written with the inverse of the DC offset measured. The application program can

also write the DC offset register values. These are two's complement values in the range of -1.0 value1.0,

with the binary point to the right of the MS B.

8.3.2 Gain for Current (I1GAIN , I2GAIN ) and Voltage (V1GAIN , V2GAIN )

Address: 1 (I1GAIN ), 3 (V1GAIN ), 8 (I2GAIN ), 10 (V2GAIN )

Default = 1.0

Gain registers I1GAIN & V1GAIN (I2GAIN & V2GAIN) are initialized to 1.0 on reset. During AC or DC gain calibra-

tion, selected register are written with the multiplicative inverse of the gain measured. These are unsigned

fixed-point values in the range of 0 value 4.0, with the binary point to the right of the second MSB.

8.3.3 Power Offset (P1OFF , P2OFF )

Address: 4 (P1OFF ), 11 (P2OFF )

Default = 0

Power of fs e t P1OFF (P2OFF ) is added to instanta neous po wer and averag ed over a low-r ate inter val to yield

P1AVG (P2AVG ) register results. It can be used to reduce systematic ener gy errors. The se are two's comple-

ment values in th e ra ng e of -1.0 value 1.0, with the binary point to the right of the MSB.

8.3.4 AC Offset for Current (I1ACOFF , I2ACOFF ) and Voltage (V1ACOFF , V2ACOFF )

Address: 5 (I1ACOFF ), 6 (V1ACOFF ), 12 (I2ACOFF ), 13 (V2ACOFF )

Default = 0

AC offset registers I1ACOFF & V1ACOFF (VACOFF & V2ACOFF ) are initialized to zero on reset. These are adde d

to the RMS results before being stored to the RMS result registers. They can be used to reduce systematic

errors in the RMS results. These are two's complement values in the range of -1.0 value 1.0, with the bi-

nary point to the right of the MSB.

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

21202-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

CS5467

DS714F3 35

8.3.5 Mode Control (Modes) – Address: 16

Default = 0

VFIX Use internal RMS voltage reference instead of voltage input for average active power.

0 = Use voltage input.

1 = Use internal RMS voltage reference, VFRMS.

E1MODE[1:0] E1, E2, and E3 alternate output mode (when enabled by E2MODE).

00 = E1, E2 = P1AVG, P2AVG

01 = E1, E2 = S1, S2

10 = E1, E2 = Q1AVG, Q2AVG

11 = E1, E2 = Q1WB, Q2WB

E2MODE[1:0] E2 Output Mode

00 = Energy Sign

01 = Total Apparent Energy

10 = Not Used

11 = Enable E1MODE

VHPF2:IHPF2 High-pass Filter Enable for Energy Channel 2

00 = No Filter

01 = HPF on Current, PMF on Voltage

10 = HPF on Voltage, PMF on Current

11 = HPF on both Voltage and Current

VHPF1:IHPF1 High-pass Filter Enable for Energy Channel 1

00 = No Filter

01 = HPF on Current, PMF on Voltage

10 = HPF on Voltage, PMF on Current

11 = HPF on both Voltage and Current

E3MODE[1:0] E3 Output Mode (with E1MODE disabled)

00 = Total Reactive Energy (default)

01 = Power Fail Monitor

10 = Voltage1 Sign

11 = Total Apparent Energy

E3MODE[1:0] E3 Output Mode (with E1MODE enabled)

00 = Power Fail Monitor

01 = Energy Sign

10 = Not Used

11 = Not Used

POS Positive Energy Only. Suppresses negative values in P1AVG and P2AVG. If a negative value

is calculated, zero will be stored instead.

AFC Enables automatic line frequency measurement which sets Epsilon every time a new line

frequency measurement completes. Epsilon is used to control the gain of the 90 degree

phase shift integrator used in quadrature power calculations.

23 22 21 20 19 18 17 16

-VFIX------

15 14 13 12 11 10 9 8

- E1MODE1 E1MODE0 - - E2MODE1 E2MODE0 VHPF2

76543210

IHPF2 VHPF1 IHPF1 - E3MODE1 E3MODE0 POS AFC

CS5467

36 DS714F3

8.3.6 Line to Sample Frequency Ratio (Epsilon) – Address: 17

Default = 0.0125 (4.0 kHz x 0.0125 or 50 Hz)

Epsilon is the ratio of the input line frequency to the output word rate (OWR). It can either be written by the ap-

plication program or ca lculated automa tically from th e line frequ ency (from the volta ge input) u sing th e AFC bit

in the Modes register. It is a two's complement value in the range of -1.0 value1.0, with the binary point to

the right of the MSB. Negative values are not used.

8.3.7 Pulse Output Width (PulseWidth) – Address: 14

Default = 1 (250 uS at OWR = 4 kHz)

PulseWidth sets the duration o f energy pulses. The actual pulse duration is the contents of PulseWidth divided

by the output word rate (OWR). PulseWidth is an integer in the range of 1 to 8,388,607.

8.3.8 Pulse Output Rate (PulseRate) – Address: 15

Default= -1

PulseRate sets the full-scale frequency for E1, E2, E3 pulse outputs. For a 4 kHz sample rate, the maximum

pulse rate is 2 kHz. This is a two's complement value in the range of -1 value1, with the binary point to the

left of the MSB.

Refer to 6.10 Energy Pulse Rate on page 21 for more inform ation.

8.3.9 Cycle Count (N) – Address: 19

Default = 4000

Determines the number of output word rate (OWR) samples to use in calculating low-rate results. Cycle Count

(N) is an integer in the range of 10 to 8,388,607. Values less than 10 should not be used.

8.3.10 Wideband Reactive Power (Q1WB , Q2WB )

Address: 20 (Q1WB ), 21 (Q2WB )

Wideband reactive power is calculated using vector subtraction. (See Section 4.8 Power and Energy Results

on page 16). The value is signed, but has a range of 0 value 1.0. The binary point is to the right of the MSB.

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

0222 221 220 219 218 217 216 ..... 26252423222120

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

22 221 220 219 218 217 216 ..... 26252423222120

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

CS5467

DS714F3 37

8.3.11 Temperature Gain (TGAIN ) – Address: 22

Default = 0x2F02C3

Refer to 6.13 Temper at ur e Me asurement on page 22 for more information.

8.3.12 Temperature Offset (TOFF ) – Address: 23

Default = 0xF3D35A

Refer to 6.13 Temper at ur e Me asurement on page 22 for more information.

8.3.13 Filter Settling Time for Conversion Startup (TSETTLE ) – Address: 25

Default = 30

Sets the number of output word rate (OWR) samples that will be used to allow filters to settle at the beginning

of Conversion and Calibration commands. This is an integer in the range of 0 to 8,38 8,607 samples.

8.3.14 No Load Threshold (LoadMIN ) – Address: 26

Default = 0

LoadMIN is used to set the no load threshold. When the magnitude of the EPULSE register is less than LoadMIN,

EPULSE will be zeroed. If the magnitude of the QPULSE register is less than LoadMIN, Qpulse will be zeroed.

LoadMIN is a two’s compliment value in th e range of -1.0 value 1.0, with the binary p oint to the right of the

MSB. Negative values are not used.

8.3.15 Voltage Fixed RMS Reference (VFRMS ) – Address 27

Default = 0.7071068 (full scale RMS)

If the application program d etects that the meter has po ssibly been tamper ed with in such a manner that the

voltage input is no longer working, it may choose to use this internal RMS reference instead of the disabled

voltage input by setting the VFIX bit in the Modes register. This is a two's complement valu e in the range of

0value1.0, with the binary point to the right of the MS B. Neg at i ve values are not used.

MSB LSB

262524232221202-1 ..... 2-11 2-12 2-13 2-14 2-15 2-16 2-17

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

223 222 221 220 219 218 217 216 ..... 26252423222120

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

CS5467

38 DS714F3

8.3.16 System Gain (G) – Address: 28

Default = 1.25

System Gain (G) is applied to all channels. By defa ult, G = 1.25, but can be finely adjusted to compensate for

voltage reference error. It is a two's complement valu e in the range of -2.0 value2.0, with the binary point

to the right of the second MSB. Values should be kept within 5% of 1.25.

8.3.17 System Time (Time) – Address: 29

Default = 0

System Time (Time) is measured in output word rate (OWR) samples. This is an unsigned integer in the range

of 0 to 16,777,215 samples. At OWR = 4.0 kHz, OWR will overflow every 1 hour, 9 minutes, and 54 seconds.

Time can be used by the application to manage real-time events.

MSB LSB

-(21)2

02-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22

MSB LSB

223 222 221 220 219 218 217 216 ..... 26252423222120

CS5467

DS714F3 39

8.4 Page 2 Registers

8.4.1 Voltage Sag and Current Fault Duration (V1SagDUR , V2SagDUR , I1FaultDUR , I2FaultDUR )

Address: 0 (V1SagDUR ), 8 (V2SagDUR ), 4 (I1FaultDUR ), 12 (I2FaultDUR )

Default = 0

Voltage sag duration, V1SagDUR (V2SagDUR) and current fault duration, I1FaultDUR (I2FaultDUR) determine

the count of output word rate (OWR) samples utilized to determine a sag or fault event. These are integers in

the range of 0 to 8,388,607 samp les. A value of zero disables the feature.

8.4.2 Voltage Sag and Current Fault Level (V1SagLEVEL , V2SagLEVEL , I1FaultLEVEL , I2FaultLEVEL )

Address: 1 (V1SagLEVEL ), 9 (V2SagLEVEL ), 5 (I1FaultLEVEL ), 13 (I2FaultLEVEL )

Default = 0

Voltage sag level, V1SagLEVEL (V2SagLEVEL ) and current fault level, I1FaultLEVEL (I2FaultLEVEL ) establish

an input level below which a sag or fault is triggered. These are two's comple ment values in the range of

-1.0 value1.0, with the binary point to the right of the MSB. Negative values are not used.

8.5 Page 5 Register

8.5.1 Temperature Measurement (TMEAS ) – Address: 26

Default = 0

The Temp er ature Meas ur e me n t (TMEAS) register is used to cycle-steal voltage channel2 for temperature

measurement. Writing a one to the LSB causes the temperature to be measured and the Temperature register

(T) to be updated.

Refer to 6.13 Temper at ur e Measureme nt on page 22 for more information.

MSB LSB

0222 221 220 219 218 217 216 ..... 26252423222120

MSB LSB

-(20)2

-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

223 222 221 220 219 218 217 216 ..... 26252423222120

CS5467

40 DS714F3

9. SYSTEM CALIBRATION

9.1 Calibration

The CS5467 provides DC offset and gain calibration

that can be applied to the voltage and current measure-

ments, and AC offset calibration which can be applied to

the voltage and current RMS calculations.

Since the voltage and current channels ha ve ind epe n-

dent offset and gain registers, offset and gain calibra-

tion can be performed on any channe l indepen dently.

The data flow of the calibration is shown in Fig ure 10.

The CS5467 must be operating in its active state and

ready to accept valid commands. Refer to 7.6 Com-

mands on page 25.

The value in the Cycle Count register (N) determines

the number of output word rate (OWR) samples that are

averaged during a calibration. DC offset and gain cali-

brations take at least N+TSETTLE samples. AC offset

calibrations take at least 6(N)+TSETTLE samples. As N

is increased, the accuracy of calibr ation results tends to

also increase.

The DRDY bit in the Status register will be set at the

completion of Calibration commands. If an overflow oc-

curs during calibration, other Status register bits may be

set as well.

9.1.1 Offset Calibration

During offset calibrations, no line voltage or current

should be applied to the meter. A zero-volt differential

signal can also be applied to the voltage inputs VIN1

VIN2 or current inputs IIN1 (IIN2of the CS5467.

(see Figu re 11.)

9.1.1.1 DC Offset Calibration

The DC Offset Calibration comman d measu res and a v-

erages DC values read on specified voltage or current

channels at zero input and stores the inverse result in

the associated offset registers. This will be added to in-

stantaneous measurements in subsequent conver-

sions, removing the offset.

Gain registers for channels being calibrated should be

set to 1.0 prior to perform in g DC offset calibration.

9.1.1.2 AC Offset Calibration

The AC Offset Calibration command measures the re-

sidual RMS values read on specified voltage or current

channels at zero input and stores the inverse result in

the associated AC offset registers. This will be added to

RMS measurements in subsequent conversions, re-

moving the offset.

AC offset registers for channe ls being calibra ted should

first be cleared prior to performing the calibration.

In Modulator +X

V1, I1, V2, I2

Filter

I1RMS, V1RMS,

I2RMS, V2RMS



I1DCOFF, V1DCOFF,

I2DCOFF, V2DCOFF

I1GAIN, V1GAIN,

I2GAIN, V2GAIN

0.6

= READABLE/WRITABLE REGISTERS.

+

X

DCAVG

RMS

I1ACOFF, V1ACOFF,

I2ACOFF, V2ACOFF



DC Gain

DC Offset

AC Offset

RMS

AC Gain

Negate DC AVG

Negate

Figure 10. Calibration Data Flow

XGAIN

External

Connections

-AIN+

AIN-

Figure 11. System Calibration of Offset

CS5467

DS714F3 41

9.1.2 Gain Calibration

During gain calibration, a full-scale reference signal

must be applied to the meter or optiona lly, scaled to th e

VIN1VIN2,IIN1 (IIN2pins of the CS5467. A DC

reference must be used for DC gain calibration. Either

an AC or DC reference can be used for RMS AC calibra-

tions. If DC is used, the associated high-pass filter

(HPF) must be off.

Figure 12 shows the basic setup for gain calibration.

Using a reference that is too large or too small can

cause an over-ran ge conditio n during calibra tion. Either

condition can set Status register bits I1OR (I2OR)

V1OR (V2OR) for DC and I1ROR (I2ROR) V1ROR

(V2ROR) for AC calibration.

Full scale (FS) for the voltage input is ±250 mV peak

and for the current inputs is ±250 mV or ±50 mV peak

depending on selected gain range. The normal peak

voltage applied to these pins should not exceed these

levels during calibration or normal operation.

The range of the gain registers limits the gain calibration

range and subsequently the range of the reference level

that can be applied. The reference should not exceed

FS or be lower than FS/4.

9.1.2.1 AC Gain Calibration

Full scale for AC RMS gain calibrations is 60% of the in-

put’s full-scale range, which is either 250 mV or 50 mV

depending on the gain range selected. That’s 150 mV or

30 mV, again depending on ran ge. So the normal r efer-

ence input level shou ld be eithe r 15 0 or 30 mVRMS, AC

or DC.

Prior to executing an AC Gain Calibration command,

gain registers for any channel to be calibrated should be

set to 1.0 if the reference level mentioned above is

used, or to that level divided by the a ctual reference lev-

el used.

During AC gain calibration the RMS level of the applied

reference is measured with the preset gain, then divided

into 0.6 and the quotient stored back into the corre-

sponding gain register.

9.1.2.2 DC Gain Calibration

With a DC reference applied, the DC Gain Calibration

command measures and averages DC values read on

the specified voltage or current channels and stores the

reciprocal result in the associated gain registers, con-

verting measured voltage into needed gain. Subse-

quent conversions will use the new gain value.

9.1.3 Calibration Order

1. DC offset.

2. DC or AC gain.

3. AC offset (if needed).

If both AC gain and offset calibrations were performed,

it is possible to repeat both to obtain additional accuracy

as AC gain and offset may interact.

9.1.4 Temperature Sensor Calibration

Temperature sensor calibration involves the adjustment

of two parameters - VBE and VBE0. These values must

be known in order to calibrate the temperature sensor.

See Section 6.13 Temperature Measurement on page

22 for an explanation of VBE and VBE0 and how to cal-

culate TGAIN and TOFF register values from them.

9.1.4.1 Temperature Offset Calibration

Offset calibration can be done at any temperature, but

should be done mid-scale if any gain error exists.

Subtract the measured T register temperature from the

actual temperature to determine the offset error. Multi-

ply this error by VBE and add it to VBE0 to yield a new

VBE0 value. Recalculate TOFF using this new value.

9.1.4.2 Temperature Gain Calibration

Two temperature points far enough apart to give rea-

sonable accuracy, for example 25°C and 85°C, are re-

quired to calibrate temperature gain.

Divide the actual temperature difference by the mea-

sured (T register) difference for the two temperatures.

This gives a gain correction factor. Update the TGAIN

Update VBE by dividing its old value by the gain cor-

rection factor. It will be needed for subsequent offset

calibrations.

External

Connections

IN+

IN-

CM +

-XGAIN

Reference

Signal

Figure 12. System Calibration of Gain.

CS5467

42 DS714F3

10. E2PROM OPERATION

The CS5467 can accept commands from a serial

E2PROM connected to the serial interface instead of a

host microcontroller. A high level (logic 1) on the MODE

input indicates that an E2PROM is connected. This

makes the CS and SCLK pins become driven outputs.

After reset and after running the initialization program,

the CS5467 begins reading commands from the con-

nected E2PROM.

10.1 E2PROM Configuration

A typical connection between the CS5467 and a

E2PROM is shown in Figure 13.

The CS5467 asserts CS (logic 0), clocks SCLK, and

sends Read commands to the E2PROM on SDO.

Command format is identical to microcontroller mode,

except the CS5467 will not attempt to write to the EE-

PROM device. The command sequence stops when the

STOP bit in the Control register (Ctrl) is written by the

command sequence.

Figure 13 also shows the external connections that

would be made to a calibrat ion device, such as a no te-

book computer, handheld calibrator, or tester during

meter assembly, The calibrator or tester can be used to

control the CS5467 during calibration and program the

required values into the E2PROM.

10.2 E2PROM Code

The EEPROM code should do the following :

1. Set any Configuration or Control register bits, such as

HPF enables and phase compensation settings.

2. Write any calibration data to gain and offset registers.

3. Set energy output pulse width, rate, and form ats.

4. Execute a Continuous Conversion command.

5. Set the STOP bit in the Control register (last).

Below is an example E2PROM code set.

-7E 00 00 01

Change to page 1.

-60 00 01 E0

Write Modes Register, turn high-pass filters on.

-42 7F C4 A9

Write value of 0x7FC4A9 to I1GAIN register.

-46 FF B2 53

Write value of 0xFFB253 to V1GAIN register.

-50 7F C4 A9

Write value of 0x7FC4A9 to I2GAIN register.

-54 FF B2 53

Write value of 0xFFB253 to V2GAIN register.

-7E 00 00 00

Change to page 0.

-74 00 00 04

Set LSD bit to 1 in the Mask register.

-E8

Start continuous conversions

-78 00 01 00

Write STOP bit to the Control register (Ctrl) to

terminate E2PROM command sequence.

10.3 Which E2PROMs Can Be Used?

Several industry-standard serial E2PROMs can be used

with the CS5467. Some are listed below:

• Atmel AT25010, AT25020 or AT25040

• National Semicon ductor NM25C040M8 or NM25020M8

• Xicor X25040SI

These serial E2PROMs expect a specific 8-bit com-

mand (00000011) in order to perform a memory read.

The CS5467 has been har dware programmed to trans-

mit this 8-bit command to the E2PROM after reset.

CS5467 EEPROM

MODE

SCLK

SDI

SDO

SCK

Conn ec tor to C alibrator

5 K

Pulse Output

Counter

Figure 13. Typical Interface of E2PROM to CS5467

CS5467

DS714F3 43

11. BASIC APPLICATION CIRCUITS

Figure 14 shows the CS5467 configured to measure

power in a singl e-pha se, 3- wire sys tem wh ile op erati ng

in a single-supply co nfiguration. In this diagr am, current

transformers (CT) are used to sense the line currents

and voltage dividers are used to sense the line voltages.

CS5467

IIN1-

20 IIN1+

PFMON

CPUCLK

XOUT

XIN Optional

Clock

Source

Serial

Data

Interface

RESET

CS 7

SDI 27

SDO 6

SCLK 5

INT 24

0.1 µF

VREFIN

VREFOUT

AGND DGND

17 4

4.096 MHz

RV-

ISOLATION

(Optional)

Pulse Output

Counter

CIdiff

CV+

CV-

CVdiff

IIN2-

IIN2+

RI-

RI+

CIdiff

VIN1-

VIN1+

LOAD

RI-

RI+

LOAD

RV-

CV+

CV-

CVdiff

VIN2-

VIN2+

VA+ VD+

0.1 µF470 µF

500 

2uF

500

L2 10 

30.1 µF

10 k



½ RBurden

CI-

CI+

CI-

CI+

Figure 14. Typical Connection Diagram (Single-phase, 3-wire – Direct Connect t o Power Line)

CS5467

44 DS714F3

12. PACKAGE DIMENSIONS

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch

and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in

excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more

than 0.07 mm at least material condition.

3. Th ese dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.084 -- -- 2.13

A1 0.002 0.006 0.010 0.05 0.15 0.25

A2 0.064 0.069 0.074 1.62 1.75 1.88

b 0.009 -- 0.015 0.22 -- 0.38 2,3

D 0.390 0.4015 0.413 9.90 10.20 10.50 1

E 0.291 0.307 0.323 7.40 7.80 8.20

E1 0.197 0.209 0.220 5.00 5.30 5.60 1

e 0.022 0.026 0.030 0.55 0.65 0.75

L 0.025 0.0354 0.041 0.63 0.90 1.03

0° 4° 8° 0° 4° 8°

JEDEC #: MO-150

Controlling Dimension is Millimeters

28L SSOP PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW



CS5467

DS714F3 45

13. ORDERING INFORMATION

14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Model Temperature Package

CS5467-ISZ (lead free) -40 to +85 °C 28-pin SSOP

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS5467-ISZ (lead free) 260 °C 3 7 Days

CS5467

46 DS714F3

15. REVISION HISTORY

Revision Date Changes

PP1 FEB 2007 Initial release.

PP2 FEB 2007 Corrections to implicitly state that temper ature measurement is a secondary func-

tion of voltage2 channel. Updated typical connection diagram. Changed Phase

Compensation Range from ±2.8° to ±5.4°.

F1 MAR 2007 Updated to F1 for qu ality process level (QPL).

F2 JAN 2010 Increased on-chip reference temperature coefficient from 25 ppm / °C typ. to

40 ppm / °C typ.

F3 APR 2011 Removed lead-containing (Pb) device ordering information.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available.

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for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents o r oth er righ ts of third

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