STU1N120 - STMicroelectronics, Inc.

Preliminary Data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

March 2008 Rev 2 1/11

STP1N120

STU1N120

N-channel 1200 V - 30 Ω - 500 mA - TO-220 - IPAK

Zener - protected SuperMESH™ Power MOSFET

Features

■100% avalanche tested

■Extremely high dv/dt capability

■ESD improved capability

■New high voltage benchmark

■Gate charge minimized

Application

■Switching applications

Description

The SuperMESH™ series is obtained through an

extreme optimization of ST’s well established

strip-based PowerMESH™ layout. In addition to

pushing on-resistance significantly down, special

care is taken to ensure a very good dv/dt

capability for the most demanding applications.

Such series complements ST full range of high

voltage Power MOSFETs including revolutionary

MDmesh™ products.

Figure 1. Internal schematic diagram

Type VDSS RDS(on)

max IDPW

STP1N120 1200 V < 38 Ω500 mA 45 W

STU1N120 1200 V < 38 Ω500 mA 45 W

TO-220

123

IPAK

Table 1. Device summary

Order codes Marking Package Packaging

STP1N120 1N120 TO-220 Tube

STU1N120 1N120 IPAK Tube

www.st.com

Contents STP1N120 - STU1N120

2/11

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

STP1N120 - STU1N120 Electrical ratings

3/11

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage (VGS=0) 1200 V

VGS Gate-source voltage ± 30 V

IDDrain current (continuous) at TC = 25 °C 500 mA

IDDrain current (continuous) at TC = 100 °C 315 mA

IDM (1)

1. Pulse width limited by safe operating area

Drain current (pulsed) 2 A

Derating factor 0.36 W/°C

PTOT Total dissipation at TC = 25 °C 45 W

Tstg Storage temperature -55 to 150 °C

TjMax operating junction temperature 150 °C

Table 3. Thermal data

Symbol Parameter Value Unit

TO-220 IPAK

Rthj-case Thermal resistance junction-case max 2.78 °C/W

Rthj-amb Thermal resistance junction-amb max 62.5 100 °C/W

TlMaximum lead temperature for soldering

purpose 300 °C

Table 4. Avalanche characteristics

Symbol Parameter Max value Unit

IAS Avalanche current, repetitive or not-

repetitive (pulse width limited by Tj max) 0.5 A

EAS

Single pulse avalanche energy

(starting Tj=25 °C, ID=IAS, VDD= 50 V) 300 mJ

Electrical characteristics STP1N120 - STU1N120

4/11

2 Electrical characteristics

(TCASE=25 °C unless otherwise specified)

Table 5. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source breakdown

voltage ID = 1 mA, VGS= 0 1200 V

IDSS

Zero gate voltage drain

current (VGS = 0)

VDS = Max rating,

VDS = Max rating,Tc=125 °C

µA

IGSS

Gate body leakage current

(VDS = 0) VGS = ± 30 V ±10 µA

VGS(th) Gate threshold voltage VDS= VGS, ID = 50 µA 345V

RDS(on) Static drain-source on

resistance VGS= 10 V, ID= 0.25 A 30 38 Ω

Table 6. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

gfs(1)

1. Pulsed: pulse duration=300µs, duty cycle 1.5%

Forward transconductance VDS = 20 V, ID = 0.25 A 1S

Ciss

Coss

Crss

Input capacitance

Output capacitance

Reverse transfer

capacitance

VDS =25 V, f=1 MHz, VGS=0

189

246 pF

Coss eq.(2)

2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

increases from 0 to 80% VDSS

Equivalent output

capacitance VGS = 0, VDS = 0 to 960 V 24 pF

Qgs

Qgd

Total gate charge

Gate-source charge

Gate-drain charge

VDD=960 V, ID = 500 mA

VGS =10 V

(see Figure 3)

7.3

1.3

4.4

RgIntrinsic gate resistance f= 1 MHz open drain 2.3 Ω

STP1N120 - STU1N120 Electrical characteristics

5/11

Table 7. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on)

td(off)

Turn-on delay time

Rise time

Turn-off delay time

Fall time

VDD=600 V, ID=0.25 A,

RG=4.7 Ω, VGS=10 V

(see Figure 5)

10.7

28.5

Table 8. Source drain diode

Symbol Parameter Test conditions Min Typ. Max Unit

ISD

ISDM

Source-drain current

Source-drain current (pulsed)

500

VSD(1)

1. Pulsed: pulse duration = 300µs, duty cycle 1.5%

Forward on voltage ISD= 500 mA, VGS=0 1.6 V

trr

Qrr

IRRM

Reverse recovery time

Reverse recovery charge

Reverse recovery current

ISD=500 mA,VDD=100 V

di/dt = 50 A/µs

(see Figure 4)

332

0.56

3.4

µC

trr

Qrr

IRRM

Reverse recovery time

Reverse recovery charge

Reverse recovery current

ISD=500 mA,VDD=100 V

di/dt=50 A/µs,Tj=150 °C

(see Figure 4)

326

0.58

6.3

µC

Table 9. Gate-source Zener diode

Symbol Parameter Test conditions Min Typ. Max Unit

BVGSO (1)

1. The built-in-back Zener diodes have specifically been designed to enhance not only the device’s ESD

capability, but also to make them safely absorb possibile voltage transients that may occasionally be

applied from gate to source. In this respect the zener voltage is appropriate to achieve an efficient and ost-

effective intervention to protect the device’s integrity. These integrated zener diodes thus avoid the usage

of external components.

Gate-source breakdown voltage Igs ± 1 mA, (open drain) 30 V

Test circuits STP1N120 - STU1N120

6/11

3 Test circuits

Figure 2. Switching times test circuit for

resistive load

Figure 3. Gate charge test circuit

Figure 4. Test circuit for inductive load

switching and diode recovery times

Figure 5. Unclamped inductive load test

circuit

Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform

STP1N120 - STU1N120 Package mechanical data

7/11

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect . The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com

Package mechanical data STP1N120 - STU1N120

8/11

TO-220 mechanical data

Dim mm inch

Min Typ Max Min Typ Max

A 4.40 4.60 0.1730.181

b0.61 0.88 0.024 0.034

b1 1.14 1.70 0.044 0.066

c0.480.70 0.0190.027

D 15.25 15.75 0.6 0.62

D1 1.27 0.050

E 10 10.40 0.393 0.409

e 2.40 2.70 0.094 0.106

e1 4.95 5.15 0.194 0.202

F1.231.32 0.0480.051

H1 6.20 6.60 0.244 0.256

J1 2.40 2.72 0.094 0.107

L1314 0.511 0.551

L1 3.50 3.93 0.137 0.154

L20 16.40 0.645

L3028.90 1.137

∅P3.75 3.85 0.147 0.151

Q2.65 2.95 0.104 0.116

STP1N120 - STU1N120 Package mechanical data

9/11

DIM. mm.

min. typ max.

A 2.20 2.40

A1 0.901.10

b0.64 0.90

b20.95

b4 5.20 5.40

c 0.45 0.60

c2 0.480.60

D 6.00 6.20

E 6.40 6.60

e2.28

e1 4.40 4.60

H 16.10

L9.00 9.40

(L1) 0.801.20

L2 0.80

V1 10 o

TO-251 (IPAK) mechanical data

0068771_H

Revision history STP1N120 - STU1N120

10/11

5 Revision history

Table 10. Document revision history

Date Revision Changes

11-Oct-2006 1 First release

20-Mar-2008 2 Added IPAK package, preliminary version

STP1N120 - STU1N120

11/11

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