2SJ530(L), 2SJ530(S)
Silicon P Channel MOS FET
High Speed Power Switching
ADE-208-655C (Z)
4th. Edition
Mar. 2001
Features
• Low on-resistance
RDS(on) = 0.08Ω typ.
• 4V gate drive devices.
• High speed switching.
Outline
123
44
123
DPAK–2
D
G
S
1. Gate
2. Drain
3. Source
4. Drain
2SJ530(L),2SJ530(S)
2
Absolute Maximum Ratings (Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS –60 V
Gate to source voltage VGSS ±20 V
Drain current ID–15 A
Drain peak current ID(pulse)Note1 –60 A
Body-drain diode reverse drain current IDR –15 A
Avalanche current IAP Note3 –15 A
Avalanche energy EAR Note3 19 mJ
Channel dissipation Pch Note2 30 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Note: 1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg ≥ 50 Ω
2SJ530(L),2SJ530(S)
3
Electrical Characteristics (Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS –60 — — V ID = –10mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS ±20 — — V IG = ±100µA, VDS = 0
Zero gate voltege drain current IDSS — — –10 µAV
DS = –60 V, VGS = 0
Gate to source leak current IGSS — — ±10 µAV
GS = ±16V, VDS = 0
Gate to source cutoff voltage VGS(off) –1.0 — –2.0 V ID = –1mA, VDS = –10V
Static drain to source on state RDS(on) — 0.08 0.10 ΩID = –8A, VGS = –10V Note4
resistance RDS(on) — 0.11 0.16 ΩID = –8A, VGS = –4V Note4
Forward transfer admittance |yfs| 6.5 11 — S ID = –8A, VDS = –10V Note4
Input capacitance Ciss — 850 — pF VDS = –10V
Output capacitance Coss — 420 — pF VGS = 0
Reverse transfer capacitance Crss — 110 — pF f = 1MHz
Turn-on delay time td(on) — 12 — ns VGS = –10V, ID = –8A
Rise time tr— 75 — ns RL = 3.75Ω
Turn-off delay time td(off) — 125 — ns
Fall time tf—75—ns
Body–drain diode forward voltage VDF — –1.1 — V IF = –15A, VGS = 0
Body–drain diode reverse
recovery time trr — 70 — ns IF = –15A, VGS = 0
diF/ dt =50A/µs
Note: 4. Pulse test
2SJ530(L),2SJ530(S)
4
Main Characteristics
40
30
20
10
050 100 150 200
–100
–30
–10
–3
–1
–0.3
–0.1
–0.1 –0.3 –1 –3 –10
–20
–16
–12
–8
–4
0–2 –4 –6 –8 –10 0 –1–2–3–4–5
–30 –100
–1000
–300
–3.5 V
–3 V
–20
–16
–12
–8
–4 –25 °C
25 °C
Tc = 75 °C
–10 V
–6 V
–5 V
100 µs
1 ms
Ta = 25 °C
10 µs
DS
Pulse Test
V = –10 V
–4 V
V = –2.5 V
GS
Pulse Test
PW = 10 ms (1 shot)
DC Operation
(Tc=25 )
Channel Dissipation Pch (W)
Case Temperature Tc (°C)
Power vs. Temperature Derating
Drain to Source Voltage V (V)
DS
Drain Current I (A)
D
Maximum Safe Operation Area
Drain to Source Voltage V (V)
DS
Drain Current I (A)
D
Typical Output Characteristics
Gate to Source Voltage V (V)
GS
Drain Current I (A)
D
Typical Transfer Characteristics
Operation in
this area is
limited by R
DS(on)
2SJ530(L),2SJ530(S)
5
500
200
100
20
50
10
5
–0.1 –0.3 –3 0 –10 –20 –30 –40 –50
5000
1000
300
100
0
–20
–40
–60
–80
0
0
–4
–8
–12
–16
–20–100 81624
32 40
1000
100
300
30
3
10
1
–0.1 –0.3 –1 –3 –10 –20
–1 –10
30
10
V = 0
f = 1 MHz
GS
Ciss
Crss
Coss
DS
V
GS
V
D
I = –15 A
V = –10 V
–25 V
–50 V
DD
V = –50 V
–25 V
–10 V
DD
tf
r
t
d(off)
t
d(on)
t
DD
V = –10 V, V = –30 V
Pw = 5 µs, duty < 1 %
GS
di / dt = 50 A / µs
V = 0, Ta = 25 °C
GS
–20
Reverse Drain Current I (A)
DR
Reverse Recovery Time trr (ns)
Body–Drain Diode Reverse
Recovery Time
Capacitance C (pF)
Drain to Source Voltage V (V)
DS
Typical Capacitance vs.
Drain to Source Voltage
Gate Charge Qg (nc)
Drain to Source Voltage V (V)
DS
Gate to Source Voltage V (V)
GS
Dynamic Input Characteristics
Drain Current I (A)
D
Switching Time t (ns)
Switching Characteristics
2SJ530(L),2SJ530(S)
6
–20
–16
–12
–8
–4
0–0.4 –0.8 –1.2 –1.6 –2.0
D. U. T
Rg
I
Monitor
AP
V
Monitor
DS
V
DD
50W
Vin
–15 V
0
I
D
V
DS
I
AP
V
(BR)DSS
L
V
DD
E = • L • I •
2
1V
V – V
AR AP DSS
DSS DD
2
V = 0, 5 V
GS
–10 V
–5 V
Pulse Test 20
16
12
8
4
25 50 75 100 125 150
0
I = –15 A
V = –25 V
duty < 0.1 %
Rg > 50
AP
DD
W
Repetitive Avalanche Energy E (mJ)
AR
Maximum Avalanche Energy vs.
Channel Temperature Derating
Avalanche Test Circuit Avalanche Waveform
Source to Drain Voltage V (V)
SD
Reverse Drain Current I (A)
DR
Reverse Drain Current vs.
Source to Drain Voltage
Channel Temperature Tch (°C)
2SJ530(L),2SJ530(S)
7
3
1
0.3
0.1
0.03
0.01
10 µ 100 µ 1 m 10 m 100 m 1 10
DM
P
PW
T
D = PW
T
ch – c(t) = s (t) • ch – c
ch – c = 4.17 °C/W, Tc = 25 °C
q g q
q
D = 1
0.5
0.2
0.01
0.02
0.1
0.05
1 shot Pulse
Tc = 25°C
Vin Monitor
D.U.T.
Vin
–10 V
R
L
V
= –30 V
DD
tr
td(on)
Vin
90% 90%
10%
10%
Vout
td(off)
Vout
Monitor
50W
90%
10%
t
f
Switching Time Test Circuit Waveform
Pulse Width PW (S)
Normalized Transient Thermal Impedance
s (t)
g
Normalized Transient Thermal Impedance vs. Pulse Width
2SJ530(L),2SJ530(S)
8
Package Dimensions
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DPAK (L)-(2)
—
—
0.42 g
6.5 ± 0.5 2.3 ± 0.2
0.55 ± 0.1
1.2 ± 0.3
0.55 ± 0.1
5.5 ± 0.5 1.7 ± 0.5
16.2 ± 0.5
4.7 ± 0.5
5.4 ± 0.5
1.15 ± 0.1
2.29 ± 0.5 2.29 ± 0.5
0.8 ± 0.1
0.55 ± 0.1
3.1 ± 0.5
(0.7)
As of January, 2001
Unit: mm
2SJ530(L),2SJ530(S)
9
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DPAK (S)-(1),(2)
—
Conforms
0.28 g
As of January, 2001
Unit: mm
6.5 ± 0.5
5.4 ± 0.5 2.3 ± 0.2
0.55 ± 0.1
0 – 0.25
0.55 ± 0.1
1.7 ± 0.5
5.5 ± 0.5
2.5 ± 0.5
1.15 ± 0.1
0.8 ± 0.1
2.29 ± 0.5
2.29 ± 0.5
1.2 Max
(4.9)
(5.3)
2SJ530(L),2SJ530(S)
10
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DPAK (S)-(3)
—
Conforms
0.28 g
As of January, 2001
Unit: mm
6.5 ± 0.5
5.4 ± 0.5 2.3 ± 0.2
0.55 ± 0.1
0 – 0.25
0.55 ± 0.1
1.5 ± 0.5
5.5 ± 0.5
2.5 ± 0.5
1.15 ± 0.1
0.8 ± 0.1
2.29 ± 0.5
2.29 ± 0.5
1.2 Max
(5.1)
(5.1)
(0.1)(0.1)
2SJ530(L),2SJ530(S)
11
Cautions
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
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for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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