VersaClock(R) 5 - 5P49V5907/08 Evaluation Boards USER GUIDE Introduction The evaluation board is designed to help the customer evaluate the 5P49V5907/08, the latest addition to the family of programmable devices in IDT's Timing portfolio. When the board is connected to a PC running IDT Timing CommanderTM Software through USB, the device can be configured and programmed to generate frequencies with best-in-class performances. Board Overview Use the following diagram and table to identify: power supply jacks, USB connector, input and output frequency SMA connectors. Figure 1. Board Overview REVISION A 06/24/15 1 (c)2015 Integrated Device Technology, Inc. VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Table 1: EBV Pins and Functions Item Name On-Board Connector Label Function 1 Output 0 J3 Single ended buffered output of input reference clock 2 Power Supply Jack J16 Connect 1.8V for the core voltage of the device 3 Output 7/7B J32/31 4 Output Voltage Power Supply Selector JP3 5 Xin J6 Single ended clock input. Maximum full swing limited to 1.2V 6 5P49V5907/08 U1 Evaluation Device 7 Aardvark Connector JP1 For Aardvark connection 8 Output 6/6B J30/J29 9 DIP Switch U2 S1: Output Enable (OE/SD) S2: Sel0 S3: Sel1 S4: Output Enable Buffer (OE_BUFFER) S5: Output Enable Buffer (for outputs 3 and 5) S6: Output Enable Buffer (for outputs 6 and 7) S8: Sel [1:0] ; Default: I2C mode 10 USB Interface J18 Used for connection with a PC and for interaction with the IDT Timing Commander Software. 11 Output 1/1B J20/J19 Can be differential pair output or two individual single ended outputs 12 Output 2/2B J22/J21 Can be differential pair output or two individual single ended outputs 13 Output Voltage Power Supply Selector OUT0_SELB_I2C:JP2 OUT1:JP4 OUT2:JP6 OUT4:JP8 4-way header to select a power supply method for outputs 0,1,2 and 4. The center pin is the output voltage. Use jumper J15 to select a 1.8V, 2.5V or 3.3V supply. VDDO_J_OUT0/1/2/4 is the voltage from J15 14 Output 3/3B J26/J25 15 Ground Jack J17 Used for grounding. If J15 and/or J16 is used for power supply, this jack functions as the power return. 16 Output Voltage Jack J33 Low power HCSL voltage jack that provides1.8V supply 17 Output Voltage Power Supply Selector JP7 3-way header to select a power supply of 1.8V through regulator supply or the output voltage from J33 to the LP-HCSL outputs 3, 5 - 7 outputs for the 5P49V5907 and output 3, 5-11 for the 5P49V5908. The center pin is the output voltage. VDDO_LP_HCSL is the voltage from J33 18 Output 4/4B J24/J23 Low Power HCSL differential output 19 Output 5/5B J28/J27 Low Power HCSL differential output 20 Output Voltage Jack J15 Low Power HCSL differential output Provides selection of 1.8V supply from regulators or supply from J16 Low Power HCSL differential output Low Power HCSL differential output Connect to 1.8V, 2.5V or 3.3V to provide output voltage supply In addition to the 5P49V5907 pinouts, 5P49V5908 has the following four outputs (refer to Table 2 below): 2 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Table 2: 5P49V5908 Extra Outputs Item Name On-Board Connector Label Function 21 Output 8/8B J34/J33 Low Power HCSL differential output 22 Output 9/9B J36/J35 Low Power HCSL differential output 23 Output 10/10B J38/J37 Low Power HCSL differential output 24 Output 11/11B J40/J39 Low Power HCSL differential output Board Power Supply Power Supply Options Bench Power Supply - An external power supply can be used to supply a 1.8V supply. To supply VDDA_1 with a bench power supply, connect power to J16. Concurrently, place the jumpers in JP3 to connect VDDA_1 to VDDD_J. USB Power Supply - When the board is connected to a PC through a USB cable, on-board voltage regulators will generate a 3.3V for the device. In this case, place the jumpers in JP3 to connect VDDA_1 to VDDA/D. See JP3 jumper position for VDDA/D in the Figure 2. USB power source is recommended for ease of use. Figure 2. Selecting the VDDA/D side will select power source from on-board regulators powered by USB; Selecting the VDDD_J side will select external bench power supply Output Clock Voltages Similar to VDDA/D having two sources, each output voltage is also provided with two sources to choose from: Bench power supply or USB power supply connection. The selection is made by a 4-way header as shown in Figure 3 below and a 3-way header as shown in Figure 4. Selection of VDDO_J_OUT0/1/2/4 will enable external power supply (J15 and J16 are connected to external power supply); Selection of 1.8V, 2.5V or 3.3V will enable each on-board voltage regulators powered by USB port. REVISION A 06/24/15 3 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 3. In the 4-way header, the central pin is the output and the other pins are 1.8V, 2.5V, 3.3V and VDDO_J_OUT 0/1/2/4(from J15) respectively. Jumper settings are selected according to the output voltage required for outputs 0, 1, 2 and 4. Note: Each output voltage can be individually selected. Use table 3 to select the jumper pin for its respective output: Table 3: Output Voltage Selection for 5P49V5907/5P49V5908 5P49V5907 5P49V5908 Pin Label Output Pin Label Output VDDO_0 OUT0 VDDO_0 OUT0 VDDO_1 OUT1 VDDO_1 OUT1 VDDO_2 OUT2 VDDO_2 OUT2 VDDO_4 OUT4 VDDO_4 OUT4 VDDO_3_5_6_7 OUT3, OUT5, OUT6, OUT7 VDDO_3_5-11 OUT3, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10, OUT11 4 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 4. In the 3-way header, the middle pin is the output node and the 1.8V and VDDO_LP_HCSL on either side. Jumper settings are selected according to the output voltage required for outputs 3, 5, 6 and 7. Connecting the Board The board is connected to a PC through a USB connector for configuring and programming the device, as shown in Figure 5 below. The USB interface will also provide +5V power supply to the board, from which on-board voltage regulators generate various voltages for the core as well as for each output. The board can also be powered by a bench power supply by connecting two banana jacks J15, J16 for output and core voltages, respectively. Please see board power supply section for details. Note: The USB port only supports USB 2.0; USB 3.0 is not supported at this time. REVISION A 06/24/15 5 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 5. Connecting 5P49V5907 - EBV USB Port for Communications with Timing Commander Software and input voltage supplies Software On-Board Crystal A 25MHz crystal is installed on the board. Board Default Frequency Output When 25MHz crystal is installed, the device will have two default outputs: OUT0 = 25MHz, OUT1 = 100MHz. 6 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Configuration and Setup Use the following steps to setup the board using I2C and start the configuration of the board. 1. Set SEL pin (pin 8) of dip switch (U2) to "0" to select I2C mode. 2. Connect J18 to a USB port of the PC using the supplied I2C cable. 3. Launch VC5 Timing Commander Software (refer to VC5 Timing Commander User Guide - Getting Started Step 1~7) Download the VersaClock 5 Timing Commander User Guide Here 4. Following the Getting Started steps in the Timing Commander software, an I2C connection is established between the GUI software and the VersaClock 5 chip. 5. Select "Open Settings File" if you have existing settings or "New Settings File" and select 5P49V5907 or 5P49V5908 depending on your evaluation board. In the same screen, browse for a personality file, by clicking on the button at the bottom right, to be used with the evaluation board. 6. Connect to the EVB by clicking on the microchip icon located at the top right of the Timing Commander. 7. Once connected, new options will be available on a green background indicating that the EVB has successfully connected with the board. Write the settings to the chip by clicking on the write all registers to the chip option. 8. All intended outputs should now be available for measurement. Board Schematics Evaluation board schematics are shown on the following pages. REVISION A 06/24/15 7 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 6. 5P49V5907 VersaClock 5 Evaluation Board Schematics - Page 1 Figure 7. 5P49V5907 VersaClock 5 Evaluation Board Schematics - Page 2 8 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 8. 5P49V5907 Evaluation Board Schematics - Page 3 REVISION A 06/24/15 9 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 9. 5P49V5907 Evaluation Board Schematics - Page 4 10 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 10. 5P49V5908 Evaluation Board Schematics - Page 1 Figure 11. 5P49V5908 Evaluation Board Schematics - Page 2 11 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 12. 5P49V5908 Evaluation Board Schematics - Page 3 12 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 13. 5P49V5908 Evaluation Board Schematics - Page 4 Signal Termination Options Termination options for OUTPUT 1 - 7 for the 5P49V5907 EBV board are displayed in Figure 14 and termination options for OUTPUT 1 - 7 for the 5P49V5908 EBV board are displayed in Figure 15 and Figure 16. The termination circuits are designed to optionally terminate the output clocks in LVPECL, LVDS, LVCMOS and LP-HCSL signal types by populating (or not-populating) some resistors. Default termination configurations which are pre-installed on the EVB are indicated in the tables. DC or AC coupling of these outputs are also supported. Table 4 - 7, tabulate component installations to support LVPECL, LP-HCSL, LVCMOS and LVDS signal types for OUTPUT1- 7 on the 5P49V5907 EBV and Table 8 - 11, tabulate component installations to support LVPECL, LP-HCSL, LVCMOS and LVDS signal types for OUTPUT1- 11 on the 5P49V5908 EBV, respectively. Please note that by doing so, the output signals will be measured and terminated by an oscilloscope with a 50 internal termination. 13 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 14. 5P49V5907 Output Termination Options LVCMOS 14 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Termination Options for 5P49V5907 Table 4: Termination Configuration for OUTPUT1 Signal Type Series Resistors: R108,R109 Pull-down Resistors: R80, R112, R113 Series Capacitor: C86, C87 Resistor Network: R18, R19, R23, R24 LVPECL* 0 R80=R112=150 , R113=0 , 0.1 F Not installed Table 5: Termination Configuration for OUTPUT2 Signal Type Series Resistors: R110,R111 150-ohm pull-down: R81, R82, R83 Series Capacitor: C88, C89 Resistor Network: R30, R31, R35, R36 LVDS* 0 Not installed 0.1 F Not installed Table 6: Termination Configuration for OUTPUT3, 5-7 Signal Type Series Resistors: R91,R92; R93,R94; R95,R96; R97,R98 150-ohm pull-down: R21, R22 Series Capacitor: C78,C79; C80,C81; C82,C83; C84,C85 Resistor Network: R41, R42, R51, R52 LPHCSL* 33 Not Installed 0.1 F Not installed Table 7: Termination Configuration for OUTPUT4 Signal Type Series Resistors: R87, R88 150-ohm pull-down: R89, R90 Series Capacitor: C76, C77 Resistor Network: R38, R40, R47, R48 LVCMOS* 33 Not installed 0.1 F Not installed LVDS Not Installed Not installed 0.1 F Not installed As noted, 4-resistor network is not installed in Table 4-7 because oscilloscope with internal 50 termination is utilized for signal termination and measurement. If an AC-coupled, stand-alone LVPECL output is needed (without oscilloscope connections), the 4-resistor network needs to be installed accordingly. * This signal type is the default configuration for the evaluation board. Contact IDT if user wants to change termination configurations to support other output signal types. 15 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 15. 5P49V5908 Output Termination Options (a) LVCMOS TERMINATION Note: For 2.5V and 3.3V HCSL termination, the C90 and C91 positions need to be assembled with 0 resistors. 16 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Figure 16. 5P49V5908 Output Termination Options (b) Termination Options for 5P49V5908 Table 8: Termination Configuration for OUTPUT1 Signal Type Series Resistors: R127,R128 Pull-down Resistors: R107, R132, R133 Series Capacitor: C92, C93 Resistor Network: R109, R110, R111, R112 LVPECL* 0 R107=R132=150 , R133=0 0.1 F Not installed Table 9: Termination Configuration for OUTPUT2 Signal Type Series Resistors: R129,R130 Pull-down Resistors: R108, R82, R83 Series Capacitor: C94, C95 Resistor Network: R113, R114, R115, R116 LVDS* 0 Not installed 0.1 F Not installed 17 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Table 10: Termination Configuration for OUTPUT3, 5-11 Signal Type Series Resistors: R134, R135; R93, R94; R95, R96; R97, R98; R117, R118; R119, R120; R121, R122; R123, R124; 150-ohm pull-down: R21, R22 Series Capacitor: C12, C14 Resistor Network: R41, R42, R51, R52 LPHCSL* 33 Installed 0.1 F Not installed Table 11: Termination Configuration for OUTPUT4 Signal Type Series Resistors: R87, R88 150-ohm pull-down: R89, R90 Series Capacitor: C90, C91 Resistor Network: R38, R40, R47, R48 LVCMOS* 33 Not installed 0.1 F Not installed As noted, 4-resistor network is not installed in Table 8-11 because oscilloscope with internal 50 termination is utilized for signal termination and measurement. If an AC-coupled, stand-alone LVPECL output is needed (without oscilloscope connections), the 4-resistor network needs to be installed accordingly. * This signal type is the default configuration for the evaluation board. Contact IDT if user wants to change termination configurations to support other output signal types. 18 REVISION A 06/24/15 VERSACLOCK(R) 5 - 5P49V5907/08 Evaluation Boards Orderable Part Numbers The following evaluation board part numbers are available for order. Table 12: Orderable Part Numbers Part Number Description EVKVC5-5907ALL 5P49V5907 Evaluation board with one output of each type of signal termination. EVKVC5-5908ALL 5P49V5908 Evaluation board with one output of each type of signal termination. 19 REVISION A 06/24/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com 480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright (c)2015 Integrated Device Technology, Inc.. All rights reserved.