CAT-5 Receiver with
Adjustable Line Equalization
AD8128
Rev. 0
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Tuned to compensate for Category-5 (CAT-5) cable losses
Up to 100 meters @ 120 MHz
2 voltage-controlled frequency response adjustment pins
High frequency peaking adjustment
Broadband gain adjustment
2700 V/μs slew rate
Low output noise
1.5 mV rms integrated noise (1 GHz) @ 100 meters
equalized bandwidth
DC output offset adjust
Low offset voltage error: 7 mV typ
Equalized pass-band ripple ±1 dB to 70 MHz
Input: differential or single ended
Supply current: 24 mA on ±5 V
Small 8-lead 3 mm × 3 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
RGB video over unshielded twisted pair (UTP) cable receivers
Professional video projection and distribution
Security video
FUNCTIONAL BLOCK DIAGRAM
V
OFFSET
V
GAIN
V
PEAK
V
OUT
V
IN+
V
IN–
AD8128
05699-001
HPF
HPF
LPF
Figure 1.
GENERAL DESCRIPTION
The AD8128 is a high speed, differential receiver/equalizer that
compensates for the transmission losses of unshielded twisted
pair (UTP) CAT-5 cables. Various frequency dependent gain
stages are summed together to best approximate the inverse
frequency response of CAT-5/CAT-5e cable. An equalized
bandwidth of 120 MHz can be achieved for 100 meters of cable.
The AD8128 can be used as a standalone receiver/equalizer or
in conjunction with the AD8143, triple differential receiver, to
provide a complete low cost solution for receiving RGB over
UTP cable in such applications as KVM.
The AD8128 has three control pins for optimal CAT-5/CAT-5e
compensation. The equalized cable length is directly proportional
to the voltage applied to the VPEAK pin, which controls the
amount of high frequency peaking. VGAIN adjusts the broadband
gain from 0 dB to 3 dB, compensating for the resistive cable
loss. VOFFSET allows the output to be shifted by ±2.5 V, adding
flexibility for dc-coupled systems.
Low integrated output noise and offset voltage adjust make the
AD8128 an excellent choice for dc-coupled wideband RGB-
over-CAT-5 applications. For systems where the UTP cable is
longer than 100 meters, two AD8128s can be cascaded to
compensate for up to 200 meters of CAT-5/CAT-5e.
The AD8128 is available in a 3 mm × 3 mm 8-lead LFCSP and
is rated to operate over the extended temperature range of
−40°C to +85°C.
AD8128
Rev. 0 | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Test Circ uit .................................................................................... 8
Theory of Operation .........................................................................9
Input Common-Mode Voltage Range Considerations ............9
Applications..................................................................................... 10
KVM Applications ..................................................................... 10
DC Control Pins......................................................................... 10
Cascaded Applications............................................................... 11
Exposed Pad (EP)....................................................................... 11
Layout and Power Supply Decoupling Considerations......... 11
Evaluation Boards ...................................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
10/05—Revision 0: Initial Version
AD8128
Rev. 0 | Page 3 of 12
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable, VOFFSET = 0 V, VGAIN and VPEAK set to optimized settings (see Figure 4), unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth VOUT = 2 V p-p, 100 meter CAT-5 120 MHz
±1 dB Equalized Bandwidth Flatness VOUT = 2 V p-p 70 MHz
Rise/Fall Time VOUT = 2 V step, 50 meter CAT-5 2 ns
Rise/Fall Time VOUT = 2 V step, 100 meter CAT-5 3.6 ns
Settling Time to 2% VOUT = 2 V step, 50 meter CAT-5 26 ns
Settling Time to 2% VOUT = 2 V step, 100 meter CAT-5 36.4 ns
Integrated Output Voltage Noise VPEAK = 0.9 V, VGAIN = 225 mV, BW = 1 GHz 1.5 mV rms
DC PERFORMANCE
Input Bias Current 15.5 24 μA
VOFFSET Pin Current 1.7 8.2 μA
VGAIN Pin Current 2 3.4 μA
VPEAK Pin Current 4.2 6.8 μA
INPUT CHARACTERISTICS
Input Differential Voltage ±2.8 V
Input Common-Mode Voltage ±3.0 V
Input Resistance Common mode 380 kΩ
Differential 675 kΩ
Input Capacitance 1.7 pF
Common-Mode Rejection Ratio (CMRR) 200 kHz, ΔVOUT/ΔVIN, cm −63 −74 dB
ADJUSTMENT PINS
VPEAK Input Voltage Relative to ground 0 1 V
Maximum Peak Gain @ 120 MHz, VPEAK = 1 V 20 dB
VGAIN Input Relative to ground 0 1 V
Maximum Broadband Gain VGAIN = 1 V 3 dB
VOFFSET Input Range Relative to ground ±2.5 V
VOFFSET to VOUT Gain 1 V/V
OUTPUT CHARACTERISTICS
Output Voltage Swing −2.55 +2.7 V
Output Offset Voltage VOFFSET = 0 V, RTO −10.9 +7 +18.7 mV
Output Offset Voltage Drift −5.5 μV/°C
Short-Circuit Output Current 100 mA
POWER SUPPLY
Operating Voltage Range ±4.5 ±5.5 V
Quiescent Supply Current, ICC/IEE @ ±5 V +24/−21 +31/−27 mA
Supply Current Drift, ICC/IEE +86/−77 μA/°C
+Power Supply Rejection Ratio (PSRR) RTO −48 −59 dB
−Power Supply Rejection Ratio (PSRR) RTO −48 −61 dB
TEMPERATURE RANGE −40 +85 °C
AD8128
Rev. 0 | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±5.5 V
Input Voltage ±VS
VPEAK and VGAIN Control Pins −3 V to +VS
VOFFSET Control Pins ±VS
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θJC Unit
8-Lead LFCSP 77 14 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8128 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8128. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for the output. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through-holes, ground, and power planes reduces
the θJA. The exposed paddle on the underside of the package
must be soldered to a pad on the PCB surface, which is
thermally connected to a copper plane to achieve the specified θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead LFCSP
(48.5°C/W) on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. Extra thermal relief is required for operation at
high supply voltages.
3.0
0
–30–40 –10–20 1003020 5040 7060 9080 110100 130120
05699-020
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIP
A
TION (W)
2.5
2.0
1.5
1.0
0.5
Figure 2. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8128
Rev. 0 | Page 5 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1V
IN+
2V
IN–
3V
GAIN
4
V
PEAK
7V
OFFSET
8VS+
6V
OUT
5VS–
TOP VIEW
(Not to Scale)
AD8128
05699-002
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN+ Positive Equalizer Input
2 VIN− Negative Equalizer Input
3 VGAIN 0 V to 1 V Broadband Gain Control
4 VPEAK 0 V to 1 V High Frequency Gain Control
5 VS− Negative Power Supply
6 VOUT Equalizer Output
7 VOFFSET DC Offset Adjust
8 VS+ Positive Power Supply
EP GND Ground Reference and Thermal Pad (see Exposed Pad (EP) section).
AD8128
Rev. 0 | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable, VOFFSET = 0 V, unless otherwise noted.
1.0
0
0 100
05699-003
CABLE LENGTH (M)
OPTIMIZED V
PEAK
AND V
GAIN
(V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
10 20 30 40 50 60 70 80 90
V
OUT
=2Vp-p
R
L
= 150
V
PEAK
V
GAIN
Figure 4. VPEAK and VGAIN Settings vs. Cable Length
10
20
30
–70
05699-014
FREQUENCY (MHz)
MAGNITUDE (dB)
0
–10
–20
–30
–40
–50
–60
0.1 1 10 100 1k 3k
V
PEAK
=1V
V
PEAK
=0.5V
V
PEAK
=0V
Figure 5. Frequency Response for Various VPEAK Settings Without Cable
10
–70
05699-013
FREQUENCY (MHz)
MAGNITUDE (dB)
0
–10
–20
–30
–40
–50
–60
0.1 1 10 100 1k 3k
V
GAIN
=1V V
GAIN
=0.5V
V
GAIN
=0V
Figure 6. Frequency Response for Various VGAIN Settings Without Cable
2
–10
0.1
05699-012
FREQUENCY (MHz)
MAGNITUDE (dB)
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
1 10 100 300
V
PEAK
AND V
GAIN
SETTINGS ARE CONSISTENT
WITH OPTIMIZED SETTINGS IN FIGURE 4
V
OUT
=2Vp-p
R
L
= 150
Figure 7. Equalized Frequency Response for 50 M Cable
2
–10
0.1
05699-011
FREQUENCY (MHz)
MAGNITUDE (dB)
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
1 10 100 300
V
PEAK
AND V
GAIN
SETTINGS ARE CONSISTENT
WITH OPTIMIZED SETTINGS IN FIGURE 4
V
OUT
=2Vp-p
R
L
= 150
Figure 8. Equalized Frequency Response for 100 M Cable
1.5
–1.5
0 200
05699-010
TIME (ns)
OUTPUT (V)
1.0
0.5
0
–0.5
–1.0
20 40 60 80 100 120 140 160 180
V
PEAK
AND V
GAIN
SETTINGS ARE
CONSISTENT WITH OPTIMIZED
SETTINGS IN FIGURE 4
Figure 9. Equalized Pulse Response for 50 M of Cable
AD8128
Rev. 0 | Page 7 of 12
1.5
–1.5
0 200
05699-009
TIME (ns)
OUTPUT (V)
1.0
0.5
0
–0.5
–1.0
20 40 60 80 100 120 140 160 180
V
PEAK
AND V
GAIN
SETTINGS ARE
CONSISTENT WITH OPTIMIZED
SETTINGS IN FIGURE 4
Figure 10. Equalized Pulse Response for 100 M of Cable
40
–40
–4 4
05699-008
V
IN, CM
(V)
V
OUT
(mV)
30
20
10
0
–10
–20
–30
–3 –2 –1 0 1 2 3
Figure 11. Output Voltage vs. Common-Mode Input Voltage
100
10
0.1 1k
05699-007
FREQUENCY (MHz)
VOLTAGE NOISE (nV/ Hz)
1 10 100
V
PEAK
=0V
V
GAIN
=0V
V
PEAK
=0.9V
V
GAIN
= 0.225V
Figure 12. Voltage Noise vs. Frequency
1.8
0
01.0
05699-006
V
PEAK
(V)
INTEG
R
ATED VOLTAGE NOISE FROM 100kHz TO
1GHz (mV)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
GAIN
SETTINGS ARE CONSISTENT
WITH OPTIMIZED SETTINGS IN FIGURE 4
Figure 13. Integrated Voltage Noise vs. VPEAK
6
–6
0 500
05699-005
TIME (ns)
VOLTAGE (V)
4
2
0
–2
–4
50 100 150 200 250 300 350 400 450
V
PEAK
=0V
V
GAIN
=0V
OUTPUT
INPUT
Figure 14. Overdrive Recovery Time
20
–80
0.1 1k
05699-004
FREQUENCY (MHz)
COMMON-MODE REJECTION (dB)
1 10 100
10
0
–10
–20
–30
–40
–50
–60
–70
V
GAIN
=1V
V
PEAK
=1V
V
GAIN
=0V
V
PEAK
=0V
Figure 15. Common-Mode Rejection vs. Frequency
AD8128
Rev. 0 | Page 8 of 12
10
–70
0.001 1k
05699-015
FREQUENCY (MHz)
POWE
R
SUPPLY REJECTION (dB)
0.01 0.1 1 10 100
0
–10
–20
–30
–40
–50
–60
–PSR
+PSR
V
OS
=0V
V
PEAK
=0V
V
GAIN
=0V
Figure 16. Power Supply Rejection vs. Frequency
TEST CIRCUIT
V
OFFSET
V
OFFSET
V
GAIN
V
GAIN
V
PEAK
V
PEAK
V
IN+
V
IN–
AD8128
HPF
HPF
LPF
05699-021
+
+
V
S+
V
S
–
1µF 10µF 10µF
0.01µF
VS+
V
S+
1µF 0.01µF
0.01µF 0.01µF 0.01µF
VS–
VS–
50
50
CAT-5 V
OUT
Figure 17.
AD8128
Rev. 0 | Page 9 of 12
THEORY OF OPERATION
The AD8128 is a high speed, low noise analog line equalizer
that compensates for losses in CAT-5/CAT-5e cables up to
100 meters with ±1 dB flatness in the pass band out to 70 MHz
(see Figure 8). Two continuously adjustable control voltages
alter the frequency response to add flexibility to the system by
allowing for the compensation of various cable lengths as well
as for variations in the cable itself. The dc control voltage pin
VGAIN adjusts ac broadband gain from 0 dB to 3 dB (see Figure 6) to
account for dc resistive losses present in the cable. A second dc
control voltage pin VPEAK adjusts the amount of high frequency
peaking (see Figure 5) from 0 dB to 20 dB. This compensates
for the high frequency loss due to the skin effect of the cable.
The AD8128 has a high impedance differential input that allows
it to receive dc-coupled signals directly from the cable. For
systems with very high CMRR specifications, the AD8128 can
also be used with a dedicated receiver, such as the AD8130 or
AD8143, placed in front of it. The output of the AD8128 is low
impedance and is capable of driving a 150 Ω load resistor and
up to 20 pF of load capacitance at its output. For systems with
high parasitic capacitances at the output, it is recommended
that a small series resistor be placed between the output and
capacitive load to reduce ringing in the pulse response.
The AD8128 is designed to be used in medium-length systems
that have stringent low noise requirements as well as longer-
length systems that can tolerate more noise. For the medium-
length requirements, a single AD8128 is able to compensate up
to 100 meters of cable with only 1.5 mV rms of output noise.
For longer-length applications that require equalization of up to
200 meters of cable, two AD8128s can be cascaded together to
achieve the desired equalization, while keeping approximately
the same pass-band bandwidth, but with a slight degradation in
settling time and slew rate.
The frequency response of the AD8128 approximates the
inverse frequency response of a lossy transmission line, which
is given by
()
()
fjkl
efH +
=1 (1)
where:
f is the frequency.
l is the length.
k is the line constant.
The AD8128 approximates the magnitude response of
Equation 1 by summing multiple zero-poles pairs offset at
different frequencies. Equalization adjustment due to varying
line lengths is done by changing the weighting factors of each of
the zero-pole pairs.
INPUT COMMON-MODE VOLTAGE RANGE
CONSIDERATIONS
When using the AD8128 as a receiver, it is important to ensure
that the input common-mode (CM) voltage range of the AD8128
stays within the specified range. The input CM level can be
easily calculated by adding the CM level of the driver, the
amplitude of any sync pulses, and the other possible induced
common-mode signals from power lines and fluorescent lights.
VICM = VCM + VSYNC + VOTHER (2)
For example, when using a single 5 V supply on the drive side,
the CM voltage of the line typically becomes the midsupply
voltage, VCM = 2.5 V. Furthermore, an addition of a sync signal,
VSYNC = 0.5 V, on to the common mode puts the peak CM
voltage at 3 V. Assuming that both the driver and receiver have
exactly the same ground potential, the signal is marginally
below the upper end of the common-mode input range of 3.1 V.
Other CM signals that can be picked up by the CAT-5 cable
result in exceeding the CM input range of the AD8128.
The most effective way of not exceeding the CM level of the
AD8128 is to lower the CM level on the driver. In the previous
example, this was the primary contributor to the CM input
level. If this is not possible, a dedicated receiver with a wider
CM input range, such as the AD8130 or AD8143, should be used.
AD8128
Rev. 0 | Page 10 of 12
APPLICATIONS
KVM APPLICATIONS
In KVM applications, cable equalization typically occurs at the
root of the KVM network. In a star configuration, a driver is
located at each of the end nodes and a receiver/equalizer is
located at the single root node. In a daisy-chain configuration,
each of the end nodes are connected to one another, and one of
them is connected to the root. Similarly, the drivers are placed
on the nodes, and the receivers/equalizers are placed at the root.
In both of these aforementioned configurations, three AD8128
receiver/equalizers can be used at the root node to equalize the
transmitted red (R), green (G), and blue (B) channels for up to
100 meters of cable. Since the skew between two pairs of cables
in CAT-5 is less than 1%, the control pins can be tied together
and used as a single set of controls.
If the common-mode levels of the inputs permit using the
AD8128 as a receiver (see the Input Common-Mode Voltage
Range Considerations section), the input signal should be
terminated by a 100 Ω shunt resistor between the pairs, or by
two 50 Ω shunt resistors with a common-mode tap in the
middle. This CM tap can be used to extract the sync information
from the signal if sync-on-common-mode is used.
V
OFFSET
V
GAIN
V
PEAK
V
OUT
V
IN+
V
IN–
AD8128
HPF
HPF
LPF
V
CM
50
50
V
CM
V
DIFF
V
CM
V
DIFF
CAT-5
05699-016
Figure 18. Single Receiver Configuration for CAT-5 Equalizer
DC CONTROL PINS
The AD8128 uses two control pins (VGAIN and VPEAK) to adjust
the equalization based on the length of the cable and one pin
(VOFFSET) to adjust the dc output offset. VGAIN is a user-adjustable
0 V to 1 V broadband gain control pin, and VPEAK is a 0 V to 1 V
adjustable high frequency gain pin to equalize for the skin effect
in CAT-5 cable. The values of both VPEAK and VGAIN are linearly
correlated to the length of the cable to be equalized. A simple
formula can be used to approximate the desired values for both
of these pins.
425m/V
)(mlength
VGAIN = (3)
110m/V
)(mlength
VPEAK = (4)
While these equations give a close approximation of the desired
value for each pin, to achieve optimal performance, it may be
necessary to adjust these values slightly.
Figure 19 and Figure 20 illustrate circuits used to adjust the
control pins on the AD8128. In Figure 19, a 1 kΩ potentiometer
is used to adjust the control pin voltage between the specified
range of 0 V to 1 V. In Figure 20, a 2 kΩ potentiometer is used
to control the offset pin from −2.5 V to +2.5 V. For both of these
configurations, a ±5V supply is assumed.
CONTROL PIN
V
GAIN
OR V
PEAK
0.01µF
+5
V
4k
1k
0
5699-017
Figure 19. Circuit to Control VGAIN and VPEAK (0 V to 1 V)
OFFSET
0.01µF
+5
V
–5V
1k
1k
2k
05699-018
Figure 20. Circuit to Control VOFFSET (±2.5 V)
AD8128
Rev. 0 | Page 11 of 12
V
OFFSET
V
GAIN
V
PEAK
V
OFFSET
V
GAIN
V
PEAK
V
OUT
V
IN+
V
IN–
AD8128
HPF
HPF
LPF
V
OFFSET
V
GAIN
V
PEAK
V
OUT
V
IN+
V
IN–
AD8128
HPF
HPF
LPF
05699-019
+
+
VS+
S–
1µF 0.01µF
VS+
V
S+
1µF 0.01µF
VS+
V
S+
1µF 0.01µF
VS–
VS–
1µF 0.01µF
VS–
VS–
Figure 21. Cascaded AD8128 Configuration
CASCADED APPLICATIONS
To equalize distances longer than the specified 100 meters, the
AD8128 can be cascaded to provide equalization for longer
distances. When combining two AD8128s in series, it is possible to
link the control pins together and use them like a single control
pin for up to 200 meters of equalization.
In this configuration, it is important to note that some key
video specifications can be slightly degraded. By combining two
equalizers in series, specifications such as rise time and settling
time both increase while 3 dB bandwidth decreases slightly.
Also, integrated noise is increased because the second equalizer
adds gain. Subjective testing should be done to determine the
appropriate setting for the three control pins for optimum
equalization.
EXPOSED PAD (EP)
The 8-lead LFCSP has an exposed paddle on the underside of
its body. To achieve the specified thermal resistance, it must
have a good thermal connection to one of the PCB planes. The
exposed paddle must be soldered to a pad on top of the board
connected to an inner plane with several thermal vias. For the
AD8128, this pad must also be electrically connected to ground
to provide a ground reference to the part.
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered to
when designing with the AD8128. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins and control pins. Small surface-mount ceramic capacitors
are recommended for these networks, and tantalum capacitors
are recommended for bulk supply decoupling.
EVALUATION BOARDS
There are two evaluation boards available for easy characterization
of the AD8128. A general-purpose evaluation board consisting
of a single AD8128, with an option of also using a dedicated
receiver, is available for simple characterization of the part.
Additionally, a KVM application specific evaluation board is
available. This evaluation board consists of six AD8128s to
equalize each of the RGB channels up to 200 meters, a 16-pin
26C32 comparator for sync-on-common-mode extract and a
triple op amp to provide additional gain if necessary.
AD8128
Rev. 0 | Page 12 of 12
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX PIN 1
INDICATOR
1.50
REF
0.50
0.40
0.30
2.75
BSC SQ
TOP
VIEW
12° MAX 0.70 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90 MAX
0.85 NOM
0.30
0.23
0.18
0.05 MAX
0.01 NOM
0.20 REF
1.89
1.74
1.59
4
1.60
1.45
1.30
3.00
BSC SQ
5
8
Figure 22. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8128ACPZ-R21–40°C to +85°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HZB
AD8128ACPZ-RL1–40°C to +85°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HZB
AD8128ACPZ-R71–40°C to +85°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HZB
1 Z = Pb-free part.
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D05699-0-10/05(0)