ISP1582BSUM - St-Ericsson - Product.Network

1. General description

The ISP1582 is a cost-optim ized and feature-optimized Hi-Speed Universal Serial Bus

(USB) peripheral controller. It fully complies with Ref. 1 “Universal Serial Bus S pecification

Rev. 2.0”, supporting data transfer at high -speed (480 Mbit/s) and full-speed (12 Mbit/s).

The ISP1582 provides high-speed USB communication capacity to systems based on

microcontrollers or microprocessors. It communicates with a microcontroller or

microprocessor of a system through a high-speed general-purpose parallel interface.

The ISP1582 supports automatic detection of Hi-Speed USB system operation. Original

USB fall-back mode allows the device to remain operational under full-speed conditions. It

is designed as a generic USB peripheral controller so that it can fit into all existing device

classes, such as imaging class, mass storage devices, communication devices, printing

devices and human interface devices.

The internal generic Direct Memory Access (DMA) blo ck allows easy integration into data

streaming applications.

The modular approach to implementing a USB peripheral contro ller allows the designer to

select the optimum system microcontroller from the wide variety available. The ability to

reuse existing architecture and firmware shortens the development time, eliminates risk

and reduces cost. The result is fast and efficient development of the most cost-effective

USB peripheral solution.

The ISP1582 also incorporates features such as SoftConnect1, a reduced freq uency

crystal oscillator, and integrated termination resistors. These features allow significant

cost savings in system design and easy implementation of advanced USB functionality

into PC peripherals.

2. Features

Complies fully with:

Ref. 1 “Universal Serial Bus Specification Rev. 2.0”

Most device class specifications

ACPI, OnNow and USB power management requirements

Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s)

High performance USB peripheral controller with integrated Serial Interface Engine

(SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver

Automatic Hi-Spee d USB mode detection and Original USB fall-back mode

Supports sharing mode

ISP1582

Hi-Speed USB peripheral controller

Rev. 09 — 29 September 2009 Product data sheet

1. SoftConnect is a trademark of ST-Ericsson.

Product data sheet Rev. 09 — 29 September 2009 2 of 64

ISP1582

Hi-Speed USB peripheral controller

Supports VBUS sensing

Supports Generic DMA (GDMA) slave mode

High-speed DMA interface

Fully autonomous and multi-configuration DMA operation

Seven IN endpoints, seven OUT endpoints, and a fixed control IN and OUT endpoint

Integrated physical 8 kB of multi-configuration FIFO memory

Endpoints with double buffering to increase throughput and ease real-time data

transfer

Bus-independent interface with most microcontrollers and microprocessors

12 MHz crystal oscillator with integrated PLL for low EMI

Software-controlled co nn e ctio n to the USB bus (SoftConnect)

Low-power consumption in operation and power-down modes; suitable for use in

bus-powered USB devices

Support s Session Request Protocol (SRP) that adheres to Ref. 2 “On-The-Go

Supplement to the USB Specification Rev. 1.3 ”

Internal powe r- on and lo w- vo ltage rese t circuits; also supports software reset

Operation over the extended USB bus voltage range (DP, DM and VBUS)

5 V tolerant I/O pads

Operating temperature range from −40 °C to +85 °C

Available in HVQFN56 halogen-free and lead-free package

3. Applications

Personal digital assistant

Digital video camera

Digital still camera

3G mobile phone

MP3 player

Communication device, for example: router and mode m

Printer

Scanner

4. Ordering information

Table 1. Ordering information

Commercial

product code Package descrip tion Packing Minimum sellable

quantity

ISP1582BSUM HVQFN56; 56 terminals; body 8 × 8 × 0.85 mm 13 inch tape and reel dry pack 2000 pieces

ISP1582BSGA HVQFN56; 56 terminals; body 8 × 8 × 0.85 mm sing le tray dry pack 260 pieces

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Product data sheet Rev. 09 — 29 September 2009 3 of 64

ISP1582

Hi-Speed USB peripheral controller

5. Block diagram

Fig 1. Block diagram

1.5 kΩ

12.0 kΩ

VCC

004aaa199

ISP1582

MEMORY

MANAGEMENT

UNIT

INTEGRATED

RAM

(8 kB)

SYSTEM

CONTROLLER

VOLTAGE

REGULATORS

POWER-ON

RESET

HI-SPEED USB

TRANSCEIVER

internal

reset

SoftConnect

analog supply

digital

supply I/O pad

supply

MICRO-

CONTROLLER

HANDLER

MICRO-

CONTROLLER

INTERFACE

OTG SRP

MODULE

DMA

REGISTERS

DMA

HANDLER DMA

INTERFACE

ST-ERICSSON

SIE/PIE

INT

DATA

[15:0]

A[7:0]

DACK

3.3 V

VCC1V8 SUSPEND WAKEUPAGNDDGND

3.3 V

RD_N

EOT

VCC(I/O)

1, 5

DREQ DIOR

DIOW

9101112

13, 26,

29, 41

CS_N

WR_N

18 to 20,

22 to 25,

21, 34, 4828, 50

30 to 33,

35 to 40,

42 to 47

12 MHz

XTAL2XTAL1

to or from USB

DMDP VBUS

43495251

53, 54

5556

RPU

RREF

RESET_N

Product data sheet Rev. 09 — 29 September 2009 4 of 64

ISP1582

Hi-Speed USB peripheral controller

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configuration HVQFN56 (top view)

004aaa536

ISP1582BSUM

ISP1582BSGA

Transparent top view

DGND

INT

DATA0

DIOW DATA1

DIOR DATA2

DACK DATA3

DREQ VCC(I/O)

EOT DATA4

RESET_N DATA5

RREF DATA6

AGND DATA7

DM DATA8

DP DATA9

RPU DGND

AGND DATA10

CS_N

RD_N

WR_N

VCC(I/O)

DGND

VCC1V8

SUSPEND

WAKEUP

VCC

XTAL1

XTAL2

VCC1V8

VBUS

VCC(I/O)

DATA15

DATA14

DATA13

DATA12

DATA11

14 29

13 30

12 31

11 32

10 33

9 34

8 35

7 36

6 37

5 38

4 39

3 40

2 41

1 42

terminal 1

index area

Table 2. Pin description

Symbol[1] Pin Type[2] Description

AGND 1 - analog ground

RPU 2 A pull-up resistor connection; connect to the external pull-up

resistor for pin DP; must be connected to 3.3 V through a 1.5 kΩ

resistor

DP 3 A USB D+ line connection (analog)

DM 4 A USB D− line connection (analog)

AGND 5 - analog ground

RREF 6 A external bias resistor connection; connect to the external bias

resistor; must be connected to ground through a 12 .0 kΩ± 1%

resistor

ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009  5 of 64
ISP1582
Hi-Speed USB peripheral controller
RESET_N 7 I reset input (500 μs); a LOW level produces an asynchronous 
reset; connect to VCC for power-on reset (internal POR circuit)
When the RESET_N pin is LOW, ensure that the W AKEUP pin 
does not go from LOW to HIGH; otherwise the device will enter 
test mode.
TTL; 5 V tolerant
EOT 8 I end-of-transfer input (programmable pol arity); when not in use, 
connect this pin to VCC(I/O) through a 10 kΩ resistor
input pad; TTL; 5 V tolerant
DREQ 9 O DMA request (programmable polarity) output; when not in use, 
connect this pin to ground  through a 10 kΩ resistor; see 
Table 51 and Table 52
TTL; 4 ns slew-rate control
DACK 10 I DMA acknowledge input (programmable polarity); when not in 
use, connect this pin to VCC(I/O) through a 10 kΩ resistor; see 
Table 51 and Table 52
TTL; 5 V tolerant
DIOR 11 I DMA read strobe input (programmable polarity); when not in 
use, connect this pin to VCC(I/O) through a 10 kΩ resistor; see 
Table 51 and Table 52
TTL; 5 V tolerant
DIOW 12 I DMA write strobe input (programmable polarity); when not in 
use, connect this pin to VCC(I/O) through a 10 kΩ resistor; see 
Table 51 and Table 52
TTL; 5 V tolerant
DGND 13 - digital ground
INT 14 O interrupt output; programmable polarity (active HIGH or LOW) 
and signaling (edge or level triggered)
CMOS output; 8 mA drive
CS_N 15 I chip select input
input pad; TTL; 5 V tolerant
RD_N 16 I read strobe input
input pad; TTL; 5 V tolerant
WR_N 17 I write strobe input
input pad; TTL; 5 V tolerant
A0 18 I bit 0 of the address bus
input pad; TTL; 5 V tolerant
A1 19 I bit 1 of the address bus
input pad; TTL; 5 V tolerant
A2 20 I bit 2 of the address bus
input pad; TTL; 5 V tolerant
VCC(I/O)[3] 21 - supply voltage; used to supply voltage to the I/O pads; see 
Section 7.15
A3 22 I bit 3 of the address bus
input pad; TTL; 5 V tolerant
Table 2. Pin description …continued
Symbol[1] Pin Type[2] Description

Product data sheet Rev. 09 — 29 September 2009 6 of 64

ISP1582

Hi-Speed USB peripheral controller

A4 23 I bit 4 of the address bus

input pad; TTL; 5 V tolerant

A5 24 I bit 5 of the address bus

input pad; TTL; 5 V tolerant

A6 25 I bit 6 of the address bus

input pad; TTL; 5 V tolerant

DGND 26 - digital ground

A7 27 I bit 7 of the address bus

input pad; TTL; 5 V tolerant

VCC1V8[3] 28 - regulator output voltage (1.8 V ± 0.15 V); tapped out voltage

from the internal regulator; this regulated voltage cannot drive

external devices; decouple this pin using a 0.1 μF capacitor; see

Section 7.15

DGND 29 - digital ground

DATA0 30 I/O bit 0 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA1 31 I/O bit 1 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA2 32 I/O bit 2 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA3 33 I/O bit 3 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

VCC(I/O)[3] 34 - supply voltage; used to supply voltage to the I/O pads; see

Section 7.15

DATA4 35 I/O bit 4 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA5 36 I/O bit 5 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA6 37 I/O bit 6 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA7 38 I/O bit 7 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA8 39 I/O bit 8 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA9 40 I/O bit 9 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DGND 41 - digital ground

DATA10 42 I/O bit 10 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA11 43 I/O bit 11 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

DATA12 44 I/O bit 12 of bidirectional data bus

bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant

Table 2. Pin description …continued

Symbol[1] Pin Type[2] Description

ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009  7 of 64
ISP1582
Hi-Speed USB peripheral controller
[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.
[2] All outputs and I/O pins can source 4 mA, unless otherwise specified.
[3] Add a decoupling capacitor (0.1 μF) to all the supply pins. For better EMI results, add a 0.01 μF  capaci tor in 
parallel to the 0.1 μF.
DATA13 45 I/O bit 13 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te  control ; TTL; 5 V tolerant
DATA14 46 I/O bit 14 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te  control ; TTL; 5 V tolerant
DATA15 47 I/O bit 15 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te  control ; TTL; 5 V tolerant
VCC(I/O)[3] 48 - supply voltage; used to supply voltage to the I/O pads; see 
Section 7.15
VBUS 49 A USB bus power sensing input — Used to detect whether the 
host is connected or not; connect a 1 μF electrolytic or tantalum 
capacitor, and a 1 MΩ pull-down resistor to ground; see 
Section 7.13
VBUS pulsing output — In OTG mode; connect a 1 μF 
electrolytic or tantalum capacitor, and a 1 MΩ pull-down resistor 
to ground; see Section 7.13
5V tolerant
VCC1V8[3] 50 - voltage regulator output (1.8 V ± 0.15 V); tapped out voltage 
from the internal regulator; this regulated voltage cannot drive 
external devices; deco uple this pin using 4.7 μF and 0.1 μF 
capacitors; see Section 7.15
XTAL2 51 O crystal oscillator output (12 MHz); connect a fundamental 
parallel-resonant crystal; leave this pin open when using an 
external clock source on pin XTAL1; see Table 79
XTAL1 52 I crystal oscillator input (12 MHz); conne ct a fundamental 
parallel-resonant crystal or an external clock source (leaving 
pin XTAL2 unconnected); see Table 79
VCC[3] 53 - supply voltage (3.3 V ± 0.3 V); this pin supplies the internal 
voltage regulator and the analog circuit; see Section 7.15
VCC[3] 54 - supply voltage (3.3 V ± 0.3 V); this pin supplies the internal 
voltage regulator and the analog circuit; see Section 7.15
WAKEUP 55 I wake-up input; when this pin is at the HIGH level, the chip is 
prevented from getting into the suspen d state and wake-up the 
chip when already in suspend mode; when not in use, connect 
this pin to ground through a 10 kΩ resistor
When the RESET_N pin is LOW, ensure that the W AKEUP pin 
does not go from LOW to HIGH; otherwise the device will enter 
test mode.
input pad; TTL; 5 V tolerant
SUSPEND 56 O suspend state indicator output; used as a power switch control 
output to power-off or power-on external devices when going 
into suspend mode or recovering from suspend mode
CMOS output; 8 mA drive
GND exposed 
die pad - ground supply; down bonded to the exposed die pad (heat sink); 
to be connected to DGND during PCB layout
Table 2. Pin description …continued
Symbol[1] Pin Type[2] Description

Product data sheet Rev. 09 — 29 September 2009 8 of 64

ISP1582

Hi-Speed USB peripheral controller

7. Functional description

The ISP1582 is a high-speed USB peripheral controller. It implements the Hi-Speed USB

or the Original USB physical layer, and the packet protocol layer. It concurrently maint ains

up to 16 USB endpoints (control IN, control OUT, and seven IN and seven OUT

configurable) along with end point EP0 setup, which accesses the set-up buf fer . The Ref. 1

“Universal Serial Bus Specification Rev. 2.0”, Chapte r 9 protocol handling is execu te d

using the external firmware.

For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer

data to or from external memory or devices. The DMA interface can be configured by

writing to proper DMA registers (see Section 8.4).

The ISP1582 supports Hi-Speed USB and Original USB signaling. The USB signaling

speed is automatically detected.

The ISP1582 has 8 kB of internal FIFO memory, which is shared among enabled USB

endpoints, including control IN and control OUT endpoints, and set-up token buffer.

There are seven IN and seven OUT configurable endpoints, and two fixed control

endpoin ts that are 64 bytes long. Any of the seven IN and seven OUT endpoints can be

separately enabled or disabled. The endpoint type (interrupt, isochrono us or bulk) and

packet size of these endpoints can be individu ally configured, depending on the

requirements of the application. Optional double buffering increases the data throughput

of these data endpoints.

The ISP1582 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an intern al

1.8 V regulator to power the digital logic.

Table 3. Endpoint access and pr ogrammability

Endpoint

identifier Maximum packet

size Double buffering Endpoint type Direction

EP0SETUP 8 bytes (fixed) no set-up token OUT

EP0RX 64 bytes (fixed) no control OUT OUT

EP0TX 64 bytes (fixed) no control IN IN

EP1RX programmable yes programmable OUT

EP1TX programmable yes programmable IN

EP2RX programmable yes programmable OUT

EP2TX programmable yes programmable IN

EP3RX programmable yes programmable OUT

EP3TX programmable yes programmable IN

EP4RX programmable yes programmable OUT

EP4TX programmable yes programmable IN

EP5RX programmable yes programmable OUT

EP5TX programmable yes programmable IN

EP6RX programmable yes programmable OUT

EP6TX programmable yes programmable IN

EP7RX programmable yes programmable OUT

EP7TX programmable yes programmable IN

Product data sheet Rev. 09 — 29 September 2009 9 of 64

ISP1582

Hi-Speed USB peripheral controller

The ISP1582 operates on a 12 MHz crystal oscillator. An integrated 40 × PLL clock

multiplier generates the internal sampling clock of 480 MHz.

7.1 DMA interface, DMA handler and DMA registers

The DMA block can be subdivided into two blocks: DMA handler and DMA interface.

The firmware writes to the DMA Command register to st art a DMA transfe r (see Table 44).

The handler interfaces to the same FIFO (internal RAM) as used by the USB core. On

receiving the DMA command, the DMA hand ler directs the da ta from the end point FIFO to

the external DM A dev ice or fro m th e ext er nal DMA de vic e to th e en dpoint FIFO .

The DMA interface configures the timing and the DMA handshake. Data can be

transferred usin g eith er the DIOR an d DIO W str ob es or by the DACK an d DREQ

handshakes. DMA configurations are set up by writing to the DMA Configuration register

(see Table 49 and Table 50).

Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.

For details on DMA registers, see Section 8.4.

7.2 Hi-Speed USB transceiver

The analog transceiver directly interfaces to the USB cab le through integrated termin ation

resistors. The high-speed transceiver requires an external resistor (12.0 kΩ± 1%)

between pin RREF and ground to ensure an accurate current mirror that gen erates the

Hi-S peed USB current drive. A full-speed tra nsceiver is integrated as we ll. This makes the

ISP1582 compliant to Hi-Speed USB and Original USB, supporting both the high-speed

and full-speed physical layers. After automatic speed detection, the ST-Ericsson Serial

Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed

signaling.

7.3 MMU and integrated RAM

The Memory Manage ment Unit (MMU) manag es the access to the integrated RAM that is

shared by the USB, microcontrolle r handler and DMA handler. Data from the USB bus is

stored in the integrated RAM, which is cleared only when the microcon troller has read the

corresponding endpoint, or the DMA controller has written all data from the RAM of the

correspond in g en dpoint to the DM A bus . Th e OU T en dpoint bu ffer can also be forcibly

cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is

available for buffering.

7.4 Microcontroller interface and microcontroller handler

The microcontroller handler allows the external microcontroller or microprocessor to

access the register set in the ST-Ericsson SIE, as well as the DMA handler. The

initialization of the DMA configuration is done through the microcontroller handler.

7.5 OTG SRP module

The OTG supplement defines a Session Request Protocol (SRP), which allows a

B-device to request the A-device to turn on VBUS and st art a session. This pro tocol allows

the A-device, which may be battery-powered, to conserve power by turning off V BUS when

there is no bus activity while still providing a means for the B-device to initiate bus activity.

Product data sheet Rev. 09 — 29 September 2009 10 of 64

ISP1582

Hi-Speed USB peripheral controller

Any A-device, including a PC or laptop, can respo nd to SRP. Any B-device, including a

standard USB peripheral, can initiate SRP.

The ISP1582 is a device that can initia te SRP.

7.6 ST-Ericsson high-speed transceiver

7.6.1 ST-Ericsson Parallel Interface Engine (PIE)

In the High-Speed (HS) transceiver, the ST-Ericsson PIE interface uses a 16-bit parallel

bidirectional data interface. The functions of the HS module also include bit-stuffing or

de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.

7.6.2 Peripheral circuit

To maintain a constant current driver for HS transmit circuits and to bias other analog

circuits, an internal band gap reference circuit and an RREF resistor form the reference

current. This circuit requires an external precision resistor (12.0 kΩ± 1 %) conn ected to

the analog ground.

7.6.3 HS detection

The ISP1582 hand les more than one electrical st ate, Full-S peed (FS) or High-S peed (HS),

under the USB specification. When the USB cable is connected fr om the periphera l to the

host controller, the ISP1582 default s to the FS st ate, until it sees a bus r eset from the host

controller.

During the bus reset, the peripheral initiates an HS chirp to detect whether the host

controller supports Hi-Speed USB or Original USB. If the HS handshake shows that th ere

is an HS host connected, then the ISP1582 switches to the HS state.

In the HS state, the ISP1582 must observe the bus for periodic activity. If the bus remains

inactive for 3 ms, the peripheral switches to the FS state to ch eck for a Single-Ended Zero

(SE0) condition on th e USB bus. If an SE0 condition is detected for the designated time

(100 μs to 875 μs; refer to Ref. 1 “Universal Serial Bus Specification Rev. 2.0”,

Section 7.1.7.6), the ISP1582 switches to the HS chirp state to perform an HS detection

handshake. Otherwise , the ISP1582 remains in the FS state, adhering to the bus-suspend

specification.

7.6.4 Isolation

Ensure that the DP and DM lines are maintained in a clean state, without any residual

voltage or glitches. Once the ISP1582 is reset and the clock is available, ensure that ther e

are no errone ous p ulses or glitch es e ven of very small amplitude on the DP and DM lines.

Remark: If there are an y erroneo us unwanted pulses or glitches de tected by the ISP1582

DP and DM lines, there is a possibility of the ISP1582 clocking this state into the internal

core, causing unknown behaviors.

Product data sheet Rev. 09 — 29 September 2009 11 of 64

ISP1582

Hi-Speed USB peripheral controller

7.7 ST-Ericsson Serial Interface Engine (SIE)

The ST -Ericsson SIE implements the full USB protocol layer . It is completely hardwired for

speed and needs no firmware intervention. The functions of this block includ e:

synchronization pattern recognition, p arallel or serial conversion, bit-stuffing or de-stuf fing,

CRC checking or generation, Packet IDentifier (PID) verification or generation, address

recognition, handshake evaluation or generation.

7.8 SoftConnect

The USB connection is established by pulling pin DP (for full-speed devices) to HIGH

through a 1.5 kΩ pull-up resistor. In the ISP1582, an external 1.5 kΩ pull-up resistor must

be connected between pin RPU and 3.3 V. Pin RPU connects the pull-up resistor to pin

DP, when bit SOFTCT in the Mode register is set (see Table 18 and Table 19). After a

hardware reset, the pull-up resistor is disconnected by default (b it SOFTCT = 0). The USB

bus reset does not change the value of bit SOFTCT.

When VBUS is not present, the SOFTCT bit must be set to logic 0 to comply with the

back-drive voltage.

7.9 Reconfiguring endpoints

The ISP1582 endpoints have a limitation when implementing a composite device with at

least two functionalities that require the support of alternate settings, for example, the

video class and audio class devices. The ISP1582 endpoin ts cannot be reconfigured on

the fly because it is implemented as a FIFO base. The internal RAM partition will be

corrupted if there is a need to reconfigure endpoints on the fly because of alternate

settings request, causing data corruption.

For det ails and workaround, refer to Ref. 3 “Using ISP1582/3 in a composite device

application with alternate settings (AN10071)”.

7.10 System controller

The system controller implements the USB power-down capabilities of the ISP1582.

Registers are protected against data corruption during wake-up following a resume (from

the suspend state) by locking the write access, until an unlock code is written in the

Unlock Device register (see Table 69 and Table 70).

7.11 Pins status

Table 4 illustrates the behavior of ISP1582 pins with VCC(I/O) and VCC in various operating

conditions.

[1] Dead: The USB cable is plugged out, and VCC(I/O) is not available.

Table 4. ISP1582 pin status

VCC VCC(I/O) State Pin

Input Output I/O

0 V 0 V dead[1] unknown unknown unknown

3.3 V VCC reset state depends on how the pin is driven output high-Z

3.3 V VCC after reset state depends on how the pin is driven output state depends on how the pin is configured

Product data sheet Rev. 09 — 29 September 2009 12 of 64

ISP1582

Hi-Speed USB peripheral controller

Table 5 illustrates the behavior of output pins with VCC(I/O) and VCC in various operating

conditions.

[1] Dead: The USB cable is plugged out, and VCC(I/O) is not available.

[2] X: Don’t care.

7.12 Interrupt

7.12.1 Interrupt output pin

The Interrupt Config uration register of the ISP1582 contro ls the behavior of the INT output

pin. The polarity an d signaling mode of pin INT can be programmed by setting bits

INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see Table 22. Bit

GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT. Default settings

afte r reset are active LOW and level mode. Whe n pulse mode is selected, a pulse of 60 ns

is generated when the OR-ed combination of all interrupt bits changes from logic 0 to

logic 1.

Figure 3 shows the relationship between interrupt events and pin INT.

Each of the indicated USB and DMA events is logged in a status bit of the Interrupt

Interrupt Enable register and the DMA Interrupt Enable register determine whether an

event will generate an interrupt.

Interrupts can be masked globally by means of bit GLINTENA of the Mode register; see

Table 19.

Field CDBGMOD[1:0] of the Interrupt Configuration register contr ols the generation of INT

signals for the control pip e. Field DDBGMODIN[1:0] of the Interrupt Configuration register

controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the

Interrupt Configuration register controls the generation of INT signals for the OUT pipe;

see Table 23.

Table 5. ISP1582 output status

VCC VCC(I/O) State INT SUSPEND

0V 0V dead

[1] X[2] X[2]

3.3 V VCC reset HIGH LOW

3.3 V VCC after reset HIGH LOW

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Product data sheet Rev. 09 — 29 September 2009 13 of 64

ISP1582

Hi-Speed USB peripheral controller

Fig 3. Interrupt logic

Interrupt register

DMA Interrupt Reason

DMA Interrupt Enable

Interrupt Enable register

DMA_XFER_OK

EXT_EOT

INT_EOT

IE_DMA_XFER_OK

IE_EXT_EOT

IE_INT_EOT

IEBRESET

IESOF

IEDMA

IEP7RX

IEP7TX

BRESET

SOF

DMA

EP7RX

EP7TX

....................

..........

004aaa275

LATCH

GLINTENA

INTPOL

Interrupt Configuration

Mode register

INT PULSE OR LEVEL

GENERATOR

Product data sheet Rev. 09 — 29 September 2009 14 of 64

ISP1582

Hi-Speed USB peripheral controller

7.12.2 Interrupt control

Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The be havior

of this bit is given in Figure 4.

The following illustrations are only applicable for level trigger.

Event A: When an interr upt event occurs (for example, SOF interrupt) with bit GLINTENA

set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in

the corresponding Interrupt register bit.

Event B: When bi t GLIN TENA is set to logi c 1, pin INT is asser ted beca use bit SOF in the

Interrupt re gist er is alread y s et .

Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The

bold line shows the desired behavior of pin INT.

Deassertion of pin INT can be achieved ei ther by clearing all the bits in the Interrupt

Remark: When clearing an interrupt event, perform write to all the bytes of the register.

For more information on interrupt control, see Section 8.2.2, Section 8.2.5 and

Section 8.5.1.

7.13 VBUS sensing

The VBUS pin is one of the ways to wake up the clock when the ISP1582 is suspended

with bit CLKAON set to logic 0 (clock off option).

To detect whether the host is connected or not, that is VBUS sensing, a 1 M Ω resistor and

a 1 μF electrolytic or tantalum capacitor must be added to damp the overshoot on plug-in.

Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled).

Fig 4. Behavior of bit GLINTENA

INT pin

004aaa394

GLINTENA = 0

SOF asserted

GLINTENA = 1

SOF asserted

GLINTENA = 0

(during this time,

an interrupt event

occurs, for example,

SOF asserted)

ABC

Product data sheet Rev. 09 — 29 September 2009 15 of 64

ISP1582

Hi-Speed USB peripheral controller

7.14 Power-on reset

The ISP1582 requires a minimum pulse width of 500 μs.

Fig 5. Resistor and electro lytic or tantalum capacitor needed for VBUS sensing

Fig 6. Oscillosco pe reading: no resistor and capacitor in the network

Fig 7. Oscilloscope reading: with resistor and capacitor in the network

1 MΩ

ISP1582

004aaa440

1 μF

49 USB

CONNECTOR

001aaf440

001aaf441

Product data sheet Rev. 09 — 29 September 2009 16 of 64

ISP1582

Hi-Speed USB peripheral controller

The RESET_N pin can either be connected to VCC (using the internal POR circuit) or

externally controlled (by the microcontroller, ASIC, and so on). When VCC is directly

connected to the RESET_N pin, the internal pulse width tPORP will typically be 200 ns.

The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5

on the VCC(POR) curve (Figure 8).

t0 — The internal POR starts with a HIGH level.

t1 — The detector will see the passing of the trip level and a delay element will add

another tPORP before it drops to LOW.

t2-t3 — The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip for

more than 11 μs.

t4-t5 — The dip is too short (< 11 μs) and the internal POR pulse will not react and will

remain LOW.

Figure 9 shows the availability of the clock with respect to the external POR.

7.15 Power supply

The ISP1582 can be powered by 3.3 V ± 0.3 V. For connection details, see Figure 10.

If the ISP1582 is powered by V CC = 3.3 V, an integrated 3.3 V-to-1.8 V voltage regulator

provides a 1.8 V supply voltage for the internal logic.

(1) PORP = Power-On Reset Pulse.

Fig 8. POR timing

Power on VCC at A.

Stable external clock is to be available at B.

The ISP1582 is operational at C.

Fig 9. Clock with respect to the external POR

004aab162

CC(POR)

t0 t1 t2 t3 t4 t5

trip

PORP

(1)

PORP

external

clock

004aaa927

500 μs

RESET_N

2 ms

Product data sheet Rev. 09 — 29 September 2009 17 of 64

ISP1582

Hi-Speed USB peripheral controller

Table 6 shows power modes in which the ISP1582 can be operated.

[1] The power supply to the IC (VCC) is 3.3 V. Therefore, if the application is bus-powered, a 3.3 V regulator

must be used.

[2] VCC(I/O) = VCC. If the application is bus-powered, a voltage regulator must be used.

(1) At the VCC input (3.3 V) to the USB controller, if the ripple voltage is less than 20 mV, then 4.7 μF

standard electrolytic or tantalum cap acitors (tested ESR up to 10 Ω) should be OK at the VCC1V8

output. If the ripple voltage at the input is higher than 20 mV, then use 4.7 μF LOW ESR cap acitors

(ESR from 0.2 Ω to 2 Ω) at the VCC1V8 output. This is to improve the high-speed signal quality at

the USB side.

Fig 10. ISP1582 with 3.3 V supply

Table 6. Power modes

VCC VCC(I/O) Power mode

VBUS[1] VBUS[2] bus-powered

System-powered system-powered self-powered

004aaa203

53, 54

VCC(I/O)

ISP1582

3.3 V ± 0.3 V

VCC(I/O)

VCC

VCC(I/O)

VCC1V8

4.7 μF(1) 0.1 μF

0.01 μF0.1 μF

0.01 µF 0.1 μF

0.01 μF0.1 μF

VCC1V8

0.1 μF

VCC

Product data sheet Rev. 09 — 29 September 2009 18 of 64

ISP1582

Hi-Speed USB peripheral controller

7.15.1 Self-powered mode

In self-powered mode, VCC and VCC(I/O) are supplied by the system. See Figure 11.

[1] When the USB cable is removed, SoftConnect is disabled.

VCC(I/O) and VCC are system powered.

Fig 11. Self-powered mode

Table 7. Operation truth table for SoftConnect

ISP1582 operation Power supply Bit SOFTCT in

Mode register

VCC VCC(I/O) RPU

(3.3 V) VBUS

Normal bus operation 3.3 V 3.3 V 3.3 V 5 V enabled

No pull-up on DP 3.3V 3.3V 3.3V 0V

[1] disabled

Table 8. Operation truth table for clock off during suspend

ISP1582 operation Power supply Clock off

during

suspend

VCC VCC(I/O) RPU

(3.3 V) VBUS

Clock will wake up:

After resume and

After a bus reset

3.3 V 3.3 V 3.3 V 5 V enabled

Clock will wake up:

After detecting the presence of VBUS

3.3V 3.3V 3.3V 0V→ 5 V enabled

Table 9. Operation truth table for back voltage compliance

ISP1582 operation Power supply Bit SOFTCT

in Mode

VCC VCC(I/O) RPU

(3.3 V) VBUS

Back voltage is not measured in this

mode 3.3 V 3.3 V 3.3 V 5 V enabled

Back voltage is not an issue because pull

up on DP will not be present when VBUS

is not present

3.3 V 3.3 V 3.3 V 0 V disabled

004aaa460

ISP1582

USB

1 MΩ

VCC

VCC(I/O)

VBUS

RPU VBUS

1.5 kΩ

1 μF

Product data sheet Rev. 09 — 29 September 2009 19 of 64

ISP1582

Hi-Speed USB peripheral controller

7.15.2 Bus-powered mode

In bus-powered mode (see Figure 12), VCC and VCC(I/O) are supplied by the output of the

5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. On plugging the

USB cable, the ISP1582 goes through the power-on reset cycle. In this mode, OTG is

disabled.

Table 10. Operation truth table for OTG

ISP1582 operation Power supply OTG register

VCC VCC(I/O) RPU

(3.3 V) VBUS

SRP is not applicable 3.3 V 3.3 V 3.3 V 5 V not applicable

SRP is possible 3.3 V 3.3 V 3.3 V 0 V operational

VCC(I/O) is powered by VBUS.

Fig 12. Bus-powered mo de

Table 11. Operation truth table for SoftConnect

ISP1582 operation Power supply Bit SOFTCT in

Mode register

VCC VCC(I/O) RPU

(3.3 V) VBUS

Normal bus operation 3.3 V 3.3 V 3.3 V 5 V enabled

Power loss 0V 0V 0V 0V not applicable

Table 12. Operation truth table for clock off during suspend

ISP1582 operation Power supply Clock off during

suspend

VCC VCC(I/O) RPU

(3.3 V) VBUS

Clock will wake up:

After resume and

After a bus reset

3.3 V 3.3 V 3.3 V 5 V enabled

Power loss 0V 0V 0V 0V not applicable

004aaa462

ISP1582

5 V-to-3.3 V

USB

VOLTAGE

REGULATOR

1 MΩ

VCC

VCC(I/O)

VBUS

RPU

1 μF

1.5 kΩ

3.3 V

Product data sheet Rev. 09 — 29 September 2009 20 of 64

ISP1582

Hi-Speed USB peripheral controller

Table 13. Operation truth table for back voltage compliance

ISP1582 operation Power supply Bit SOFTCT in

Mode register

VCC VCC(I/O) RPU

(3.3 V) VBUS

Back voltage is not measured in this

mode 3.3 V 3.3 V 3.3 V 5 V enabled

Power loss 0V 0V 0V 0V not applicable

Table 14. Operation truth table for OTG

ISP1582 operation Power supply OTG register

VCC VCC(I/O) RPU

(3.3 V) VBUS

SRP is not applicable 3.3 V 3.3 V 3.3 V 5 V not applicable

Power loss 0V 0V 0V 0V not applicable

ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009  21 of 64
ISP1582
Hi-Speed USB peripheral controller
8. Register description
 
Table 15. Register overview
Name Destination Address Description Size 
(bytes) Reference
Initialization registers
Address device 00h USB device address and enable 1 Section 8.2.1 
on page 22
Mode device 0Ch power-down options, global interrupt 
enable, SoftConnect 2Section 8.2.2 
on page 23
Interrupt Configuration device 10h interrupt sources, trigger mode, output 
polarity 1Section 8.2.3 
on page 24
OTG device 12h OTG implementation 1 Section 8.2.4 
on page 25
Interrupt Enable device 14h interrupt source ena bling 4 Section 8.2.5 
on page 27
Data flow registers
Endpoint Index endpoints 2Ch endpoint selection, data flow direction 1 Section 8.3.1 
on page 29
Control Function endpoint 28h endpoint buffer management 1 Section 8.3.2 
on page 30
Data Port endpoint 20h data access to endpoint FIFO 2 Section 8.3.3 
on page 31
Buffer Length endpoint 1Ch packet size counter 2 Section 8.3.4 
on page 32
Buffer Status endpoint 1Eh buffer status for each endpoint 1 Section 8.3.5 
on page 33
Endpoint MaxPacketSize endpoint 04h maximum packet size 2 Section 8.3.6 
on page 34
Endpoint Type endpoint 08h selects endpoint type: isochronous, bulk 
or interrupt 2Section 8.3.7 
on page 35
DMA regi sters
DMA Command DMA controller 30h controls all DMA transfers 1 Section 8.4.1 
on page 37
DMA Transfer Counter DMA controller 34h sets byte count for DMA transfer 4 Section 8.4.2 
on page 38
DMA Configuration DMA controller 38h sets GDMA configuration (counter 
enable, data strobing, bus width) 2Section 8.4.3 
on page 39
DMA Hardware DMA controller 3Ch endian type, signal polarity for DACK, 
DREQ, DIOW, DIOR, EOT 1Section 8.4.4 
on page 40
DMA Interrupt Reason DMA controller 50h shows reason (source) for DMA interrupt 2 Section 8.4.5 
on page 41
DMA Interrupt Enable DMA controller 54h enables DMA interrupt sources 2 Section 8.4.6 
on page 42
DMA Endpoint DMA controller 58h selects endpoint FIFO, data flow direction 1 Section 8.4.7 
on page 43
DMA Burst Counter DMA controller 64h DMA burst counter 2 Section 8.4.8 
on page 43

ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009  22 of 64
ISP1582
Hi-Speed USB peripheral controller
8.1 Register access
The ISP1582 uses a 16-bit b us access. For single-byte registers, the  upper byte (MSByte) 
must be ignored.
Endpoint sp ecific registers are indexed using the Endpoint Index register. The target 
endpoint mu st be selected before accessing the following registers:
•Buffer length
•Buffer status
•Control function
•Data port
•Endpoint MaxPacketSize
•Endpoint type
Remark: Write zero to all reserved bits, unless otherwise specified.
8.2 Initialization registers
8.2.1 Address register (address: 00h)
This register sets the USB assigned address and enables the USB device . Table 16 
shows the Address register bit allocation.
Bits DEVADDR[6:0] will be cleared whenever a bus reset, a power-on reset or a sof t reset 
occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs.
In response to the standard USB request SET_ADDRESS, firmware must write the 
(enabled) device  address to th e Address  register, followed by se nding an  empty p acket to 
the host. The new device address is activated when the device receives an 
acknowledgment from the host for the em pty packet token.
General registers
Interrupt device 18h shows interrupt sources 4 Section 8.5.1 
on page 44
Chip ID device 70h product ID code and hardware version 3 Section 8.5.2 
on page 46
Frame Number device  74h last successfully received 
Start-Of-Frame: lower byte (byte 0) is 
accessed first
2Section 8.5.3 
on page 46
Scratch device 78h allows save or restore of firmware status 
during suspend 2Section 8.5.4 
on page 47
Unlock Device device 7Ch re-enables register write access after 
suspend 2Section 8.5.5 
on page 47
Test Mode PHY 84h direct se tting of the DP and DM states, 
internal transceiver test (PHY) 1Section 8.5.6 
on page 48
Table 15. Register overview …continued
Name Destination Address Description Size 
(bytes) Reference

Product data sheet Rev. 09 — 29 September 2009 23 of 64

ISP1582

Hi-Speed USB peripheral controller

8.2.2 Mode register (address: 0Ch)

This register consists of 2 b ytes (bit allocation: see Table 18).

The Mode register contro ls resume, suspend and wake-up behavior, interrupt activity, soft

reset, clock signals and SoftConnect operation.

[1] Value depends on the status of the VBUS pin.

Table 16. Address register: bit allocatio n

Bit 76543210

Symbol DEVEN DEVADDR[6:0]

Reset 00000000

Bus reset unchanged 0 0 00000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 17. Address register: bit description

Bit Symbol Description

7 DEVEN Device Enable : Logic 1 enables the device. The device will not respond to

the host, unless this bit is set.

6 to 0 DEVADDR

[6:0] Device Address: This field specifies the USB device address.

Table 18. Mode register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved DMA

CLKON VBUSSTAT

Reset ------0-

[1]

Bus reset ------0-

[1]

Access RRRRRRR/WR

Bit 76543210

Symbol CLKAON SNDRSU GOSUSP SFRESET GLINTENA WKUPCS PWRON SOFTCT

Reset 00000000

Bus reset unchanged 0 0 0 unchanged 0 unchanged unchanged

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 19. Mode register: bit description

Bit Symbol Description

15 to 10 - reserved

9DMACLKONDMA Clock On:

0 — Power save mode; the DMA circuit wi ll stop completely to save

power.

1 — Supply clock to the DMA circuit.

8 VBUSSTAT VBUS Pin Status: This bit reflects the VBUS pin status.

Product data sheet Rev. 09 — 29 September 2009 24 of 64

ISP1582

Hi-Speed USB peripheral controller

The status of the chip is shown in Table 20.

8.2.3 Interrupt Configuration register (address: 10h)

This 1-byte register determines the behavior and polarity of the INT output. The bit

allocation is shown in Table 21. When the USB SIE receives or generates an ACK, NAK

or NYET, it will generate interrupts, depending on three Debug mode fields.

7 CLKAON Clock Always On: Logic 1 indicates that internal clocks are always

running when in the suspend state. Logic 0 switches off the internal

oscillator and PLL when the device goes into suspend mode. The

device will consume less power if this bit is set to logic 0. The clock is

stopped about 2 ms after bit GOSUSP is set and then cleared.

6 SNDRSU Send Resume: Writing logic 1, followed by logic 0 will generate a 10 ms

upstream resume signal.

Remark: The upstream resume signal is generated 5 ms after this bit is

set to logic 0.

5GOSUSPGo Suspend: Writing logic 1, followed by logic 0 will activate suspend

mode.

4 SFRESET Sof t Reset: Writing logic 1, followed by logic 0 will enable a

software-initiated reset to the ISP1582. A soft reset is similar to a

hardware-initiated reset (using pin RESET_N).

3GLINTENAGlobal Interrupt Enable: Logic 1 enables all interrupts. Individual

interrupts can be masked by clearing the corresponding bits in the

Interrupt Enable register.

When this bit is not set, an unmasked interrup t will not genera te an

interrupt trigger on the interrupt pin. If global interrupt, however, is

enabled while there is any pending unmasked interrupt, an interrupt

signal will be immediately generated on the interrupt pin. (If the interrupt

is set to pulse mode, the interrupt events that were generated before the

global interrupt is enabled will not app ear on the interrupt pin).

2 WKUPCS Wake Up On Chip Sele ct: Logic 1 enables wake-up from suspend

mode through a valid register read on the ISP1582. (A read will invoke

the chip clock to restart. If you write to the register before the clock gets

stable, it may cause malfunctioning).

1PWRONPower On: The SUSPEND pin output control.

0 — The SUSPEND pin is HIGH when the ISP1582 is in the su spend

state. Otherwise, the SUSPEND pin is LOW.

1 — When the device is woken up from the suspend state, there will be

a 1 ms active HIGH pulse on the SUSPEND pin. The SUSPEND pin will

remain LOW in all other states.

0 SOFTCT SoftConnect: Logic 1 enables the connection of the 1.5 kΩ pull-up

resistor on pin RPU to the DP pin.

Table 19. Mode register: bit description …continued

Bit Symbol Description

Table 20. Status of the chip

VBUS SoftConnect = on Sof tConnect = off

On pull-up resistor on pin DP pull-up resistor on pin DP is removed; suspend interrupt is

generated after 3 m s of no bus activity

Off pull-up resistor on pin DP is present; suspend

interrupt is generated after 3 ms of no bus activity pull-up resistor on pin DP is removed; suspend interrupt is

generated after 3 m s of no bus activity

Product data sheet Rev. 09 — 29 September 2009 25 of 64

ISP1582

Hi-Speed USB peripheral controller

CDBGMOD[1:0] — Interrupts for control endpoint 0

DDBGMODIN[1:0] — Interrupts for DATA IN endpoints 1 to 7

DDBGMODOUT[1:0] — Interrupts for DATA OUT endpoints 1 to 7

The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you

to individually configure when the ISP1582 sends an interrupt to the external

microprocessor. Table 23 lists the available combinations.

Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or

falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to

logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).

[1] First NAK: the first NAK on an IN or OUT token is generated after a set-up token and an ACK sequence.

8.2.4 OTG register (address: 12h)

The bit allocation of the OTG register is given in Table 24.

Table 21. Interrupt Configuration register: bit allocation

Bit 76543210

Symbol CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] INTLVL INTPOL

Reset 11111100

Bus reset 1 1 1 1 1 1 unchanged unchanged

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 22. Interrupt Config uration register: bit des cription

Bit Symbol Description

7 to 6 CDBGMOD[1:0] Control Endpoint 0 Debug Mode: For values, see Table 23

5 to 4 DDBGMODIN[1:0] Data Debug Mode IN: For values, see Table 23

3 to 2 DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see Table 23

1INTLVL Interrupt Level: Selects signaling mode on output INT (0= level;

1= pulsed). In pulsed mode, an interrupt produces a 60 ns pulse.

0INTPOL Interrupt Polarity: Selects signal polarity on output INT (0=

active LOW; 1= active HIGH).

Table 23. Debug mode settings

Value CDBGMOD DDBGMODIN DDBGMODOUT

00h interrupt on all ACK and

NAK interrupt on all ACK and

NAK interrupt on all ACK, NYET and

NAK

01h interrupt on all ACK interrupt on ACK interrupt on ACK and NYET

1Xh interrupt on all ACK and

first NAK[1] interrupt on all ACK and

first NAK[1] interrupt on all ACK, NYET and

first NAK[1]

Table 24. OTG register: bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol reserved DP BSESSVALID INITCOND DISCV VP OTG

Reset --0 - - 0 0 0

Bus reset --0 - - 0 0 0

Access - - R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 26 of 64

ISP1582

Hi-Speed USB peripheral controller

[1] No interrupt is designed for OTG. The VBUS interrupt, however, may assert as a side effect during the VBUS

pulsing (see note 2).

[2] When OTG is in progress, the VBUS interrupt may be set because VBUS is charged over the VBUS sensing

threshold or the OTG host has turned on the VBUS supply to the device. Even if the VBUS interrupt is found

during SRP, the device must complete data-line pulsing and VBUS pulsing before starting the

B_SESSION_VALID detection.

[3] OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it

must provide a switch circuit to supply power to the ISP1582 core during SRP.

Table 25. OTG register: bit description

Bit Symbol Description[1][2][3]

7 to 6 - reserved

5DPData Pulsing: Used for data-line pulsing to toggle DP to generate the required

data-line pulsing signal. The default value of this bit is logic 0. This bit must be

cleared when data-line pulsing is completed.

4 BSESS

VALID B-Session V a lid: The device can initiate another VBUS discharge sequence after

data-line pulsing and VBUS pulsing, and before it clears this bit and detects a

session valid.

This bit is latched to logic 1 once VBUS exceeds the B-device session valid

threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The

ISP1582 continuously updates this bit to logic 1 when the B-session is valid. If

the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1582).

0 — It implies that SRP has failed. To proceed to a normal operation, the device

can restart SRP, clear bit OTG or proceed to an error handling process.

1 — It implies that the B-session is valid. The device clears bit OTG, goes into

normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register.

The OTG host has a maximum of 5 s before it responds to a session request.

During this period, the ISP1582 may request to suspend. Therefore, the device

firmware must wait for some time if it wishes to know the SRP result (success: if

there is minimum response from the host within 5 s; failure; if there is no

response from the host within 5 s).

3INIT

COND Initial Co ndition: Write logic 1 to clear this bit. Wait for more than 2 ms and

check the bit status. If it reads logic 0, it means that VBUS remains lower than

0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then

start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP

is violated. So, the device must abort SRP.

The bit is set to logic 1 by th e ISP1582 when initial conditions are not met, and

only writing logic 1 clears the bit. (If initial conditions are not met after this bit has

been cleared, it will be set again).

Remark: This implementation does not cover the case if an initial SRP condition

is violated when this bit is read and data-line pulsing is started.

2DISCV

Discharge VBUS: Set to logic 1 to discharge VBUS. The device discharges VBUS

before starting a new SRP. The discharge can take as long as 30 ms for VBUS to

be charged less than 0.8 V. This bit must be cleared (write logic 0) before

starting a session end detection.

1VPVBUS Pulsing: Used for VBUS pulsing to toggle VP to generate the required VBUS

pulsing signal. This bit must be set for more than 16 ms and must be cleared

before 26 ms.

0OTGOn-The-Go:

1 — Enables the OTG function. The VBUS sensing functionality will be disabled.

0 — Normal operation. All OTG control bi ts will be masked. Status bits are

undefined.

Product data sheet Rev. 09 — 29 September 2009 27 of 64

ISP1582

Hi-Speed USB peripheral controller

8.2.4.1 Session Request Protocol (SRP)

The ISP1582 can initiate an SRP. The B-device initiates SRP by data-line pulsing,

followed by VBUS pulsing. The A-device can detect either data-line pulsing or VBUS

pulsing.

The ISP1582 can initiate the B-device SRP by performing the following steps:

1. Set the OTG bit to start SRP.

2. Detect initial conditions by following the instructions given in bit INITCOND of the

OTG register.

3. Start data-line pulsing: set bit DP of the OTG register to logic 1.

4. Wait for 5 ms to 10 ms.

5. Stop data-line pulsing: set bit DP of the OTG reg iste r to logi c 0.

6. Start VBUS pulsing: set bit VP of the OTG register to logic 1.

7. Wait for 10 ms to 20 ms.

8. Stop VBUS pulsing: set bit VP of the OTG register to logic 0.

9. Discharge VBUS for abou t 30 ms: optional by using bit DISCV of the OTG register.

10. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG

cleared.

11. Once bit BSESSVALID is detected, turn on the SOFTCT bit to start normal bus

enumeration.

The B-device must complete both data-line pulsing and V BUS pulsing within 100 ms.

Remark: When disabling OTG, data-line pulsing bit DP and VBUS pulsing bit VP must be

cleared by writing logic 0.

8.2.5 Interrupt Enable register (address: 14h)

This register enables or disables individual interrupt sources. The interru pt for each

endpoint can ind ividual ly be controlled using the associated bits IEPnRX or IEPnTX, here

n represents the endpoint number. All interrupts can be globally disabled using bit

GLINTENA in the Mode register (see Table 18).

An interrupt is gene rated when the USB SIE rece ives or generate s an ACK or NAK on the

USB bus. The interrupt generation depends on Debug mode settings of bit fields

CDBGMOD[1:0], DDBGMODI N[1:0] and DDBGMODOUT[1:0] in the Interrupt

Configuration register.

All data IN transactions use the Transmit buffers (TX), which are handled by bits

DDBGMODIN[1:0]. All data OUT transactions go through the Receive buf fers (RX), which

are handled by bits DDBGMODOUT[1:0]. Transactions on control endpoint 0 (IN, OUT

and SETUP) are handled by bits CDBGMOD[1:0].

Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up

and high-speed status) can also be individually controlled. A bus reset disables all

enabled interrupts, except bit IEBRST (bus reset), which remains logic 1.

The Interrupt Enable register consists of 4 bytes. The bit allocation is given in Table 26.

Product data sheet Rev. 09 — 29 September 2009 28 of 64

ISP1582

Hi-Speed USB peripheral controller

Table 26. Interrupt Enable register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved IEP7TX IEP7RX

Reset ------00

Bus reset ------00

Access ------R/WR/W

Bit 23 22 21 20 19 18 17 16

Symbol IEP6TX IEP6RX IEP5TX IEP5RX IEP4TX IEP4RX IEP3TX IEP3RX

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol IEP2TX IEP2RX IEP1TX IEP1RX IEP0TX IEP0RX reserved IEP0SETUP

Reset 000000-0

Bus reset 000000-0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol IEVBUS IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF IEBRST

Reset 00000000

Bus reset 00000001

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 27. Interrupt Enable register: bit description

Bit Symbol Description

31 to 26 - reserved

25 IEP7TX Logic 1 enables interrupt from the indicated endpoint.

24 IEP7RX Logic 1 enables interrup t from the indicated endpoint.

23 IEP6TX Logic 1 enables interrupt from the indicated endpoint.

22 IEP6RX Logic 1 enables interrup t from the indicated endpoint.

21 IEP5TX Logic 1 enables interrupt from the indicated endpoint.

20 IEP5RX Logic 1 enables interrup t from the indicated endpoint.

19 IEP4TX Logic 1 enables interrupt from the indicated endpoint.

18 IEP4RX Logic 1 enables interrup t from the indicated endpoint.

17 IEP3TX Logic 1 enables interrupt from the indicated endpoint.

16 IEP3RX Logic 1 enables interrup t from the indicated endpoint.

15 IEP2TX Logic 1 enables interrupt from the indicated endpoint.

14 IEP2RX Logic 1 enables interrup t from the indicated endpoint.

13 IEP1TX Logic 1 enables interrupt from the indicated endpoint.

12 IEP1RX Logic 1 enables interrup t from the indicated endpoint.

11 IEP0TX Logic 1 enables in terrupt from the control IN endpoint 0.

10 IEP0RX Logic 1 enables interrupt from the control OUT endpoint 0.

9- reserved

8 IEP0SETUP Lo gic 1 enables interrupt for the set-up data received on endpoint 0.

Product data sheet Rev. 09 — 29 September 2009 29 of 64

ISP1582

Hi-Speed USB peripheral controller

8.3 Data flow registers

8.3.1 Endpoint Index register (address: 2Ch)

The Endpoint Index register selects a target endpoint for register access by the

microcontroller. The register consists of 1 byte, and the bit allocation is shown in Table 28.

The following registers are indexed:

•Buffer length

•Buffer status

•Control function

•Data port

•Endpoint MaxPacketSize

•Endpoint type

For example, to access the OUT dat a buffer of end point 1 using the Data Port register, the

Endpoint Index register must be written first with 02h.

Remark: The End point Index register and the DMA Endpoint r egister must not point to the

same endpoint, irrespective of IN and OUT.

Remark: The delay time from the Write Endpoint Index register to the Read Data Port

Remark: The delay time from the Write Endpoint Index register to the Wr ite Data Port

7 IEVBUS Logic 1 enables interrupt for VBUS sensing.

6 IEDMA Logic 1 enables in terrupt on the DMA Interrupt Reason registe r cha nge

detection.

5 IEHS_STA Logic 1 enables interrupt on detection of a high-speed status change.

4 IERESM Logic 1 enables interrupt on detection of a resume state.

3 IESUSP Logic 1 enables interrupt on detection of a suspend state.

2 IEPSOF Logic 1 enables interrupt on detection of a pseudo SOF.

1 IESOF Logic 1 enables interrupt on detection of an SOF.

0 IEBRST Logic 1 enables interrup t on detection of a bus reset.

Table 27. Interrupt Enable register: bit description …continued

Bit Symbol Description

Table 28 . Endpoint Index register: bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol reserved EP0SETUP ENDPIDX[3:0] DIR

Reset - - 100000

Bus reset - -unchanged00000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 30 of 64

ISP1582

Hi-Speed USB peripheral controller

8.3.2 Control Function register (address: 28h)

The Control Function registe r performs the buffer managem ent on endpoint s. It consists of

1 byte, and the bit configuration is given in Table 31. Register bits can stall, clear or

validate any enabled data endpoint. Before accessing this register, the Endpoint Index

Table 29. Endpoint Index register: bit description

Bit Symbol Description

7 to 6 - reserved

5 EP0SETUP Endpoint 0 Setup: Selects the SETUP buffer of endpoint 0.

0 — Da ta buff er

1 — SETUP buffer

Must be logic 0 for access to endpoints other than set-up token buffer.

4 to 1 ENDPIDX[3:0] Endpoint Index : Selects the target endpoint for register access of

buffer length, buffer status, control function, data port, endpoint type

and MaxPacketSize.

0DIR Direction: Sets the target endpoint as IN or OUT.

0 — Target endpoint refers to OUT (RX) FIFO

1 — Target endpoint refers to IN (TX) FIFO

Table 30. Addressing of endpoint buffers

Buffer name EP0SETUP ENDPIDX DIR

SETUP 1 00h 0

Control OUT 0 00h 0

Control IN 0 00h 1

Data OUT 0 0Xh 0

Data IN 0 0Xh 1

Table 31. Control Function reg is ter: bit allocation

Bit 76543210

Symbol reserved CLBUF VENDP DSEN STATUS STALL

Reset - - -00000

Bus reset - - -00000

Access - - - R/W R/W W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 31 of 64

ISP1582

Hi-Speed USB peripheral controller

8.3.3 Data Port register (address: 20h)

This 2-byte register provides direct access for a m icrocontroller to th e FIFO of the indexed

endpoint. The bit allocation is shown in Table 33.

Table 32. Control Function register : bit description

Bit Symbol Description

7 to 5 - reserved

4CLBUFClear Buffer: Logic 1 clears the TX or RX buf fer of the indexed endpoint. The

RX buffer is automatically cleared once the endpoint is compl e tely read. This

bit is set only when it is necessary to forcefully clear the buffer.

Remark: If using double buffer, to clear both the buffers issue the CLBUF

command two times. For details on clearing buffers , refer to Ref. 4

“ISP1582/83 and ISP1761 clearing an IN buffer (AN10045)”.

3 VENDP V alidate End point: Logic 1 validates data in the TX FIFO of an IN endpoint to

send on the next IN token. In general, the endpoint is automatically validated

when its FIFO byte count has reached endpoint MaxPacketSize. This bit is set

only when it is necessary to validate the endpoint with the FIFO byte count,

which is bel o w en dpoin t Ma xPacketSize.

Remark: Use either bit VENDP or register Buffer Length to validate endpoint

FIFO with FIFO bytes.

2 DSEN Data St age Enable: This bit controls the response of the ISP1582 to a control

transfer. After the completion of the set-up stage, firmware must determine

whether a data stage is required. For control OUT, firmware will set this bit

and the ISP1582 goes into the data stage. Otherwise, the ISP1582 will NAK

the data stage transfer. For control IN, firmware will set this bit before writing

data to the TX FIFO and validate the endpoint. If no data stage is required,

firmware can immediately set the STATUS bit after the set-up stage.

Remark: The DSEN bit is cleared once the OUT token is acknowledged by

the device and the IN token is acknowledged by the PC host. This bit cannot

be read back and reading this bit will return logic 0.

1STATUSStatus Acknowledge: Only applicable for control IN or OUT.

This bit controls the generation of ACK or NAK during the status stage of a

SETUP transfer. It is automatically cleared when the status stage is

completed, or when a SETUP token is received. No in terrupt signal will be

generated.

0 — Sends NAK

1 — Sends an empty packet following the IN token (peripheral-to-host) or

ACK following the OUT token (host-to-peripheral).

Remark: The STATUS bit is cleared to zero once the zero-length packet is

acknowledged by the device or the PC host.

Remark: Data transfers preceding the status stage must first be fully

completed before the STATUS bit can be set.

0STALLStall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable

for isochronous transfers.

Remark: Stalling a data endpoint will confuse the Data Toggle bit about the

stalled endpoint because the internal logic picks up from where it is stalled.

Therefore, the Data Toggle bit must be reset by disabling and re-enabling the

corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1

in the Endpoint Type register) to reset the PID.

Product data sheet Rev. 09 — 29 September 2009 32 of 64

ISP1582

Hi-Speed USB peripheral controller

Peripheral-to-host (IN endpoint): After each write action, an inte rnal counter is auto

incremente d by two to th e ne xt location in the TX FIFO. When all bytes are written (FIFO

byte count = endpoint MaxPacketSize), the buffer is automatically validated. The data

packet will then be sent on the next IN token. When it is necessary to validate the endpoint

whose byte coun t is less th an Max Pac ke tSize , it can be done usin g th e Co ntr o l Func tion

Remark: The buffer can automatically be validated by using the Buffe r Length register

(see Table 35).

Host-to-peripheral (OUT endpoint): After each read action, an internal counter is auto

decremented by two to the next location in the RX FIFO. When all bytes are read, bu ffer

contents are automatically cleared. A new data packet can then be received on the next

OUT token. Buffer contents can also be cleared using the Control Function register (bit

CLBUF), when it is necessary to forcefully clear contents.

Remark: The delay time from the Write Endpoint Index register to the Read Data Port

Remark: The delay time from the Write Endpoint Index register to the Wr ite Data Port

8.3.4 Buffer Length register (address: 1Ch)

This register determines the current packet size (DATACOUNT) of the indexed endpoint

FIFO. The bit allocation is given in Table 35.

The Buffer Length register is automatically loaded with the FIFO size, when the Endpoi nt

MaxPacketSize register is written (see Table 39). A smaller value can be written when

required. After a bus reset, the Buffer Length registe r is made zero.

Table 33. Dat a Por t re gister: bit allo ca ti on

Bit 15 14 13 12 11 10 9 8

Symbol DATAPORT[15:8]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol DATAPORT[7:0]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 34. Data Port register: bit description

Bit Symbol Description

15 to 8 DATAPORT[15:8] d ata (uppe r byte)

7 to 0 DATAPORT[7:0] data (lower byte)

Product data sheet Rev. 09 — 29 September 2009 33 of 64

ISP1582

Hi-Speed USB peripheral controller

IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer

Length register is not significant. This register is useful only when transferring data that is

not a multiple of MaxPacketSize. The following two examples demonstrate the

significance of the Buffer Length register.

Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register need not be filled. This is because

the transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be

automatically validated because the last packet is also of MaxPa cketSize.

Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register must be filled with 62 bytes just

before the microprocessor writes the last packet of 62 bytes. This ensures that the last

packet, which is a short packet of 62 bytes, is automatically validated.

Use bit VENDP in the Control register if you are not using the Buffer Length register.

This is applicable only to the PIO mode access.

OUT endpoint: The DATACOUNT value is automatically initialized to the number of data

bytes sent by the host on eac h ACK.

Remark: When using a 16-bit micro processor bus, th e last byte of an odd-sized p acket is

output as the lower byte (LSByte).

Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint.

8.3.5 Buffer Status register (address: 1Eh)

This register is accessed using index. The endpoint index must first be set before

accessing this register for the corresponding endpoint. It reflects the status of the double

buffered endpoint FIFO.

Remark: This register is not applicable to the control endpoint.

Table 35 . Buffer Length register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol DATACOUNT[15:8]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol DATACOUNT[7:0]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 36. Buffer Length registe r: bi t description

Bit Symbol Description

15 to 0 DATACOUNT[15:0] Data Count: Determines the current packet size of the indexed

endpoint FIFO.

Product data sheet Rev. 09 — 29 September 2009 34 of 64

ISP1582

Hi-Speed USB peripheral controller

Remark: For endpoint IN data transfer, firmware must ensure a 200 ns delay between

writing of the data packet and reading the Buffer Status register. For endpoint OUT data

transfer, firmware must also ensure a 200 ns delay between receiving the endpoint

interrupt and re ading the Buffer Status register. For more informatio n, refer to Ref. 3

“Using ISP1582/3 in a composite device application with alternate settings (AN10071)”.

Table 37 shows the bit allocation of the Buffer Status register.

8.3.6 Endpoint MaxPacketSize register (address: 04h)

This register dete rm in es th e ma xim u m packet size for all endpoints, except set- up toke n

buffer, control IN and control OUT. The register contains 2 byte s, an d th e bit alloca tio n is

given in Table 39.

Each time the register is written, the Buffer Length register of the corresponding endpoint

is re-initialized to th e FFOSZ field value. Bit s NTRANS control the nu mber of transactions

allowed in a single microframe (for high-speed isochronous and interrupt endpoints only).

Table 37. Buffer Status register: bit allocation

Bit 76543210

Symbol reserved BUF1 BUF0

Reset ------00

Bus reset ------00

Access ------RR

Table 38. Buffer Status register: bit descriptio n

Bit Symbol Description

7 to 2 - reserved

1 to 0 BUF[1:0] Buffer:

00 — The buffers are not filled.

01 — One of the buffers is filled.

10 — One of the buffers is filled.

11 — Both the buffers are filled.

Table 39. Endpoint MaxPacketSize register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved NTRANS[1:0] FFOSZ[10:8]

Reset - - -00000

Bus reset - - -00000

Access - - - R/W R/W R/W R/W R/W

Bit 76543210

Symbol FFOSZ[7:0]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 35 of 64

ISP1582

Hi-Speed USB peripheral controller

The ISP1582 supports all the transfers given in Ref. 1 “Universal Serial Bus Specification

Rev. 2.0”.

Each programmable FIFO can independently be configured using its Endpoint

MaxPacketSize register (R/W : 04h), but the total physical size of all enabled end points (IN

plus OUT) includin g se t-u p toke n bu ffer, control IN and control OUT, must not exceed

8192 bytes.

8.3.7 Endpoint Type register (address: 08h)

This register sets the endpoint type of the indexed endpoint: isochronous, bulk or

interrupt. It also serves to enable the endpoint and configure it for double buffering.

Automatic generation of an empty packet for a zero-length TX buffer can be disabled

using bit NOEMPKT. The register contains 2 bytes, and the bit allocation is shown in

Table 41.

Table 40. Endpoint MaxPacketSize register: bit description

Bit Symbol Description

15 to 13 - reserved

12 to 11 NTRANS[1:0] Number of Transactions: HS mode only.

00 — 1 packet per microframe

01 — 2 packets per microframe

10 — 3 packets per microframe

11 — reserved

These bits are applicable only for isochronous or interrupt

transactions.

10 to 0 FFOSZ[10:0] FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint.

Applies to both high-speed and full-speed operations.

Table 41. Endpoint Type register: bit allo cation

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset --------

Bus reset --------

Access --------

Bit 76543210

Symbol reserved NOEMPKT ENABLE DBLBUF ENDPTYP[1:0]

Reset - - -00000

Bus reset - - -00000

Access - - - R/W R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 36 of 64

ISP1582

Hi-Speed USB peripheral controller

8.4 DMA registers

The Generic DMA (GDMA) transfer can be done b y writing the proper opcode in the DMA

Command register. Control bits are given in Table 43.

GDMA read/write (opcode = 00h/01h) for GDMA mode: De pe nd in g on the MODE[1:0]

bits set in the DMA configuration register, the DACK, DIOR or DIOW signal strobes data.

These signals are driven by the external DMA controller.

GDMA mode can operate in eith er counter mode or EOT-only mode.

In counter mode, bit DIS_XFER_CNT in the DMA Configuration reg ister must be set to

logic 0. The DMA Transfer Counter register must be programmed before any DMA

command is issued. Th e DMA transfer counter is set by writing from the LSByte to the

MSByte (address: 34h to 37h). The DMA transfe r count is internally updated only af ter th e

MSByte is written. Once the DMA transfer is started, the transfer counter starts

decrementing and on re achin g 0, bit DMA_XFER_OK is set and a n interr upt is gener ated

by the ISP1582. If the DMA master wishes to terminate the DMA transfer, it can issue an

EOT signal to the ISP1582. This EOT signal overrides the transfer counter and can

terminate the DMA transfer at any time.

Table 42. Endpoint Type register: bit description

Bit Symbol Description

15 to 5 - reserved

4NOEMPKTNo Empty Packet: Logic 0 causes the ISP1582 to return a null length

packet for the IN token after the DMA IN transfer is complete. For the

IN DMA transfer , which does not require a null length packet after DMA

completion, set to logic 1 to disable the generation of the null length

packet.

3 ENABLE Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint.

The memory size is allocated as specified in the Endpoint

MaxPacketSize register. Logic 0 disables the FIFO.

Remark: Stalling a data endpoint will confuse the Data Toggle bit on

the stalled end point because the in ternal logic picks up from where it

has stalled. Therefore, the Data Toggle bit must be reset by disabling

and re-enabling the corresponding endpoint (by setting bit ENABLE to

logic 0 or logic 1 in the Endpoint Type register) to reset the PID.

2DBLBUF Double Buffering: Logic 1 enables double buffering for the indexed

endpoint. Logic 0 disables double buffering.

Remark: When performing a write to two empty buffers, ensure that a

minimum of 200 ns delay is provided from the last write of the first

buffer to the first write of the second buffer. Otherwise, the first few

data bytes may not be written to the second buffer, causing data

corruption.

1 to 0 ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type as follows.

00 — Not used

01 — Isochronous

10 — Bulk

11 — Interrupt

Product data sheet Rev. 09 — 29 September 2009 37 of 64

ISP1582

Hi-Speed USB peripheral controller

In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer

counter can still be programmed, it will not have any effect on the DMA transfer . The DMA

transfer will start once the DMA command is issued. Any of the following three ways will

terminate this DMA transfer:

•Detecting an external EOT

•Detecting an internal EOT (short packet on an OUT token)

•Issuing a GDMA stop command

There are three interrupts programmable to differentiate the method of DMA termination:

bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register. For

details, see Table 55.

Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the

other contro l sign als ar e no t 3- stated.

8.4.1 DMA Command register (address: 30h)

The DMA Command register is a 1-byte register (for bit allocation, see Table 44) that

initiates all DMA transfer activity on the DMA controller. The register is write-only: reading

it will return FFh.

Remark: The DMA bus will be in 3-state, until a DMA command is executed.

Table 43. Control bits for GDMA read/write (opcode = 00h/01h)

Control bits Description Reference

DMA Configuration register

MODE[1:0] determines the active read/write data strobe signals Table 49

WIDTH selects the DMA bus width: 8 or 16 bits

DIS_XFER_CNT disables the use of the DMA Transfer Counter

DMA Hardware register

EOT_POL selects the polarity of the EOT signal Table 51

ENDIAN[1:0] determines whether the data is to be byte swapped or

normal; applicable only in 16-bit mode

ACK_POL, DREQ_POL,

WRITE_POL, READ_POL select polarity of DMA handshake signals

Table 44. DMA Command register: bit allocation

Bit 76543210

Symbol DMA_CMD[7:0]

Reset 11111111

Bus reset 11111111

Access WWWWWWWW

Table 45. DMA Command register: bit description

Bit Symbol Description

7 to 0 DMA_CMD[7:0] DMA command code; see Table 46.

Product data sheet Rev. 09 — 29 September 2009 38 of 64

ISP1582

Hi-Speed USB peripheral controller

8.4.2 DMA Transfer Counter register (address: 34h)

This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates

the remaining number of bytes left for tra nsfer. The bit allocation is given in Table 47.

For IN endpoint — Because there is a FIFO in the ISP1582 DMA controller, some data

may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and

the maximum delay time for data to be shifted to endpoint buffer is 60 ns.

For OUT endpoint — Data will not be cleared from the end point buffer, until all the data is

read from the DMA FIFO.

If the DMA counter is disabled in the DMA transfer , it will still decrement and rollover when

it reaches zero.

Table 46. DMA commands

Code Name Description

00h GDMA Read Generic DMA IN token transfer: Data is transferred from the external DMA bus to the

internal buffer. Strobe: DIOW by the external DMA controller.

01h GDMA Write Generic DMA OUT token transfer: Data is transferred from the internal buffer to the external

DMA bus. Strobe: DIOR by the external DMA controller.

02h to 0Dh - reserved

0Eh Validate Buffer Validate Buffer (for debugging only): Request from the microcontroller to validate the

endp oi n t buffer, following a DMA-to-U SB da ta transfer.

0Fh Clear Buffer Clear Buffer: Request from the microcontroller to clear the endpoint buffer, after a

DMA-to-USB data transfer . Logic 1 clears the TX buffer of the indexed endpoint; the RX buffer

is not affected. The TX buffer is automatically cleared once data is sent on the USB bus. This

bit is set only when it is necessary to forcefully clear the buffer.

Remark: If using double buffer, to clear both the buffers issue the Clear Buffer command two

times, that is, set and clear this bit two times.

10h - reserved

11h Reset DMA R eset DMA: Initializes the DMA core to its power-on reset state.

Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK,

DIOW and DIOR handshake pins will temporarily be asserted. This can confuse the external

DMA controller. To prevent this, start the external DMA controller only after the DMA reset.

12h - reserved

13h GDMA Stop GDMA stop: This command stops the GDMA data transfer . Any dat a in the OUT endpoint that

is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint will

be written to the endpoint buffer. An interrupt bit will be set to indicate the completion of the

DMA Stop command.

Remark: For the DMA OUT transfer, if the DMA Burst Counter register is programmed to

some value, for example 512 bytes, and if a GDMA Stop command is issued in the middle of a

transfer, the transfer will continue until the end of the burst size (512 bytes). Issuing a GDMA

stop command does not allow the ISP1582 to stop in the middle of the burst. It can only be

stopped in between bursts.

14h to FFh - reserved

Table 47. DMA Transfer Counter register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol DMACR4 = DMACR[31:24]

Product data sheet Rev. 09 — 29 September 2009 39 of 64

ISP1582

Hi-Speed USB peripheral controller

8.4.3 DMA Configuration register (address: 38h)

This register defines the DMA configuration for GDMA mode. The DMA Configuration

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol DMACR3 = DMACR[23:16]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol DMACR2 = DMACR[15:8]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol DMACR1 = DMACR[7:0]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 47. DMA Transfer Counter register: bit allocation …continued

Bit 31 30 29 28 27 26 25 24

Table 48. DMA Transfer Counter register: bit description

Bit Symbol Description

31 to 24 DMACR4 = DMACR[31:24] DMA transfer counter byte 4 (MSByte)

23 to 16 DMACR3 = DMACR[23:16] DMA transfer counter byte 3

15 to 8 DMACR2 = DMACR[15:8] DMA transfer counter byte 2

7 to 0 DMACR1 = DMACR[7:0] DMA transfer counter byte 1 (LSByte)

Table 49. DMA Configuration register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset --------

Bus reset --------

Access --------

Bit 7 6 5 4 3 2 1 0

Symbol DIS_

XFER_CNT reserved MODE[1:0] reserved WIDTH

Reset 0---00-1

Bus reset 0---00-1

Access R/W - - - R/W R/W - R/W

Product data sheet Rev. 09 — 29 September 2009 40 of 64

ISP1582

Hi-Speed USB peripheral controller

[1] The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is,

after configuring the DMA Configuration register).

8.4.4 DMA Hardware register (address: 3Ch)

The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 51.

This register de term in es th e po lar i ty of bus control signals (EOT, DACK, DREQ, DIOR

and DIOW). It also controls whether the upper and lower parts of the data bus ar e

swapped (bits ENDIAN[1:0]).

Table 50. DMA Configuration register: bit description

Bit Symbol Description[1]

15 to 8 - reserved

7 DIS_XFER_CNT Disable T ransfer Count: Logic 1 disables the DMA Transfer

Counter (see Table 47).

6 to 4 - reserved

3 to 2 MODE[1:0] Mode: These bits affect GDMA handshake signals.

00 — DIOW strobes data from the DMA bus into the ISP1582; DIOR

puts data from the ISP1582 on the DMA bus.

01 — DACK strobes data from the DMA bus into the ISP1582; DIOR

puts data from the ISP1582 on the DMA bus.

10 — DACK strobes data from the DMA bus into the ISP1582 and

also puts data from the ISP1582 on the DMA bus.

11 — reserved

1 - reserved

0WIDTH Width: This bit selects the DMA bus width.

0 — 8-bit data bus

1 — 16-bit data bus

Table 51. DMA Hardware register: bit allocation

Bit 76543210

Symbol ENDIAN[1:0] EOT_POL reserved ACK_POL DREQ_

POL WRITE_

POL READ_

POL

Reset 000-0100

Bus reset 000-0100

Access R/W R/W R/W - R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 41 of 64

ISP1582

Hi-Speed USB peripheral controller

8.4.5 DMA Interrupt Reason register (address: 50h)

This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a

DMA command is executed. An interrupt source is cleared by writing logic 1 to the

corresponding bit. On detecting the interrupt, the external microprocessor must read the

DMA Interrupt Reaso n register and mask it with the corresponding bits in the DMA

Interrupt Enable register to determine the source of the interrupt.

The bit allocation is given in Table 53.

Table 52. DMA Hardware register: bit description

Bit Symbol Description

7 to 6 ENDIAN[1:0] Endian: These bits determine whether the data bus is swapped between

the internal RAM and the DMA bus.

00 — Normal data representation; 16-bit bus: MSByte on DATA[15:8],

LSByte on DATA[7:0]

01 — Swapped data representation; 16-bit bus: MSByte on DATA[7:0],

LSByte on DATA[15:8]

10 — reserved

11 — reserved

Remark: While operating with the 8-bit data bus, bits ENDIAN[1:0] must

always be set to 00b.

5EOT_POLEOT Polarity: Selects the polarity of the End-Of-Transfer input.

0 — EOT is active LOW

1 — EOT is active HIGH

4 - reserved; must be set to logic 0.

3ACK_POLAcknowledgment Polarity: Selects the DMA acknowledgment polarity.

0 — DACK is active LOW

1 — DACK is active HIGH

2DREQ_POLDREQ Polarity: Selects the DMA request polarity.

0 — DREQ is active LOW

1 — DREQ is active HIGH

1WRITE_POLWrite Polarity: Selects the DIOW strobe polarity.

0 — DIOW is active LOW

1 — DIOW is active HIGH

0 READ_POL Read Polarity: Selects the DIOR strobe polarity.

0 — DIOR is active LOW

1 — DIOR is active HIGH

Table 53. DMA Interrupt Reason register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol TEST3 reserved GDMA_

STOP EXT_EOT INT_EOT reserved DMA_

XFER_OK

Reset ---000-0

Bus reset ---000-0

Access R - - R/W R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 42 of 64

ISP1582

Hi-Speed USB peripheral controller

8.4.6 DMA Interrupt Enable register (address: 54h)

This 2-byte register controls the interrupt generation of the source bits in the DMA

Interrupt Reason register. The bit allocation is given in Table 56. The bit description is

given in Table 54.

Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is

disabled, with the values turning to logic 0.

Bit 76543210

Symbol reserved

Reset --------

Bus reset --------

Access --------

Table 54. DMA Interrupt Reason register: bit description

Bit Symbol Description

15 TEST3 This bit is set when the DMA transfer for a packet (OUT transfer)

terminates before the whole packet has been transferred. This bit is

a status bit, and the corresponding mask bit of this register is always

logic 0 . Writing an y value other than logic 0 has no effect.

14 to 13 - reserved

12 GDMA_STOP GDMA Stop: When the GDMA_STOP command is issued to DMA

Command registers, it means the DMA transfer has successfully

terminated.

11 EXT_EOT External EOT: Logic 1 indicates that an external EOT is detected.

10 INT_EOT Internal EOT: Logic 1 indicates that an internal EOT is detected; see

Table 55.

9 - reserved

8DMA_XFER_OKDMA Transfer OK: Logic 1 indicates that the DMA transfer is

completed (DMA Transfer Counter has become zero).

7 to 0 - reserved

Table 55. Internal EOT-functional relation with bit DMA_XFER_OK

INT_EOT DMA_XFER_OK Description

1 0 During the DMA transfer, there is a premature termination with

short packet.

1 1 DMA transfer is completed with short packet and the DMA

transfer counter has reached 0.

0 1 DMA transfer is completed without any short packet and the DMA

transfer counter has reached 0.

Table 56. DMA Interrupt Enable register: bit allo cation

Bit 15 14 13 12 11 10 9 8

Symbol TEST4 reserved IE_GDMA_

STOP IE_EXT_

EOT IE_INT_

EOT reserved IE_DMA_

XFER_OK

Reset - - -00000

Bus reset - - -00000

Access R - - R/W R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 43 of 64

ISP1582

Hi-Speed USB peripheral controller

8.4.7 DMA Endpoint register (address: 58h)

This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA

transfers. The bit allocation is given in Table 57.

The DMA Endpoint register must not reference the endpoint that is indexed by the

Endpoint Index register (2Ch) at any time. Doing so will result in data corruption.

Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the

DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not

reference the same endpoint on the Endpoint Index register.

8.4.8 DMA Burst Counter register (address: 64h)

Table 59 shows the bit allocation of the 2-byte register.

Bit 76543210

Symbol reserved

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 57. DMA Endpoint register: bit allocation

Bit 76543210

Symbol reserved EPIDX[2:0] DMADIR

Reset - - - -0000

Bus reset - - - -0000

Access - - - - R/W R/W R/W R/W

Table 58. DMA Endpoint register: bit description

Bit Symbol Description

7 to 4 - reserved

3 to 1 EPIDX[2:0] Endpoint Index: Selects the indicated endpoint for DMA access

0DMADIRDMA Direction:

0 — Selects the RX/OUT FIFO for DMA read transfers

1 — Selects the TX/IN FIFO for DMA write transfers

Table 59. DMA Burst Counter register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved BURSTCOUNTER[12:8]

Reset - - -00000

Bus reset - - -00000

Access - - - R/W R/W R/W R/W R/W

Bit 76543210

Symbol BURSTCOUNTER[7:0]

Reset 00000010

Bus reset 00000010

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 09 — 29 September 2009 44 of 64

ISP1582

Hi-Speed USB peripheral controller

8.5 General registers

8.5.1 Interrupt register (address: 18h)

The Interrupt register consists of 4 bytes. The bit allocation is given in Table 61.

When a bit is set in the Interrupt register, it indicates that the hardware condition for an

interrupt has occurred. When the Interrupt register content is nonzero, the INT output will

be asserted correspon ding to the Inte rr up t En ab le r egister. On detecting the in te rrupt, the

external micro pr o ces s o r must re ad the Interrupt register and mask it with the

corresponding bits in the Interrupt Enable register to determine the source of the interrupt.

Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various

bus states can generate an interrupt: resu me, suspend, p seudo SOF, SOF and bus reset.

The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in

the DMA Interrupt Reason register.

Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can

be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt

Reason register, followed by writing logic 1 to the DMA bit of the Interrup t re gist er.

Table 60. DMA Burst Counter register: bit description

Bit Symbol Description

15 to 13 - reserved

12 to 0 BURST

COUNTER

[12:0]

Burst Counter: This register defines the burst length. The counter must

be programmed to be a multiple of two in 16-bit mode.

The value of the burst counter must be programmed so tha t th e bu rst

counter is a factor of the buffer size.

It is used to determine the assertion and deassertion of DREQ.

Table 61. Interrupt register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved EP7TX EP7RX

Reset ------00

Bus reset ------00

Access ------R/WR/W

Bit 23 22 21 20 19 18 17 16

Symbol EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX EP3TX EP3RX

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX reserved EP0SETUP

Reset 000000-0

Bus reset 000000-0

Access R/W R/W R/W R/W R/W R/W - R/W

Product data sheet Rev. 09 — 29 September 2009 45 of 64

ISP1582

Hi-Speed USB peripheral controller

Bit 76543210

Symbol VBUS DMA HS_STAT RESUME SUSP PSOF SOF BRESET

Reset 00000000

Bus reset 00000001

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 62. Interrupt register: bit description

Bit Symbol Description

31 to 26 - reserved

25 EP7TX logic 1 indicates the endpoint 7 TX buffer as interrupt so urce

24 EP7 RX logic 1 indicates the endpoint 7 RX buffer as interrupt source

23 EP6TX logic 1 indicates the endp oint 6 TX buffer as interr up t so urce

22 EP6 RX logic 1 indicates the endpoint 6 RX buffer as interrupt source

21 EP5TX logic 1 indicates the endp oint 5 TX buffer as interr up t so urce

20 EP5 RX logic 1 indicates the endpoint 5 RX buffer as interrupt source

19 EP4TX logic 1 indicates the endp oint 4 TX buffer as interr up t so urce

18 EP4 RX logic 1 indicates the endpoint 4 RX buffer as interrupt source

17 EP3TX logic 1 indicates the endp oint 3 TX buffer as interr up t so urce

16 EP3 RX logic 1 indicates the endpoint 3 RX buffer as interrupt source.

15 EP2TX logic 1 indicates the endp oint 2 TX buffer as interr up t so urce

14 EP2 RX logic 1 indicates the endpoint 2 RX buffer as interrupt source

13 EP1TX logic 1 indicates th e e ndpoint 1 TX buffer as interrupt so urce

12 EP1 RX logic 1 indicates the endpoint 1 RX buffer as interrupt source

11 EP0TX logic 1 indicates the e ndpoint 0 data TX buf fe r as interrupt source

10 EP0 RX logic 1 indicates the endpoint 0 data RX buffer as interrupt source

9 - reserved

8 EP0SETUP logic 1 indicates that a SETUP token was received on endpoint 0

7 VBUS logic 1 indicates a transition from LOW to HIGH transition on VBUS

6DMA DMA St atus: Logic 1 indicates a change in the DMA Interrupt Reason

5 HS_STAT High-S peed Status: Logic 1 indicate s a change from full-speed to

high-speed mode (HS connection). This bit is not set when the system

goes into full-speed suspend.

4 RESUME Resume Status: Logic 1 indicates that a status change from suspend

to resume (active) was detected.

3SUSPSuspend St a tus: Logic 1 indicates that a status change from active to

suspend was detected on the bus.

2PSOFPseudo SOF Interrupt: Logic 1 indicates that a pseudo SOF or μSOF

was received. Pseudo SOF is an internally generated clock signal

(full-speed: 1 ms period, high -speed: 125 μs period) that is not

synchronized to the USB bus SOF or μSOF.

1SOF SOF Interrupt: Logic 1 indicates that a SOF or μSOF was received.

0 BRESET Bus Reset: Logic 1 indicates that a USB bus reset was de tected.

When bit OTG in the OTG register is set, BRESET will not be set;

instead, this interrupt bit will report SE0 on DP and DM for 2 ms.

Product data sheet Rev. 09 — 29 September 2009 46 of 64

ISP1582

Hi-Speed USB peripheral controller

8.5.2 Chip ID register (address: 70h)

This read-only regi ster contains th e chip identification and hardware version numbers.

Firmware must check this information to determine functions and features supp orted. The

8.5.3 Frame Number register (address: 74h)

This read-only register contains the frame number of the last successfully received

Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in

Table 65. In case of 8-bit access, the register content is returned lower byte first.

Table 63. Chip ID register: bit allocation

Bit 23 22 21 20 19 18 17 16

Symbol CHIPID[15:8]

Reset 00010101

Bus reset 00010101

Access RRRRRRRR

Bit 15 14 13 12 11 10 9 8

Symbol CHIPID[7:0]

Reset 10000010

Bus reset 10000010

Access RRRRRRRR

Bit 76543210

Symbol VERSION[7:0]

Reset 00110000

Bus reset 00110000

Access RRRRRRRR

Table 64. Chip ID register: bit description

Bit Symbol Description

23 to 16 CHIPID[15:8] Chip ID: Lower byte (15h)

15 to 8 CHIPID[7:0] Chip ID: Upper byte (82h)

7 to 0 VERSION[7:0] Version: Version number (30h)

Table 65. Frame Number register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved MICROSOF[2:0] SOFR[10:8]

Reset - -000000

Bus reset - -000000

Access - -RRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol SOFR[7:0]

Reset 00000000

Bus reset 00000000

Access RRRRRRRR

Product data sheet Rev. 09 — 29 September 2009 47 of 64

ISP1582

Hi-Speed USB peripheral controller

8.5.4 Scratch register (address: 78h)

This 16-bit register can be used by the firmware to save and restore information. For

example, the device st atus before it enters the suspend st ate. The bit allocation is given in

Table 67.

8.5.5 Unlock Device register (address: 7Ch)

To protect registers from getting corrupted when th e ISP1582 goes into suspend, the write

operation is disabled if bit PWRON in the Mode register is se t to logic 0. In this c ase, when

the chip resumes, the Unlock Device command must first be issued to this register befo re

attempting to write to the rest of the registers. This is done by writing unlock co de (AA37h)

to this register. The bit allocation of the Unlock Device register is given in Table 69.

Table 66. Frame Number register: bit description

Bit Symbol Description

15 to 14 - reserved

13 to 11 MICROSOF[2:0] microframe number

10 to 0 SOFR[10:0] frame number

Table 67. Scratch register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol SFIRH[7:0]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol SFIRL[7:0]

Reset 00000000

Bus reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 68. Scratch register: bit description

Bit Symbol Description

15 to 8 SFIRH[7:0] Scratch firmware information register (higher byte)

7 to 0 SFIRL[7:0] Scratch firmware informati on register (lower byte)

Table 69. Unlock Device register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol ULCODE[15:8] = AAh

Reset not applicable

Bus reset not applicable

Access WWWWWWWW

Bit 76543210

Symbol ULCODE[7:0] = 37h

Product data sheet Rev. 09 — 29 September 2009 48 of 64

ISP1582

Hi-Speed USB peripheral controller

When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you

do not need to issue the Unlock comman d because the microprocessor is powered and

therefore, the RD_N, WR_N and CS_N signals maintain their states.

When bit PWRON is logic 0, the RD_N, WR_N and CS_N signals are fl oating because the

microprocessor is not powered. To protect the ISP1582 registers from being corrupted

during suspend, register write is locked when the chip goes into suspend. Therefore, you

need to issue the Unlock command to unlock the ISP1582 registers.

8.5.6 Test Mode register (address: 84h)

This 1-byte register allows the firmware to set p ins DP and DM to predetermined st ates for

testing purposes. The bit allocation is given in Table 71.

Remark: Only one bit can be set to logic 1 at a time. This must be implemented for the

Hi-Speed USB logo compliance testing. To exit test mode, power cycle is required.

[1] Either FORCEHS or FORCEFS must be set at a time.

[2] Of the four bits (PRBS, KSTATE, JSTAT E and SE0_NAK), only one bit must be set at a time.

Reset not applicable

Bus reset not applicable

Access WWWWWWWW

Bit 76543210

Table 70. Unlock Device register: bit description

Bit Symbol Description

15 to 0 ULCODE[15:0] Unlock Code: Writing data AA37h unlocks the internal registers

and FIFOs for writing, following a resume.

Table 71. Test Mode registe r: bi t allocation

Bit 76543210

Symbol FORCEHS reserved FORCEFS PRBS KSTATE JSTATE SE0_NAK

Reset 0- -00000

Bus reset unchanged - - unchanged 0000

Access R/W - - R/W R/W R/W R/W R/W

Table 72. Test Mode register: bit description

Bit Symbol Description

7 FORCEHS Force High-Speed: Logic 1[1] forces the hardware to high-speed mode only

and disables the chirp detection logic.

6 to 5 - reserved

4 FORCEFS Force Fu ll-Speed: Logic 1[1] forces the physical layer to full-speed mode

only and disables the chirp detection log ic.

3PRBSPredetermined Random Pattern: Logic 1[2] sets pins DP and DM to toggle

in a predetermined random pattern.

2KSTATEK-State: Logic 1[2] sets pins DP and DM to the K state.

1JSTATEJ-State: Logic 1[2] sets pins DP and DM to the J state.

0 SE0_NAK SE0 NAK: Logic 1[2] sets pins DP and DM to a high-speed quiescent state.

The device only responds to a valid high-speed IN token with a NAK.

Product data sheet Rev. 09 — 29 September 2009 49 of 64

ISP1582

Hi-Speed USB peripheral controller

9. Limiting values

[1] The maximum value for 5 V tolerant pins is 6 V.

10. Recommended operating conditions

11. Static characteristics

[1] ICC(I/O) test condition: device set up under the test mode vector and I/O is subjected to external conditions.

Table 73. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +4.6 V

VCC(I/O) input/out pu t su pp l y voltage −0.5 +4.6 V

VIinput voltage [1] −0.5 VCC + 0.5 V

Ilu latch-up current VI< 0 V or VI> VCC -100 mA

Vesd electrostatic discharge voltage ILI < 1 μA−2000 +2000 V

Tstg storage temperature −40 +125 °C

Table 74. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 3.0 - 3.6 V

VCC(I/O) input/output supply voltage VCC -V

CC V

VIinput voltage VCC = 3.3 V 0 - 3.3 V

VIA(I/O) input voltage on analog I/O pins on pins DP and DM 0 - 3.6 V

V(pu)OD open-drain pull-up voltage 0 - VCC V

Tamb ambient temperature −40 - +85 °C

Tjjunction temperature −40 - +125 °C

Table 75. Static characteristics: supply pins

VCC = 3.3 V

0.3 V; VGND = 0 V; Tamb =

−

C to +85

C; typical values at Tamb = 25

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply voltage

VCC supply voltage 3.0 3.3 3.6 V

ICC supply current VCC = 3.3 V

high-speed - 45 60 mA

full-speed - 17 25 mA

ICC(susp) suspend supply current VCC = 3.3 V - 160 - μA

I/O pad supply voltage

VCC(I/O) input/output supply voltage VCC VCC VCC V

ICC(I/O) supply current on pin VCC(I/O) [1] -3-mA

Regulated supply volt age

VCC(1V8) supply voltage (1.8 V) with voltage converter 1.65 1.8 1.95 V

Product data sheet Rev. 09 — 29 September 2009 50 of 64

ISP1582

Hi-Speed USB peripheral controller

[1] This value is applicable to transistor input only. The value will be different if internal pull-up or pull-down resistors are used.

Table 76. Static characteristics: digital pins

VCC(I/O) = VCC; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Input levels

VIL LOW-level input voltage - - 0.3VCC(I/O) V

VIH HIGH-level input voltage 0.7VCC(I/O) -- V

Output levels

VOL LOW-level output voltage IOL = rated drive - - 0.15VCC(I/O) V

VOH HIGH-level output voltage IOH = rated drive 0.8V CC(I/O) -- V

Leakage current

ILI input leakage curren t [1] −5- +5 μA

Table 77. Static characteristics: OTG detection

VCC(I/O) = VCC; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Charging and discharging resistor

RDN(VBUS) pull-down resistance on pin

VBUS

only when bit DISCV is

set in the OTG register 680 800 1030 Ω

RUP(DP) pull-up resistance on pin DP only when bit DP is set

in the OTG register 300 550 780 Ω

Comparator levels

VBVALID VBUS valid detection 2.0 - 4.0 V

VSESEND VBUS B-session end detection 0.2 - 0.8 V

Table 78. Static characteristics: analog I/O pi ns DP and DM

VCC = 3.3 V

0.3 V; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.[1]

Symbol Parameter Conditions Min Typ Max Unit

Input levels

VDI differential input sensitivity voltage |VI(DP) − VI(DM)|0.2 - - V

VCM differential common mode voltage

range includes VDI range 0.8 - 2.5 V

VSE single-ended receiver threshold 0.8 - 2.0 V

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

Schmitt-trigger inputs

Vth(LH) positive-going threshold voltage 1.4 - 1.9 V

Vth(HL) negative-going threshold voltage 0.9 - 1.5 V

Vhys hysteresis voltage 0.4 - 0.7 V

Output levels

VOL LOW-level output voltage RL= 1.5 kΩ to 3.6 V - - 0.4 V

VOH HIGH-level output voltage RL= 15 kΩ to GND 2.8 - 3.6 V

Leakage current

ILZ OFF-state leakage current 0 V < VI< 3.3 V −10 - +10 μA

Product data sheet Rev. 09 — 29 September 2009 51 of 64

ISP1582

Hi-Speed USB peripheral controller

[1] Pin DP is the USB positive data pin, and pin DM is the USB negative data pin.

12. Dynamic characteristics

Capacitance

Cin input capacitance pin to GND - - 10 pF

Resistance

ZDRV driver output impedance for driver

which is not high-speed capable steady-state drive 40.5 - 49.5 Ω

ZINP input impedance exclusive of

pull-up/pull-down (fo r

low-/full-speed)

10 - - MΩ

Table 78. Static characteristics: analog I/O pi ns DP and DM …continued

VCC = 3.3 V

0.3 V; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.[1]

Symbol Parameter Conditions Min Typ Max Unit

Table 79. Dynamic character istics

VCC = 3.3 V

0.3 V; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Reset

tW(RESET_N) external RESET_N pulse width crystal oscillator running 500 - - μs

Crystal oscillator

fXTAL1 frequency on pin XTAL1 - 12 - MHz

RSseries resistance - - 100 Ω

CLload capacitance - 18 - pF

External clock input

VIinput voltage 1.65 1.8 1.95 V

tJexternal clock jitter - - 500 ps

δclock duty cycle 45 50 55 %

trrise time - - 3 ns

tffall time - - 3 ns

Table 80. Dynamic character istics: analog I/O pins DP and DM

VCC = 3.3 V

0.3 V; VGND = 0 V; Tamb =

−

C to +85

C; CL= 50 pF; RPU = 1.5 k

on DP to VTERM; test circuit of Figure 23;

unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Driver characteristics

Full-speed mode

tFR rise time CL= 50 pF; 10 % to 90 % of |VOH −

VOL|

4- 20ns

tFF fall time CL= 50 pF; 90 % to 10 % of |VOH −

VOL|

4- 20ns

FRFM differential rise time/fall time

matching tFR/tFF [1] 90 - 111.11 %

VCRS output signal crossover voltage [1][2] 1.3- 2.0V

High-speed mode

tHSR rise time (10 % to 90 %) with captive cable 500 - - ps

Product data sheet Rev. 09 — 29 September 2009 52 of 64

ISP1582

Hi-Speed USB peripheral controller

[1] Excluding the first transition from the idle state.

[2] Characterized only, not tested. Limits guaranteed by design.

tHSF fall time (10 % to 90 %) with captive cable 500 - - ps

Data source timing

Full-speed mode

tFEOPT source SE0 interval of EOP see Figure 13 [2] 160- 175ns

tFDEOP source jitter for differential

transition to SE0 transition see Figure 13 [2] −2- +5ns

Receiver timing

Full-speed mode

tJR1 receiver jitter to next transition see Figure 14 [2] −18.5 - +18.5 ns

tJR2 receiver jitter for paired

transitions see Figure 14 [2] −9- +9ns

tFEOPR receiver SE0 interval of EOP accepted as EOP; see Figure 13 [2] 82 - - ns

tFST width of SE0 interval during

differential transition rejected as EOP; see Figure 15 [2] --14ns

Table 80. Dynamic character istics: analog I/O pins DP and DM …continued

VCC = 3.3 V

0.3 V; VGND = 0 V; Tamb =

−

C to +85

C; CL= 50 pF; RPU = 1.5 k

on DP to VTERM; test circuit of Figure 23;

unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

TPERIOD is the bit duration corresponding to the USB data rate.

Full-speed timing symbols have a subscript prefix ‘F’, low-speed timing symbols have a prefix 'L'.

Fig 13. Source differential data-to-EOP transition skew and EOP width

mgr776

PERIOD

differential

data lines

crossover point

differential data to

SE0/EOP skew

N × T

PERIOD

+ t

DEOP

source EOP width: t

EOPT

receiver EOP width: t

EOPR

crossover point

extended

+3.3 V

0 V

Product data sheet Rev. 09 — 29 September 2009 53 of 64

ISP1582

Hi-Speed USB peripheral controller

12.1 Register access timing

TPERIOD is the bit duration corresponding to the USB data rate.

Fig 14. Receiver differential data jitter

mgr871

PERIOD

differential

data lines

+3.3 V

0 V t

JR1

JR2

consecutive

transitions

N × T

PERIOD

+ t

JR1

paired

transitions

N × T

PERIOD

+ t

JR2

Fig 15. Receiver SE0 width tolerance

mgr872

differential

data lines

+3.3 V

0 V

tFST

VIH(min)

Table 81. Register access timing parameters: separate address and data buses

VCC(I/O) = VCC = 3.3 V; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Reading

tRLRH RD_N LOW pulse width > tRLDV -- ns

tAVRL address set-up time before RD_N LOW 0 - - ns

tRHAX address hold time after RD_N HIGH 0 - - ns

tRLDV RD_N LOW to data valid delay - - 26 ns

tRHDZ RD_N HIGH to data outputs three-state

delay 0 - 15 ns

tRHSH RD_N HIGH to CS_N HIGH delay 0 - - ns

tSLRL CS_N LOW to RD_N LOW delay 2 - - ns

Writing

tWLWH WR_N LOW pulse width 15 - - ns

tAVWL address set-up time before WR_N LOW 0 - - ns

tWHAX address hold time after WR_N HIGH 0 - - ns

tDVWH data set-up time before WR_N HIGH 11 - - ns

tWHDZ data hold time after WR_N HIGH 5 - - ns

Product data sheet Rev. 09 — 29 September 2009 54 of 64

ISP1582

Hi-Speed USB peripheral controller

tWHSH WR_N HIGH to CS_N HIGH delay 0 - - ns

tSLWL CS_N LOW to WR_N LOW delay 2 - - ns

General

Tcy(RW) read or write cycle time 50 - - ns

tWHRL WR_N HIGH to RD_N LOW time 91 - - ns

Table 81. Register access timing parameters: separate address and data buses …continued

VCC(I/O) = VCC = 3.3 V; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Fig 16. Re gister access timing: separate address and data buses

(write) DATA[15:0]

(read) DATA[15:0]

004aaa276

A[7:0]

tWHSH

tAVWL

tDVWH

tRHDZ

tAVRL

Tcy(RW)

tWHAX

tRHAX

tRLDV

tWHDZ

WR_N

CS_N

RD_N

tRHSH

tRLRH

tWLWH

tSLWL

tSLRL

Applies only to write followed by read to the same or different registers.

Fig 17. ISP1582 ready signal timing

004aab064

WR_N

RD_N

WHRL

Product data sheet Rev. 09 — 29 September 2009 55 of 64

ISP1582

Hi-Speed USB peripheral controller

12.2 DMA timing

Table 82. GDMA mode timing parameters

VCC(I/O) = VCC = 3.3 V; VGND = 0 V; Tamb =

−

C to +85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Tcy1 read or write cycle time 75 - - ns

tsu1 DREQ set-up time before first DACK on 10 - - ns

td1 DREQ on delay after last strobe off 33.33 - - ns

th1 DREQ hold time after last strobe on 0 - 53 ns

tw1 DIOR or DIOW pulse width 39 - 600 ns

tw2 DIOR/DIOW recovery time 36 - - ns

td2 read data valid delay after strobe on - - 20 ns

th2 read data hold time after strobe off - - 5 ns

th3 write data hold time after strobe off 1 - - ns

tsu2 write data set-up time before strobe off 10 - - ns

tsu3 DACK set-up time before DIOR/DIOW

assertion 0--ns

ta1 DACK deassertion after DIOR/DIOW

deassertion 0 - 30 ns

DREQ is continuously asserted, until the last transfer is done or the FIFO is full.

Data strobes: DIOR (read) and DIOW (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 18. GDMA mode timing (bits MODE[1:0] = 00)

th1

tw1

tsu1

td1

tsu2

td2 th2

Tcy1

(write) DATA[15:0]

(read) DATA[15:0]

DREQ(2)

DACK(1)

DIOR or DIOW(1)

mgt500

tsu3

tw2

ta1

th3

Product data sheet Rev. 09 — 29 September 2009 56 of 64

ISP1582

Hi-Speed USB peripheral controller

DREQ is asserted for every transfer.

Data strobes: DIOR (read) and DACK (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 19. GDMA mode timing (bits MODE[1:0] = 01)

td1

tw1

tsu1 th1

tsu2

td2

th2

Tcy1

(write) DATA[15:0]

(read) DATA[15:0]

DREQ(2)

DACK(1)

DIOR or DIOW(1)

mgt502

tsu3

ta1

th3

DREQ is continuously asserted, until the last transfer is done or the FIFO is full.

Data strobe: DACK (read/write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 20. GDMA mode timing (bits MODE[1:0] = 10)

th1

tw1

tsu1

td1

tsu2

td2

th2

Tcy1

(write) DATA[15:0]

(read) DATA[15:0]

DREQ(2)

HIGH

DACK(1)

DIOR or DIOW(1)

mgt501

tw2

th3

Product data sheet Rev. 09 — 29 September 2009 57 of 64

ISP1582

Hi-Speed USB peripheral controller

13. Application information

14. Test information

The dynamic characteristics of the analog I/O ports DP and DM were determined using

the circuit show n in Figure 23.

(1) Programmable polarity: shown as active LOW.

Remark: EOT must be valid for 36 ns (minimum) when RD_N or WR_N is active.

Fig 21. EOT timing in generic processor mode

EOT

(1)

RW_N or WR_N

004aaa928

36 ns (min)

DREQ

Fig 22. Typical interface connections for generic processor mode

004aaa206

data

read strobe

ISP1582

CPU DATA[15:0]

RD_N

address 8A[7:0]

write strobe WR_N

chip select CS_N

In full-speed mode, an internal 1.5 kΩ pull-up resistor is connected to pin DP.

Fig 23. Load impedance for pins DP and DM (full-speed mode)

test point

15 kΩ

DUT

mgt495

50 pF

Product data sheet Rev. 09 — 29 September 2009 58 of 64

ISP1582

Hi-Speed USB peripheral controller

15. Package outline

Fig 24. Package outline SOT684-1 (HVQFN56)

0.5

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

4.45

4.15

4.45

4.15

6.5

0.30

0.18

0.05

0.00 8.1

7.9 8.1

7.9 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT684-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT684-1

HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;

56 terminals; body 8 x 8 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

15 28

56 43

01-08-08

02-10-22

terminal 1

index area

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 09 — 29 September 2009 59 of 64

ISP1582

Hi-Speed USB peripheral controller

16. Abbreviations

17. References

[1] Universal Serial Bus Specification Rev. 2.0

[2] On-The-Go Supplement to the USB Specification Rev. 1.3

[3] Using ISP1582/3 in a composite device application with alternate settings

(AN10071)

[4] ISP1582/83 and ISP1761 clearing an IN buffer (AN10045)

Table 83. Abbreviations

Acronym Description

ACK Acknowledgement

ACPI Advanced Configuration and Power Interface

ASIC Application-Specific Integrated Circuit

CRC Cyclic Redundancy Code

DMA Direct Memory Access

EMI ElectroMagnetic Interference

ESR Equivalent Series Resistance

FS Full-Speed

GDMA Generic DMA

HS High-Speed

MMU Memory Management Unit

NAK Not Acknowledged

NRZI Non-Return-to-Zero Inverted

NYET Not Yet

OTG On-The-Go

PCB Printed-Circuit Board

PHY Physical

PID Packet IDentifier

PIE Parallel Interface Engine

PIO Parallel Input/Output

PLL Phase-Locked Loop

POR Power-On Reset

RX Receive

SE0 Single-Ended zero

SIE Serial Interface Engine

SRP Session Request Protocol

TTL Transist or- Transistor Logic

TX Transmit

USB Universal Serial Bus

Product data sheet Rev. 09 — 29 September 2009 60 of 64

ISP1582

Hi-Speed USB peripheral controller

18. Revision history

Table 84. Revision history

Document ID Release date Data sheet status Change notice Supersedes

ISP1582_9 20090929 Product data sheet - ISP1582_8

Modifications: •Rebranded to the ST-Ericsson template.

•Table 1 “Ordering information”: updated.

•Removed soldering information.

ISP1582_8 20090122 Product data sheet - ISP1582_7

ISP1582_7 20080922 Product data sheet - ISP1582_6

ISP1582_6 20070920 Product data sheet - ISP1582_5

ISP1582_5 20070201 Product data sheet - ISP1582-04

ISP1582-04

(9397 750 14033) 20050104 Product data 20 0412038 ISP1582-03

ISP1582-03

(9397 750 13699) 20040825 Preliminary data - ISP1582-02

ISP1582-02

(9397 750 12979) 20040629 Preliminary data - ISP1582-01

ISP1582-01

(9397 750 11496) 20040223 Preliminary data - -

ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009  61 of 64
ISP1582
Hi-Speed USB peripheral controller
19. Tables
Table 1. Ordering information  . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 3. Endpoint access and programmability . . . . . . . .8
Table 4. ISP1582 pin status . . . . . . . . . . . . . . . . . . . . . .11
Table 5. ISP1582 output status . . . . . . . . . . . . . . . . . . .12
Table 6. Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 7. Operation truth table for SoftConnect  . . . . . . .18
Table 8. Operation truth table for clock off during 
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 9. Operation truth table for back voltage 
compliance  . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 10. Operation truth table for OTG  . . . . . . . . . . . . .19
Table 11. Operation truth table for SoftConnect  . . . . . . .19
Table 12. Operation truth table for clock off during 
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 13. Operation truth table for back voltage 
compliance  . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 14. Operation truth table for OTG  . . . . . . . . . . . . .20
Table 15. Register overview  . . . . . . . . . . . . . . . . . . . . . .21
Table 16. Address register: bit allocation  . . . . . . . . . . . .23
Table 17. Address register: bit description  . . . . . . . . . . .23
Table 18. Mode register: bit allocation . . . . . . . . . . . . . . .23
Table 19. Mode register: bit description  . . . . . . . . . . . . .23
Table 20. Status of the chip . . . . . . . . . . . . . . . . . . . . . . .24
Table 21. Interrupt Configuration register: bit allocation  .25
Table 22. Interrupt Configuration register: bit description 25
Table 23. Debug mode settings . . . . . . . . . . . . . . . . . . . .25
Table 24. OTG register: bit allocation  . . . . . . . . . . . . . . .25
Table 25. OTG register: bit description  . . . . . . . . . . . . . .26
Table 26. Interrupt Enable register: bit allocation  . . . . . .28
Table 27. Interrupt Enable register: bit description  . . . . .28
Table 28. Endpoint Index register: bit allocation  . . . . . . .29
Table 29. Endpoint Index register: bit description  . . . . . .30
Table 30. Addressing of endpoint buffers  . . . . . . . . . . . .30
Table 31. Control Function register: bit allocation . . . . . .30
Table 32. Control Function register: bit description . . . . .31
Table 33. Data Port register: bit allocation . . . . . . . . . . . .32
Table 34. Data Port register: bit description  . . . . . . . . . .32
Table 35. Buffer Length register: bit allocation  . . . . . . . .33
Table 36. Buffer Length register: bit description  . . . . . . .33
Table 37. Buffer Status register: bit allocation . . . . . . . . .34
Table 38. Buffer Status register: bit description . . . . . . . .34
Table 39. Endpoint MaxPacketSize register: bit 
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4
Table 40. Endpoint MaxPacketSize register: bit 
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 41. Endpoint Type register: bit allocation . . . . . . . .35
Table 42. Endpoint Type register: bit description . . . . . . .36
Table 43. Control bits for GDMA read/write (opcode = 
00h/01h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 44. DMA Command register: bit allocation  . . . . . .37
Table 45. DMA Command register: bit description  . . . . .37
Table 46. DMA commands  . . . . . . . . . . . . . . . . . . . . . . .38
Table 47. DMA Transfer Counter register: bit allocation  .38
Table 48. DMA Transfer Counter register: bit description 39
Table 49. DMA Configuration register: bit allocation . . . .39
Table 50. DMA Configuration register: bit description  . . 40
Table 51. DMA Hardware register: bit allocation  . . . . . . 40
Table 52. DMA Hardware register: bit description  . . . . . 41
Table 53. DMA Interrupt Reason register: bit allocation . 41
Table 54. DMA Interrupt Reason registe r : bit description 42
Table 55. Internal EOT-functional relation with bit 
DMA_XFER_OK . . . . . . . . . . . . . . . . . . . . . . . 42
Table 56. DMA Interrupt Enable register: bit allocation  . 42
Table 57. DMA Endpoint register: bit allocation  . . . . . . . 43
Table 58. DMA Endpoint register: bit description  . . . . . . 43
Table 59. DMA Burst Counter register: bit allocation  . . . 43
Table 60. DMA Burst Counter register: bit description  . . 44
Table 61. Interrupt register: bit allocation  . . . . . . . . . . . . 44
Table 62. Interrupt register: bit description . . . . . . . . . . . 45
Table 63. Chip ID register: bit allocation . . . . . . . . . . . . . 46
Table 64. Chip ID register: bit description . . . . . . . . . . . . 46
Table 65. Frame Number register: bit allocation . . . . . . . 46
Table 66. Frame Number register: bit description . . . . . . 47
Table 67. Scratch register: bit allocation . . . . . . . . . . . . . 47
Table 68. Scratch register: bit description . . . . . . . . . . . . 47
Table 69. Unlock Device register: bit allocation  . . . . . . . 47
Table 70. Unlock Device register: bit description  . . . . . . 48
Table 71. Test Mode register: bit allocation  . . . . . . . . . . 48
Table 72. Test Mode register: bit description  . . . . . . . . . 48
Table 73. Limiting values  . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 74. Recommended operating conditions  . . . . . . . 49
Table 75. Static characteristics: supply pins . . . . . . . . . . 49
Table 76. Static characteristics: digital pins  . . . . . . . . . . 50
Table 77. Static characteristics: OTG detection  . . . . . . . 50
Table 78. Static characteristics: analog I/O pins DP and 
DM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 79. Dynamic characteristics  . . . . . . . . . . . . . . . . . 51
Table 80. Dynamic characteristics: analog I/O pins DP and 
DM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 81. Register access timing parameters: separate 
address and data buses  . . . . . . . . . . . . . . . . . 53
Table 82. GDMA mode timing parameters . . . . . . . . . . . 55
Table 83. Abbreviations  . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 84. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 60

ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009  62 of 64
ISP1582
Hi-Speed USB peripheral controller
20. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration HVQFN56 (top view) . . . . . . . . .4
Fig 3. Interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 4. Behavior of bit GLINTENA. . . . . . . . . . . . . . . . . .14
Fig 5. Resistor and electrolytic or tantalum capacitor 
needed for VBUS sensing . . . . . . . . . . . . . . . . . . .15
Fig 6. Oscilloscope reading: no resistor and capacitor in 
the network  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5
Fig 7. Oscilloscope reading: with resistor and capacitor in 
the network  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5
Fig 8. POR timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Fig 9. Clock with respect to the external POR. . . . . . . .16
Fig 10. ISP1582 with 3.3 V supply. . . . . . . . . . . . . . . . . .17
Fig 11. Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .18
Fig 12. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .19
Fig 13. Source differential data-to-EOP transition skew and 
EOP width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Fig 14. Receiver differential data jitter . . . . . . . . . . . . . . .53
Fig 15. Receiver SE0 width tolerance . . . . . . . . . . . . . . .53
Fig 16. Register access timi ng: separate address and data 
buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Fig 17. ISP1582 ready signal timing . . . . . . . . . . . . . . . .54
Fig 18. GDMA mode timing (bits MODE[1:0] = 00) . . . . .55
Fig 19. GDMA mode timing (bits MODE[1:0] = 01) . . . . .56
Fig 20. GDMA mode timing (bits MODE[1:0] = 10) . . . . .56
Fig 21. EOT timing in generic processor mode . . . . . . . .57
Fig 22. Typical interface connections for generic processor 
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Fig 23. Load impedance for pins DP and DM (full-speed 
mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Fig 24. Package outline SOT684-1 (HVQFN56) . . . . . . .58

ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009  63 of 64
ISP1582
Hi-Speed USB peripheral controller
Contents
General description. . . . . . . . . . . . . . . . . . . . . .  1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2
Ordering information. . . . . . . . . . . . . . . . . . . . .  2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .  3
Pinning information. . . . . . . . . . . . . . . . . . . . . .  4
1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  4
Functional description  . . . . . . . . . . . . . . . . . . .  8
1 DMA interface, DMA handler and DMA 
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
2 Hi-Speed USB transceiver . . . . . . . . . . . . . . . .  9
3 MMU and integrated RAM . . . . . . . . . . . . . . . .  9
4 Microcontroller interface and microcontrolle r 
handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
5 OTG SRP module. . . . . . . . . . . . . . . . . . . . . . .  9
6 ST-Ericsson high-speed transceiver. . . . . . . .  10
6.1 ST-Ericsson Parallel Interface Engine (PIE). .  10
6.2 Peripheral circuit. . . . . . . . . . . . . . . . . . . . . . .  10
6.3 HS detection. . . . . . . . . . . . . . . . . . . . . . . . . .  10
6.4 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
7 ST-Ericsson Serial Interface Engine (SIE) . . .  11
8 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . .  11
9 Reconfiguring endpoints. . . . . . . . . . . . . . . . .  11
10 System controller . . . . . . . . . . . . . . . . . . . . . .  11
11 Pins status . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
12 Interrupt  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
12.1 Interrupt output pin . . . . . . . . . . . . . . . . . . . . .  12
12.2 Interrupt control  . . . . . . . . . . . . . . . . . . . . . . .  14
13 VBUS sensing  . . . . . . . . . . . . . . . . . . . . . . . . .  14
14 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . .  15
15 Power supply . . . . . . . . . . . . . . . . . . . . . . . . .  16
15.1 Self-powered mode  . . . . . . . . . . . . . . . . . . . .  18
15.2 Bus-powered mode  . . . . . . . . . . . . . . . . . . . .  19
Register description . . . . . . . . . . . . . . . . . . . .  21
1 Register access . . . . . . . . . . . . . . . . . . . . . . .  22
2 Initialization registers . . . . . . . . . . . . . . . . . . .  22
2.1 Address register (address: 00h). . . . . . . . . . .  22
2.2 Mode register (address: 0Ch). . . . . . . . . . . . .  23
2.3 Interrupt Configuratio n re gi ster (address: 10h) 24
2.4 OTG register (address: 12h). . . . . . . . . . . . . .  25
2.4.1 Session Request Protocol (SRP) . . . . . . . . . .  27
2.5 Interrupt Enable register (address: 14h). . . . .  27
3 Data flow registers . . . . . . . . . . . . . . . . . . . . .  29
3.1 Endpoint Index register (address: 2Ch) . . . . .  29
3.2 Control Function register (address: 28h) . . . .  30
3.3 Data Port register (address: 20h) . . . . . . . . . .  31
3.4 Buffer Length register (address: 1Ch)  . . . . . .  32
3.5 Buffer Status register (address: 1Eh) . . . . . . .  33
3.6 Endpoint MaxPacketSize register 
(address: 04h)  . . . . . . . . . . . . . . . . . . . . . . . .  34
3.7 Endpoint Type register (address: 08h) . . . . . .  35
4 DMA registers. . . . . . . . . . . . . . . . . . . . . . . . .  36
4.1 DMA Command register (address: 30h). . . . .  37
4.2 DMA Transfer Counter register (address: 34h) 38
4.3 DMA Configuration register (address: 38h) . .   39
4.4 DMA Hardware register (address: 3Ch). . . . .   40
4.5 DMA Interrupt Reason register (a dd re ss: 50 h ) 41
4.6 DMA Interrupt Enable register (address: 54h)  42
4.7 DMA Endpoint register (address: 58h). . . . . .   43
4.8 DMA Burst Counter register (address: 64h). .   43
5 General registers . . . . . . . . . . . . . . . . . . . . . .   44
5.1 Interrupt register (address: 18h)  . . . . . . . . . .   44
5.2 Chip ID register (address: 70h) . . . . . . . . . . .   46
5.3 Frame Number register (address: 74h) . . . . .   46
5.4 Scratch register (address: 78h) . . . . . . . . . . .   47
5.5 Unlock Device register (address: 7Ch) . . . . .   47
5.6 Test Mode register (address: 84h). . . . . . . . .   48
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .   49
Recommended operating conditions . . . . . .   49
Static characteristics . . . . . . . . . . . . . . . . . . .   49
Dynamic characteristics. . . . . . . . . . . . . . . . .   51
1 Register access timing. . . . . . . . . . . . . . . . . .   53
2 DMA timing  . . . . . . . . . . . . . . . . . . . . . . . . . .   55
Application information . . . . . . . . . . . . . . . . .   57
Test information  . . . . . . . . . . . . . . . . . . . . . . .   57
Package outline. . . . . . . . . . . . . . . . . . . . . . . .   58
Abbreviations  . . . . . . . . . . . . . . . . . . . . . . . . .   59
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .   59
Revision history  . . . . . . . . . . . . . . . . . . . . . . .   60
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   61
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   62
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   63

Product data sheet Rev. 09 — 29 September 2009 64 of 64

ISP1582

Hi-Speed USB peripheral controller

Please Read Carefully:

The conten ts of this document are subject to ch ange without prior noti ce. ST-Erics son makes no representati on or warra nty of any nat ure

whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to warranties of

merchantability or fitness for a particular purpose, interpretability or interoperability or, against infringement of third party intellectual property

rights, an d in no ev ent shal l ST-E ricsso n be li able to an y part y for any direc t, indi rect, incide ntal and or cons equen tial da mag es and or loss

whatsoever (including but not limited to monetary losses or loss of data), that might arise from the use of this document or the information in it.

ST-Eric sson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of companies or used under a license from

STMicroelectronics NV or Telefonaktiebolaget LM Ericsson.

All other names are the property of their respective owners.

Contact information at www.stericsson.com under Contacts