Description
The ADNS-3080 is a high
performance addition to Agilent’s
popular ADNS family of optical
mouse sensors.
The ADNS-3080 is based on a
new, faster architecture with
improved navigation. The sensor
is capable of sensing high speed
mouse motion - up to 40 inches
per second and acceleration up
to 15g – for increased user
precision and smoothness.
The ADNS-3080 along with the
ADNS-2120 (or ADNS-2120-001)
lens, ADNS-2220 (or ADNS-
2220-001) assembly clip and
HLMP-ED80-XX000 form a
complete, compact optical mouse
tracking system. There are no
moving parts, which means high
reliability and less maintenance
for the end user. In addition,
precision optical alignment is not
required, facilitating high volume
assembly.
The sensor is programmed via
registers through a four-wire
serial port. It is packaged in a
20-pin staggered dual inline
package (DIP).
Features
••
••
•High speed motion detection – up
to 40 ips and 15g
••
••
•New architecture for greatly
improved optical navigation
technology
••
••
•Programmable frame rate over
6400 frames per second
••
••
•SmartSpeed self-adjusting frame
rate for optimum performance
••
••
•Serial port burst mode for fast
data transfer
••
••
•400 or 1600 cpi selectable
resolution
••
••
•Single 3.3 volt power supply
••
••
•Four-wire serial port along with
Chip Select, Power Down, and
Reset pins
Applications
••
••
•Mice for game consoles and
computer games
••
••
•Mice for desktop PC’s,
Workstations, and portable PC’s
••
••
•Trackballs
••
••
•Integrated input devices
Agilent ADNS-3080
High-performance
Optical Mouse Sensor
Data Sheet
Theory of Operation
The ADNS-3080 is based on
Optical Navigation Technology,
which measures changes in
position by optically acquiring
sequential surface images
(frames) and mathematically
determining the direction and
magnitude of movement.
It contains an Image
Acquisition System (IAS), a
Digital Signal Processor (DSP),
and a four-wire serial port.
The IAS acquires microscopic
surface images via the lens
and illumination system. These
images are processed by the
DSP to determine the direction
and distance of motion. The
DSP calculates the ∆x and ∆y
relative displacement values.
An external microcontroller
reads the ∆x and ∆y
information from the sensor
serial port. The
microcontroller then translates
the data into PS2 or USB
signals before sending them to
the host PC or game console.
2
Pinout
GND
NC
GND
VDD3
REFC
VDD3
NC
OPTP
NC
REFB
NCS
MISO
SCLK
GUARD
LED_CTRL
RESET
NPD
OSC_OUT
MOSI
OSC_IN
TOP VIEW
PINOUT
A3080
XYYWWZ
1
3
4
2
5
6
7
8
9
10
20
18
17
19
16
15
14
13
12
11
Figure 1. Package outline drawing (top view)
Pin Name Description
1 NCS Chip select (active low input)
2 MISO Serial data output (Master In/Slave Out)
3 SCLK Serial clock input
4 MOSI Serial data input (Master Out/Slave In)
5 LED_CTRL LED control output
6 RESET Reset input
7 NPD Power down (active low input)
8 OSC_OUT Oscillator output
9 GUARD Oscillator gnd for PCB guard (optional)
10 OSC_IN Oscillator input
11 NC No connect
12 OPTP Connect to VDD3
13 REFC Reference capacitor
14 REFB Reference capacitor
15 VDD3 Supply voltage
16 GND Ground
17 VDD3 Supply voltage
18 NC No connect
19 GND Ground
20 NC No connect
3
Figure 2. Package outline drawing
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation which may be induced by ESD.
4
down. There is an aperture
stop and features on the
package that align to the lens.
The ADNS-2120 lens provides
optics for the imaging of the
surface as well as illumination
of the surface at the optimum
angle. Features on the lens
align it to the sensor, base
plate, and clip with the LED.
The lens also has a large
round flange to provide a long
creepage path for any ESD
events that occur at the
opening of the base plate.
Figure 3. Recommended PCB mechanical cutouts and spacing
2D Assembly Drawing of ADNS-3080
Shown with ADNS-2120,
ADNS-2220 and HLMP ED80-
XX000.
Agilent Technologies provides
an IGES file drawing
describing the base plate
molding features for lens and
PCB alignment.
The components interlock as
they are mounted onto defined
features on the base plate.
The ADNS-3080 sensor is
designed for mounting on a
through hole PCB, looking
Overview of Optical Mouse Sensor Assembly
The ADNS-2220-001 clip holds
the LED in relation to the
lens. The LED must be
inserted into the clip and the
LED’s leads formed prior to
loading on the PCB. The clip
interlocks the sensor to the
lens, and through the lens to
the alignment features on the
base plate.
The HLMP-ED80-XX000 LED
is recommended for
illumination. If used with the
bin table, sufficient
illumination can be guaranteed.
5
Figure 4. 2D Assembly drawing of ADNS-3080 (top and side view)
NOTE: These new Agilent optical mouse sensors, lenses and clips have different physical
configurations that require a different PCB mounting method to optimize the navigation
performance.
Refer Application Notes AN 5035 for further information.
6
PCB Assembly Considerations
Figure 5. Exploded view drawing
1. Insert the sensor and all
other electrical components
into PCB.
2. Insert the LED into the
assembly clip and bend the
leads 90 degrees.
3. Insert the LED/clip assembly
into PCB.
4. Wave Solder the entire
assembly in a no-wash
solder process utilizing
solder fixture. The solder
fixture is needed to protect
the sensor during the solder
process. It also sets the
correct sensor-to -PCB
distance as the lead
shoulders do not normally
rest on the PCB surface.
The fixture should be
designed to expose the
sensor leads to solder while
shielding the optical
aperture from direct solder
contact.
5. Place the lens onto the base
plate.
6. Remove the protective
kapton tape from optical
aperture of the sensor. Care
must be taken to keep
contaminants from entering
the aperture. During mouse
assembly process, it is
recommended that the PCB
is held vertically when
kapton tapes are being
removed.
7. Insert PCB assembly over
the lens onto the base plate
aligning post to retain PCB
assembly. The sensor
aperture ring should self-
align to the lens.
8. The optical position
reference for the PCB is set
by the base plate and lens.
Note that the PCB motion
due to button presses must
be minimized to maintain
optical alignment.
9. Install mouse top case.
There MUST be a feature in
the top case to press down
Customer supplied base
plate with recommended
alignment features per
IGES drawing.
ADNS-2120 (Lens)
Customer supplied PCB
ADNS-3080 (Sensor)
ADNS-2220 (Clip)
HLMP-ED80-XX000 (LED)
Figure 6. Block diagram of ADNS-3080 optical mouse sensor
IMAGE
PROCESSOR
REFERENCE
VOLTAGE
FILTER NODE
3.3 V POWER
REFB
REFC
GND
RESONATOR
OSC_IN
OSC_OUT
MOSI
NCS
SCLK
OPTP
V
DD3
MISO
LED_CTRL
RESET
NPD
VOLTAGE REGULATOR
AND POWER CONTROL
Serial Port
CTRL
OSCILLATOR
7
Figure 7. Cross section of PCB assembly
Design considerations for improving
ESD Performance
The flange on the lens has
been designed to increase the
creepage and clearance
distance for electrostatic
discharge. The table below
shows typical values assuming
base plate construction per the
Agilent supplied IGES file and
ADNS-2120 lens flange.
Clip LED
PCB
Sensor
Lens/Light Pipe
Surface
Base Plate
Typical Distance Millimeters
Creepage 16.0
Clearance 2.1
For improved ESD
performance, the lens flange
can be sealed (i.e. glued) to
the base plate. Note that the
lens material is polycarbonate
and therefore, cyanoacrylate
based adhesives or other
adhesives that may damage the
lens should NOT be used.
8
Figure 8. Schematic Diagram for USB, PS/2 mouse application with ADNS-3080
Notes
•Caps for pins 15 and 17 MUST have trace lengths LESS than 5 mm to nearest ground pin.
•Pins 15 and 17 caps MUST use pin 16 GND.
•Pin 9, if used, should not be connected to PCB GND to reduce potential RF emissions.
•The 0.1 uF caps must be ceramic.
•Caps should have less than 5 nH of self inductance.
•Caps should have less than 0.2 Ω ESR.
•NC pins should not be connected to any traces.
•Surface mount parts are recommended.
•Care must be taken when interfacing a 5V microcontroller to the ADNS-3080. Serial port inputs on the sensor should
be connected to open-drain outputs from the microcontroller or use an active drive level shifter. NPD and RESET
should be connected to 5V microcontroller outputs through a resistor divider or other level shifting technique.
•VDD3 and GND should have low impedance connections to the power supply.
•Capacitors connected to pin 15 and 17 should be connected to pin 16 and then to pin 19.
ADNS-3080
CYPRESS
CY7C63743A-PC
0.1
uF
14
10
Vcc
Vpp
9
VSS
Ceramic Resonator
Murata
CSALS 24 M 0X 53 -B 0
TDK FCR 24. 0 M 2G
17
5
VDD
LED_CTRL
SURFACE
Internal
Image
Sensor
ADNS
2120
Lens HLMP-ED80
24 MHz
8
10
OSC_OUT
OSC_IN
15
GND
24
P0.5*
3
P0.4*
4
6
MOSI
RESET
P0.2
23
1.3 KΩ
16
15 D -
D +
Vreg
11
P1.7
P1.5
P1.4
17
18
7
Vcc
D +
D -
GND
SHLD
6 MHz
1213
XTALINXTALOUT
(Optional)
6
5
P1.2
P1.0
Buttons
L
M
VDD
19
16 GND
REFB 14
P0.3 7NPD
4
P0.7* 3SCLK
21
P0.6 2MISO
22
9
GUARD
NC
NC
11 18
20
P1.1 R
20KΩ
20KΩ
1NCS
LP2950ACZ-3.3
13
REFC
2.2
uF
187Ω
1/8 W
Vcc
Vo 3.3V
12
OPTP
NC
20
10 KΩ
10 KΩ
Vcc
Vcc
QA
QB
ALPS
EC10E
Scroll Wheel
Encoder
1
2
3
20kΩ
20kΩ
0.1uF
4.7uF
0.1uF
Vin Vo
GND
2
4.7uF
+0.1uF
31
BS170
+
+
Notes:
- All capacitors close to chip
- 24MHz and 6MHz oscillators close to chip
- * Outputs configured as open drain
9
Enabling the SROM
For best tracking
performance,SROM is required
to be loaded into ADNS-3080.
This architecture enables
immediate adoption of new
features and improved
performance algorithms. The
external program is supplied
by Agilent as a file which may
be burned into a
programmable device. A
micro-controller with sufficient
memory may be used. On
power-up and reset, the
ADNS-3080 program is
downloaded into volatile
memory using the burst-mode
procedure described in the
Synchronous Serial Port
section. The program size is
1986 x 8 bits.
Regulatory Requirements
•Passes FCC B and
worldwide analogous
emission limits when
assembled into a mouse
with shielded cable and
following Agilent
recommendations.
•Passes IEC-1000-4-3
radiated susceptibility level
when assembled into a
mouse with shielded cable
and following Agilent
recommendations.
•Passes EN61000-4-4/IEC801-
4 EFT tests when assembled
into a mouse with shielded
cable and following Agilent
recommendations.
•UL flammability level UL94
V-0.
•Provides sufficient ESD
creepage/clearance distance
to avoid discharge up to
15kV when assembled into a
mouse according to usage
instructions above.
Figure 9. Distance from lens reference plane to surface
Sensor
Lens
Object Surface
2.40
0.094
10
Absolute Maximum Ratings
Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Units Notes
Storage Temperature TS-40 85 oC
Operating Temperature TA-15 55 oC
Lead Solder Temp 260 oC For 10 seconds,
1.6mm below seating plane.
Supply Voltage VDD3 -0.5 3.7 V
ESD 2 kV All pins, human body model
MIL 883 Method 3015
Input Voltage VIN -0.5 VDD3+0.5 V NPD, NCS, MOSI, SCLK, RESET, OSC_IN,
OSC_OUT, REFC.
Output current Iout 20 mA LED_CTRL, MISO
Parameter Symbol Minimum Typical Maximum Units Notes
Operating Temperature TA040°C
Power supply voltage VDD3B 3.10 3.30 3.60 Volts
Power supply rise time VRT 1 us 0 to 3.0V
Supply noise (Sinusoidal) VNB 30
80
mV p-p 10kHz- 300KHZ
300KHz-50MHz
Oscillator capable Frequency fCLK 23 24 25 MHz Set by ceramic resonator
Serial Port Clock Frequency fSCLK 2
500
MHz
kHz
Active drive, 50% duty cycle
Open drain drive with pull-ups on,
50 pF load
Resonator Impedance XRES 55 Ω
Distance from lens reference
plane to surface
Z 2.3 2.4 2.5 mm Results in ±0.2 mm DOF, See drawing
below
Speed S 0 40 in/sec @ 6469fps
Acceleration A 15 g @ 6469fps
Light level onto IC IRRINC 20
24
100
120
6,000
7,200
6,000
7,200
mW/m2 λ = 639 nm, FR=1500 fps
λ = 875 nm, FR=1500 fps
λ = 639 nm, FR=6469 fps
λ = 875 nm, FR=6469 fps
Frame Rate FR 2000 6469 Frames/s See Frame_Period register section
LED Drive Current ILED 10 mA HLMP-ED80-XX000, bin N and brighter.
Maximum frame rate may not be
maintained on dark surfaces at the
minimum LED drive current
11
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz.
Parameter Symbol Minimum Typical Maximum Units Notes
VDD to RESET tOP 250 µsFrom VDD = 3.0V to RESET sampled
Data delay after
RESET
tPU-RESET 35 ms From RESET falling edge to valid motion data at 2000
fps and shutter bound 8290.
Input delay after reset TIN-RST 500 µsFrom RESET falling edge to inputs active (NPD,
MOSI, NCS, SCLK)
Power Down tPD 2.1 ms From NPD falling edge to initiate the power down
cycle at 500fps (tpd = 1 frame period + 100ms )
Wake from NPD tPUPD 75 ms From NPD rising edge to valid motion data at 2000
fps and shutter bound 8290. Max assumes surface
change while NPD is low.
Data delay after NPD tCOMPUTE 3.1 ms From NPD rising edge to all registers contain data
from new images at 2000fps (see Figure 10) .
RESET pulse width tPW-RESET 10 µs
MISO rise time tr-MISO 40 200 ns CL = 50pF
MISO fall time tf-MISO 40 200 ns CL = 50pF
MISO delay after SCLK tDLY-MISO 120 ns From SCLK falling edge to MISO data valid, no load
conditions
MISO hold time thold-MISO 250 ns Data held until next falling SCLK edge
MOSI hold time thold-MOSI 200 ns Amount of time data is valid after SCLK rising edge
MOSI setup time tsetup-MOSI 120 ns From data valid to SCLK rising edge
SPI time between
write commands
tSWW 50 µsFrom rising SCLK for last bit of the first data byte, to
rising SCLK for last bit of the second data byte.
SPI time between
write and read
commands
tSWR 50 µsFrom rising SCLK for last bit of the first data byte, to
rising SCLK for last bit of the second address byte.
SPI time between read
and subsequent
commands
tSRW
tSRR
250 ns From rising SCLK for last bit of the first data byte, to
falling SCLK for first bit of the second address byte.
SPI read address-data
delay
tSRAD 50 µsFrom rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. All
registers except Motion & Motion_Burst
SPI motion read
address-data delay
tSRAD-MOT 75 µsFrom rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. Applies to
0x02 Motion, and 0x50 Motion_Burst, registers
NCS to SCLK active tNCS-SCLK 120 ns From NCS falling edge to first SCLK rising edge
SCLK to NCS inactive tSCLK-NCS 120 ns From last SCLK falling edge to NCS rising edge, for
valid MISO data transfer
NCS to MISO high-Z tNCS-MISO 250 ns From NCS rising edge to MISO high-Z state
SROM download and
frame capture byte-to-
byte delay
tLOAD 10 µs(see Figure 23 and 24)
NCS to burst mode
exit
tBEXIT 4µsTime NCS must be held high to exit burst mode
Transient Supply
Current
IDDT 85 mA Max supply current during a VDD3 ramp from 0 to 3.6V
12
Detail of NPD rising edge timing
Figure 10. NPD Rising Edge Timing Detail
LED CURRENT
(shutter mode)
Oscillator Start
NPD
250 us
Reset
Count
340 us
SCLK
Optional SPI transactions
with old image data
590 us
tCOMPUTE = 590us + 5 Frame Periods
Motion bit set if
motion was detected.
First read dX = dY = 0
Frame
2
Frame
3
Frame
4 Frame
5
Frame
1
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz.
Parameter Symbol Minimum Typical Maximum Units Notes
DC Supply Current IDD_AVG 52 mA DC average at 6469 fps. No DC load on LED_CTRL,
MISO.
Power Down
Supply Current
IDDPD 590 µANPD=GND; SCLK, MOSI, NCS=GND or VDD3;
RESET=GND
Input Low Voltage VIL 0.8 V SCLK, MOSI, NPD, NCS, RESET
Input High Voltage VIH 0.7 * VDD3 V SCLK, MOSI, NPD, NCS, RESET
Input hysteresis VI_HYS 200 mV SCLK, MOSI, NPD, NCS, RESET
Input current,
pull-up disabled
IIH_DPU 0±10µAVin=0.8*VDD3, SCLK, MOSI, NCS
Input current,
CMOS inputs
IIH 0±10µANPD, RESET, Vin=0.8*VDD3
Output current, pulled-
up inputs
IOH_PU 150 300 600 µAVin=0.2V, SCLK, MOSI, NCS
Output Low Voltage
LED_CTRL
VOL,LED 0.5 V Iout=2mA, LED_CTRL
Output High voltage,
LED_CTRL
VOH_LED 0.8*VDD3 VIout=-2mA, LED_CTRL
Output Low Voltage,
MISO
VOL 0.5 V Iout=2mA, MISO
Output High Voltage,
MISO
VOH 0.8*VDD3 VIout=-2mA, MISO
Input Capacitance CIN 14-22 pF OSC_IN, OSC_OUT
13
Figure 12. Average error vs. Distance (mm)
Typical Performance Characteristics
Figure 11. Mean Resolution vs. Z (White Paper)
Mean Resolution vs. Z (White Paper)
0
200
400
600
800
1000
1200
1400
1600
1800
2000
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Distance from Nominal Focus (mm)
Resolution (counts/inch)
White Paper
Manila
Burl
Black Walnut
Black Copy
Z
DOF
DOF
OPERATING REGION
Typical Path Deviation
Largest Single Perpendicular Deviation From A Straight Line At 45 Degrees
Path length = 4 inches; Speed = 6 ips; Resolution = 1600 cpi
0
5
10
15
20
25
30
35
40
45
50
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
Distance From Lens Reference Plane To Navigation Surface (mm)
Relationship of mouse count to distance = m (mouse count) / n (cpi)
eg: Deviation of 7 mouse count = 7/1600 = 0.004375 inch ~ 0.004 inch
where m = 7, n = 1600
Maximum Distance (Mouse Count)
White Paper
Manila
Burl
Black Walnut
Black Copy
14
Figure 14. Idd vs. Frame Rate
Figure 13. Relative responsivity
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
400 500 600 700 800 900 1000
wavelength (nm)
Relative responsivity
Average Supply Current vs Frame Rate VDD=3.6V
72%
88%
100%
51%
55%
0%
20%
40%
60%
80%
100%
120%
0 2000 4000 6000 8000
Frame Rate (Hz)
Relative Current
15
Synchronous Serial Port
The synchronous serial port is
used to set and read
parameters in the ADNS-3080,
and to read out the motion
information. The serial port is
also used to load SROM data
into the ADNS-3080.
The port is a four-wire, serial
port. The host micro-
controller always initiates
communication; the ADNS-
3080 never initiates data
transfers. The serial port
cannot be activated while the
chip is in power down mode
(NPD low) or reset (RESET
high). SCLK, MOSI, and NCS
may be driven directly by a
3.3V output from a micro-
controller, or they may be
placed in an open drain
configuration by enabling on-
chip pull-up current sources.
The open drain drive allows
the use of a 5V micro-
controller without any level
shifting components. The port
Chip Select Operation
The serial port is activated
after NCS goes low. If NCS is
raised during a transaction,
the entire transaction is
aborted and the serial port
will be reset. This is true for
all transactions including
SROM download. After a
transaction is aborted, the
normal address-to-data or
transaction-to-transaction
delay is still required before
beginning the next transaction.
To improve communication
reliability, all serial
transactions should be framed
by NCS. In other words, the
port should not remain
enabled during periods of non-
use because ESD and EFT/B
events could be interpreted as
serial communication and put
the chip into an unknown
state. In addition, NCS must
be raised after each burst-
mode transaction is complete
to terminate burst-mode. The
port is not available for
further use until burst-mode is
terminated.
pins may be shared with other
SPI slave devices. When the
NCS pin is high, the inputs are
ignored and the output is tri-
stated.
The lines which comprise the
SPI port are:
SCLK: Clock input. It is always
generated by the master (the
micro- controller).
MOSI: Input data (Master Out/
Slave In).
MISO: Output data (Master In/
Slave Out).
NCS: Chip select input (active
low).
NCS needs to be low to
activate the serial port;
otherwise, MISO will be high-Z,
and MOSI & SCLK will be
ignored. NCS can also be used
to reset the serial port in case
of an error.
16
Figure 17. Read operation
1
2
3
4
5
6
7
8
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
9
10
11
12
13
14
15
16
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
t
SRAD delay
SCLK
Cycle #
SCLK
MOSI
MISO
NCS
Figure 15. MOSI setup and hold time
Write Operation
Write operation, defined as
data going from the micro-
controller to the ADNS-3080,
is always initiated by the
micro-controller and consists
of two bytes. The first byte
contains the address (seven
bits) and has a “1” as its MSB
to indicate data direction. The
second byte contains the data.
The ADNS-3080 reads MOSI on
rising edges of SCLK.
Figure 18. MISO delay and hold time
Read Operation
A read operation, defined as
data going from the ADNS-
3080 to the micro-controller, is
always initiated by the micro-
controller and consists of two
bytes. The first byte contains
the address, is sent by the
micro-controller over MOSI,
and has a “0” as its MSB to
indicate data direction. The
second byte contains the data
and is driven by the ADNS-
3080 over MISO. The sensor
outputs MISO bits on falling
edges of SCLK and samples
MOSI bits on every rising edge
of SCLK.
NOTE:
The 250 ns minimum high state of
SCLK is also the minimum MISO data
hold time of the ADNS-3080. Since
the falling edge of SCLK is actually the
start of the next read or write
command, the ADNS-3080 will hold
the state of data on MISO until the
falling edge of SCLK.
SCLK
MOSI
t
Setup, MOSI
t
Hold,MOSI
A
6
A
5
A
2
A
3
A
4
A
0
A
1
D
7
D
4
D
5
D
6
D
0
D
1
D
2
D
3
15
7
8
9
10
11
12
14
16
2
3
4
5
6
1
1
1
1
A
6
2
SCLK
MOSI
NCS
MISO
MOSI Driven by Micro-Controller
SCLK
MISO D0
tHOLD-MISO
tDLY-MISO
Figure 16. Write Operation
17
Required timing between Read and Write Commands (tsxx)
There are minimum timing requirements between read and write commands on the serial port.
Figure 19. Timing between two write commands
If the rising edge of the SCLK for the last data bit of the second write command occurs before
the 50 microsecond required delay, then the first write command may not complete correctly.
Figure 20. Timing between write and read commands
If the rising edge of SCLK for the last address bit of the read command occurs before the 50
microsecond required delay, the write command may not complete correctly.
Figure 21. Timing between read and either write or subsequent read commands
The falling edge of SCLK for the first address bit of either the read or write command must be at
least 250 ns after the last SCLK rising edge of the last data bit of the previous read operation.
In addition, during a read operation SCLK should be delayed after the last address bit to ensure
that the ADNS-3080 has time to prepare the requested data.
SCLK
Address Data
tSWW ≥ 50µs
Write Operation
Address Data
Write Operation
Address Data
Write Operation
Address
Next Read
Operation
SCLK
tSWR ≥ 50µs
t
SRAD
≥ 50 µs for non-motion read
t
SRAD-MOT
≥ 75 µs for register 0x02
t
SRW
& t
SRR
> 250 ns
Next Read or
Write Operation
Data
Read Operation
AddressAddress
SCLK
18
Burst Mode Operation
Burst mode is a special serial
port operation mode which
may be used to reduce the
serial transaction time for
three predefined operations:
motion read and SROM
download and frame capture.
The speed improvement is
achieved by continuous data
clocking to or from multiple
registers without the need to
specify the register address,
and by not requiring the
normal delay period between
data bytes.
Figure 22. Motion burst timing
Motion Read
This mode is activated by
reading the Motion_Burst
register. The ADNS-3080 will
respond with the contents of
the Motion, Delta_X, Delta_Y,
SQUAL, Shutter_Upper,
Shutter_Lower and
Maximum_Pixel registers in
that order. After sending the
register address, the micro-
controller must wait tSRAD-MOT
and then begin reading data.
All 56 data bits can be read
with no delay between bytes
by driving SCLK at the normal
rate. The data are latched
into the output buffer after the
last address bit is received.
After the burst transmission is
complete, the micro-controller
must raise the NCS line for at
least tBEXIT to terminate burst
mode. The serial port is not
available for use until it is
reset with NCS, even for a
second burst transmission.
Motion_Burst Register Address Read First Byte
First Read Operation Read Second Byte
SCLK
tSRAD-MOT ≥ 75 µs
Read Third Byte
19
SROM Download
This function is used to load
the Agilent-supplied firmware
file contents into the ADNS-
3080. The firmware file is an
ASCII text file with each 2-
character byte (hexadecimal
representation) on a single
line.
This mode is activated by the
following steps:
1. Perform hardware reset by
toggling the RESET pin
2. Write 0x44 to register 0x20
3. Write 0x07 to register 0x23
4. Write 0x88 to register 0x24
5. Wait at least 1 frame period
6. Write 0x18 to register 0x14
(SROM_Enable register)
Figure 23. SROM download burst mode
7. Begin burst mode write of
data file to register 0x60
(SROM_Load register)
After the first data byte is
complete, the SROM or micro-
controller must write
subsequent bytes by presenting
the data on the MOSI line and
driving SCLK at the normal
rate. A delay of at least tLOAD
must exist between data bytes
as shown. After the download
is complete, the micro-
controller must raise the NCS
line for at least tBEXIT to
terminate burst mode. The
serial port is not available for
use until it is reset with NCS,
even for a second burst
transmission.
Agilent recommends reading
the SROM_ID register to verify
that the download was
successful. In addition, a
self-test may be executed,
which performs a CRC on the
SROM contents and reports the
results in a register. The test
is initiated by writing a
particular value to the
SROM_Enable register; the
result is placed in the
Data_Out register. See those
register descriptions for more
details.
Agilent provides the data file
for download; the file size is
1986 data bytes. The chip
will ignore any additional
bytes written to the
SROM_Load register after the
SROM file.
SROM file is now available for
download at Agilent’s website.
NCS
address key data address byte 0
MOSI
SCLK
tNCS-SCLK
SROM_Enable reg write SROM_Load reg write
exit burst mode
enter burst
mode
≥
4µs
tLOAD tLOAD
byte 1 byte 1985
tBEXIT
>120ns
address
soonest to read SROM_ID
3 reg writes, see text
≥
1 frame
period
≥
40µs
≥
10µs
≥
10µs
≥
10µs
≥
100µs
20
Frame Capture
This is a fast way to download
a full array of pixel values
from a single frame. This
mode disables navigation and
overwrites any downloaded
firmware. A hardware reset is
required to restore navigation,
and the firmware must be
reloaded afterwards if
required.
To trigger the capture, write to
the Frame_Capture register.
The next available complete 1
2/3 frames (1536 values) will
be stored to memory. The data
are is retrieved by reading the
Pixel_Burst register once using
the normal read method, after
which the remaining bytes are
clocked out by driving SCLK at
the normal rate. The byte time
must be at least tLOAD. If the
Pixel_ Burst register is read
before the data is ready, it will
return all zeros.
To read a single frame, read a
total of 900 bytes. The next
636 bytes will be
approximately 2/3 of the next
frame. The first pixel of the
first frame (1st read) has bit 6
set to 1 as a start-of-frame
marker. The first pixel of the
second partial frame (901st
read) will also have bit 6 set
to 1. All other bytes have bit 6
set to zero. The MSB of all
bytes is set to 1. If the
Pixel_Burst register is read
past the end of the data (1537
reads and on) , the data
returned will be zeros.
After the download is
complete, the micro-controller
must raise the NCS line for at
least tBEXIT to terminate burst
mode. The read may be
aborted at any time by raising
NCS.
Alternatively, the frame data
can also be read one byte at a
time from the Frame_Capture
register. See the register
description for more
information.
Figure 24. Frame capture burst mode timing
NCS
address data address address
MOSI
SCLK
P0 P1 P899
MISO
tNCS-SCLK
>120ns
frame capture reg write
enter burst
mode
t
CAPTURE
tLOAD
Notes:
1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker.
2. Reading beyond pixel 899 will return the first pixel of the second partial frame.
3. tCAPTURE = 10µs + 3 frame periods.
4. This figure illustrates reading a single complete frame of 900 pixels. An additional 636 pixels from the next frame are available.
tLOAD
tSRAD
pixel dump reg read
P0 bit 6 set to 1 all MSB = 1 see note 2
soonest to begin again
frame capture reg
exit burst mode
tBEXIT
≥
10µs
≥
10µs
≥
50µs
≥
4µs
≥
10µs
21
Figure 25. Pixel address map (surface referenced)
The pixel output order as related to the surface is shown below.
Cable
RB
LB
A3080
10
1 20
11
Top Xray View of Mouse
Positive X
Positive Y
899 898 897 896 895 894 893 892 891 890 889 888 887 886 885 884 883 882 881 880 879 878 877 876 875 874 873 872 871 870
869 868 867 866 865 864 863 862 861 860 859 858 857 856 855 854 853 852 851 850 849 848 847 846 845 844 843 842 841 840
839 838
etc.
61 60
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
expanded view of the
surface as viewed
through the lens
last output
first output
•••
•••
Error detection and recovery
1. The ADNS-3080 and the
micro-controller might get
out of synchronization due
to ESD events, power supply
droops or micro-controller
firmware flaws. In such a
case, the micro-controller
should pulse NCS high for
at least 1 ms. The ADNS-
3080 will reset the serial
port (but not the control
registers) and will be
prepared for the beginning
of a new transmission after
the normal transaction
delay.
2. Invalid addresses: Writing
to an invalid address will
have no effect. Reading from
an invalid address will
return all zeros.
3. Termination of a
transmission by the micro-
controller may sometimes be
required (for example, due
to a USB suspend interrupt
during a read operation).
To accomplish this the
micro-controller should raise
NCS. The ADNS-3080 will
not write to any register
and will reset the serial port
(but not the control
registers) and be prepared
for the beginning of future
transmissions after NCS goes
low. The normal delays
between reads or writes
(tSWW, tswr, tSRAD, tSRAD-mot)
are still required after
aborted transmissions.
4. The micro-controller can
verify success of write
operations by issuing a read
command to the same
address and comparing
written data to read data.
5. The micro-controller can
verify the synchronization of
the serial port by
periodically reading the
product ID and inverse
product ID registers.
6. The microcontroller can read
the SROM_ID register to
verify that the sensor is
running downloaded SROM
code. ESD or similar noise
events may cause the sensor
to revert to native ROM
execution. If this should
happen, pulse RESET and
reload the SROM
instructions.
22
Notes on Power-up and the serial
port
Reset Circuit
The ADNS-3080 does not
perform an internal power up
self-reset. The reset pin must
be raised and lowered to reset
the chip. This should be done
every time power is applied.
During power-up there will be
a period of time after the
power supply is high but
before any clocks are available.
The table below shows the
state of the various pins
during power-up and reset
when the RESET pin is driven
high by a micro-controller.
Power Down Circuit
The following table lists the
pin states during power down.
The chip is put into the power
down (PD) mode by lowering
the NPD input. When in PD
mode, the oscillator is stopped
but all register contents are
retained. To achieve the
lowest current state, all inputs
must be held externally within
200mV of a rail, either ground
or VDD3. The chip outputs are
driven low or hi-Z during PD
to prevent current
consumption by an external
load.
LED Drive Mode
The LED has 2 modes of
operation: DC and Shutter. In
DC mode it is on at all times
the chip is powered except
when in the power down mode
via the NPD pin. In shutter
mode the LED is on only
during the portion of the
frame that light is required.
The LED_MODE bit in the
Configuration_bits register sets
the LED mode.
State of Signal Pins After VDD is Valid
Pin Before Reset During Reset After Reset
SPI pullups Undefined Off On (default)
NCS Hi-Z control
functional
Hi-Z control
functional
Functional
MISO Driven or hi-Z
(per NCS)
Driven or hi-Z
(per NCS)
Low or hi-Z
(per NCS)
SCLK Undefined Ignored Functional
MOSI Undefined Ignored Functional
LED_CTRL Undefined Low High
RESET Functional High
(externally driven)
Functional
NPD Undefined Ignored Functional
State of Signal Pins During Power Down
Pin NPD low After wake from PD
SPI pullups off pre-PD state
NCS hi-Z control functional functional
MISO low or hi-Z (per NCS) pre-PD state or hi-Z
SCLK ignored functional
MOSI ignored functional
LED_CTRL low high
RESET functional functional
NPD low (driven externally) functional
REFC VDD3 REFC
OSC_IN low OSC_IN
OSC_OUT high OSC_OUT
23
Registers
The ADNS-3080 registers are accessible via the serial port. The registers are used to read motion
data and status as well as to set the device configuration.
Address Register Read/Write SROM Default Value
0x00 Product_ID R 0x17
0x01 Revision_ID R 0xNN
0x02 Motion R 0x00
0x03 Delta_X R 0x00
0x04 Delta_Y R 0x00
0x05 SQUAL R 0x00
0x06 Pixel_Sum R 0x00
0x07 Maximum_Pixel R 0x00
0x08 Reserved
0x09 Reserved
0x0a Configuration_bits R/W 0x09
0x0b Extended_Config R/W 0x00
0x0c Data_Out_Lower R Any
0x0d Data_Out_Upper R Any
0x0e Shutter_Lower R 0x85
0x0f Shutter_Upper R 0x00
0x10 Frame_Period_Lower R Any
0x11 Frame_Period_Upper R Any
0x12 Motion_Clear W Any
0x13 Frame_Capture R/W 0x00
0x14 SROM_Enable W 0x00
0x15 Reserved
0x16 Reserved
0x17 Reserved
0x18 Reserved
0x19 Frame_Period_Max_Bound Lower R/W 0xE0
0x1a Frame_Period_Max_Bound_Upper R/W 0x2E
0x1b Frame_Period_Min_Bound_Lower R/W 0x7E
0x1c Frame_Period_Min_Bound_Upper R/W 0x0E
0x1d Shutter_Max_Bound_Lower R/W 0x00
0x1e Shutter_Max_Bound_Upper R/W 0x20
0x1f SROM_ID R 0x00
0x20-0x3c Reserved
0x3d Observation R/W 0x00
0x3e Reserved
0x3f Inverse Product ID R 0xF8
0x40 Pixel_Burst R 0x00
0x50 Motion_Burst R 0x00
0x60 SROM_Load W Any
24
Product_ID Address: 0x00
Access: Read Reset Value: 0x17
Data Type: 8-Bit unsigned integer
USAGE: This register contains a unique identification assigned to the ADNS-3080. The value in
this register does not change; it can be used to verify that the serial communications link is
functional.
Revision_ID Address: 0x01
Access: Read Reset Value: 0xNN
Data Type: 8-Bit unsigned integer.
USAGE: This register contains the IC revision. It is subject to change when new IC versions are
released.
NOTE: The downloaded SROM firmware revision is a separate value and is available in the
SROM_ID register.
Motion Address: 0x02
Access: Read Reset Value: 0x00
Data Type: Bit field.
USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it
was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated
motion. It also tells if the motion buffers have overflowed, and the current resolution setting.
Bit76543210
Field PID7PID6PID5PID4PID3PID2PID1PID0
Bit7 6 543210
Field RID7RID6RID5RID4RID3RID2RID1RID0
Bit76543210
Field MOT Reserved Reserved OVF Reserved Reserved Reserved RES
Field Name Description
MOT Motion since last report or PD
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
Reserved Reserved
Reserved Reserved
OVF Motion overflow, Delta_Y and/or Delta_X buffer has overflowed since last report
0 = no overflow
1 = Overflow has occurred
Reserved Reserved
Reserved Reserved
Reserved Reserved
RES Resolution in counts per inch
0 = 400
1 = 1600
25
Notes for Motion:
1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If
Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost.
2. Agilent RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. See Motion burst mode also.
3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data is
lost and the OVF bit is set. This bit is cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buffers are not at
full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated until the
motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale. If the
motion register has not been read for long time, at 400 cpi it may take up to 16 read cycles to clear the buffers, at 1600 cpi, up to 64 cycles.
Alternatively, writing to the Motion_Clear register (register 0x12) will clear all stored motion at once.
Delta_X Address: 0x03
Access: Read Reset Value: 0x00
Data Type: Eight bit 2’s complement number.
USAGE: X movement is counts since last report. Absolute value is determined by resolution.
Reading clears the register.
Bit 7 6 5 4 3 2 1 0
Field X7X6X5X4X3X2X1X0
Bit7 6 543210
Field Y7Y6Y5Y4Y3Y2Y1Y0
Delta_Y Address: 0x04
Access: Read Reset Value: 0x00
Data Type: Eight bit 2’s complement number.
USAGE: Y movement is counts since last report. Absolute value is determined by resolution.
Reading clears the register.
00 01 02 7E 7F
+127+126+1 +2
FFFE8180
0-1-2-127-128
Motion
Delta_X
00 01 02 7E 7F
+127+126+1 +2
FFFE8180
0-1-2-127-128
Motion
Delta_Y
26
SQUAL Address: 0x05
Access: Read Reset Value: 0x00
Data Type: Upper 8 bits of a 10-bit unsigned integer.
USAGE: SQUAL (Surface Quality) is a measure of ¼ of the number of valid* features visible by
the sensor in the current frame. Use the following formula to find the total number of valid
features.
Number of features = SQUAL register value *4
The maximum SQUAL register value is 169. Since small changes in the current frame can result
in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph
below shows 250 sequentially acquired SQUAL values, while a sensor was moved slowly over
white paper. SQUAL is nearly equal to zero, if there is no surface below the sensor. SQUAL is
typically maximized when the navigation surface is at the optimum distance from the imaging lens
(the nominal Z-height).
Bit76543210
Field SQ7SQ6SQ5SQ4SQ3SQ2SQ1SQ0
Figure 26. Squal values (white paper)
60
65
70
75
80
85
0 25 50 75 100 125 150 175 200 225 250
Squal Values (White Paper)
SQUAL Value
27
Pixel_Sum Address: 0x06
Access: Read Reset Value: 0x00
Data Type: High 8 bits of an unsigned 16-bit integer.
USAGE: This register is used to find the average pixel value. It reports the upper byte of a 16-
bit counter which sums all 900 pixels in the current frame. It may be described as the full sum
divided by 256. To find the average pixel value, use the following formula:
Average Pixel = Register Value * 256 / 900 = Register Value/3.51
The maximum register value is 221 (63 * 900/256 truncated to an integer). The minimum is 0.
The pixel sum value can change on every frame.
Maximum_Pixel Address: 0x07
Access: Read Reset Value: 0x00
Data Type: Six bit number.
USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The
maximum pixel value can vary with every frame.
Reserved Address: 0x08
Reserved Address: 0x09
Bit 7 6 5 4 3 2 1 0
Field AP7AP6AP5AP4AP3AP2AP1AP0
Bit 7 6 5 4 3 2 1 0
Field 0 0 MP5MP4MP3MP2MP1MP0
Figure 27. Mean squal vs. Z (white paper)
0
10
20
30
40
50
60
70
80
90
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
Avg
Avg - 3sigma
Avg + 3sigma
Mean SQUAL vs Z (White Paper)
Delta from Nominal Focus (mm)
SQUAL
28
Bit765432 1 0
Field 0 LED_MODE Sys Test RES Reserved Reserved Reserved Reserved
Configuration_bits Address: 0x0a
Access: Read/Write Reset Value: 0x09
Data Type: Bit field
USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are
the bits, their default values, and optional values.
Field Name Description
BIT 7 Must always be zero
LED_MODE LED Shutter Mode
0 = Shutter mode off (LED always on)
1 = Shutter mode on (LED only on when illumination is required)
Sys Test System Tests
0 = no tests
1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower
registers.
NOTE: The test will fail if SROM is loaded. Perform a hardware reset before executing this test.
Reload SROM after the test is completed.
NOTE: Since part of the system test is a RAM test, the RAM and SRAM will be overwritten with
the default values when the test is done. If any configuration changes from the default are
needed for operation, make the changes AFTER the system test is run. The system test takes
200ms (@24MHz) to complete.
NOTE: Do not access the Synchronous Serial Port during system test.
RES Resolution in counts per inch
0 = 400
1 = 1600
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
29
Extended_Config Address: 0x0b
Access: Read/Write Reset Value: 0x00
Data Type: Bit field
USAGE: Register 0x0b allows the user to change the configuration of the sensor. Shown below are
the bits, their default values, and optional values.
Bit76543210
Field Busy Reserved Reserved Reserved Reserved Serial_NPU NAGC Fixed_FR
Field Name Description
Busy Read-only bit. Indicates if it is safe to write to one or more of the following registers:
Frame_Period_Max_Bound_Upper and Lower
Frame_Period_Min_Bound_Upper and Lower
Shutter_Max_Bound_Upper and Lower
After writing to the Frame_Period_Max_Bound_Upper register, at least two frames must pass
before writing again to any of the above registers. This bit may be used in lieu of a timer since
the actual frame rate may not be known when running in auto mode.
0 = writing to the registers is allowed
1 = do not write to the registers yet
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Serial_NPU Disable serial port pull-up current sources
0 = no, current sources are on
1 = yes, current sources are off
NAGC Disable AGC. Shutter will be set to the value in the Shutter_Max_Bound registers.
0 = no, AGC is active
1 = yes, AGC is disabled
Fixed_FR Fixed frame rate (disable automatic frame rate control). When this bit is set, the frame rate will
be determined by the value in the Frame_Period_Max_Bound registers.
0 = automatic frame rate
1 = fixed frame rate
30
Shutter_Lower Address: 0x0e
Access: Read Reset Value: 0x85
System Test: This test is initiated via the Configuration_Bits register. It performs several tests to
verify that the hardware is functioning correctly. Perform a hardware reset just prior to running
the test. SROM contents and register settings will be lost.
SROM CRC Test: Performs a CRC on the SROM contents. The test is initiated by writing a
particular value to the SROM_Enable register.
Bit 7 6 5 4 3 2 1 0
Field DO7DO6DO5DO4DO3DO2DO1DO0
Bit 7 6 5 4 3 2 1 0
Field DO15 DO14 DO13 DO12 DO11 DO10 DO9DO8
Data_Out_Upper Data_Out_Lower
System test results: 0x1B 0xBF
SROM CRC Test Result: 0xBE 0xEF
Shutter_Upper Address: 0x0f
Access: Read Reset Value: 0x00
Data Type: Sixteen bit unsigned integer.
USAGE: Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be
read consecutively. The shutter is adjusted to keep the average and maximum pixel values within
normal operating ranges. The shutter value is checked and automatically adjusted to a new value
if needed on every frame when operating in default mode. When the shutter adjusts, it changes
by ± 1/16 of the current value. The shutter value can be set manually by setting the AGC mode
to Disable using the Extended_Config register and writing to the Shutter_Maximum_Bound
registers. Because the automatic frame rate feature is related to shutter value. It may also be
appropriate to enable the Fixed Frame Rate mode using the Extended_Config register.
Shown below is a graph of 250 sequentially acquired shutter values, while the sensor was moved
slowly over white paper.
Bit765432 1 0
Field S7S6S5S4S3S2S1S0
Bit765432 1 0
Field S15 S14 S13 S12 S11 S10 S9S8
Data_Out_Lower Address: 0x0c
Access: Read Reset Value: Undefined
Data_Out_Upper Address: 0x0d
Access: Read Reset Value: Undefined
Data Type: Sixteen bit word.
USAGE: Data in these registers come from the system self test or the SROM CRC test. The data
can be read out 0x0d, or 0x0d first, then 0x0c.
31
Figure 28. Mean shutter vs. Z (white paper)
The maximum value of the shutter is dependent upon the setting in the Shutter_Max_Bound_
Upper and Shutter_Max_Bound_Lower registers.
Mean Shutter vs Z (White Paper)
Distance from Nominal Focus (mm)
Shutter value (counts)
0
20
40
60
80
100
120
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
Avg
Avg - 3sigma
Avg + 3sigma
32
Frame_Period_Lower Address: 0x10
Access: Read Reset Value: Undefined
Frame_Period_Upper Address: 0x11
Access: Read Reset Value: Undefined
Motion_Clear Address: 0x12
Access: Write Reset Value: Undefined
Data Type: Any.
USAGE: Writing any value to this register will cause the Delta_X, Delta_Y, and internal motion
registers to be cleared. Use this as a fast way to reset the motion counters to zero without
resetting the entire chip.
Data Type: Sixteen bit unsigned integer.
USAGE: Read these registers to determine the current frame period and to calculate the frame
rate. Units are clock cycles. The formula is
Frame Rate = Clock Frequency/Register value
To read from the registers, read Frame_Period_Upper first followed by Frame_Period Lower.
To set the frame rate manually, disable automatic frame rate mode via the Extended_Config
register and write the desired count value to the Frame_Period_Maximum_Bound registers.
The following table lists some Frame_Period values for popular frame rates with a 24MHz clock.
Bit 7 6 5 4 3 2 1 0
Field FP7FP6FP5FP4FP3FP2FP1FP0
Bit 7 6 5 4 3 2 1 0
Field FP15 FP14 FP13 FP12 FP11 FP10 FP9FP8
Frames/second
Counts Frame_Period
Decimal Hex Upper Lower
6469 3,710 OE7E OE 7E
5000 4,800 12C0 12 C0
3000 8,000 1F40 1F 40
2000 12,000 2EE0 2E E0
33
Frame_Capture Address: 0x13
Access: Read/Write Reset Value: 0x00
SROM_Enable Address: 0x14
Access: Write Reset Value: 0x00
Data Type: Bit field
USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel
values to be stored to SROM RAM. Writing to this register is required before using the Frame
Capture burst mode to read the pixel values (see the Synchronous Serial Port section for more
details). Writing to this register will stop navigation and cause any firmware loaded in the SROM
to be overwritten. A hardware reset is required to restore navigation, and the firmware must be
reloaded using the SROM Download burst method.
This register can also be used to read the frame capture data. The same data available by reading
the Pixel_Burst register using burst mode is available by reading this register in the normal
fashion. The data pointer is automatically incremented after each read so all 1536 pixel values (1
and 2/3 frames) may be obtained by reading this register 1536 times in a row. Both methods
share the same pointer such that reading pixel values from this register will increment the pointer
causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to
start at the current pointer location. This register will return all zeros if read before the frame
capture data is ready. See the Frame Capture description in the Synchronous Serial Port section
for more information.
This register will not retain the last value written. Reads will return zero or frame capture data.
Data Type: 8-bit number.
USAGE: Write to this register to start either SROM download or SROM CRC test.
Write 0x18 to this register before downloading SROM firmware to the SROM_Load register. The
download will not be successful unless this register contains the correct value.
Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period , then read result from
the Data_Out_Lower and Data_Out_Upper registers. Navigation is halted and the SPI port should
not be used during this test.
Bit 7 6 5 4 3 2 1 0
Field FC7FC6FC5FC4FC3FC2FC1FC0
Bit76543 2 10
Field SE7SE6SE5SE4SE3SE2SE1SE0
Reserved Address: 0x15 – 0x18
Bit 7 6 5 4 3 2 1 0
Field FBm7FBm6FBm5FBm4FBm3FBm2FBm1FBm0
Bit765432 1 0
Field FBm15 FBm14 FBm13 FBm12 FBm11 FBm10 FBm9FBm8
Frame_Period_Max_Bound_Lower Address: 0x19
Access: Read/Write Reset Value: 0xE0
Frame_Period_Max_Bound_Upper Address: 0x1A
Access: Read/Write Reset Value: 0x2E
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be
selected by the automatic frame rate control, or sets the actual frame period when operating in
manual mode. Units are clock cycles. The formula is
Frame Rate = Clock Frequency / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write
Lower first, followed by Upper. To set the frame rate manually, disable automatic frame rate
mode via the Extended_Config register and write the desired count value to these registers.
Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new values
in the following registers:
• Frame_Period_Max_Bound_Upper and Lower
• Frame_Period_Min_Bound_Upper and Lower
• Shutter_Max_Bound_Upper and Lower
Any data written to these registers will be saved but will not take effect until the write to the
Frame_Period_Max_Bound_Upper and Lower is complete. After writing to this register, two
complete frame times are required to implement the new settings. Writing to any of the above
registers before the implementation is complete may put the chip into an undefined state
requiring a reset. The “Busy” bit in the Extended_Config register may be used in lieu of a timer
to determine when it is safe to write. See the Extended_Config register for more details.
The following table lists some Frame_Period values for popular frame rates (clock rate = 24MHz).
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
Frames/second
Counts Frame_Period
Decimal Hex Upper Lower
6469 3,710 OE7E OE 7E
5000 4,800 12C0 12 C0
3000 8,000 1F40 1F 40
2000 12,000 2EE0 2E E0
Frame_Period_Min_Bound_Lower Address: 0x1B
Access: Read/Write Reset Value: 0xAC (before SROM download)
0x7E (after SROM download)
Frame_Period_Min_Bound_Upper Address: 0x1C
Access: Read/Write Reset Value: 0x0D (before SROM download)
0x0E (after SROM download)
Bit 7 6 5 4 3 2 1 0
Field FBm7FBm6FBm5FBm4FBm3FBm2FBm1FBm0
Data Type: 16-bit unsigned integer.
USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) that may be
selected by the automatic frame rate control. Units are clock cycles. The formula is
Frame Rate = Clock Rate / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write
Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and
Lower registers. The minimum allowed write value is 0x7E0E; the maximum is 0xFFFF.
Reading this register will return the most recent value that was written to it. However, the value
will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers.
After writing to Frame_Period_Max_Bound_Upper, wait at least two frame times before writing to
Frame_Period_Min_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register
may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config
register for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
Bit765432 1 0
Field FBm15 FBm14 FBm13 FBm12 FBm11 FBm10 FBm9FBm8
Shutter_Max_Bound_Lower Address: 0x1D
Access: Read/Write Reset Value: 0x8C (before SROM download)
0x00 (after SROM download)
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum allowable shutter value when operating in automatic mode.
Units are clock cycles. Since the automatic frame rate function is based on shutter value, the
value in these registers can limit the range of the frame rate control. To read from the registers,
read Upper first followed by Lower. To write to the registers, write Lower first, followed by
Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. To set
the shutter manually, disable the AGC via the Extended_Config register and write the desired
value to these registers.
Reading this register will return the most recent value that was written to it. However, the value
will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers.
After writing to Frame_Period_Max_Bound_Upper, wait at least two frame times before writing to
Shutter_Max_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register may be
used in lieu of a timer to determine when it is safe to write. See the Extended_Config register
for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
Shutter_Max_Bound_Upper Address: 0x1E
Access: Read/Write Reset Value: 0x20
SROM_ID Address: 0x1F
Access: Read Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field SR7SR6SR5SR4SR3SR2SR1SR0
Bit 7 6 5 4 3 2 1 0
Field SB7SB6SB5SB4SB3SB2SB1SB0
Bit 7 6 5 4 3 2 1 0
Field SB15 SB14 SB13 SB12 SB11 SB10 SB9SB8
Data Type:8-Bit unsigned integer.
USAGE: Contains the revision of the downloaded Shadow ROM firmware. If the firmware has been
successfully downloaded and the chip is operating out of SROM, this register will contain the
SROM firmware revision, otherwise it will contain 0x00.
Note: The IC hardware revision is available by reading the Revision_ID register (register 0x01).
Reserved Address: 0x20 – 0x3C
Observation Address: 0x3D
Access: Read/Write Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field OB7Reserved OB5Reserved Reserved Reserved OB1OB0
Field Name Description
OB7 If set, chip is running SROM code
Reserved Reserved
OB5 NPD pulse was detected
Reserved Reserved
Reserved Reserved
Reserved Reserved
OB1 Set once per frame
OB0 Set once per frame
Bit 7 6 5 4 3 2 1 0
Field NPID7NPID6NPID5NPID4NPID3NPID2NPID1NPID0
Reserved Address: 0x3E
Inverse_Product_ID Address: 0x3F
Access: Read Reset Value: 0xF8
Data Type: Bit field
USAGE: Each bit is set by some process or action at regular intervals, or when the event occurs.
The user must clear the register by writing 0x00, wait an appropriate delay, and read the register.
The active processes will have set their corresponding bit(s). This register may be used as part
of a recovery scheme to detect a problem caused by EFT/B or ESD.
Data Type: Inverse 8-Bit unsigned integer
USAGE: This value is the inverse of the Product_ID, located at the inverse address. It can be
used to test the SPI port.
Pixel_Burst Address: 0x40
Access: Read Reset Value: 0x00
Data Type: Eight bit unsigned integer
USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values from one
and 2/3 complete frame. See the Synchronous Serial Port section for use details.
Bit 7 6 5 4 3 2 1 0
Field PB7PB6PB5PB4PB3PB2PB1PB0
Bit 7 6 5 4 3 2 1 0
Field MB7MB6MB5MB4MB3MB2MB1MB0
Data Type: Various, depending on data
USAGE: The Motion_Burst register is used for high-speed access to the Motion, Delta_X, and
Delta_Y, SQUAL, Shutter_Upper, and Shutter_Lower and Maximum_Pixel registers. See the
Synchronous Serial Port section for use details.
Motion_Burst Address: 0x50
Access: Read Reset Value: 0x00
SROM_Load Address: 0x 60
Access: Write Rset Value: N/A
Data Type: Eight bit unsigned integer
USAGE: The SROM_Load register is used for high-speed programming of the ADNS-3080 from an
external SROM or microcontroller. See the Synchronous Serial Port section for use details.
Read Also
ADNS-3080 Product Overview
ADNK-3080 Sample Kit
Relevant Application Notes
Application Note AN 5035*
Application Note AN 5034*
Application Note AN 5036*
* The application notes content are applicable for ADNS-3080 as well.
Ordering Information
Specify part number as follows:
ADNS-3080 = Sensor IC in a 20 pin plastic optical package, 20 per tube.
ADNB-3081 = Sensor IC and ADNS-2120 round lens bundle kit, 1000 pc incremental
ADNB-3082 = Sensor IC and ADNS-2120-001 trim lens bundle kit, 1000 pc incremental
ADNS-2120 = Round Optical Mouse Lens
ADNS-2120-001 = Trim Optical Mouse Lens
ADNS-2220 = LED Assembly Clip (Clear)
ADNS-2220-001 LED Assembly Clip (Black)
HLMP-ED80-XX000 = LED
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Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
Obsoletes 5989-1830EN
June 30, 2005
5989-3422EN