DC1012A-C - Linear Technology

LTC2495

2495fe

For more information www.linear.com/LTC2495

Features

applications

Description

16-Bit 8-/16-Channel

ADC with PGA, Easy Drive

and I2C Interface

The LTC

2495 is a 16-channel (eight differential), 16-bit,

No Latency DS

ADC with Easy Drive technology and a

2-wire, I2C interface. The patented sampling scheme elim-

inates dynamic input current errors and the shortcomings

of on-chip buffering through automatic cancellation of

differential input current. This allows large external source

impedances and rail-to-rail input signals to be directly

digitized while maintaining exceptional DC accuracy.

The LTC2495 includes programmable gain, a high accuracy

temperature sensor, and an integrated oscillator. This device

can be conﬁgured to measure an external signal (from com-

binations of 16 analog input channels operating in single-

ended or differential modes) or its internal temperature

sensor

. The integrated temperature sensor offers 1/2°C

resolution and 2°C absolute accuracy. The LTC2495 can

be conﬁgured to provide a programmable gain from 1 to

256 in 8 steps.

The LTC2495 allows a wide common mode input range

(0V to VCC), independent of the reference voltage. Any

combination of single-ended or differential inputs can

be selected and the ﬁrst conversion, after a new channel

is selected, is valid. Access to the multiplexer output en-

ables optional external ampliﬁers to be shared between all

analog inputs and auto calibration continuously removes

their associated offset and drift.

Data Acquisition System with Temperature Compensation

n Up to Eight Differential or 16 Single-Ended Inputs

n Easy Drive

Technology Enables Rail-to-Rail

Inputs with Zero Differential Input Current

n Directly Digitizes High Impedance Sensors with

Full Accuracy

n 2-Wire I2C Interface with 27 Addresses Plus One

Global Address for Synchronization

n 600nV RMS Noise

n Programmable Gain from 1 to 256

n Integrated High Accuracy Temperature Sensor

n GND to VCC Input/Reference Common Mode Range

n Programmable 50Hz, 60Hz, or Simultaneous

50Hz/60Hz Rejection Mode

n 2ppm INL, No Missing Codes

n 1ppm Offset and 15ppm Full-Scale Error

n 2x Speed/Reduced Power Mode (15Hz Using Internal

Oscillator and 80µA at 7.5Hz Output)

n No Latency: Digital Filter Settles in a Single Cycle,

Even After a New Channel is Selected

n Single Supply 2.7V to 5.5V Operation (0.8mW)

n Internal Oscillator

n Tiny 5mm × 7mm QFN Package

n Direct Sensor Digitizer

n Direct Temperature Measurement

n Instrumentation

n Industrial Process Control

Built-In High Performance Temperature Sensor

SCL

SDA

REF+

VCC

MUXOUT/

ADCIN

MUXOUT/

ADCIN

2.7V TO 5.5V

10µF

1.7k

COM

REF–

16-BIT ∆Σ ADC

WITH EASY DRIVE

16-CHANNEL

MUX

TEMPERATURE

SENSOR

IN+

IN–

2495 TA01

2-WIRE

C INTERFACE

CH0

CH1

•

CH7

CH8

CH15

0.1µF

OSC

TEMPERATURE (°C)

–55 –30 –5

ABSOLUTE ERROR (°C)

–4

–3

–2

–1

12095704520

2495 TA02

–5

typical application

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

No Latency DS and Easy Drive are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

LTC2495

2495fe

For more information www.linear.com/LTC2495

pin conFigurationabsolute MaxiMuM ratings

Supply Voltage (VCC) ................................... –0.3V to 6V

Analog Input Voltage

(CH0-CH15, COM) .....................–0.3V to (VCC + 0.3V)

REF+, REF– ...............................–0.3V to (VCC + 0.3V)

ADCINN, ADCINP, MUXOUTP,

MUXOUTN ................................–0.3V to (VCC + 0.3V)

Digital Input Voltage......................–0.3V to (VCC + 0.3V)

Digital Output Voltage ...................–0.3V to (VCC + 0.3V)

Operating Temperature Range

LTC2495C ................................................ 0°C to 70°C

LTC2495I .............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 150°C

(Notes 1, 2)

13 14 15 16

TOP VIEW

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

17 18 19

38 37 36 35 34 33 32

1GND

SCL

SDA

GND

COM

CH0

CH1

CH2

CH3

CH4

GND

REF–

REF+

VCC

MUXOUTN

ADCINN

ADCINP

MUXOUTP

CH15

CH14

CH13

CH12

CA2

CA1

CA0

GND

CH5

CH6

CH7

CH8

CH9

CH10

CH11

TJMAX = 125°C, θJA = 34°C/W

EXPOSED PAD (PIN #39) IS GND, MUST BE SOLDERED TO PCB

electrical characteristics (norMal speeD)

The l denotes the speciﬁcations which

apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 16 Bits

Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)

2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)

20 ppm of VREF

ppm of VREF

Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l0.5 5 µV

Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 10 nV/°C

Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l32 ppm of VREF

Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C

Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF l32 ppm of VREF

Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 0.1 ppm of VREF/°C

orDer inForMation

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2495CUHF#PBF LTC2495CUHF#TRPBF 2495 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C

LTC2495IUHF#PBF LTC2495IUHF#TRPBF 2495 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

LTC2495

2495fe

For more information www.linear.com/LTC2495

electrical characteristics (2x speeD)

The l denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 16 Bits

Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)

2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)

20 ppm of VREF

ppm of VREF

Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l0.2 2 mV

Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 100 nV/°C

Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l32 ppm of VREF

Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C

Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF l32 ppm of VREF

Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 0.1 ppm of VREF/°C

Output Noise 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC 0.85 µVRMS

Programmable Gain l1 128

converter characteristics

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB

Input Common Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l140 dB

Input Common Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) l140 dB

Input Normal Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l110 120 dB

Input Normal Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) l110 120 dB

Input Normal Mode Rejection 50Hz/60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) l87 dB

Reference Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l120 140 dB

Power Supply Rejection DC VREF = 2.5V, IN+ = IN– = GND 120 dB

Power Supply Rejection, 50Hz ±2%, 60Hz ±2% VREF = 2.5V, IN+ = IN– = GND (Notes 7, 8, 9) 120 dB

PARAMETER CONDITIONS MIN TYP MAX UNITS

Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V

5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V

2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V

ppm of VREF

Output Noise 2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC,

GND ≤ IN+ = IN– ≤ VCC (Note 12)

0.6 µVRMS

Internal PTAT Signal TA = 27°C (Note 13) 27.8 28.0 28.2 mV

Internal PTAT Temperature Coefﬁcient 93.5 µV/°C

Programmable Gain l1 256

electrical characteristics (norMal speeD)

The l denotes the speciﬁcations which

apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)

analog input anD reFerence

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN+Absolute/Common Mode IN+ Voltage

(IN+ Corresponds to the Selected Positive Input Channel)

GND – 0.3V VCC + 0.3V V

IN–Absolute/Common Mode IN– Voltage

(IN– Corresponds to the Selected Negative Input Channel or COM)

GND – 0.3V VCC + 0.3V V

LTC2495

2495fe

For more information www.linear.com/LTC2495

i2c inputs anD Digital outputs

The l denotes the speciﬁcations which apply over the full

operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)

analog input anD reFerence

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage l0.7VCC V

VIL Low Level Input Voltage l0.3VCC V

VIHA Low Level Input Voltage for Address Pins CA0, CA1, CA2 and Pin fO l 0.05VCC V

VILA High Level Input Voltage for Address Pins CA0, CA1, CA2 l0.95VCC V

RINH Resistance from CA0, CA1, CA2 to VCC to Set Chip Address Bit to 1 l 10 kW

RINL Resistance from CA0, CA1, CA2 to GND to Set Chip Address Bit to 0 l10 kW

RINF Resistance from CA0, CA1, CA2 to GND or VCC to Set Chip Address Bit

to Float

l2 MW

IIDigital Input Current (fO)l–10 10 µA

VHYS Hysteresis of Schmitt Trigger Inputs (Note 5) l0.05VCC V

VOL Low Level Output Voltage (SDA) I = 3mA l 0.4 V

tOF Output Fall Time VIH(MIN) to VIL(MAX) Bus Load CB 10pF to

400pF (Note 14)

l20 + 0.1CB250 ns

IIN Input Leakage (SDA/SCL) 0.1VCC ≤ VIN ≤ 0.9 • VCC l1 µA

CCAX External Capacitative Load on Chip Address Pins (CA0, CA1, CA2) for

Valid Float

l10 pF

power requireMents

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage l2.7 5.5 V

ICC Supply Current Conversion Current (Note 11)

Temperature Measurement (Note 11)

Sleep Mode (Note 11)

160

200

275

300

µA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Input Voltage Range (IN+ – IN–) Differential/Single-Ended l–FS +FS V

FS Full-Scale of the Input (IN+ – IN–) Differential/Single-Ended l0.5VREF/Gain V

LSB Least Signiﬁcant Bit of the Output Code lFS/216

REF+Absolute/Common Mode REF+ Voltage l0.1 VCC V

REF–Absolute/Common Mode REF– Voltage lGND REF+ – 0.1V V

VREF Reference Voltage Range (REF+ – REF–)l0.1 VCC V

CS(IN+) IN+ Sampling Capacitance 11 pF

CS(IN–) IN– Sampling Capacitance 11 pF

CS(VREF) VREF Sampling Capacitance 11 pF

IDC_LEAK(IN+)IN+ DC Leakage Current Sleep Mode, IN+ = GND l–10 1 10 nA

IDC_LEAK(IN–)IN– DC Leakage Current Sleep Mode, IN– = GND l–10 1 10 nA

IDC_LEAK(REF+)REF+ DC Leakage Current Sleep Mode, REF+ = VCC l–100 1 100 nA

IDC_LEAK(REF–)REF– DC Leakage Current Sleep Mode, REF– = GND l–100 1 100 nA

tOPEN MUX Break-Before-Make 50 ns

QIRR MUX Off Isolation VIN = 2VP-P DC to 1.8MHz 120 dB

LTC2495

2495fe

For more information www.linear.com/LTC2495

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fEOSC External Oscillator Frequency Range (Note 16) l10 1000 kHz

tHEO External Oscillator High Period l0.125 100 µs

tLEO External Oscillator Low Period l0.125 100 µs

tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode

60Hz Mode

Simultaneous 50Hz/60Hz Mode

External Oscillator (Note 10)

157.2

131

144.1

160.3

133.6

146.9

41036/fEOSC (in kHz)

163.5

136.3

149.9

tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode

60Hz Mode

Simultaneous 50Hz/60Hz Mode

External Oscillator (Note 10)

78.7

65.6

72.2

80.3

66.9

73.6

20556/fEOSC (in kHz)

81.9

68.2

75.1

Digital inputs anD Digital outputs

The l denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSCL SCL Clock Frequency l0 400 kHz

tHD(SDA) Hold Time (Repeated) START Condition l0.6 µs

tLOW LOW Period of the SCL Pin l1.3 µs

tHIGH HIGH Period of the SCL Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated START Condition l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time for SDA Signals (Note 14) l20 + 0.1CB300 ns

tfFall Time for SDA Signals (Note 14) l20 + 0.1CB300 ns

tSU(STO) Set-Up Time for STOP Condition l0.6 µs

tBUF Bus Free Time Between a Second START Condition l1.3 µs

i2c tiMing characteristics

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3, 15)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: Unless otherwise speciﬁed: VCC = 2.7V to 5.5V

VREFCM = VREF/2, FS = 0.5VREF/Gain

VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,

where IN+ and IN– are the selected input channels.

Note 4: Use internal conversion clock or external conversion clock source

with fEOSC = 307.2kHz unless otherwise speciﬁed.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator).

Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator).

Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =

280kHz ±2% (external oscillator).

Note 10: The external oscillator is connected to the fO pin. The external

oscillator frequency, fEOSC, is expressed in kHz.

Note 11: The converter uses its internal oscillator.

Note 12: The output noise includes the contribution of the internal

calibration operations.

Note 13: Guaranteed by design and test correlation.

Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).

Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.

Note 16: Refer to Applications Information section for Performance vs

Data Rate graphs.

LTC2495

2495fe

For more information www.linear.com/LTC2495

typical perForMance characteristics

Integral Nonlinearity

(VCC = 5V, VREF = 5V)

Integral Nonlinearity

(VCC = 5V, VREF = 2.5V)

Integral Nonlinearity

(VCC = 2.7V, VREF = 2.5V)

Total Unadjusted Error

(VCC = 5V, VREF = 5V)

Total Unadjusted Error

(VCC = 5V, VREF = 2.5V)

Total Unadjusted Error

(VCC = 2.7V, VREF = 2.5V)

Noise Histogram (6.8sps) Noise Histogram (7.5sps)

INPUT VOLTAGE (V)

–3

INL (ppm of V

REF

)

–1

–2

–1.5 –0.5 0.5 1.5

2495 G01

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

fO = GND

85°C

–45°C 25°C

INPUT VOLTAGE (V)

–3

INL (ppm of V

REF

)

–1

–2

–0.75 –0.25 0.25 0.75

2495 G02

1.25–1.25

VCC = 5V

VREF = 2.5V

VIN(CM) = 1.25V

fO = GND

–45°C, 25°C, 85°C

INPUT VOLTAGE (V)

–3

INL (ppm of V

REF

)

–1

–2

–0.75 –0.25 0.25 0.75

2495 G03

1.25–1.25

VCC = 2.7V

VREF = 2.5V

VIN(CM) = 1.25V

fO = GND

–45°C, 25°C, 85°C

INPUT VOLTAGE (V)

–12

TUE (ppm of V

REF

)

–4

–8

–1.5 –0.5 0.5 1.5

2495 G04

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

fO = GND 85°C

25°C

–45°C

INPUT VOLTAGE (V)

–12

TUE (ppm of V

REF

)

–4

–8

–0.75 –0.25 0.25 0.75

2495 G05

1.25–1.25

VCC = 5V

VREF = 2.5V

VIN(CM) = 1.25V

fO = GND

85°C

25°C

–45°C

INPUT VOLTAGE (V)

–12

TUE (ppm of V

REF

)

–4

–8

–0.75 –0.25 0.25 0.75

2495 G06

1.25–1.25

VCC = 2.7V

VREF = 2.5V

VIN(CM) = 1.25V

fO = GND 85°C

25°C

–45°C

OUTPUT READING (µV)

–3

NUMBER OF READINGS (%)

0.6

2495 G07

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 5V

VIN = 0V

TA = 25°C

GAIN = 256

RMS = 0.60µV

AVERAGE = –0.69µV

OUTPUT READING (µV)

–3

NUMBER OF READINGS (%)

0.6

2495 G08

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

14 10,000 CONSECUTIVE

READINGS

VCC = 2.7V

VREF = 2.5V

VIN = 0V

TA = 25°C

GAIN = 256

RMS = 0.59µV

AVERAGE = –0.19µV

LTC2495

2495fe

For more information www.linear.com/LTC2495

typical perForMance characteristics

Long-Term ADC Readings

RMS Noise

vs Input Differential Voltage RMS Noise vs VIN(CM)

RMS Noise vs Temperature (TA)RMS Noise vs VCC RMS Noise vs VREF

Offset Error vs VIN(CM) Offset Error vs Temperature

TIME (HOURS)

–5

ADC READING (µV)

–3

–1

10 20 30 40

2495 G09

–4

–2

VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = 2.5V

TA = 25°C

RMS NOISE = 0.60µV

GAIN = 256

INPUT DIFFERENTIAL VOLTAGE (V)

0.4

RMS NOISE (µV)

0.6

0.8

1.0

0.5

0.7

0.9

–1.5 –0.5 0.5 1.5

2495 G10

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

fO = GND

VIN(CM) (V)

–1

RMS NOISE (µV)

0.8

0.9

1.0

2 4

2495 G11

0.7

0.6

0 1 3 5 6

0.5

0.4

VCC = 5V

VREF = 5V

VIN = 0V

TA = 25°C

fO = GND

GAIN = 256

TEMPERATURE (°C)

–45

0.4

RMS NOISE (µV)

0.5

0.6

0.7

0.8

1.0

–30 –15 15

0 30 45 60

2495 G12

75 90

0.9

VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = GND

fO = GND

GAIN = 256

VCC (V)

2.7

RMS NOISE (µV)

0.8

0.9

1.0

3.9 4.7

2495 G13

0.7

0.6

3.1 3.5 4.3 5.1 5.5

0.5

0.4

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

TA = 25°C

fO = GND

GAIN = 256

VREF (V)

0.4

RMS NOISE (µV)

0.5

0.6

0.7

0.8

0.9

1.0

1 2 3 4

2495 G14

VCC = 5V

VIN = 0V

VIN(CM) = GND

TA = 25°C

fO = GND

GAIN = 256

VIN(CM) (V)

–1

OFFSET ERROR (ppm of VREF)

0.1

0.2

0.3

2 4

2495 G15

–0.1

0 1 3 5 6

–0.2

–0.3

VCC = 5V

VREF = 5V

VIN = 0V

TA = 25°C

fO = GND

TEMPERATURE (°C)

–45

–0.3

OFFSET ERROR (ppm of V

REF

)

–0.2

0.1

0.2

–15 15 30 90

2495 G16

–0.1

–30 0 45 60 75

0.3

VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = GND

fO = GND

LTC2495

2495fe

For more information www.linear.com/LTC2495

typical perForMance characteristics

On-Chip Oscillator Frequency

vs Temperature

On-Chip Oscillator Frequency

vs VCC PSRR vs Frequency at VCC PSRR vs Frequency at VCC

PSRR vs Frequency at VCC

Conversion Current

vs Temperature

TEMPERATURE (°C)

–45 –30

300

FREQUENCY (kHz)

304

310

–15 30 45

2495 G19

302

308

306

150 60 75 90

VCC = 4.1V

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

fO = GND

VCC (V)

2.5

300

FREQUENCY (kHz)

302

304

306

308

310

3.0 3.5 4.0 4.5

2495 G20

5.0 5.5

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

fO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

–20

–40

–60

–80

–100

–120

–140 1k 100k

2495 G21

10 100 10k 1M

REJECTION (dB)

VCC = 4.1V DC

VREF = 2.5V

IN+ = GND

IN– = GND

fO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

–140

REJECTION (dB)

–120

–80

–60

–40

20 100 140

2495 G22

–100

–20

80 180 220200

40 60 120 160

VCC = 4.1V DC ±1.4V

VREF = 2.5V

IN+ = GND

IN– = GND

fO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

30600

–60

–40

30750

2495 G23

–80

–100

30650 30700 30800

–120

–140

–20

REJECTION (dB)

VCC = 4.1V DC ±0.7V

VREF = 2.5V

IN+ = GND

IN– = GND

fO = GND

TA = 25°C

TEMPERATURE (°C)

–45

100

CONVERSION CURRENT (µA)

120

160

180

200

–15 15 30 90

2495 G24

140

–30 0 45 60 75

VCC = 5V

VCC = 2.7V

fO = GND

Offset Error vs VCC Offset Error vs VREF

VCC (V)

2.7

OFFSET ERROR (ppm of VREF)

0.1

0.2

0.3

3.9 4.7

2495 G17

–0.1

3.1 3.5 4.3 5.1 5.5

–0.2

–0.3

REF+ = 2.5V

REF– = GND

VIN = 0V

VIN(CM) = GND

TA = 25°C

fO = GND

VREF (V)

–0.3

OFFSET ERROR (ppm of V

REF

)

–0.2

–0.1

0.1

0.2

0.3

1 2 3 4

2495 G18

VCC = 5V

REF– = GND

VIN = 0V

VIN(CM) = GND

TA = 25°C

fO = GND

LTC2495

2495fe

For more information www.linear.com/LTC2495

typical perForMance characteristics

Sleep Mode Current

vs Temperature

Conversion Current

vs Output Data Rate

Integral Nonlinearity (2x Speed

Mode; VCC = 5V, VREF = 5V)

Integral Nonlinearity (2x Speed

Mode; VCC = 5V, VREF = 2.5V)

Integral Nonlinearity (2x Speed

Mode; VCC = 2.7V, VREF = 2.5V)

Noise Histogram

(2x Speed Mode)

RMS Noise vs VREF

(2x Speed Mode)

Offset Error vs VIN(CM)

(2x Speed Mode)

TEMPERATURE (°C)

–45

SLEEP MODE CURRENT (µA)

0.2

0.6

0.8

1.0

2.0

1.4

–15 15 30 90

2495 G25

0.4

1.6

1.8

1.2

–30 0 45 60 75

VCC = 5V

VCC = 2.7V

fO = GND

OUTPUT DATA RATE (READINGS/SEC)

SUPPLY CURRENT (µA)

500

450

400

350

300

250

200

150

100

2495 G26

0 20 3010

VCC = 3V

VCC = 5V

VREF = VCC

IN+ = GND

IN– = GND

fO = EXT OSC

TA = 25°C

INPUT VOLTAGE (V)

–3

INL (µV)

–1

–2

–1.5 –0.5 0.5 1.5

2495 G27

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

fO = GND

25°C, 85°C

–45°C

INPUT VOLTAGE (V)

–3

INL (ppm OF V

REF

)

–1

–2

–0.75 –0.25 0.25 0.75

2495 G28

1.25–1.25

VCC = 5V

VREF = 2.5V

VIN(CM) = 1.25V

fO = GND

85°C

–45°C, 25°C

INPUT VOLTAGE (V)

–3

INL (ppm OF V

REF

)

–1

–2

–0.75 –0.25 0.25 0.75

2495 G29

1.25–1.25

VCC = 2.7V

VREF = 2.5V

VIN(CM) = 1.25V

fO = GND

85°C

–45°C, 25°C

OUTPUT READING (µV)

179

NUMBER OF READINGS (%)

186.2

2495 G30

181.4 183.8 188.6

10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 5V

VIN = 0V

TA = 25°C

GAIN = 128

RMS = 0.85µV

AVERAGE = 0.184µV

VREF (V)

RMS NOISE (µV)

0.6

0.8

1.0

2495 G31

0.4

0.2

01235

VCC = 5V

VIN = 0V

VIN(CM) = GND

fO = GND

TA = 25°C

GAIN = 128

VIN(CM) (V)

–1

180

OFFSET ERROR (µV)

182

186

188

190

200

194

134

2495 G32

184

196

198

192

0256

VCC = 5V

VREF = 5V

VIN = 0V

fO = GND

TA = 25°C

LTC2495

2495fe

For more information www.linear.com/LTC2495

typical perForMance characteristics

PSRR vs Frequency at VCC

(2x Speed Mode)

PSRR vs Frequency at VCC

(2x Speed Mode)

PSRR vs Frequency at VCC

(2x Speed Mode)

FREQUENCY AT VCC (Hz)

–20

–40

–60

–80

–100

–120

–140 1k 100k

2495 G36

10 100 10k 1M

REJECTION (dB)

VCC = 4.1V DC

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GNDf

fO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

–140

RREJECTION (dB)

–120

–80

–60

–40

20 100 140

2495 G37

–100

–20

80 180 220200

40 60 120 160

VCC = 4.1V DC ±1.4V

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GND

fO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

30600

–60

–40

30750

2495 G38

–80

–100

30650 30700 30800

–120

–140

–20

REJECTION (dB)

VCC = 4.1V DC ±0.7V

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GND

fO = GND

TA = 25°C

Offset Error vs VCC

(2x Speed Mode)

Offset Error vs VREF

(2x Speed Mode)

VCC (V)

2 2.5

OFFSET ERROR (µV)

100

250

344.5

2495 G34

200

150

3.5 55.5

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

fO = GND

TA = 25°C

VREF (V)

OFFSET ERROR (µV)

190

200

210

2495 G35

180

170

160 1 2 4

220

230

240 VCC = 5V

VIN = 0V

VIN(CM) = GND

fO = GND

TA = 25°C

Offset Error vs Temperature

(2x Speed Mode)

TEMPERATURE (°C)

–45

OFFSET ERROR (µV)

200

210

220

2495 G33

190

180

160 –15 15 45

–30 90

030 60

170

240

230

VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = GND

fO = GND

LTC2495

2495fe

For more information www.linear.com/LTC2495

GND (Pins 1, 4, 6, 31, 32, 33, 34): Ground. Multiple

ground pins internally connected for optimum ground

current ﬂow and VCC decoupling. Connect each one of these

pins to a common ground plane through a low impedance

connection. All seven pins must be connected to ground

for proper operation.

SCL (Pin 2): Serial Clock Pin of the I2C Interface. The

LTC2495 can only act as a slave and the SCL pin only

accepts an external serial clock. Data is shifted into the

SDA pin on the rising edges of the SCL clock and output

through the SDA pin on the falling edges of the SCL clock.

SDA (Pin 3): Bidirectional Serial Data Line of the I2C Inter-

face. In the transmitter mode (read), the conversion result

is output through the SDA pin, while in the receiver mode

(write), the device channel select and conﬁguration bits

are input through the SDA pin. The pin is high impedance

during the data input mode and is an open drain output

(requires an appropriate pull-up device to VCC) during the

data output mode.

NC (Pin 5): No Connect. This pin can be left ﬂoating or

tied to GND.

COM (Pin 7): The Common Negative Input (IN–) for All

Single-Ended Multiplexer Conﬁgurations. The voltage on

CH0-CH15 and COM pins can have any value between

GND – 0.3V to VCC + 0.3V. Within these limits, the two

selected inputs (IN+ and IN– ) provide a bipolar input range

VIN = (IN+ – IN–) from –0.5 • VREF/Gain to 0.5 • VREF/Gain.

Outside this input range, the converter produces unique

over-range and under-range output codes.

CH0 to CH15 (Pin 8-Pin 23): Analog Inputs. May be pro-

grammed for single-ended or differential mode.

MUXOUTP (Pin 24): Positive Multiplexer Output. Connect

to the input of external buffer/ampliﬁer or short directly

to ADCINP

ADCINP (Pin 25): Positive ADC Input. Connect to the

output of a buffer/ampliﬁer driven by MUXOUTP or short

directly to MUXOUTP.

ADCINN (Pin 26): Negative ADC Input. Connect to the

output of a buffer/ampliﬁer driven by MUXOUTN or short

directly to MUXOUTN.

MUXOUTN (Pin 27): Negative Multiplexer Output. Connect

to the input of an external buffer/ampliﬁer or short directly

to ADCINN.

VCC (Pin 28): Positive Supply Voltage. Bypass to GND with

a 10µF tantalum capacitor in parallel with a 0.1µF ceramic

capacitor as close to the part as possible.

REF+, REF– (Pin 29, Pin 30): Differential Reference Input.

The voltage on these pins can have any value between

GND and VCC as long as the reference positive input,

REF+, remains more positive than the negative reference

input, REF–, by at least 0.1V. The differential voltage (VREF

= REF+ – REF–) sets the full-scale range (–0.5 • VREF/Gain

to 0.5 • VREF/Gain) for all input channels. When performing

an on-clip temperature measurement, the minimum value

of REF = 2V.

fO (Pin 35): Frequency Control Pin. Digital input that

controls the internal conversion clock rate. When fO is

connected to GND, the converter uses its internal oscillator

running at 307.2kHz. The conversion clock may also be

overridden by driving the fO pin with an external clock

in order to change the output rate and the digital ﬁlter

rejection null.

CA0, CA1, CA2 (Pins 36, 37, 38): Chip Address Control

Pins. These pins are conﬁgured as a three-state (LOW,

HIGH, Floating) address control bits for the device I2C

address.

Exposed Pad (Pin 39): Ground. This pin is ground and

must be soldered to the PCB ground plane. For prototyping

purposes, this pin may remain ﬂoating.

pin Functions

LTC2495

2495fe

For more information www.linear.com/LTC2495

Functional block DiagraM

AUTOCALIBRATION

AND CONTROL

DIFFERENTIAL

3RD ORDER

∆Σ MODULATOR

DECIMATING FIR

ADDRESS

INTERNAL

OSCILLATOR

I2C

2-WIRE

INTERFACE

GND

VCC

CH0

CH1 •

•

CH15

COM

MUX SDA

REF+

REF–

ADCINNMUXOUTN

ADCINPMUXOUTP

SCL

(INT/EXT)

2495 BD

–

TEMP

SENSOR

applications inForMation

Figure 1. State Transition Table

CONVERSION

SLEEP

2495 F01

YES

NO ACKNOWLEDGE

YES

NO STOP

OR READ

24 BITS

DATA OUTPUT/INPUT

POWER-ON RESET

DEFAULT CONFIGURATION:

IN+ = CH0, IN– = CH1

50Hz/60Hz REJECTION

1x OUTPUT, GAIN = 1

CONVERTER OPERATION

Converter Operation Cycle

The LTC2495 is a multichannel, low power, delta-sigma,

analog-to-digital converter with a 2-wire, I2C interface. Its

operation is made up of four states (see Figure 1). The con-

verter operating cycle begins with the conversion, followed

by the sleep state, and ends with the data input/output cycle.

Initially, at power-up, the LTC2495 performs a conversion.

Once the conversion is complete, the device enters the

sleep state. While in the sleep state, power consumption

is reduced by two orders of magnitude. The part remains

in the sleep state as long it is not addressed for a read/

write operation. The conversion result is held indeﬁnitely

in a static shift register while the part is in the sleep state.

The device will not acknowledge an external request during

the conversion state. After a conversion is ﬁnished, the

device is ready to accept a read/write request. Once the

LTC2495 is addressed for a read operation, the device be-

gins outputting the conversion result under the control of

the serial clock (SCL). There is no latency in the conversion

result. The data output is 24 bits long and contains a 16-bit

plus sign conversion result. Data is updated on the falling

edges of SCL allowing the user to reliably latch data on

the rising edge of SCL. A new conversion is initiated by

LTC2495

2495fe

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a STOP condition following a valid write operation or an

incomplete read operation. The conversion automatically

begins at the conclusion of a complete read cycle (all 24

bits read out of the device).

Ease of Use

The LTC2495 data output has no latency, ﬁlter settling

delay, or redundant data associated with the conversion

cycle. There is a one-to-one correspondence between the

conversion and the output data. Therefore, multiplexing

multiple analog inputs is straightforward. Each conversion,

immediately following a newly selected input or mode, is

valid and accurate to the full speciﬁcations of the device.

The LTC2495 automatically performs offset and full-scale

calibration every conversion cycle independent of the

input channel selected. This calibration is transparent

to the user and has no effect on the operation cycle de-

scribed above. The advantage of continuous calibration

is extreme stability of offset and full-scale readings with

respect to time, supply voltage variation, input channel

and temperature drift.

Easy Drive Input Current Cancellation

The LTC2495 combines a high precision, delta-sigma ADC

with an automatic, differential, input current cancellation

front end. A proprietary front-end passive sampling network

transparently removes the differential input current. This

enables external RC networks and high impedance sensors to

directly interface to the LTC2495 without external ampliﬁers.

The remaining common mode input current is eliminated

by either balancing the differential input impedances or

setting the common mode input equal to the common mode

reference (see the Automatic Differential Input Current Can-

cellation section). This unique architecture does not require

on-chip buffers, thereby enabling signals to swing beyond

ground and VCC. Moreover, the cancellation does not interfere

with the transparent offset and full-scale auto-calibration

and the absolute accuracy (full-scale + offset + linearity +

drift) is maintained even with external RC networks.

Power-Up Sequence

The LTC2495 automatically enters an internal reset state

when the power supply voltage, VCC, drops below a

applications inForMation

threshold of approximately 2.0V. This feature guarantees

the integrity of the conversion result and input channel

selection.

When VCC rises above this threshold, the converter creates

an internal power-on-reset (POR) signal with a duration

of approximately 4ms. The POR signal clears all internal

registers. The conversion immediately following a POR

cycle is performed on the input channels IN+ = CH0 and

IN– = CH1 with simultaneous 50Hz/60Hz rejection, 1x

output rate, and gain = 1. The ﬁrst conversion following a

POR cycle is accurate within the speciﬁcation of the device

if the power supply voltage is restored to (2.7V to 5.5V)

before the end of the POR interval. A new input channel,

rejection mode, speed mode, temperature selection or

gain can be programmed into the device during this ﬁrst

data input/output cycle.

Reference Voltage Range

This converter accepts a truly differential external reference

voltage. The absolute/common mode voltage range for the

REF+ and REF– pins covers the entire operating range of

the device (GND to VCC). For correct converter operation,

VREF must be positive (REF+ > REF–).

The LTC2495 differential reference input range is 0.1V to

VCC. For the simplest operation, REF+ can be shorted to VCC

and REF– can be shorted to GND. The converter output noise

is determined by the thermal noise of the front-end circuits

and, as such, its value in nanovolts is nearly constant with

reference voltage. A decrease in reference voltage will not

signiﬁcantly improve the converter’s effective resolution.

On the other hand, a decreased reference will improve the

converter’s overall INL performance.

Input Voltage Range

The LTC2495 input measurement range is –0.5 • VREF

to +0.5 • VREF in both differential and single-ended

conﬁgurations as shown in Figure 38. Highest linearity

is achieved with Fully Differential drive and a constant

common mode voltage (Figure 38b). Other drive schemes

may incur an INL error of approximately 50ppm. This error

can be calibrated out using a three point calibration and

a second-order curve ﬁt.

LTC2495

2495fe

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The analog inputs are truly differential with an absolute,

common mode range for the CH0-CH15 and COM input pins

extending from GND – 0.3V to VCC + 0.3V. Outside these

limits, the ESD protection devices begin to turn on and the

errors due to input leakage current increase rapidly. Within

these limits, the LTC2495 converts the bipolar differential

input signal VIN = IN+ – IN– (where IN+ and IN– are the

selected input channels), from – FS = – 0.5 • VREF/Gain

to + FS = 0.5 • VREF/Gain where VREF = REF+ – REF–. Outside

this range, the converter indicates the overrange or the un-

derrange condition using distinct output codes (see Table 1).

Signals applied to the input (CH0-CH15, COM) may extend

300mV below ground and above VCC. In order to limit

any fault current, resistors of up to 5k may be added in

series with the input. The effect of series resistance on

the converter accuracy can be evaluated from the curves

presented in the Input Current/Reference Current sections.

In addition, series resistors will introduce a temperature

dependent error due to input leakage current. A 1nA

input leakage current will develop a 1ppm offset error

on a 5k resistor if VREF = 5V. This error has a very strong

temperature dependency.

MUXOUT/ADCIN

The outputs of the multiplexer (MUXOUTP/MUXOUTN)

and the inputs to the ADC (ADCINP/ADCINN) can be used

to perform input signal conditioning on any of the select-

ed input channels or simply shorted together for direct

digitization. If an external ampliﬁer is used, the LTC2495

automatically calibrates both the offset and drift of this

circuit and the Easy Drive sampling scheme enables a

wide variety of ampliﬁers to be used.

In order to achieve optimum performance, if an external

ampliﬁer is not used, short these pins directly together

(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and

minimize their capacitance to ground.

I2C INTERFACE

The LTC2495 communicates through an I2C interface. The

I2C interface is a 2-wire, open-drain interface supporting

multiple devices and multiple masters on a single bus. The

connected devices can only pull the data line (SDA) LOW

and can never drive it HIGH. SDA is required to be exter-

nally connected to the supply through a pull-up resistor.

When the data line is not being driven, it is HIGH. Data on

the I2C bus can be transferred at rates up to 100kbits/s in

the standard mode and up to 400kbits/s in the fast mode.

The VCC power should not be removed from the device

when the I2C bus is active to avoid loading the I2C bus

lines through the internal ESD protection diodes.

Each device on the I2C bus is recognized by a unique

address stored in that device and can operate either as a

transmitter or receiver, depending on the function of the

device. In addition to transmitters and receivers, devices

can also be considered as masters or slaves when perform-

ing data transfers. A master is the device which initiates a

data transfer on the bus and generates the clock signals

to permit that transfer. Devices addressed by the master

are considered a slave.

The LTC2495 can only be addressed as a slave. Once

addressed, it can receive conﬁguration bits (channel

selection, rejection mode, speed mode) or transmit the

last conversion result. The serial clock line, SCL, is always

an input to the LTC2495 and the serial data line SDA is

bidirectional. The device supports the standard mode and

the fast mode for data transfer speeds up to 400kbits/s.

Figure 2 shows the deﬁnition of the I2C timing.

applications inForMation

Figure 2. Deﬁnition of Timing for Fast/Standard Mode Devices on the I2C Bus

SDA

SCL

S Sr P S

tHD(SDA) tHD(DAT)

tSU(STA) tSU(STO)

tSU(DAT)

tLOW tHD(SDA) tSP tBUF

trtftr

tHIGH 2495 F02

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For more information www.linear.com/LTC2495

The START and STOP Conditions

A START (S) condition is generated by transitioning SDA

from HIGH to LOW while SCL is HIGH. The bus is consid-

ered to be busy after the START condition. When the data

transfer is ﬁnished, a STOP (P) condition is generated by

transitioning SDA from LOW to HIGH while SCL is HIGH.

The bus is free after a STOP is generated. START and STOP

conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr) is generated instead of a STOP condition. The repeated

START timing is functionally identical to the START and is

used for writing and reading from the device before the

initiation of a new conversion.

Data Transferring

After the START condition, the I2C bus is busy and data

transfer can begin between the master and the addressed

slave. Data is transferred over the bus in groups of nine

bits, one byte followed by one acknowledge (ACK) bit. The

master releases the SDA line during the ninth SCL clock

cycle. The slave device can issue an ACK by pulling SDA

LOW or issue a Not Acknowledge (NACK) by leaving the

SDA line high impedance (the external pull-up resistor will

hold the line HIGH). Change of data only occurs while the

clock line (SCL) is LOW.

DATA FORMAT

After a START condition, the master sends a 7-bit address

followed by a read/write (R/W) bit. The R/W bit is 1 for a

read request and 0 for a write request. If the 7-bit address

matches the hard wired LTC2495’s address (one of 27

pin-selectable addresses) the device is selected. When

the device is addressed during the conversion state, it will

not acknowledge R/W requests and will issue a NACK by

leaving the SDA line HIGH. If the conversion is complete,

the LTC2495 issues an ACK by pulling the SDA line LOW.

The LTC2495 has two registers. The output register (24

bits long) contains the last conversion result. The input

temperature sensor, rejection mode, gain and speed mode.

DATA OUTPUT FORMAT

The output register contains the last conversion result.

After each conversion is completed, the device automat-

ically enters the sleep state where the supply current is

reduced to 1µA. When the LTC2495 is addressed for a read

operation, it acknowledges (by pulling SDA LOW) and acts

as a transmitter. The master/receiver can read up to three

bytes from the LTC2495. After a complete read operation

(3 bytes), a new conversion is initiated. The device will

NACK subsequent read operations while a conversion is

being performed.

applications inForMation

Table 1. Output Data Format

Differential Input Voltage

VIN*

Bit 23

SIG

Bit 22

MSB

Bit 21

Bit 20

Bit 19 … Bit 6

LSB

Bits 5-0

Always 0

VIN* ≥ FS** 1 1 0 0 0 … 0 000000

FS** – 1LSB 1 0 1 1 1 … 1 000000

0.5 • FS** 1 0 1 0 0 … 0 000000

0.5 • FS** – 1LSB 1 0 0 1 1 … 1 000000

0 1/0†0 0 0 0 … 0 000000

–1LSB 0 1 1 1 1 … 1 000000

–0.5 • FS** 0 1 1 0 0 … 0 000000

–0.5 • FS** – 1LSB 0 1 0 1 1 … 1 000000

–FS** 0 1 0 0 0 … 0 000000

VIN* < –FS** 0 0 1 1 1 … 1 000000

*The differential input voltage VIN = IN+ – IN–.

**The full-scale voltage FS = 0.5 • VREF/Gain.

†The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.

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The data output stream is 24 bits long and is shifted out

on the falling edges of SCL (see Figure 3a). The ﬁrst bit is

the conversion result sign bit (SIG) (see Tables 1 and 2).

This bit is HIGH if VIN ≥ 0 and LOW if VIN < 0 (where VIN

corresponds to the selected input signal IN+ – IN–). The

second bit is the most signiﬁcant bit (MSB) of the result.

The ﬁrst two bits (SIG and MSB) can be used to indicate

over and underrange conditions (see Table 2). If both bits

are HIGH, the differential input voltage is equal to or above

+FS. If both bits are set LOW, the input voltage is below –FS.

The function of these bits is summarized in Table 2. The

16 bits following the MSB bit are the conversion result in

binary, two’s complement format. The remaining six bits

are always 0.

As long as the voltage on the selected input channels (IN+

and IN–) remains between –0.3V and VCC + 0.3V (absolute

maximum operating range) a conversion result is generated

for any differential input voltage VIN from –FS = –0.5 •

VREF/Gain to +FS = 0.5 • VREF/Gain. For differential input

voltages greater than +FS, the conversion result is clamped

to the value corresponding to +FS. For differential input

voltages below –FS, the conversion result is clamped to

the value –FS – 1LSB.

Table 2. LTC2495 Status Bits

Input Range

Bit 23

SIG

Bit 22

MSB

VIN ≥ FS 1 1

0V ≤ VIN < FS 1/ 0 0

–FS ≤ VIN < 0V 0 1

VIN < –FS 0 0

INPUT DATA FORMAT

The serial input word to the LTC2495 is 16 bits long and

is written into the device input register in two 8-bit words.

The ﬁrst word (SGL, ODD, A2, A1, A0) is used to select the

input channel. The second word of data (IM, FA, FB, SPD,

GS2, GS1, GS0) is used to select the frequency rejection,

speed mode (1x, 2x), temperature measurement and gain.

applications inForMation

Figure 3a. Timing Diagram for Reading from the LTC2495

Figure 3b. Timing Diagram for Writing to the LTC2495

SLEEP DATA OUTPUT

ACK BY

LTC2497

ACK BY

MASTER ALWAYS LOW

START BY

MASTER

NACK BY

MASTER

LSBR MSBSGN BIT 21

7 … …8 9 1 2 9

1 2 3 4 5 6 7 8 9

7-BIT

ADDRESS

2495 F03a

SCL

SDA

SLEEP DATA INPUT

ACK BY

LTC2495

ACK

LTC2495

ACK

LTC2495

(OPTIONAL 2ND BYTE)

START BY

MASTER

SGL ODD

W01

SCL

SDA

EN A2 A1 A0

7 … 8 9 12 9 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9

7-BIT ADDRESS

2495 F03b

IM FAEN2 FB SPD GS2 GS1 GS0

LTC2495

2495fe

For more information www.linear.com/LTC2495

Table 3. Channel Selection

MUX ADDRESS CHANNEL SELECTION

SGL

ODD/

SIGN A2 A1 A0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COM

*0 0 0 0 0 IN+IN–

00001 IN+IN–

00010 IN+IN–

00011 IN+IN–

00100 IN+IN–

00101 IN+IN–

00110 IN+IN–

00111 IN+IN–

01000IN–IN+

01001 IN–IN+

01010 IN–IN+

01011 IN–IN+

01100 IN–IN+

01101 IN–IN+

01110 IN–IN+

01111 IN–IN+

10000IN+IN–

10001 IN+IN–

10010 IN+IN–

10011 IN+IN–

10100 IN+IN–

10101 IN+IN–

10110 IN+IN–

10111 IN+IN–

11000 IN+IN–

11001 IN+IN–

11010 IN+IN–

11011 IN+IN–

11100 IN+IN–

11101 IN+IN–

11110 IN+IN–

11111 IN+IN–

*Default at power-up

applications inForMation

LTC2495

2495fe

For more information www.linear.com/LTC2495

Table 4. Converter Conﬁguration

1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0 CONVERTER CONFIGURATION

1 0 0

Any

Input

Channel

X X X X X X X X Keep Previous

1 0 1 0 X X X X X X X Keep Previous

1 0 1 1 0

Any

Rejection

Mode

0 0 0 0 External Input, Gain = 1, Auto-Calibration

1 0 1 1 0 0 0 0 1 External Input, Gain = 4, Auto-Calibration

1 0 1 1 0 0 0 1 0 External Input, Gain = 8, Auto-Calibration

1 0 1 1 0 0 0 1 1 External Input, Gain = 16, Auto-Calibration

1 0 1 1 0 0 1 0 0 External Input, Gain = 32, Auto-Calibration

1 0 1 1 0 0 1 0 1 External Input, Gain = 64, Auto-Calibration

1 0 1 1 0 0 1 1 0 External Input, Gain = 128, Auto-Calibration

1 0 1 1 0 0 1 1 1 External Input, Gain = 256, Auto-Calibration

1 0 1 1 0 1 0 0 0 External Input, Gain = 1, 2x Speed

1 0 1 1 0 1 0 0 1 External Input, Gain = 2, 2x Speed

1 0 1 1 0 1 0 1 0 External Input, Gain = 4, 2x Speed

1 0 1 1 0 1 0 1 1 External Input, Gain = 8, 2x Speed

1 0 1 1 0 1 1 0 0 External Input, Gain = 16, 2x Speed

1 0 1 1 0 1 1 0 1 External Input, Gain = 32, 2x Speed

1 0 1 1 0 1 1 1 0 External Input, Gain = 64, 2x Speed

1 0 1 1 0 1 1 1 1 External Input, Gain = 128, 2x Speed

1 0 1 1 0 0 0

Any

Speed

Any

Gain

External Input, Simultaneous 50Hz/60Hz Rejection

1 0 1 1 0 0 1 External Input, 50Hz Rejection

1 0 1 1 0 1 0 External Input, 60Hz Rejection

1 0 1 1 0 1 1 Reserved, Do Not Use

10 1 1 1 0 0 X X X X Temperature Input, Simultaneous 50Hz/60Hz Rejection

1 0 1 1 1 0 1 X X X X Temperature Input, 50Hz Rejection

1 0 1 1 1 1 0 X X X X Temperature Input, 60Hz Rejection

1 0 1 1 1 1 1 X X X X Reserved, Do Not Use

After power-up, the device initiates an internal reset cycle

which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =

CH1), the frequency rejection to simultaneous 50Hz/60Hz,

and 1x output rate (auto-calibration enabled), and gain =

1. The ﬁrst conversion automatically begins at power-up

using this default conﬁguration. Once the conversion is

complete, up to two words may be written into the device.

The ﬁrst three bits of the ﬁrst input word consist of two

preamble bits and one enable bit. Valid settings for these

three bits are 000, 100, and 101. Other combinations

should be avoided.

If the ﬁrst three bits are 000 or 100, the following data is

ignored (don’t care) and the previously selected input chan-

nel and conﬁguration remain valid for the next conversion.

If the ﬁrst three bits shifted into the device are 101, then

the next ﬁve bits select the input channel for the next

conversion cycle (see Table 3).

The ﬁrst input bit (SGL) following the 101 sequence de-

termines if the input selection is differential (SGL = 0) or

single ended (SGL = 1). For SGL = 0, two adjacent channels

can be selected to form a differential input. For SGL = 1,

one of 16 channels is selected as the positive input. The

negative input is COM for all single-ended operations.

The remaining four bits (ODD, A2, A1, A0) determine

which channel(s) is/are selected and the polarity (for a

differential input).

Once the ﬁrst word is written into the device, a second

word may be input in order to select a conﬁguration mode.

The ﬁrst bit of the second word is the enable bit for the

conversion conﬁguration (EN2). If this bit is set to 0, then

the next conversion is performed using the previously

selected converter conﬁguration.

If the EN2 bit is set to a 1, a new conﬁguration can be

loaded into the device (see Table 4). The ﬁrst bit (IM) is

used to select the internal temperature sensor. If IM = 1,

the following conversion will be performed on the internal

applications inForMation

LTC2495

2495fe

For more information www.linear.com/LTC2495

temperature sensor rather than the selected input channel.

The next two bits (FA and FB) are used to set the rejection

frequency. The next bit (SPD) is used to select either the

1x output rate if SPD = 0 (auto-calibration is enabled and

the offset is continuously calibrated and removed from the

ﬁnal conversion result) or the 2x output rate if SPD = 1

(offset calibration disabled, multiplexing output rates up

to 15Hz with no latency). The ﬁnal three bits (GS2, GS1,

GS0) are used to set the gain. When IM = 1 (temperature

measurement) SPD, GS2, GS1 and GS0 will be ignored

and the device will operate in 1x mode.

The conﬁguration remains valid until a new input word

with EN = 1 (the ﬁrst three bits are 101 for the ﬁrst word)

and EN2 = 1 (for the second write byte) is shifted into

the device.

Rejection Mode (FA, FB)

The LTC2495 includes a high accuracy on-chip oscillator

with no required external components. Coupled with an

integrated fourth-order digital lowpass ﬁlter, the LTC2495

rejects line frequency noise. In the default mode, the

LTC2495 simultaneously rejects 50Hz and 60Hz by at least

87dB. If more rejection is required, the LTC2495 can be

conﬁgured to reject 50Hz or 60Hz to better than 110dB.

Speed Mode (SPD)

Every conversion cycle, two conversions are combined

to remove the offset (default mode). This result is free

from offset and drift. In applications where the offset is

not critical, the auto-calibration feature can be disabled

with the beneﬁt of twice the output rate.

While operating in the 2x mode (SPD = 1), the linearity

and full-scale errors are unchanged from the 1x mode

performance. In both the 1x and 2x mode there is no

latency. This enables input steps or multiplexer changes

to settle in a single conversion cycle, easing system over-

head and increasing the effective conversion rate. During

temperature measurements, the 1x mode is always used

independent of the value of SPD.

GAIN (GS2, GS1, GS0)

The input referred gain of the LTC2495 is adjustable

from 1 to 256 (see Tables 5a and 5b). With a gain of 1,

the differential input range is ±VREF/2 and the common

mode input range is rail-to-rail. As the gain is increased,

the differential input range is reduced to ±0.5 • VREF/Gain

but the common mode input range remains rail-to-rail.

As the differential gain is increased, low level voltages

are digitized with greater resolution. At a gain of 256, the

LTC2495 digitizes an input signal range of ±9.76mV with

over 16,000 counts.

applications inForMation

Table 5a. Performance vs Gain in Normal Speed Mode (VCC = 5V, VREF = 5V)

GAIN 1 4 8 16 32 64 128 256 UNIT

Input Span ±2.5 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m ±9.76m V

LSB 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 µV

Noise Free Resolution* 65536 65536 65536 65536 65536 65536 32768 16384 Counts

Gain Error 5 5 5 5 5 5 5 8 ppm of FS

Offset Error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 µV

Table 5b. Performance vs Gain in 2x Speed Mode (VCC = 5V, VREF = 5V)

GAIN 1 2 4 8 16 32 64 128 UNIT

Input Span ±2.5 ±1.25 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m V

LSB 38.1 19.1 9.54 4.77 2.38 1.19 0.596 0.298 µV

Noise Free Resolution* 65536 65536 65536 65536 65536 65536 45875 22937 Counts

Gain Error 5 5 5 5 5 5 5 5 ppm of FS

Offset Error 200 200 200 200 200 200 200 200 µV

*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.

LTC2495

2495fe

For more information www.linear.com/LTC2495

Temperature Sensor

The LTC2495 includes an integrated temperature sensor.

The temperature sensor is selected by setting IM = 1.

During temperature readings, MUXOUTN/MUXOUTP

remains connected to the selected input channel. The

ADC internally connects to the temperature sensor and

performs a conversion.

The digital output is proportional to the absolute tem-

perature of the device. This feature allows the converter

to perform cold junction compensation for external

thermocouples or continuously remove the temperature

effects of external sensors.

The internal temperature sensor output is 28mV at 27°C

(300°K), with a slope of 93.5µV/°C independent of VREF

(see Figures 4 and 5). Slope calibration is not required if

the reference voltage (VREF) is known. A 5V reference has

a slope of 2.45 LSBs16/°C. The temperature is calculated

from the output code (where DATAOUT16 is the decimal

representation of the 16-bit result) for a 5V reference using

the following formula:

DATAOUT

inKelvin

K=16

245.

If a different value of VREF is used, the temperature

output is:

DATAOUT V

in Kelvin

KREF

=16

12 25

•

If the value of VREF is not known, the slope is determined

by measuring the temperature sensor at a known tempera-

ture TN (in K) and using the following formula:

SLOPEDATAOUT

=16

This value of slope can be used to calculate further tem-

perature readings using:

DATAOUT

SLOPE

K=16

All Kelvin temperature readings can be converted to TC

(°C) using the fundamental equation:

TC = TK – 273

Initiating a New Conversion

When the LTC2495 ﬁnishes a conversion, it automatically

enters the sleep state. Once in the sleep state, the device is

ready for a read operation. After the device acknowledges

a read request, the device exits the sleep state and enters

the data output state. The data output state concludes

and the LTC2495 starts a new conversion once a STOP

condition is issued by the master or all 24 bits of data are

read out of the device.

During the data read cycle, a STOP command may be issued

by the master controller in order to start a new conversion

and abort the data transfer. This STOP command must be

issued during the ninth clock cycle of a byte read when

the bus is free (the ACK/NACK cycle).

applications inForMation

Figure 4. Internal PTAT Digital Output vs Temperature

Figure 5. Absolute Temperature Error

TEMPERATURE (K)

DATAOUT16

450

600

750

900

1050

400

2495 F04

300

0300200100

150

VCC = 5V

VREF = 5V

SLOPE = 2.45 LSB16/K

TEMPERATURE (°C)

–55 –30 –5

ABSOLUTE ERROR (°C)

–4

–3

–2

–1

12095704520

2495 F05

–5

LTC2495

2495fe

For more information www.linear.com/LTC2495

LTC2495 Address

The LTC2495 has three address pins (CA0, CA1, CA2).

Each may be tied HIGH, LOW, or left ﬂoating enabling one

of 27 possible addresses (see Table 6).

In addition to the conﬁgurable addresses listed in Table 6,

the LTC2495 also contains a global address (1110111)

which may be used for synchronizing multiple LTC2495s or

other LTC24XX delta-sigma I2C devices (see Synchronizing

Multiple LTC2495s with a Global Address Call section).

Operation Sequence

The LTC2495 acts as a transmitter or receiver, as shown

in Figure 6. The device may be programmed to perform

several functions. These include input channel selection,

measure the internal temperature, selecting the line fre-

quency rejection (50Hz, 60Hz, or simultaneous 50Hz and

60Hz), a 2x speed mode and gain.

Continuous Read

In applications where the input channel/conﬁguration does

not need to change for each cycle, the conversion can be

continuously performed and read without a write cycle

(see Figure 7). The conﬁguration/input channel remains

unchanged from the last value written into the device. If

the device has not been written to since power up, the

conﬁguration is set to the default value. At the end of a

read operation, a new conversion automatically begins.

At the conclusion of the conversion cycle, the next result

may be read using the method described above. If the

conversion cycle is not concluded and a valid address

applications inForMation

Table 6. Address Assignment

CA2 CA1 CA0 ADDRESS

LOW LOW LOW 0010100

LOW LOW HIGH 0010110

LOW LOW Float 0010101

LOW HIGH LOW 0100110

LOW HIGH HIGH 0110100

LOW HIGH Float 0100111

LOW Float LOW 0010111

LOW Float HIGH 0100101

LOW Float Float 0100100

HIGH LOW LOW 1010110

HIGH LOW HIGH 1100100

HIGH LOW Float 1010111

HIGH HIGH LOW 1110100

HIGH HIGH HIGH 1110110

HIGH HIGH Float 1110101

HIGH Float LOW 1100101

HIGH Float HIGH 1100111

HIGH Float Float 1100110

Float LOW LOW 0110101

Float LOW HIGH 0110111

Float LOW Float 0110110

Float HIGH LOW 1000111

Float HIGH HIGH 1010101

Float HIGH Float 1010100

Float Float LOW 1000100

Float Float HIGH 1000110

Float Float Float 1000101

Figure 6. Conversion Sequence

Figure 7. Consecutive Reading with the Same Input/Conﬁguration

S ACK DATA Sr DATA TRANSFERRING P

SLEEP DATA INPUT/OUTPUT CONVERSIONCONVERSION

7-BIT ADDRESS R/W

2495 F05

7-BIT ADDRESS

CONVERSION CONVERSION

CONVERSION

SLEEP SLEEPDATA OUTPUT DATA OUTPUT

7-BIT ADDRESSS SR RACK ACKREAD READP P

2495 F07

LTC2495

2495fe

For more information www.linear.com/LTC2495

applications inForMation

Discarding a Conversion Result and Initiating a New

Conversion with Optional Write

At the conclusion of a conversion cycle, a write cycle

can be initiated. Once the write cycle is acknowledged, a

STOP command will start a new conversion. If a new input

channel or conversion conﬁguration is required, this data

can be written into the device and a STOP command will

initiate the next conversion (see Figure 9).

Synchronizing Multiple LTC2495s with a Global

Address Call

In applications where several LTC2495s (or other I2C

delta-sigma ADCs from Linear Technology Corporation)

are used on the same I2C bus, all converters can be syn-

chronized through the use of a global address call. Prior

to issuing the global address call, all converters must have

completed a conversion cycle. The master then issues a

START, followed by the global address 1110111, and a write

Figure 10. Synchronize Multiple LTC2495s with a Global Address Call

Figure 8. Write, Read, START Conversion

Figure 9. Start a New Conversion Without Reading Old Conversion Result

7-BIT ADDRESS

CONVERSION CONVERSIONADDRESSSLEEP DATA OUTPUTDATA INPUT

7-BIT ADDRESSS RW ACK ACKWRITE Sr PREAD

2495 F08

7-BIT ADDRESS

CONVERSION CONVERSIONSLEEP DATA INPUT

S W ACK WRITE (OPTIONAL) P

2495 F09

GLOBAL ADDRESS

SCL

SDA

LTC2495 LTC2495 LTC2495…

ALL LTC2495s IN SLEEP CONVERSION OF ALL LTC2495s

DATA INPUT

S W ACK WRITE (OPTIONAL) P

2495 F10

selects the device, the LTC2495 generates a NACK signal

indicating the conversion cycle is in progress.

Continuous Read/Write

Once the conversion cycle is concluded, the LTC2495

can be written to and then read from using the repeated

START (Sr) command.

Figure 8 shows a cycle which begins with a data write, a

repeated START, followed by a read and concluded with a

STOP command. The following conversion begins after all

24 bits are read out of the device or after a STOP command.

The following conversion will be performed using the newly

programmed data. In cases where the same speed (1x/2x

mode), rejection frequency (50Hz, 60Hz, 50Hz and 60Hz)

and gain is used but the channel is changed, a STOP or

repeated START may be issued after the ﬁrst byte (channel

selection data) is written into the device.

LTC2495

2495fe

For more information www.linear.com/LTC2495

request. All converters will be selected and acknowledge

the request. The master then sends a write byte (optional)

followed by the STOP command. This will update the chan-

nel selection (optional) converter conﬁguration (optional)

and simultaneously initiate a START of conversion for all

delta-sigma ADCs on the bus (see Figure 10). In order

to synchronize multiple converters without changing the

channel or conﬁguration, a STOP may be issued after ac-

knowledgement of the global write command. Global read

commands are not allowed and the converters will NACK

a global read request.

Driving the Input and Reference

The input and reference pins of the LTC2495 are connected

directly to a switched capacitor network. Depending on

the relationship between the differential input voltage and

the differential reference voltage, these capacitors are

switched between these four pins. Each time a capacitor

is switched between two of these pins, a small amount

of charge is transferred. A simpliﬁed equivalent circuit is

shown in Figure 11.

When using the LTC2495’s internal oscillator, the input

capacitor array is switched at 123kHz. The effect of the

charge transfer depends on the circuitry driving the

input/reference pins. If the total external RC time constant

is less than 580ns the errors introduced by the sampling

process are negligible since complete settling occurs.

Typically, the reference inputs are driven from a low

impedance source. In this case, complete settling occurs

even with large external bypass capacitors. The inputs

(CH0-CH15, COM), on the other hand, are typically driven

from larger source resistances. Source resistances up

to 10k may interface directly to the LTC2495 and settle

completely; however, the addition of external capacitors

at the input terminals in order to ﬁlter unwanted noise

(anti-aliasing) results in incomplete settling.

The LTC2495 offers two methods of removing these errors.

The ﬁrst is automatic differential input current cancellation

(Easy Drive) and the second is the insertion of an external

buffer between the MUXOUT and ADCIN pins, thus isolating

the input switching from the source resistance.

applications inForMation

Figure 11. Equivalent Analog Input Circuit

IINIIN VV

IREF

AVG AVG

IN CM REFCM

()

=−

•

–() ()

.05

()

≈+

()

AVG

REFREF CM IN CM

VV V

.–

.• –

() ()

RREFEQ

REF

REFCM

where

VREF REF

VREFREF

•

–

()

=−

+−













=−

+− +−

VININWHERE IN ANDINARE THESELECT

IN , EEDINPUTCHANNELS

VIN IN

IN CM

()

–

=











+−

271160MINTERNALOSCILLATORHzMODEΩ

R 2.98MINTERNA

EQ =Ω LLOSCILLATOR 50Hz/60HzMODE

R 0.833 10 /f

EQ 12 EOS

=•

()

CC EXTERNALOSCILLATOR

IN+

IN–

10k

INTERNAL

SWITCH

NETWORK

10k

CEQ

12µF

10k

IIN–

REF+

IREF+

IIN+

IREF–

2495 F11

SWITCHING FREQUENCY

fSW = 123kHz INTERNAL OSCILLATOR

fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR

REF–

10k

100Ω

INPUT

MULTIPLEXER EXTERNAL

CONNECTION

100Ω

MUXOUTP ADCINP

EXTERNAL

CONNECTION

MUXOUTN ADCINN

LTC2495

2495fe

For more information www.linear.com/LTC2495

Automatic Differential Input Current Cancellation

In applications where the sensor output impedance is

low (up to 10kW with no external bypass capacitor or up

to 500W with 0.001µF bypass), complete settling of the

input occurs. In this case, no errors are introduced and

direct digitization is possible.

For many applications, the sensor output impedance

combined with external input bypass capacitors produces

RC time constants much greater than the 580ns required

for 1ppm accuracy. For example, a 10kW bridge driving a

0.1µF capacitor has a time constant an order of magnitude

greater than the required maximum.

The LTC2495 uses a proprietary switching algorithm that

forces the average differential input current to zero indepen-

dent of external settling errors. This allows direct digitization

of high impedance sensors without the need for buffers.

The switching algorithm forces the average input current

on the positive input (IIN+) to be equal to the average input

current on the negative input (IIN–). Over the complete

conversion cycle, the average differential input current

(IIN+ – IIN–) is zero. While the differential input current is

zero, the common mode input current (IIN+ + IIN–)/2 is

proportional to the difference between the common mode

input voltage (VIN(CM)) and the common mode reference

voltage (VREF(CM)).

In applications where the input common mode voltage is

equal to the reference common mode voltage, as in the

case of a balanced bridge, both the differential and common

mode input current are zero. The accuracy of the converter

is not compromised by settling errors.

In applications where the input common mode voltage is

constant but different from the reference common mode

voltage, the differential input current remains zero while

the common mode input current is proportional to the

difference between VIN(CM) and VREF(CM). For a reference

common mode voltage of 2.5V and an input common mode

of 1.5V, the common mode input current is approximately

0.74µA (in simultaneous 50Hz/60Hz rejection mode). This

common mode input current does not degrade the accuracy

if the source impedances tied to IN+ and IN– are matched.

Mismatches in source impedance lead to a ﬁxed offset

error but do not effect the linearity or full-scale reading.

A 1% mismatch in a 1k source resistance leads to a 74µV

shift in offset voltage.

In applications where the common mode input voltage

varies as a function of the input signal level (single-ended

applications inForMation

Figure 12. External Buffers Provide High Impedance Inputs

and Ampliﬁer Offsets are Automatically Cancelled

–

1/2 LTC6078

∆Σ ADC

WITH

EASY DRIVE

INPUTS

INPUT

MUX

MUXOUTP

MUXOUTN

2495 F12

LTC2495

ANALOG

INPUTS SCL

SDA

0.1µF

LTC2495

2495fe

For more information www.linear.com/LTC2495

type sensors), the common mode input current varies

proportionally with input voltage. For the case of balanced

input impedances, the common mode input current effects

are rejected by the large CMRR of the LTC2495, leading

to little degradation in accuracy. Mismatches in source

impedances lead to gain errors proportional to the dif-

ference between the common mode input and common

mode reference. A 1% mismatch in 1k source resistanc-

es lead to gain errors on the order of 15ppm. Based on

the stability of the internal sampling capacitors and the

accuracy of the internal oscillator, a one-time calibration

will remove this error

In addition to the input sampling current, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA max), results

in a small offset shift. A 1k source resistance will create a

1µV typical and a 10µV maximum offset voltage.

Automatic Offset Calibration of External Buffers/

Ampliﬁers

In addition to the Easy Drive input current cancellation,

the LTC2495 allows an external ampliﬁer to be inserted

between the multiplexer output and the ADC input (see

Figure 12). This is useful in applications where balanced

source impedances are not possible. One pair of external

buffers/ampliﬁers can be shared between all 17 analog

inputs. The LTC2495 performs an internal offset calibration

every conversion cycle in order to remove the offset and

drift of the ADC. This calibration is performed through a

combination of front-end switching and digital process-

ing. Since the external ampliﬁer is placed between the

multiplexer and the ADC, it is inside this correction loop.

This results in automatic offset correction and offset drift

removal of the external ampliﬁer.

The LTC6078 is an excellent ampliﬁer for this function.

It operates with supply voltages as low as 2.7V and its

noise level is 18nV/√Hz. The Easy Drive input technology

of the LTC2495 enables an RC network to be added directly

to the output of the LTC6078. The capacitor reduces the

magnitude of the current spikes seen at the input to the

ADC and the resistor isolates the capacitor load from the

op amp output enabling stable operation. The LTC6078

can also be biased at supply rails beyond those used by

the LTC2495. This allows the external sensor to swing rail-

to-rail (–0.3V to VCC + 0.3V) without the need of external

level-shift circuitry.

Reference Current

Similar to the analog inputs, the LTC2495 samples the

differential reference pins (REF+ and REF–) transferring

small amounts of charge to and from these pins, thus pro-

ducing a dynamic reference current. If incomplete settling

occurs (as a function the reference source resistance and

reference bypass capacitance) linearity and gain errors

are introduced.

For relatively small values of external reference capacitance

(CREF < 1nF), the voltage on the sampling capacitor settles

for reference impedances of many kW (if CREF = 100pF up

to 10kW will not degrade the performance (see Figures

13 and 14)).

applications inForMation

Figure 13. +FS Error vs RSOURCE at VREF (Small CREF)

Figure 14. –FS Error vs RSOURCE at VREF (Small CREF)

RSOURCE (Ω)

+FS ERROR (ppm)

10k

2495 F13

–10 10 100 1k 100k

VCC = 5V

VREF = 5V

VIN+ = 3.75V

VIN– = 1.25V

fO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

RSOURCE (Ω)

–FS ERROR (ppm)

–30

–10

10k

2495 F14

–50

–70

–40

–20

–60

–80

–90 10 100 1k 100k

VCC = 5V

VREF = 5V

VIN+ = 1.25V

VIN– = 3.75V

fO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

LTC2495

2495fe

For more information www.linear.com/LTC2495

In cases where large bypass capacitors are required on

the reference inputs (CREF > 0.01µF), full-scale and lin-

earity errors are proportional to the value of the reference

resistance. Every ohm of reference resistance produces

a full-scale error of approximately 0.5ppm (while oper-

ating in simultaneous 50Hz/60Hz mode (see Figures 15

and 16)). If the input common mode voltage is equal to

the reference common mode voltage, a linearity error of

approximately 0.67ppm per 100W of reference resistance

results (see Figure 17). In applications where the input

and reference common mode voltages are different, the

errors increase. A 1V difference in between common mode

input and common mode reference results in a 6.7ppm

INL error for every 100W of reference resistance.

In addition to the reference sampling charge, the reference

ESD protection diodes have a temperature dependent

leakage current. This leakage current, nominally 1nA

(±10nA max) results in a small gain error. A 100W reference

resistance will create a 0.5µV full-scale error.

Normal Mode Rejection and Anti-Aliasing

One of the advantages delta-sigma ADCs offer over

conventional ADCs is on-chip digital ﬁltering. Combined

with a large oversample ratio, the LTC2495 signiﬁcantly

simpliﬁes anti-aliasing ﬁlter requirements. Additionally,

the input current cancellation feature allows external

lowpass ﬁltering without degrading the DC performance

of the device.

applications inForMation

Figure 17. INL vs Differential Input

Voltage and Reference Source

Resistance for CREF > 1µF

Figure 19. Input Normal Mode Rejection, Internal

Oscillator and 60Hz Rejection Mode

Figure 18. Input Normal Mode Rejection, Internal

Oscillator and 50Hz Rejection Mode

Figure 15. +FS Error vs RSOURCE

at VREF (Large CREF)

Figure 16. –FS Error vs RSOURCE

at VREF (Large CREF)

RSOURCE (Ω)

+FS ERROR (ppm)

300

400

500

800

2495 F15

200

100

0200 400 600 1000

VCC = 5V

VREF = 5V

VIN+ = 3.75V

VIN– = 1.25V

fO = GND

TA = 25°C

CREF = 1µF, 10µF

CREF = 0.1µF

CREF = 0.01µF

RSOURCE (Ω)

–FS ERROR (ppm)

–200

–100

800

2495 F16

–300

–400

–500 200 400 600 1000

VCC = 5V

VREF = 5V

VIN+ = 1.25V

VIN– = 3.75V

fO = GND

TA = 25°C

CREF = 1µF, 10µF

CREF = 0.1µF

CREF = 0.01µF

VIN/VREF

–0.5

INL (ppm OF VREF)

0.3

2495 F17

–2

–6

–4

–8

–10 –0.3 –0.1 0.1 0.5

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

CREF = 10µF

R = 1k

R = 100Ω

R = 500Ω

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

0 fS2fS3fS4fS5fS6fS7fS8fS9fS10fS

11fS

12fS

INPUT NORMAL MODE REJECTION (dB)

2495 F18

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

0 fS

INPUT NORMAL MODE REJECTION (dB)

2495 F19

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120 2fS3fS4fS5fS6fS7fS8fS9fS10fS

LTC2495

2495fe

For more information www.linear.com/LTC2495

Figure 21. Input Normal Mode Rejection at fS = 256 • fN

Figure 20. Input Normal Mode Rejection at DC

applications inForMation

Figure 22. Input Normal Mode Rejection vs Input Frequency with

Input Perturbation of 100% (60Hz Notch)

Figure 23. Input Normal Mode Rejection vs Input Frequency with

Input Perturbation of 100% (50Hz Notch)

INPUT SIGNAL FREQUENCY (Hz)

INPUT NORMAL MODE REJECTION (dB)

2495 F20

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120 fN

0 2fN3fN4fN5fN6fN7fN8fN

fN = fEOSC/5120

INPUT SIGNAL FREQUENCY (Hz)

250fN252fN254fN256fN258fN260fN262fN

INPUT NORMAL MODE REJECTION (dB)

2495 F21

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

fN = fEOSC/5120

INPUT FREQUENCY (Hz)

015 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2495 F23

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

INPUT FREQUENCY (Hz)

012.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

NORMAL MODE REJECTION (dB)

2495 F24

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

LTC2495

2495fe

For more information www.linear.com/LTC2495

Figure 26. Measure Input Normal Mode Rejection vs Input

Frequency with Input Perturbation of 150% (50Hz Notch)

Figure 25. Measure Input Normal Mode Rejection vs Input

Frequency with Input Perturbation of 150% (60Hz Notch)

applications inForMation

Figure 24. Input Normal Mode Rejection vs Input Frequency with

Input Perturbation of 100% (50Hz/60Hz Notch)

The SINC4 digital ﬁlter provides excellent normal mode

rejection at all frequencies except DC and integer multiples

of the modulator sampling frequency (fS) (see Figures

18 and 19). The modulator sampling frequency is fS =

15,360Hz while operating with its internal oscillator and

fS = fEOSC/20 when operating with an external oscillator

of frequency fEOSC.

When using the internal oscillator, the LTC2495 is designed

to reject line frequencies. As shown in Figure 20, rejection

nulls occur at multiples of frequency fN, where fN is deter-

mined by the input control bits FA and FB (fN = 50Hz or

60Hz or 55Hz for simultaneous rejection). Multiples of the

modulator sampling rate (fS = fN • 256) only reject noise

to 15dB (see Figure 21); if noise sources are present at

these frequencies anti-aliasing will reduce their effects.

The user can expect to achieve this level of performance

using the internal oscillator, as shown in Figures 22, 23,

and 24. Measured values of normal mode rejection are

shown superimposed over the theoretical values in all

three rejection modes.

Traditional high order delta-sigma modulators suffer from

potential instabilities at large input signal levels. The

proprietary architecture used for the LTC2495 third-order

modulator resolves this problem and guarantees stability

INPUT FREQUENCY (Hz)

020 40 60 80 100 120 140 160 180 200 220

NORMAL MODE REJECTION (dB)

2495 F25

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

INPUT FREQUENCY (Hz)

015 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2495 F26

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

VIN(P-P) = 5V

VIN(P-P) = 7.5V

(150% OF FULL SCALE)

INPUT FREQUENCY (Hz)

NORMAL MODE REJECTION (dB)

2495 F27

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

VIN(P-P) = 5V

VIN(P-P) = 7.5V

(150% OF FULL SCALE)

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

LTC2495

2495fe

For more information www.linear.com/LTC2495

with input signals 150% of full scale. In many industrial

applications, it is not uncommon to have microvolt level

signals superimposed over unwanted error sources with

several volts if peak-to-peak noise. Figures 25 and 26

show measurement results for the rejection of a 7.5V

peak-to-peak noise source (150% of full scale) applied to

the LTC2495. These curves show that the rejection perfor-

mance is maintained even in extremely noisy environments.

Using the 2x speed mode of the LTC2495 alters the rejection

characteristics around DC and multiples of fS. The device

bypasses the offset calibration in order to increase the output

rate. The resulting rejection plots are shown in Figures 27

and 28. 1x type frequency rejection can be achieved using

the 2x mode by performing a running average of the previous

two conversion results (see Figure 29).

Output Data Rate

When using its internal oscillator, the LTC2495 produces

up to 15 samples per second (sps) with a notch frequency of

60Hz. The actual output data rate depends upon the length

of the sleep and data output cycles which are controlled

by the user and can be made insigniﬁcantly short. When

operating with an external conversion clock (fO connected

to an external oscillator), the LTC2495 output data rate

can be increased. The duration of the conversion cycle is

41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves

as if the internal oscillator is used.

An increase in fEOSC over the nominal 307.2kHz will trans-

late into a proportional increase in the maximum output

data rate (up to a maximum of 100sps). The increase in

output rate leads to degradation in offset, full-scale error,

and effective resolution as well as a shift in frequency re-

jection. When using the integrated temperature sensor, the

internal oscillator should be used or an external oscillator

fEOSC = 307.2kHz maximum.

A change in fEOSC results in a proportional change in the

internal notch position. This leads to reduced differential

mode rejection of line frequencies. The common mode

rejection of line frequencies remains unchanged, thus fully

differential input signals with a high degree of symmetry

on both the IN+ and IN– pins will continue to reject line

frequency noise.

An increase in fEOSC also increases the effective dynamic

input and reference current. External RC networks will

continue to have zero differential input current, but the

time required for complete settling (580ns for fEOSC =

307.2kHz) is reduced, proportionally.

Once the external oscillator frequency is increased above

1MHz (a more than 3x increase in output rate) the effective-

ness of internal auto calibration circuits begins to degrade.

This results in larger offset errors, full-scale errors, and

decreased resolution, as seen in Figures 30 to 37.

Figure 27. Input Normal Mode Rejection 2x Speed Mode Figure 28. Input Normal Mode Rejection 2x Speed Mode

applications inForMation

INPUT SIGNAL FREQUENCY (fN)

INPUT NORMAL REJECTION (dB)

2495 F27

–20

–40

–60

–80

–100

–120 0fN2fN3fN4fN5fN6fN7fN8fNINPUT SIGNAL FREQUENCY (fN)

INPUT NORMAL REJECTION (dB)

2495 F28

–20

–40

–60

–80

–100

–120 250248 252 254 256 258 260 262 264

LTC2495

2495fe

For more information www.linear.com/LTC2495

Figure 29. Input Normal Mode

Rejection 2x Speed Mode with and

Without Running Averaging

Figure 30. Offset Error vs Output Data

Rate and Temperature

Figure 31. +FS Error vs Output Data

Rate and Temperature

Figure 32.–FS Error vs Output Data

Rate and Temperature

Figure 33. Resolution (NoiseRMS ≤ 1LSB)

vs Output Data Rate and Temperature

Figure 34. Resolution (INLMAX ≤ 1LSB)

vs Output Data Rate and Temperature

Figure 36. Resolution (NoiseRMS ≤ 1LSB)

vs Output Data Rate and Reference Voltage

Figure 37. Resolution (INLMAX ≤ 1LSB) vs

Output Data Rate and Reference Voltage

Figure 35. Offset Error vs Output

Data Rate and Reference Voltage

applications inForMation

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

–70

–80

–90

–100

–110

–120

–130

–140 54 58

2495 F29

50 52 56 60 62

NORMAL MODE REJECTION (dB)

NO AVERAGE

WITH

RUNNING

AVERAGE

OUTPUT DATA RATE (READINGS/SEC)

–10

OFFSET ERROR (ppm OF VREF)

2495 F30

0 20 3010

VIN(CM) = VREF(CM)

VCC = VREF = 5V

VIN = 0V

fO = EXT CLOCK

TA = 25°C

TA = 85°C

OUTPUT DATA RATE (READINGS/SEC)

+FS ERROR (ppm OF VREF)

500

1500

2000

2500

3500

2495 F31

1000

3000

0 20 3010

TA = 25°C

TA = 85°C

VIN(CM) = VREF(CM)

VCC = VREF = 5V

fO = EXT CLOCK

OUTPUT DATA RATE (READINGS/SEC)

–3500

–FS ERROR (ppm OF VREF)

–3000

–2000

–1500

–1000

2495 F32

–2500

–500

0 20 3010

VIN(CM) = VREF(CM)

VCC = VREF = 5V

fO = EXT CLOCK

TA = 25°C

TA = 85°C

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

2495 F33

0 20 3010

VIN(CM) = VREF(CM)

VCC = VREF = 5V

VIN = 0V

fO = EXT CLOCK

RES = LOG 2 (VREF/NOISERMS)

TA = 25°C, 85°C

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

2495 F34

0 20 3010

TA = 25°C, 85°C

VIN(CM) = VREF(CM)

VCC = VREF = 5V

fO = EXT CLOCK

RES = LOG 2 (VREF/INLMAX)

OUTPUT DATA RATE (READINGS/SEC)

–10

OFFSET ERROR (ppm OF VREF)

–5

2495 F35

0 20 3010

VIN(CM) = VREF(CM)

VIN = 0V

fO = EXT CLOCK

TA = 25°C

VCC = 5V, VREF = 2.5V

VCC = VREF = 5V

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

2495 F36

0 20 3010

VIN(CM) = VREF(CM)

VIN = 0V

fO = EXT CLOCK

TA = 25°C

RES = LOG 2 (VREF/NOISERMS)

VCC = 5V, VREF = 2.5V, 5V

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

2495 F37

0 20 3010

VIN(CM) = VREF(CM)

VIN = 0V

REF– = GND

fO = EXT CLOCK

TA = 25°C

RES = LOG 2 (VREF/INLMAX)

VCC = 5V, VREF = 2.5V, 5V

LTC2495

2495fe

For more information www.linear.com/LTC2495

applications inForMation

Figure 38. Input Range

VCC + 0.3V

GND GND

GND

–0.3V

GND

–0.3V

(a) Arbitrary (b) Fully Differential

(d) Pseudo-Differential Unipolar

IN– or COM Grounded

IN– or COM Biased

VREF

–VREF

Selected IN+ Ch

Selected IN– Ch or COM

VCC

2495 F38

LTC2495

2495fe

For more information www.linear.com/LTC2495

package Description

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701 Rev C)

5.00 ± 0.10

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

PIN 1

TOP MARK

(SEE NOTE 6)

BOTTOM VIEW—EXPOSED PAD

5.50 REF 5.15 ± 0.10

7.00 ± 0.10

0.75 ± 0.05

R = 0.125

TYP

R = 0.10

TYP

0.25 ± 0.05

(UH) QFN REF C 1107

0.50 BSC

0.200 REF

0.00 – 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.00 REF

3.15 ± 0.10

0.40 ±0.10

0.70 ± 0.05

0.50 BSC

5.5 REF

3.00 REF 3.15 ± 0.05

4.10 ± 0.05

5.50 ± 0.05 5.15 ± 0.05

6.10 ± 0.05

7.50 ± 0.05

0.25 ± 0.05

PACKAGE

OUTLINE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

LTC2495

2495fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation

that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision history

REV DATE DESCRIPTION PAGE NUMBER

C 11/09 Update Tables 1 and 2 16

D 07/10 Revised Typical Application drawing 1

Added fO pin to parameter of VIHA in I2C Inputs and Outputs section 4

Added information to I2C Interface section 15

E 11/14 Clarify performance vs f0 frequency, reduced external oscillator max frequency to 1MHz

Clarify Input Voltage Range

Corrected Table 4 External Input, Gain = 256, Auto-Calibration

5, 9, 30

3, 4, 13, 31

(Revision history begins at Rev C)

LTC2495

2495fe

 LINEAR TECHNOLOGY CORPORATION 2007

LT 1114 REV E • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2495

PART NUMBER DESCRIPTION COMMENTS

1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift

LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift

LT1790 Micropower SOT-23 Low Dropout Reference Family 0.05% Max Initial Accuracy, 10ppm/°C Max Drift

LTC2400 24-Bit, No Latency DS ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2410 24-Bit, No Latency DS ADC with Differential Inputs 0.8µVRMS Noise, 2ppm INL

LTC2411/

LTC2411-1 24-Bit, No Latency DS ADCs with Differential Inputs in MSOP 1.45µVRMS Noise, 2ppm INL, Simultaneous 50Hz/60Hz

Rejection (LTC2411-1)

LTC2413 24-Bit, No Latency DS ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise

LTC2440 24-Bit, High Speed, Low Noise DS ADC 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs

LTC2442 24-Bit, High Speed, 2-/4-Channel DS ADC with Integrated

Ampliﬁer

8kHz Output Rate, 200nVRMS Noise, Simultaneous 50Hz/60Hz

Rejection

LTC2449 24-Bit, High Speed, 8-/16-Channel DS ADC 8kHz Output Rate, 200nVRMS Noise, Simultaneous 50Hz/60Hz

Rejection

LTC2480/LTC2482/

LTC2484 16-Bit/24-Bit DS ADCs with Easy Drive Inputs, 600nVRMS Noise,

Programmable Gain, and Temperature Sensor

Pin Compatible with 16-Bit and 24-Bit Versions

LTC2481/LTC2483/

LTC2485 16-Bit/24-Bit DS ADCs with Easy Drive Inputs, 600nVRMS Noise,

I2C Interface, Programmable Gain, and Temperature Sensor

Pin Compatible with 16-Bit and 24-Bit Versions

LTC2496 16-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and

SPI Interface

Pin Compatible with LTC2498/LTC2449

LTC2497 16-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and

I2C Interface

Pin Compatible with LTC2495/LTC2499

LTC2498 24-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and

SPI Interface, Temperature Sensor

Pin Compatible with LTC2496/LTC2449

LTC2499 24-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and

I2C Interface

Pin Compatible with LTC2495/LTC2497

relateD parts

typical application

External Buffers Provide High Impedance Inputs and

Ampliﬁer Offsets are Automatically Cancelled

–

1/2 LTC6078

∆Σ ADC

WITH

EASY DRIVE

INPUTS

INPUT

MUX

MUXOUTP

MUXOUTN

2495 TA03

LTC2495

ANALOG

INPUTS SCL

SDA

0.1µF