DDATA SHEET
Product specification June 2001
DISCRETE SEMICONDUCTORS
BT136X series E
Triacs
sensitive gate
NXP Semiconductors Product specification
Triacs BT136X series E
sensitive gate
GENERAL DESCRIPTION QUICK REFERENCE DATA
Passivated, sensitive gate triacs in a SYMBOL PARAMETER MAX. MAX. UNIT
full pack plastic envelope, intended for
use in general purpose bidirectional BT136X- 600E 800E
switching and phase control VDRM Repetitive peak off-state 600 800 V
applications, where high sensitivity is voltages
required in all four quadrants. IT(RMS) RMS on-state current 4 4 A
ITSM Non-repetitive peak on-state 25 25 A
current
PINNING - SOT186A PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 main terminal 1
2 main terminal 2
3 gate
case isolated
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
-600 -800
VDRM Repetitive peak off-state - 6001800 V
voltages
IT(RMS) RMS on-state current full sine wave; Ths ≤ 92 ˚C - 4 A
ITSM Non-repetitive peak full sine wave; Tj = 25 ˚C prior to
on-state current surge
t = 20 ms - 25 A
t = 16.7 ms - 27 A
I2tI
2t for fusing t = 10 ms - 3.1 A2s
dIT/dt Repetitive rate of rise of ITM = 6 A; IG = 0.2 A;
on-state current after dIG/dt = 0.2 A/μs
triggering T2+ G+ - 50 A/μs
T2+ G- - 50 A/μs
T2- G- - 50 A/μs
T2- G+ - 10 A/μs
IGM Peak gate current - 2 A
VGM Peak gate voltage - 5 V
PGM Peak gate power - 5 W
PG(AV) Average gate power over any 20 ms period - 0.5 W
Tstg Storage temperature -40 150 ˚C
TjOperating junction - 125 ˚C
temperature
T1T2
G
123
case
1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the triac may
switch to the on-state. The rate of rise of current should not exceed 3 A/μs.
June 2001 1 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Visol R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal - - 2500 V
three terminals to external waveform;
heatsink R.H. ≤ 65% ; clean and dustfree
Cisol Capacitance from T2 to external f = 1 MHz - 10 - pF
heatsink
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Rth j-hs Thermal resistance full or half cycle
junction to heatsink with heatsink compound - - 5.5 K/W
without heatsink compound - - 7.2 K/W
Rth j-a Thermal resistance in free air - 55 - K/W
junction to ambient
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IGT Gate trigger current VD = 12 V; IT = 0.1 A
T2+ G+ - 2.5 10 mA
T2+ G- - 4.0 10 mA
T2- G- - 5.0 10 mA
T2- G+ - 11 25 mA
ILLatching current VD = 12 V; IGT = 0.1 A
T2+ G+ - 3.0 15 mA
T2+ G- - 10 20 mA
T2- G- - 2.5 15 mA
T2- G+ - 4.0 20 mA
IHHolding current VD = 12 V; IGT = 0.1 A - 2.2 15 mA
VTOn-state voltage IT = 5 A - 1.4 1.70 V
VGT Gate trigger voltage VD = 12 V; IT = 0.1 A - 0.7 1.5 V
VD = 400 V; IT = 0.1 A; Tj = 125 ˚C 0.25 0.4 - V
IDOff-state leakage current VD = VDRM(max); Tj = 125 ˚C - 0.1 0.5 mA
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
dVD/dt Critical rate of rise of VDM = 67% VDRM(max); Tj = 125 ˚C; - 50 - V/μs
off-state voltage exponential waveform; gate open circuit
tgt Gate controlled turn-on ITM = 6 A; VD = VDRM(max); IG = 0.1 A; - 2 - μs
time dIG/dt = 5 A/μs
June 2001 2 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
Fig.1. Maximum on-state dissipation, Ptot, versus rms
on-state current, IT(RMS), where α = conduction angle.
Fig.2. Maximum permissible non-repetitive peak
on-state current ITSM, versus pulse width tp, for
sinusoidal currents, tp ≤ 20ms.
Fig.3. Maximum permissible non-repetitive peak
on-state current ITSM, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
Fig.4. Maximum permissible rms current IT(RMS) ,
versus heatsink temperature Ths.
Fig.5. Maximum permissible repetitive rms on-state
current IT(RMS), versus surge duration, for sinusoidal
currents, f = 50 Hz; Ths ≤ 92˚C.
Fig.6. Normalised gate trigger voltage
VGT(Tj)/ VGT(25˚C), versus junction temperature Tj.
012345
0
1
2
3
4
5
6
7
8
= 180
120
90
60
30
IT(RMS) / A
Ptot / W Ths(max) / C
125
119.5
114
108.5
103
97.5
92
86.5
81
1
-50 0 50 100 150
0
1
2
3
4
5BT136X
92 C
Ths / C
IT(RMS) / A
10us 100us 1ms 10ms 100ms
10
100
1000
T / s
ITSM / A
TITSM
time
I
Tj initial = 25 C max
T
dI /dt limit
T
T2- G+ quadrant
0.01 0.1 1 10
0
2
4
6
8
10
12
surge duration / s
IT(RMS) / A
1 10 100 1000
0
5
10
15
20
25
30 BT136
Number of cycles at 50Hz
ITSM / A
TITSM
time
I
Tj initial = 25 C max
T
-50 0 50 100 150
0.4
0.6
0.8
1
1.2
1.4
1.6
Tj / C
VGT(Tj)
VGT(25 C)
June 2001 3 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
Fig.7. Normalised gate trigger current
IGT(Tj)/ IGT(25˚C), versus junction temperature Tj.
Fig.8. Normalised latching current IL(Tj)/ IL(25˚C),
versus junction temperature Tj.
Fig.9. Normalised holding current IH(Tj)/ IH(25˚C),
versus junction temperature Tj.
Fig.10. Typical and maximum on-state characteristic.
Fig.11. Transient thermal impedance Zth j-hs, versus
pulse width tp.
Fig.12. Typical, critical rate of rise of off-state voltage,
dVD/dt versus junction temperature Tj.
-50 0 50 100 150
0
0.5
1
1.5
2
2.5
3
Tj / C
IGT(Tj)
IGT(25 C)
T2+ G+
T2+ G-
T2- G-
T2- G+
0 0.5 1 1.5 2 2.5 3
0
2
4
6
8
10
12
VT / V
IT / A
Tj = 125 C
Tj = 25 C typ max
Vo = 1.27 V
Rs = 0.091 ohms
-50 0 50 100 150
0
0.5
1
1.5
2
2.5
3
Tj / C
IL(Tj)
IL(25 C)
10us 0.1ms 1ms 10ms 0.1s 1s 10s
0.01
0.1
1
10
tp / s
Zth j-hs (K/W)
tp
P
t
D
unidirectional
with heatsink compound
without heatsink compound
bidirectional
-50 0 50 100 150
0
0.5
1
1.5
2
2.5
3
Tj / C
IH(Tj)
IH(25C)
0 50 100 150
1
10
100
1000
Tj / C
dVD/dt (V/us)
June 2001 4 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Fig.13. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Refer to mounting instructions for F-pack envelopes.
2. Epoxy meets UL94 V0 at 1/8".
10.3
max
3.2
3.0
4.6
max
2.9 max
2.8
seating
plane
6.4
15.8
max
0.6
2.5
2.54
5.08
123
3 max.
not tinned
3
0.5
2.5
0.9
0.7
M
0.4
15.8
max. 19
max.
13.5
min.
Recesses (2x)
2.5
0.8 max. depth
1.0 (2x)
1.3
June 2001 5 Rev 1.400
NXP Semiconductors
Legal information
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DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for product
development.
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