Integrated Device Technology, Inc.
FAST CMOS
BUFFER/CLOCK DRIVER
FEATURES:
0.5 MICRON CMOS Technology
Guaranteed low skew < 500ps (max.)
Very low duty cycle distortion < 1.0ns (max.)
Very low CMOS power levels
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
1:5 fanout per bank
‘Heartbeat’ monitor output
Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
Military product compliant to MIL-STD-883, Class B
•V
CC = 3.3V ± 0.3V
DESCRIPTION:
The FCT3805/A is a 3.3 volt, non-inverting clock driver built
using advanced dual metal CMOS technology. The device
consists of two banks of drivers, each with a 1:5 fanout and its
own output enable control. The device has a "heartbeat"
monitor for diagnostics and PLL driving. The MON output is
identical to all other outputs and complies with the output
specifications in this document. The FCT3805/A offers low
capacitance inputs with hysteresis.
The FCT3805/A is designed for high speed clock distribu-
tion where signal quality and skew are critical. The FCT 3805
also allows single point-to-point transmission line driving in
applications such as address distribution, where one signal
must be distributed to multiple receivers with low skew and
high signal quality.
IDT49FCT3805/A
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1995
1996 Integrated Device Technology, Inc. 9.5 DSC-3102/4
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
OEA
5
5
INA
INB
OEB
OA1-OA5
OB1-OB5
MON
3102 drw 01
3102 drw 02
3102 drw 03
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
INDEX
LCC
TOP VIEW
3 2 20 19
1
4
5
6
7
8
18
17
16
15
14
910111213
L20-2
OA3
GNDA
OA4
OA5
GNDQ
OB2
OB3
GNDB
OB4
OB5
OEA
INA
INB
OEB
MON
OA2
OA1
VCCA
VCCB
OB1
OB
1
OA
1
OA
3
GND
A
OA
4
OA
5
OA
2
OE
A
IN
A
OB
2
OB
3
GND
B
OB
4
MON
IN
B
OB
5
OE
B
V
CCB
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
V
CCA
GND
Q
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.5 2
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION FUNCTION TABLE(1)
3102 tbl 01
NOTE: 3102 tbl 02
1. H = HIGH, L = LOW, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1) CAPACITANCE (TA = +25°C, f = 1.0MHz)
3102 lnk 04
Symbol Rating Commercial Military Unit
VTERM(2) Terminal Voltage
with Respect to
GND
–0.5 to +4.6 –0.5 to +4.6 V
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0 V
VTERM(4) Terminal Voltage
with Respect to
GND
–0.5 to VCC
+ 0.5 –0.5 to VCC
+ 0.5 V
TAOperating
Temperature 0 to +70 –55 to +125 °C
TBIAS Temperature
Under Bias –55 to +125 –65 to +135 °C
TSTG Storage
Temperature –55 to +125 –65 to +150 °C
IOUT DC Output
Current –60 to +60 –60 to +60 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
3102 lnk 03
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
Capacitance VIN = 0V 3.5 5.0 pF
COUT Output
Capacitance VOUT = 0V 3.5 5.0 pF
Pin Names Description
OE
A
,
OE
B
3-State Output Enable Inputs (Active LOW)
IN
A
, IN
B
Clock Inputs
OA
n
, OB
n
Clock Outputs
MON Monitor Output
Inputs Outputs
OE
OE
A,
OE
OE
BINA, INBOAn, OBnMON
LLLL
LHHH
HLZL
HH ZH
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.5 3
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V; Military: TA = –55°C to +125°C, VCC = 3.3V ± 0.3V
3102 lnk 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC -0.6V at rated current.
6. The test limit for this parameter is ±5µA at TA = –55°C.
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 5.5 V
Input HIGH Level (I/O pins) 2.0 VCC+0.5
VIL Input LOW Level Guaranteed Logic LOW Level –0.5 0.8 V
(Input and I/O pins)
II H Input HIGH Current (Input pins)(6) VCC = Max. VI = 5.5V ±1µA
Input HIGH Current (I/O pins)(6) VI = VCC ——±1
II L Input LOW Current (Input pins)(6) VI = GND ±1
Input LOW Current (I/O pins)(6) VI = GND ±1
IOZH High Impedance Output Current VCC = Max. VO = VCC ——±1µA
IOZL (3-State Output pins)(6) VO = GND ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 –60 –110 mA
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 90 200 mA
VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC0.2 V
VIN = VIH or VIL IOH = –6mA MIL.
IOH = –8mA COM'L. 2.4(5) 3.0
VOL Output LOW Voltage VCC = Min. IOL = 0.1mA 0.2 V
VIN = VIH or VIL IOL = 16mA 0.2 0.4
IOL = 24mA 0.3 0.50
IOFF Input Power Off Leakage(6) VCC = 0V, VIN 4.5V ±1µA
IOS Short Circuit Current(4) VCC = Max., VO = GND(3) –60 –135 –240 mA
VHInput Hysteresis 150 mV
ICCL Quiescent Power Supply Current VCC = Max., COM'L. 0.1 10 µA
ICCH
ICCZ VIN = GND or VCC MIL. 0.1 100
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.5 4
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
3102 tbl 06
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
ICC Quiescent Power Supply Current
TTL Inputs HIGH VCC = Max.
VIN = VCC –0.6V(3) 2.0 30 µA
ICCD Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
OE
A =
OE
B = GND
Per Output Toggling
50% Duty Cycle
VIN = VCC
VIN = GND 0.035 0.06 mA/
MHz
ICTotal Power Supply Current(6) VCC = Max.
Outputs Open
fo = 25MHz
VIN = VCC
VIN = GND 0.9 1.6 mA
50% Duty Cycle
OE
A =
OE
B =VCC
Mon. Output Toggling
VIN = VCC –0.6V
VIN = GND 0.9 1.6
VCC = Max.
Outputs Open
fo = 50MHz
VIN = VCC
VIN = GND 20.0 33.0(5)
50% Duty Cycle
OE
A =
OE
B = GND
Eleven Outputs
Toggling
VIN = VCC –0.6V
VIN = GND 20.0 33.0(5)
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.5 5
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
3102 tbl 07
FCT3805 FCT3805A
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max.Min.(2) Max. Min.(2) Max. Unit
tPLH
tPHL Propagation Delay
INA to OAn, INB to OBnCL = 50pF
RL = 5001.5 5.8 1.5 5.0 ns
tROutput Rise Time 2.0 2.0 ns
tFOutput Fall Time 2.0 2.0 ns
tSK(o) Output skew: skew between outputs of all
banks of same package (inputs tied together) 0.7 0.5 ns
tSK(p) Pulse skew: skew between opposite
transitions of same output (|tPHL–tPLH|) 1.2 1.0 ns
tSK(t) Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
1.5 1.2 ns
tPZL
tPZH Output Enable Time
OE
A to OAn,
OE
B to OBn1.5 6.5 1.5 6.0 ns
tPLZ
tPHZ Output Disable Time
OE
A to OAn,
OE
B to OBn1.5 5.5 1.5 5.0 ns
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.5 6
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS ENABLE AND DISABLE TIME
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT =Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Test Switch
Disable LOW
Enable LOW 6.0V
Disable HIGH
Enable HIGH GND
PACKAGE DELAY OUTPUT SKEW- tSK(o)
PACKAGE SKEW- tSK(t)PULSE SKEW- tSK(p)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns
ENABLE AND DISABLE TIMES
3102 drw 05
3102 drw 07
3102 drw 06
3102 tbl 08
3102 drw 04
tPLH1
OUTPUT 1
OUTPUT 2
tSK(o)
tPLH2
3V
0V
VOH
1.5V
1.5V
VOL
VOH
1.5V
VOL
INPUT tPHL1
tPHL2
tSK(o)
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
3V
1.5V
0V
3.5V
0V
SWITCH
CLOSED
SWITCH
OPEN
VOL
VOH
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
3V
0V
VOH
tPLH tPHL
VOL
1.5V
1.5V
tRtF
2.0V
0.8V
INPUT
OUTPUT
INPUT tPLH1
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tSK(t)
tPLH2
3V
0V
VOH
1.5V
1.5V
VOL
VOH
1.5V
VOL
tPHL1
tPHL2
tSK(t)
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
tPLH tPHL
3V
0V
VOH
1.5V
1.5V
VOL
tSK(p) = |tPHL - tPLH|
INPUT
OUTPUT
3102 drw 09
3102 drw 08
Pulse
Generator D.U.T.
VCC
VIN VOUT
500
GND
6.0V
500
RT
50pF
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.5 7
ORDERING INFORMATION
XXX
Device Type XX
Package X
Process/
Blank
B
P
D
E
L
SO
PY
Q
3805
3805A
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
Non-Inverting 3.3V Buffer/Clock Driver
Temperature
Range
IDT 49FCT
3102 drw 10