PH28F320W18TD60 - Micron Technology, Inc.

Order Number: 290701, Revi sion: 015

07-Dec-2005

Intel® Wireless Flash Memory (W18)

28F320W18, 28F640W18, 28F128W18

Datasheet

Product Featu res

The I nte l® Wireless Flas h Mem ory (W18) device with flexible multi-partition dual-operati on

architecture, provides high-performance Asynchronous and Synchronous Burst reads. It is an

ideal m emory for low-voltage burst CPUs. Combining high read performance with flash

memor y intrinsic no n- volat ility, the W18 device eliminates the traditional system-perf ormance

paradigm of shadowing redundant code memory f rom slow nonvolati le storage to faster

execution memory. It reduces total memory requirement that increases reliability and reduces

overall system power consumption and cost. The W18 device’s flexible multi-partition

architecture allows program or eras e to occur in one partit ion while reading from another

part iti on. This al lows for high er data writ e th roughput compa red to single -parti tio n archite cture s

and designers can choose code and data partition s izes. The dual-operation archit ecture al lows

two pr oce ssors to interleave code operations while program and erase operation s take place in

the background.

■High Perf orm an ce Read-Whil e-Write/

Erase

—B u rst frequ en cy at 66 MHz

(ze ro wai t stat es)

—60 ns Initia l access read spe ed

—11 ns Burst mode read sp ee d

—20 ns Page mode read speed

—4-, 8-, 16-, and Continuous-Word Burst

mode reads

—Burst and Page mode reads in all

Blocks, across all partition boundaries

—Burst Susp end fe ature

—Enhance d F actory Programmi ng at

3.1 µs/word

■Security

—128- b it OTP Protection Regis ter:

64 unique pre-programmed bits +

64 user-programm able bits

—Absolute Write Protection with VPP at

ground

—Individual and Instant ane ous Block

Loc king/Unlo cking with Lock -Down

Capability

■Quality and Reliability

—Temperature Range: –40 °C to +85 °C

—1 00 K Erase Cy cle s pe r Block

—90 nm ETOX™ IX Process

—130 nm E TOX™ V I I I P r o c e s s

■Architecture

—Multipl e 4-Mbit partitions

—Dua l Operation: RWW or RWE

—Parameter block size = 4-Kword

—Mai n block size = 32-Kword

—Top or bottom parameter devices

—16-bit wide data bus

■Software

—5 µs (typ.) Program and Erase Suspend

latency time

—Flash Data Integrator (FDI) and

Common Flash Interface (CFI)

Compatible

—Programmable WAIT signal polarity

■Packaging and Power

—90 nm: 32- and 64-Mbit in VF BGA

—130 nm: 32-, 64-, and 128-Mbit in VF

BGA; 128-Mbit in QUAD+ package

—56 Active Ball Matrix, 0.75 m m Ba ll-

Pitch

—VCC = 1.70 V to 1 .95 V

—VCCQ (90 nm) = 1.70 V to 1.95 V

—VCCQ (130 nm) = 1.70 V to 2.24 V or

1.35 V to 1.80 V

—VCCQ (130 nm) = 1.3 5 V to 2.24 V

—Standby current (130 nm): 8 µA (typ.)

—Read current: 8 mA (4-word burs t, t yp.)

07-Dec-2005 Intel® Wireless Flash Memory (W18) Datasheet

2 Order Numbe r: 290701 , Revision: 015

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estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

The Intel® Wireless Flash Memory (W18) may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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Int el® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 3

Contents

1.0 Introduction ...............................................................................................................................9

1.1 Nomenclature .......................................................................................................................9

1.2 Conventions..........................................................................................................................9

2.0 Functional Overview ............................................................................................................11

2.1 Memo r y Map and Par tition ing...... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... .......... .... ..... ..12

3.0 P ack age Info rmat ion............................................................................................................15

3.1 W18 - 90 nm Lithography ....... ............ ....... ....... ............ ....... ....... ............ ....... ....... ............ ..15

3.2 W18 - 130 nm Lithography .......................... ............ ....... ....... ............ ....... ....... ............ .......16

4.0 Ballout and Signal Descriptions ......................................................................................18

4.1 Signal Ballout......................................................................................................................18

4.2 Signal Descriptions..... ............ ....... ............ ............ ....... ......... ............ ....... ....... ............ .......20

5.0 Maxi mum R atings and Ope rating Conditions ...........................................................24

5.1 Absolute Maxi mu m Ratings.... .......... .... .......... ..... .... .......... .... .......... ..... ......... ..... ......... ..... ..24

5.2 Ope r at i n g Condi tions......... ..... ..... ......... ..... .......... .... .......... .... ..... .......... .... .......... ..... ......... ..25

6.0 Electrical Specifications.....................................................................................................26

6.1 DC Curr ent Char a cte ristics..... ..... ..... ......... ..... ......... ..... ......... ..... .......... .... .......... ..... ......... ..26

6.2 DC Volt a ge Characteristics... ......... ..... ......... ..... .......... .... .......... ..... ......... ..... ......... ..... .........28

7.0 AC Characteristics................................................................................................................29

7.1 AC Write Characteristics ...................................................................................................41

7.2 Er as e an d Prog ra m Ti mes...... .......... .... ..... .......... .... .......... .... ..... .......... .... .......... ..... .... .......47

7.3 Rese t Sp e cifications........ ..... .... .......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... .........48

7.4 AC I/O Test Conditions.... .. ....... ..... ....... ..... ....... ..... ....... .. ..... ....... ..... ....... .. ....... ..... ....... ..... ..49

7.5 Device Capacitanc e................................ .......................... ................................. .................50

8.0 Power and Reset Specifications .....................................................................................51

8.1 Active Power.......................................................................................................................51

8.2 Automatic Power Savings (APS) ........................................................................................51

8.3 Sta n dby Po we r .... ..... ......... ..... .......... .... .......... ..... .... .......... .... .......... ..... ......... ..... ..... ...........51

8.4 Power -U p /Down Characteristics........... .......... ..... .... .......... .... .......... ..... ......... ..... ..... ......... ..51

8.4.1 System Reset and RST# ....................... .............. ................... .............. .................52

8.4.2 VCC, VPP, and RST# Tra n sition s ....... ..... ......... ..... .......... .... .......... .... ..... .......... ....52

8.5 Power Su p ply De co upling..... .... .......... ..... ......... ..... ..... ......... ..... ......... ..... ......... ..... ..... .........52

9.0 Bus Operations Overview..................................................................................................53

9.1 Bus Opera tions.... .......... .... ..... .......... .... .......... ..... .... .......... .... .......... ..... .... .......... ..... ...... .....53

9.1.1 Reads ....................................................................................................................53

9.1.2 Writes.....................................................................................................................54

9.1.3 Outp u t Disa b l e...... .......... ..... .... .......... ..... ......... ..... ......... ..... ......... ..... ..... ......... ..... ..54

9.1.4 Burst Suspend.......................................................................................................54

9.1.5 Standby..................................................................................................................55

9.1.6 Reset .....................................................................................................................55

Intel® Wireless Flash Memo ry (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

4 Order Numbe r: 290701 , Revision: 014

9.2 Device Commands ........ ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ....... ....55

9.3 Command Sequencing...................................................... ................... .............. ................59

10.0 Read Operations....................................................................................................................60

10.1 Async hronous P age Read M ode........................... ..................... .......................... ..............60

10.2 Synchronous Burst Read Mode............................. ..................... ................... ................... ..60

10.3 Read Array..........................................................................................................................61

10.4 R ead Iden tifier ..... ............................................. ............................................. .....................61

10.5 CFI Query...... .... ..... .......... .... .......... ..... .... .......... ..... ......... ..... .... .......... ..... ......... ..... .............62

10.6 R ead Status Register.............. ................... ................... .......................... .............. ..............62

10.7 Clear Status Register..........................................................................................................64

11.0 Program Operations.............................................................................................................65

11.1 Word Program ....................................................................................................................65

11.2 Factory Programmin g.........................................................................................................66

11.3 Enhanced Factory Program (EFP).....................................................................................67

11.3.1 EF P Requirem ents and Conside rations ... ..................... .......................... ..............67

11.3.2 Setup.....................................................................................................................68

11.3.3 Program.................................................................................................................68

11.3.4 Verify......................................................................................................................68

11.3.5 Exit.........................................................................................................................69

12.0 Program and Erase Operations.......................................................................................71

12.1 Program /Erase Sus pend and Resum e................................ ................... ................... .........71

12.2 Block Erase.........................................................................................................................73

12.3 R ead-Whi le-Write and Read-While-Eras e.................... .............. ...................................... ..75

13.0 Security Modes.......................................................................................................................77

13.1 Block Lock Operations........................................................................................................77

13.1.1 Lock.......................................................................................................................78

13.1.2 Unlock....................................................................................................................78

13.1.3 Lock-Down.............................................................................................................78

13.1.4 Blo ck Lock Status..................................................................................................79

13.1.5 Lock During Erase Suspe nd..................................................................................79

13.1.6 Status Register Error Checking.............................................................................79

13.1 .7 WP# Lock-D o wn Con tro l.......... ..... ......... ..... ..... ......... ..... ......... ..... ......... ..... .......... .80

13.2 Protection Register.............................................................................................................80

13.2.1 R eading the Protection Register...................... ................................. .....................81

13.2.2 Programing the Protection Register.......................................................................81

13.2.3 Locking the Protection Register .............................................................................82

13.3 VPP Prote ction.......... .... ..... ......... ..... ..... ......... ..... .......... .... ..... .......... .... ..... ......... ..... ..... ......83

14.0 Set Read Configuration Register....................................................................................84

14.1 Read Mod e (RCR[15])........................ ............................................. .......................... .........86

14.2 First Acce ss Latency Cou nt (RCR[13:11])..........................................................................86

14.2.1 Laten cy Count Settings........................ .......................... ................... .....................87

14.3 WAIT Signal Polarity (RCR[10])..........................................................................................88

14.4 WAIT Sign al Fun ction........... .......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... ......... ....88

14.5 Data Hold (RCR[9]).............................................................................................................89

14.6 WAIT Delay (RCR[8]).... .......... ......... ..... ......... ..... .......... ......... ..... ......... .......... .... .......... ......90

14.7 Burst Sequence (RCR[7])........ .. .. ..... ..... .. ..... .. ... .. ..... .. ..... .. ..... .. ... .. ..... .. ..... .. ... .. .. ..... ..... .. ....90

Int el® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 5

14.8 Clock Edge (RCR[6])..........................................................................................................91

14.9 Burst Wrap (RCR[3])...........................................................................................................92

14.10 B urst Length (RCR[2:0])...... ............ .............. ......................................................... ............92

Appendix A Write State Machine States............................................................................93

Appendix B Common Flash Interface (CFI).....................................................................96

Appendix C Ordering Information......................................................................................105

Intel® Wireless Flash Memo ry (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

6 Order Numbe r: 290701 , Revision: 014

Revision History

Date Revision Description

09/13/00 -001 Initial Rele ase

01/29/01 -002

Deleted 16-Mbit density

Revised ADV#, Section 2.2

Revised P rotection Registers, Sec tion 4.16

Revised Program Protection Register, Section 4.18

Revised Example in First Access Latency Count , Secti on 5. 0.2

Revised Figure 5, Data Output with LC Setting at Code 3

Added WAIT Signal Function, Sec ti on 5. 0.3

Revised WAIT Signal Polar ity, Section 5.0.4

Revised Data O utput Confi gu rat ion, Section 5.0.5

Added Figure 7, Data Output Configuration with WAIT Signal Delay

Revised WAIT Delay Configuration, Section 5.0.6

Changed VCCQ Spec from 1.7 V – 1.95 V to 1.7 V – 2.24 V in Section 8.2, Extended Tempe rature

Operation

Changed ICCS Spec from 15 µA to 18 µA in Section 8.4, DC

Characteristics

Changed ICCR Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13 mA (CLK = 52 MHz,

burst length = 4) to 13 mA, and 16 mA respectively in Section 8.4, DC Characteristics

Changed ICCWS Spec from 15 µA t o 18 µA in Section 8.4, DC

Characteristics

Changed ICCES Spec from 15 µA to 18 µA in Section 8.4, DC

Characteristics

Changed tCHQX Spec fr om 5 ns to 3 ns i n Section 8.6, AC Read

Characteristics

Added Figure 25, WAIT Signal in Synchronous Non-Read Array Operation Waveform

Added Figure 26, WAIT Signal in Async hronous Page Mo de Read

Operation Waveform

Added Figure 27, WAIT Signal in Asynch ro nous Single Word Read

Operation Waveform

Revised Appendix E, Ordering Information

06/12/01 -003

Re vi sed en ti re S ect io n 4 .10 , En ha nce d Fac to ry P rog ram C o mmand ( EFP) an d Fi gur e 6, Enhanced

Factory Program Flowchart

Revised Section 4.13, Protection Register

Revised Section 4.15, Program Protection Register

Revised Section 7.3, Capacitance, to include 12 8-Mbit specs

Revised Section 7.4, DC Characteristics, to include 128-Mbit specs

Revised Section 7.6, AC Read Characteristics, to i nclu de 128-Mbi t device specification s

Added tVHGL Spec in Section 7.6, AC Read Characterist ics

Revised Section 7.7, AC Write C haracter istics, to include 1 28-Mbit device specifications

Minor text edits

Int el® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 7

04/05/02 -004

New Sections Organization

Added 16-Word Burst Feature

Added Burst Suspend Section

Revised Block Locking State Diagram

Revised Active Power Section

Revised Automatic Power Savings Section

Revised Power-Up/Down Operation Section

Revised Extende d Tempera ture Operation

Added 128 Mb DC Characteristics Table

Added 128 Mb AC Read Characteristics

Revised Table 17. Test Configuration Component Values for Worst Case Speed Conditions

Added 0.13 µm Pr oduct DC and AC Read C haract eristics

Revised AC W rite Characteristics

Added Read to Write and Write to Rea d Trans ition W ave forms

Revised Reset Specifications

Various text edits

10/10/02 -005

Various text edits

Updated Latency C ount Section, including add ing La tency Count Tables

Added section 8.4 WAIT Function and WAIT Summary Table

Updated Package Drawing and Dimensions

11/12/02 -006 Various text cl arifications

01/14/03 -007 Removed Intel Burst Order

Revised Tabl e 10 “DC Current C haracteristics”

Various text edits

03/21/03 -008 Revised Table 22, Read Operations, tAPA

Added note to table 1 5, Configuration Register Desc riptions

Added note to section 3.1.1, Read

12/17/03 -009

Updated Block-L ock Operations ( Sec tion 7.1 and Figure 11)

Updated Table 21 (128 Mb ICCR)

Updated Table 4 (WAIT behavior)

Added QUAD+ ballout, package mechanicals, and order information

Various text edits including latest product-naming convention

02/12/04 -010

Added 90 nm product line

Removed µBGA* package

Added Page- and Burst-Mode description s

Minor text edits

05/06/04 -011 Fixed omitted text for Table 21, note 1 regarding max DC voltage on I/O pins

Removed E x tended I/O Supply Vol tage for 90 nm products

Minor text edits

06/0 3/04 -012 Updated the title and layout of the datasheet

Date Revision Description

Intel® Wireless Flash Memo ry (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

8 Order Numbe r: 290701 , Revision: 014

06/29/04 -013

VCCQ Max. ch ange d for 90 nm pro duct s

Updated “Absolute Maximum Ratings” table

Typical ICCS upda t ed as 35 µA

Updated subtitle

01/21/05 -014 Typical ICCS upda t ed as 22 µA

Minor text edits

07-Dec-2005 -015

Typical 90nm APS updated t o 22 µA in Ta ble 9 “DC Current Characteristics” on page 26.

Updated 90nm VLKO to 0.7 V in Table 10 “DC Voltage Characteristics” on page 28.

Product ordering information updat ed t o W in Tab le 47 “W 18 Fam il y: Av a ila bl e P rod uc t Or de ring

Information” on page 106.

Date Revision Description

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 9

1.0 Introduction

This datas heet contains information about the Intel® Wireless Flash Memo ry (W18) devic e fa m ily.

This section describes nom enclature used in the da tasheet. Section 2.0 provides an overview of the

W18 flash memory device. Section 6.0, Section 7.0, and Section 8.0 describe the electrical

spe cificati ons for extended te mperatur e product offerings. Or dering information can be found in

Appendix C.

1.1 Nomenclature

Acronyms that describe product features or usage are defined here:

1.2 Conventions

The fol lowing list des cribes abbrevi ated terms and phrases used throu ghout this doc ument:

APS Auto mati c Powe r Savin gs

BBA Block Base Address

CFI Common Flash Interface

CUI Command U s er Inter face

DU Don’t Use

EFP Enhanced Factory P rogramming

FDI Flash Data Integrat or

NC No Connect

OTP One-Time Programmable

PBA Parti tio n Base Address

RCR Read Configuration Register

RWE Read-While-Erase

RWW Read-While-Write

SCSP Stack ed Chip Scale Package

SRD Status Regi ster Data

VF BGA Very-thin, Fine-pitch, Ball Grid Array

WSM Wri te State Ma chin e

“1.8 V” Re fe rs to th e full VCC voltage range of 1.7 V – 1.95 V (except where noted) and

“VPP = 12 V” refers to 12 V ±5%.

Set Refers to registers means the bit is a logica l 1 and cleared means the bit is a logical 0.

Pin and sign al Often used interchangeably to refer to the external signal connections on the package

(ball is the term used for VF BGA).

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

10 Order Numbe r: 290701 , Revision: 015

Throughout this docume nt, references ar e made to top, bottom, paramet er, and partition. To clarify

these references, the follow ing conventions have been adopted:

Word 2 byte s or 16 bits.

Signal Names are in all CA PS (see Section 4.2, “Signal Descriptions ” on page 20 .)

Voltage Applied to the signal is subscripted for example VPP.

Block A group of bits (or words) that erase s imul taneousl y with one block erase instruction.

Main block Contains 32-Kword s.

Parame ter

block Contains 4- Kw ords.

Block Base

Address (BBA) The first address of a block.

Partition A g roup of blocks that share erase and program circu itry and a common Status Register.

Par titi on Bas e

Address (PBA) The first address of a partition. For example, on a 32-Mbit top-parameter device partition

number 5 has a PBA of 0x 14000 0.

Top partition Located at the highest physical device address. This partition may be a main partition or a

parameter partition.

Bottom

partition Loc at ed at the lo wes t ph ysi cal de vic e ad dres s. Thi s par t iti on ma y be a mai n p ar ti tio n or a

parameter partition.

Main partition Contains only main blocks.

Parame ter

partition Contains a mixture of main blocks and parameter blocks.

Top parameter

de v ice (TPD) Has the parameter partition at the top of the memory map with the parameter blocks at

the top of that partition. This was formerly referred to as a Top-Boot device.

Bottom

parameter

device (BPD)

Has the parameter partition at the bottom of the memory map with the parameter blocks

at the bottom of that partition. This was formerly referred to as a Bottom-Boot Block flash

device.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 11

2.0 Functional Overview

This section provides an overview of the W18 device features and architecture.

The W18 device provid es Read-While-Write (RWW) and Read-White-Erase (RWE) capab ility

with hi gh-pe rformance synch ronou s and as ynchronou s rea ds on pa ckage-compa ti ble den siti es with

a 16-bit data bus. Individually-erasable memory blocks are optimally sized for code and data

storage. Eight 4- Kwor d para me ter blocks are l oca ted in the parame ter partition at either t he top o r

bottom of the memory map. The rest of the memory array is grouped into 32-Kword main blocks.

The memory architec ture for the W18 devic e consists of multiple 4- Mbit partitions, the exa ct

number depending on device density. By dividing the memory array into partitions, program or

erase operations can take plac e s im ultaneously during read operations. Burst reads ca n traverse

partition boundaries, but user applic ation code is responsible for ensuring tha t they don’t extend

into a partition t hat is active ly programming or erasing. Although each partition has burs t-read,

write, and erase capabilities, simultaneous operation is limited to write or erase in one partition

while other partitions are in a read mode.

Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An

erase can be susp ended to perform a program or rea d operation wi thi n any block , except th at which

is erase-suspe nded. A program operation nested within a sus pended erase c an s ubs equently be

suspended to read yet another memory location.

After dev ice power-up or r eset, the W18 device defaults to asynchronous page-m ode read

configuration. W riti ng to the d evice’s Read Configuration Register (RCR) enables synchronous

bur st -mo de read operation. In sy nchronous mode, the CLK input i ncrements an inte rnal burst

addre ss genera tor. CLK also syn chroniz es the flash memory with th e host CPU an d outputs data on

every, or on every o ther, valid CL K cycl e after an ini tial latency. A pro grammable WAIT ou tput

signals to th e CPU when data from th e flas h memory d evic e is ready.

In addition to its improved architecture and interface, the W18 device incorporates Enhanced

Factory Programmin g (EFP) , a feature that enables fast programmi ng and low-power designs. The

EFP feature prov ide s the fast est cu rrently-avail abl e program performance, which c an increase a

fact ory’s manuf acturing throughput.

The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.

W ith t he 1. 8 V option, VCC and VPP can be tied together for a simple, ultra-low- power design . In

addition to voltage flex ibility, the dedicated VPP input provides complete data protection when

VPP ≤ VPPLK.

This device (130 nm) allows I/O operation at voltages lower than the minimum VCCQ of 1.70 V.

This Extended VCCQ range, 1.35 V – 1.8 V, permits even greater system design flexibility.

A 128-bit prote ction register enhances the user’s ability to im plement new s ecurity te chniques and

data pr otection sche m es . Unique flash dev ice identification and fraud-, cloning-, or content -

protection schemes are possible through a combination of factory-p r ogrammed and user-OTP data

cells. Zero-latency locking/unlocking on any m emory block provides instant and complete

protection for cri tical system code and data . An additiona l block lock-down capability provi des

hardware protection where software comma nds alone cannot cha nge the block’s prote ction status.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

12 Order Numbe r: 290701 , Revision: 015

The Command User Interfac e ( CUI ) is the sys tem pr ocess o r’s l ink to inte r n al flas h memory

operation. A valid com mand sequence written to the CUI initiates device Write State Machine

( WSM) ope ration that autom atical ly executes the al gorithms, timings, and verifications neces sar y

to manage flash memory pro gram and e r ase. An internal Status Register provides ready/busy

indication results of the operation (success, fail, and so on).

Thre e powe r-savi ng features– Automatic Power Savings (APS), standby, and RST # – can

significantly reduce power co nsumption. Th e device automatically enters APS mo de following

r ead cycle complet ion. St andby mode begins when the system deselects the flash memory by

de-asserting CE#. Driving RS T# l ow produces power sav ings similar to standby mode. It al so

re sets the part to read-array mode (important for system-level reset), clears internal Status

Registers, and provides an addi tional level of flash writ e protectio n.

2.1 Memory Map an d Partitioning

The W18 device is divided into 4-Mbit physi cal partit ions, whic h all ows simultaneou s RWW or

RWE operations and allows users to segment code and data areas on 4-Mbit boundaries. The

device’s memory array is as ymmetrically blocked, whi ch enable s system code and da ta integration

within a single flash device. Each block can be erased independently in block erase mode.

Si mul taneous pr ogram and erase operations are not allowed; only one partition a t a time can be

act ively programm ing or erasing. S ee Table 1, “Bottom Parameter Memory Map” on page 13 and

Table 2, “Top Parameter Memory Map” on page 14.

The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit

device has 32 partitions. Each device density contains one parameter partition and several main

partitions . The 4-Mbit parameter partiti on contains eight 4-Kword parameter blocks and seven 32-

Kwor d main blocks. Eac h 4-Mbit main partition contains eight 32-Kwo rd blocks each.

The bulk of the array is divided into main b locks that can store code or data , and parameter bloc ks

tha t allo w stora ge of frequent ly upda ted s mall para meters th at are norm ally st ored in EEPROM. By

using software te chniques, the word-rewrit e functiona lity of EEPROMs can be emulated.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 13

Table 1. Bottom Parameter Memory Map

Size

(KW) Blk # 32-Mbit Blk # 64-Mbit Blk # 128-Mbit

Main Partitions

Sixteen

Partitions

32 262 7F8000-7FFFFF

32 135 400000-407FFF

Eight

Partitions

32 134 3F8000-3FFFFF 134 3F8000-3FFFFF

32 71 200000-207FFF 71 200000-207FFF

Four

Partitions

32 70 1F8000-1FFFFF 70 1F8000-1FFFFF 70 1F8000-1FFFFF

32 39 100000-107FFF 39 100000-107FFF 39 100000-107FFF

One

Partition

32 38 0F8000-0FFFFF 38 0F8000-0FFFFF 38 0F8000-0FFFFF

32 31 0C0000-0C7FFF 31 0C0000-0C7FFF 31 0C0000-0C7FFF

One

Partition

32 30 0B8000-0BFFFF 30 0B8000-0BFFFF 30 0B8000-0BFFFF

32 23 080000-087FFF 23 080000-087FFF 23 080000-087FFF

One

Partition

32 22 078000-07FFFF 22 078000-07FFFF 22 078000-07FFFF

32 15 040000-047FFF 15 040000-047FFF 15 040000-047FFF

Parameter Partition

One Partition

32 14 038000-03FFFF 14 038000-03FFFF 14 038000-03FFFF

32 8 008000-00FFFF 8 008000-00FFFF 8 008000-00FFFF

4 7 007000-007FFF 7 007000-007FFF 7 007000-007FFF

4 0 000000-000FFF 0 000000-000FFF 0 000000-000FFF

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

14 Order Numbe r: 290701 , Revision: 015

Table 2. Top Par ame ter Me mory M ap

Size

(KW) Blk # 32-Mbit Blk # 64-Mbit Blk # 128-Mbit

Parameter Partition

One Partition

4 70 1FF000-1FFFFF 134 3FF000-3FFFFF 262 7FF000-7FFFFF

4 63 1F8000-1F8FFF 127 3F8000-3F8FFF 255 7F8000-7F8FFF

32 62 1F0000-1F7FFF 126 3F0000-3F7FFF 254 7F0000-7F7FFF

32 56 1C0000-1C7FFF 120 3C0000-3C7FFF 248 7C0000-7C7FFF

Main Partitions

One

Partition

32 55 1B8000-1BFFFF 119 3B8000-3BFFFF 247 7B8000-7BFFFF

32 48 18000-187FFF 112 380000-387FFF 240 780000-787FFF

One

Partition

32 47 178000-17FFFF 111 378000-37FFFF 239 778000-77FFFF

32 40 140000-147FFF 104 340000-347FFF 232 740000-747FFF

One

Partition

32 39 138000-13FFFF 103 338000-33FFFF 231 738000-73FFFF

32 32 100000-107FFF 96 300000-307FFF 224 700000-707FFF

Four

Partitions

32 31 0F8000-0FFFFF 95 2F8000-2FFFFF 223 6F8000-6FFFFF

32 0 000000-007FFF 64 200000-207FFF 192 600000-607FFF

Eight

Partitions

32 63 1F8000-1FFFFF 191 5F8000-5FFFFF

32 0 000000-007FFF 128 400000-407FFF

Sixteen

Partitions

32 127 3F8000-3FFFFF

32 0 000000-007FFF

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 15

3.0 Package Informatio n

3 .1 W18 - 90 nm Lit ho graph y

Figure 1. 32- and 64-Mb it VF BGA Package Drawing

Table 3. 32- and 64- Mbit VF BGA Package Dimensions

Dimension Symbol Millimeters Inches

Min Nom Max Min Nom Max

Package Height A - - 1.000 - - 0.0394

Ba ll Heigh t A10.150 - - 0.0059 - -

Pa ck ag e B od y Th ic kn es s A2- 0.665 - - 0.0262 -

Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Pa ck ag e B od y Width D 7. 60 0 7 .700 7.8 00 0.2 9 92 0.30 31 0.3 071

Pa ck ag e B od y Leng th E 8.90 0 9.00 0 9.1 00 0.3 5 04 0.3543 0 . 3 58 3

Pitch [e] - 0.750 - - 0.0295 -

Ball (Lead) Count N - 56 - - 56 -

Seating Plane Coplanarity Y - - 0.100 - - 0.0039

Corner to Ball A1 Distance Along D S11.125 1.225 1.325 0.0443 0.0482 0.0522

Corner to Ball A1 Distance Along E S22.150 2.250 2.350 0.0846 0.0886 0.0925

Seating

Plane

T op Vi ew - Bump Side D own Bottom V iew - Bal l S ide Up

Ball A1

Corne

87654321

Ball A1

Corner

87654321

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

16 Order Numbe r: 290701 , Revision: 015

3.2 W18 - 130 nm Lithography

Figure 2. 32-, 64-, and 128-Mbit VF BGA Package Drawing

Table 4. 32-, 64-, and 128-Mbit VF BGA Package Dimensions

Dimension Symbol Millimeters Inches

Min Nom Max Min Nom Max

Package Height A - - 1.000 - - 0.0394

Ball Height A10.150 - - 0.0059 - -

Package Body Thic kness A2- 0.665 - - 0.0262 -

Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Package Body Width (32/64-Mbit) D 7.600 7.700 7.800 0.2992 0.3031 0.3071

Package Body Width (128-Mbit) D 10.900 11.000 11.100 0.4291 0.4331 0.4370

P ac ka g e B od y Le ng th ( 32 /6 4/128 - M bi t) E 8.900 9. 000 9 .10 0 0. 3 50 4 0. 35 43 0. 35 83

Pitch [e] - 0.750 - - 0.0295 -

Ball (Lead) Count N - 56 - - 56 -

S ea tin g P la ne Co pl an ar i ty Y - - 0. 10 0 - - 0.00 39

Corner to Ball A1 Distance Along D (32/64-Mbit) S11.125 1.225 1.325 0.0443 0.0482 0.0522

Corner to Ball A1 Distance Along D (128-Mbit) S12.775 2.2875 2.975 0.1093 0.1132 0.1171

Corner to Ball A1 Distance Along E (32/64/128-Mbit) S22.150 2.250 2.350 0.0846 0.0886 0.0925

Seating

Plane

Top View - Bump Side Down Bottom Vie w - Ball Sid e Up

Ba ll A1

Corner

87654321

Ball A1

Corner

87654321

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 17

Figure 3. 128-M bit QUAD+ Packag e Drawing

Millimeters Inches

Dimensions Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.200 0.0472

Ball Height A1 0.200 0.0079

Pa ckage Body Thi ckness A2 0.860 0.0339

Ball (L ead) Width b 0 .3 25 0.375 0.42 5 0.012 8 0.014 8 0.01 67

Pa ckage Body Le ngth D 9.900 1 0. 00 0 10.100 0.3898 0.3937 0 .3 976

Pa ckage Body W idth E 7. 900 8.000 8 .1 00 0.31 10 0.3150 0 .3 189

Pi tch e 0.8 00 0 .0 31 5

Bal l (Lead) Count N 8 8 88

Se ating P lane Coplanarity Y 0.100 0.0039

Corner to Bal l A1 D istance Along E S1 1 .100 1.200 1.300 0.043 3 0.0472 0.0512

Corner to B all A1 D istance Along D S2 0 .500 0.600 0.700 0.0197 0.023 6 0.0276

Top View - Ball Down Bottom View - Ball Up

Draw ing not to scale.

2345678

A1 Index

Mark

12345678

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

18 Order Numbe r: 290701 , Revision: 015

4.0 Ballout and Signal Descriptions

4 .1 Signal Ballou t

The W18 de vice is ava il abl e in a 56-bal l VF BGA and µBGA Chip Scal e Pac kage with 0.75 mm

ball pitch, or the 88-ball (80 active balls) QUAD+ SCSP package. Figure 4 shows the device

ballout for the VF BGA package. Figure 5 shows the de vic e ballout for the QUAD+ package.

Figure 4. 56-Ball VF BGA Ballout

Notes:

1. On lower density devices, u pper address ba lls ca n be treated as NC. (Example: For 32- Mbit density, A21 and A22 are

NC).

2. See Section 3.0, “Package Information” on page 15 for mechanical specificat ions for the package.

Top View - Ball Side Down

Complete Ink Mark Not Shown

8 7 6 5 4 3 2 11 2 3 4 5 6 7 8

Botto m Vi ew - Ball Side Up

A4 A6 A18 VPP VCC VSS A8 A11

A3 A5 A17 RST# CLK A20 A9 A12

A2 A7 WE# ADV#

A19 A10 A13

A1 A14WP# DQ12 A16 WAIT A15

A0 CE# DQ1 DQ2 DQ4 DQ6 DQ15 VCCQ

OE# DQ0 DQ9 DQ10 DQ11 DQ13 DQ14 VSS

VSSQ DQ8 VCCQ DQ3 VCC DQ5 VSSQ DQ7

A22

A21

A4A6A18VPPVCCVSSA8A11

A3A5A17

RST#

CLKA20A9A12

A2A7

WE#ADV# A19

A10A13

A1A14 WP#DQ12A16WAITA15

A0CE#DQ1DQ2DQ4DQ6DQ15VCCQ

OE#DQ0DQ9DQ10DQ11DQ13DQ14VSS

VSSQDQ8VCCQDQ3VCCDQ5VSSQDQ7

A22

A21

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 19

Figure 5. 88-Ball (80 Active Ba lls) QUAD+ Ballout

Notes:

1. Unused upper address balls can be treated as NC (for 128-Mbit device, A[25:23] are not used).

2. S ee S ection 3.0, “ Package I nformation” on pa ge 15 for the mechanical specifications for the package.

Flash specific

SRAM/P SR AM speci fi c

Global

Legend:

Top Vi ew - Ball Side Down

87654321

DU DU DU

DUDUDU DU

A2 A7

A1 A6

A18 A19 VSS

VSSA23

A24

A25

A17

F2-VCC

CLK

A21

A22 A12

A11

A13A9P1-CS#

F-VPP,

F-VPEN

A20 A10 A15

F-WE# A8

D8 D2 D10 D5 D13 WAIT

A14 A16

F1-CE# P-Mode,

P-CRE

VSS VSS VSS

P2-CS#

F1-VCC

F2-VCC VCCQF3-CE#

D0 D1

D4 D6

D15D11

D12 D14

F1-OE#

F2-OE#

P-VCC

S-CS2

R-WE#

R-UB#

R-LB#

R-OE#

S-VCC

S-CS1#

F1-VCC

F-WP# ADV#

F-RST#

F2-CE#

VCCQ

VSS VSSVCCQ VSS

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

20 Order Numbe r: 290701 , Revision: 015

4.2 Signa l D escriptions

Table 5 describes the signals used on the VF BGA package. Table 6 describes the signa ls used on

the QUAD+ pac kage .

Table 5. Signal Descriptions - VF BGA Package

Symbol Type Name and Function

A[22:0] Input ADDRESS INPUTS: For memory addresses. 32-Mbit: A[20:0]; 64-Mbit: A[21:0]; 128-Mbit: A[22:0]

D[15:0] Input/

Output

DATA INPUTS/OUTPUTS: Inputs data a nd commands during write cycl es; outputs da ta during

m emory, Stat us Register, protection register, a nd configurat ion c ode reads. Data pins float wh en the

chip or outputs are deselected. Data is internally latched during writes.

ADV# Input ADDRESS VALID: AD V# indicates valid address prese nce on address inputs . During synchronous

read operations, all addresses are l atc hed on AD V#’s rising edge or the next valid CLK ed ge with

ADV# low , whichever occurs first.

CE# Input CHI P ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.

De-asserting CE# deselects the device, places it in standby mode, and places all outputs in High-Z.

CLK Input CLOCK: CLK synchronizes the device to the system bus frequency during synchronous r eads and

increments an internal address generator . During synchronous read operations, addresses are latched

on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first.

OE# Input OUTP UT ENABLE: When a sse r ted, OE # enabl es t he d ev ic e’s ou tp ut dat a bu ff er s dur i ng a re ad cyc le .

When OE# is deasserted, data outputs are placed in a high-impedance state.

RST# Input RESET: When low, RST# resets internal automation and inhibits write operations. This provides data

protection during power transitions. de-asserting RST# enable s normal op eration and places t he

device in asynchronous read-array mode.

WAIT Output WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to

be asse rted- hig h or asserted-low based on bit 10 of the Read Configuration Register. WAIT is tri-

s tated if CE# is deasserted. WAIT is not gated by OE#.

WE# Input WRITE ENABLE: WE# controls wri tes to the CUI and array. Addresses and data are latched on the

rising edge of WE#.

WP# Input WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down

mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See

Section 13.1, “Block Lock Operations” on page 77 for details on block locking.

VPP Power

ERASE AND PROGRAM POWER: A valid voltage on th is pin allows erasing or programming.

M emory contents cann ot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP

v oltages should not be attempted.

Set VPP = VCC for in - sys t em pro gr a m and er a se ope ratio ns. To ac c om m od ate re s is tor or di ode drops

from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain abov e VPP1

m in to perfor m in-system flash modification. VPP may be 0 V durin g read operations.

VPP2 c an be ap pl ied t o m ai n blo cks fo r 10 00 cyc le s maxi mu m an d to p a rame t er bl o cks for 25 00 cyc le s.

VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin

at 12 V ma y red uce bl oc k cyc ling capa bilit y.

VCC Power DEVICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device o perations at invalid VCC

v oltages should not be attempted.

VCCQ Power OUTPUT POWER SUPPLY: Enables a ll ou tputs to be driven at VCCQ. This input may be tied directly

to VCC.

VSS Power GROUND: Pins for all internal device circuitry must be connected to system ground.

VSSQ Power OUTPUT GROUND: Pr ov ides gr o un d to al l o ut put s whi ch ar e dri ven by VC CQ . Th is si gn al may be t ie d

directly to VSS.

DU — DO NOT USE: D o not use this pin. This pin sh ould not be c onne c ted to any p ower supplies, signals or

other pins and mu st be floated.

NC — NO CONNECT: No i nternal c onne c tion; can be driven or float ed.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 21

Table 6. Signal Descriptions - QUAD+ Package (Sheet 1 of 3)

Symbol Type Description

A[MAX:MIN] Input

ADDRESS INPUTS: Inputs for all die addresses during read an d writ e operations.

•256-Mbit Die : AMAX= A23

•128-Mbit Die : AMAX = A22

•64-Mbit Die : AMAX = A21

•32-Mbit Die : AMAX = A20

•8-Mbit Die : AMAX = A18

A0 is the lowest-order 16-b it wide address.

A[25:24] denote high-order addresses reserved for fu ture device densities.

D[15:0] Input/

Output

DATA INPUTS/OUTPUT S: Inputs da ta and comma nds du ring write cycles, outputs data during rea d

cy cles. Data signals float when the device or its outputs are deselected. Data are intern ally latched

during writes on the flash device.

F[3:1]-CE# Input

FLASH CHIP ENABLE: Low-true inpu t.

F[3:1]-CE# low selects t he associated f lash memory die. When asserted, flash internal control logi c,

input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is

deselected, power is reduced to standby levels, data and WA IT outputs are placed in high-Z state.

F1-CE# selects or deselects flash die #1 ; F2-CE# selects or deselects flash die #2 an d is RFU on

combin ations with only one flash di e. F3-CE# selects or deselects flas h die #3 and is RFU on st acke d

combin atio ns with only on e or tw o flas h die s .

S-CS1#

S-CS2 Input

SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 resp ectivel y ).

When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input buffers,

decoders, and sense amplifiers are active. When either/both SRAM Chip Select signals are

deasserted, the SRAM is deselected and its pow er is reduced to standby level s .

S-CS1# and S-CS2 are ava ila ble on s tac ked co mbinations wi th SR AM die and are RF U on stacked

combinations without SRAM die.

P[2:1]-CS# Input

PSRAM CHIP SELECT: Low-true in put.

When asserted, PSRAM internal control logic, input buf fers, decoders, and sense amplifiers are active.

When deasserted, the PSRAM is deselected and its power is reduced to standb y levels.

P1- CS# selects PSR AM die #1 and is available only on st acked combinations wit h PSRAM die. This

ball is an RFU on stacked combinations without PSRAM. P2-CS# selects PSRAM die #2 and is

avail able only on stacked co mbin ations with two PSRAM dies. This ball is an RFU on stacked

combin ations without PSRAM or wi th a single PS RAM.

F[2:1]-OE# Input

FLASH OUTPUT ENABLE: Low-true input.

Fx-OE# low enables the selected flash’s output buffers. F[2: 1]-OE# high disabl es th e selected flas h’s

output buffers, placing them in High-Z.

F1-OE# controls the outputs of flas h die # 1; F2-OE# controls the outputs of flash die #2 and flas h die

#3. F2-OE# is available on stacked combinations with two or three flash die and is RFU on stacked

combin atio ns with only one flas h die .

R-OE# Input

RAM OUTPUT ENABLE: Low-true input.

R-OE# low enables the selected RAM’s output buffers. R-OE# high disables the RAM output buffers,

and places the selected RAM outputs in High-Z.

R- O E# is available on stacked co mbinations wi th PSRAM or SR AM die, and is an RFU on flas h-only

sta c ke d co mbin atio ns .

F-WE# Input F LASH WRITE ENABLE: Low-true input.

F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of F-

WE#.

R-WE# Input

RAM WRITE ENABLE: Low-true input.

R-WE # co nt r ol s wr ite s to t h e se lec ted R AM die.

R-WE# is available on stacked combinations with PSRAM or SRAM die and is an RFU on flash-only

sta c ke d co mbin atio ns .

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

22 Order Numbe r: 290701 , Revision: 015

CLK Input

CLOCK: Synchronizes the flash d ie with the s y stem bus cl ock in s y nchrono us read mode and

increments th e int ernal address generator.

During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next

v alid CLK ed ge with ADV# low, whichever occurs first.

In asynchr onou s mode, addresse s are latched on the rising edge ADV#, or ar e continuously flow-

through when ADV# is kept as serted.

WAIT Output

WAIT: Out p ut si gn al .

Indicates invalid data during synchronous array or non-array flash reads. Read Configuration Register

bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is

deasserted; WAIT is not gated by F-OE#.

• In synchronous array or no n-arr ay flash read m odes, WAIT indicates invalid d ata when asserted

and vali d data when deasserted.

• In asynchronous flash pa ge read, and all flas h wri te mo des, WAIT is asserted.

F-WP# Input

FLASH WRITE PROTECT: Low-true input.

F-WP# enables/disables the lock-down protection mechanism of the selected flash die.

• F -WP # low enabl e s t he lo ck - down me ch anism w her e l oc ke d dow n bloc ks c an no t be un lo cke d wi t h

softw are command s.

• F-WP# high disables the lock-do wn mechanism, allo wing locked down blocks to be unlocke d with

softw are command s.

ADV# Input

ADDRESS VALID: Low-true input.

During synchronous flash read operations, addresses are latched on the rising edge of ADV#, or on

the next valid CLK edge with ADV# low, whichever occurs first.

In asynchronous flash read operations, addresses are latched on the rising edge of ADV#, or are

c ontinuously flow- through wh en ADV# is ke pt ass erted.

R-UB#

R-LB# Input

RAM UPPER / LOWER BYTE ENABLES: Low -true input.

Durin g RAM read an d write cycles, R-UB# low en able s the RA M hig h order bytes on D [15:8], and R-

LB# low enables the RAM low-ord er bytes on D[ 7:0].

R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die and are RFU on

flas h-only stacke d comb inations.

F-RST# Input FLASH RESET: Low-true input.

F-RST# low ini tialize s flash in ternal circuitry and disables flash oper atio ns. F-RST# high enables flash

operation. Exit from reset places the flas h in asynchr onous read ar ray m ode.

P-Mode,

P-CRE Input

P-Mode (PSRAM Mode): Low-true input.

P-Mode is used t o program the Configuration Register, and enter/exit Low Power Mode of PSRAM die.

P-Mode is available on stacked combinations with asynchronous-only PSRAM die.

P-CRE (PSRAM Configuration Register Enable): High-true input.

P-CRE is high, write operations load the refresh control register or bus control register.

P-CRE is applicable only on combinations with synchronous PSRAM die.

P- Mode , P-CR E i s an RFU on stacked comb inations witho ut PSRA M die .

F-VPP,

F-VPEN Power

FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this ball enables flash program/

eras e operations.

Flash memory array contents cannot be al tered when F-VPP(F-VPEN) < VPPLK (VPENLK). Erase /

pr og ram o pe rat io ns at inva li d F -VPP (F-VPEN) vo lt a ges s hou l d no t be at te mpte d. Ref e r to flas h d isc r ete

product da tasheet for additional de tails.

F-VPEN (Er ase/Pr ogram/Block Lock Enables) is not available for L18/L30 SCSP product s.

F[2:1]-VCC Power

FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies

power to the core logic of flash die #2 and flash die #3. Wr ite operations are inhibited when F-VCC <

VLKO. Devic e oper a ti ons at in va lid F- VCC vo lta g e s sh ou ld not be attemp ted.

F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked

c ombi nations with only on e flash di e.

Table 6. Signal Descriptions - Q UAD+ Packag e (Sheet 2 of 3)

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 23

S-VCC Power SRAM POWER SUPPLY: Supplies power for SRAM operations.

S-VCC is available on stacked c ombin ations with SRAM die, and is RFU on stacke d combi nations

without SRAM die.

P-VCC Power PSRAM POWER SU PPLY: Supplies power for PSRAM operations.

P-VCC is available on stacked c ombin ations with PSRAM die, and is RFU on stacked combinations

without PSRAM die.

VCCQ Power DEVICE I/O POWER: Supply power for th e devi ce in put and output buffers.

VSS Power DEVICE GROUND: Connect to system ground. Do not float any VSS connection.

RFU — RESERVED for FUTURE USE: Reserved for future device functionality/ enhancements. Contact Intel

regarding the use of ball s desi gnat ed RFU.

DU — DO NOT USE: Do not connect to any other signal, or power s upply ; mus t be left floating.

Table 6. Signal Descriptions - QUAD+ Package (Sheet 3 of 3)

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

24 Order Numbe r: 290701 , Revision: 015

5. 0 M a x im um Ratings and Ope r a ting Conditions

5.1 Absolute Maximum Ratings

Warning: S tressing the devic e beyo nd the “Abs olut e Max im um Rati ngs ” may ca use pe rma nen t damage.

These ar e stre ss r at in g s only.

Notice: This datasheet contain s inf ormation on products in the d esign phase of

development. The information here is subject to change without notice. Do not final-

ize a design with this information.

Table 7. Absolute Maximum Ratings

Parameter Maximum Rating Notes

Tem p eratu r e un de r Bias –40 °C to +8 5 °C

Storag e Te m pe rature –65 °C to +1 25 °C

Voltage on Any Pin (except VCC, VCCQ, VPP) –0.5 V to +2.4 5 V 1,2

VPP Voltage –0.2 V to +13.1 V 1,3,4

VCC and VCCQ Voltage –0.2 V to +2.45 V 1,2

Out put Short Circuit Current 100 mA 5

Notes:

1. Specified voltages ar e with respect to VSS.

2. During transitions, this level may undershoot to

(130 nm) –2.0 V for periods < 20 ns and overshoot to VCCQ +2.0 V for periods < 20 ns

(9 0 nm ) –1.0 V for periods < 20 ns and o v ershoot to VCCQ +1.0 V for periods < 20 ns.

3. Maxim um DC vo ltage on VPP may overshoot to +14.6 V for periods < 20 ns.

4. VPP program vol ta ge is normally VPP1. VPP can be 12 V ± 0.6 V for 1000 c ycles on the main

blocks and 2500 cycles on the parameter blocks during program/erase.

5. Outpu t shorted for no more than one second. No more than one output shor ted at a time.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 25

5.2 Operating Conditions

Warning: Ope ration beyon d the “Opera ting Condi tions” i s not reco mmended, an d extended e xposure be yond

the “Operating Conditio ns” ma y af fec t de vic e relia bi lit y.

Ta ble 8. Extended Tem peratu re Op erati on

Symbol Parameter1Min Nom Max Unit Note

TAOperating Temp erature –40 25 85 °C

VCC Supply Voltage 1.7 1.8 1 .95

I/O Supply Voltage (90 nm) 1.7 1.8 1.95 3

I/O Supply Voltage (130 nm) 1.70 1.8 2.24 3

Extended I/O Sup ply Voltage (130 nm) 1.35 1 .5 1.8 4

VPP1 VPP Voltage Supply (Logic Level) 0.90 1.80 1.95 2

Programming VPP 11.4 12.0 12.6 2

tPPH Maximum VPP Hours VPP = 12 V - - 80 Hours 2

Block

Erase

Cycles

Main and Parameter Blocks VPP ≤ VCC 100,000 - -

Cycles

Main Blocks VPP = 12 V - - 1000 2

Parameter Blocks VPP = 12 V - - 2500 2

Notes:

1. See Section 6.1, “DC Current Characteristics” on page 26 and Section 6. 2, “D C Voltage Characteristics” on pag e 28 for

specific voltage-range specifications.

2. VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks at extended

tempe ratur es and 2500 cycles on parameter blocks at extended temperatures.

3. Contact your Intel field representative for VCC/VCCQ operations down to 1.65 V.

4. See the tables in Section 5.0, “Maximum Ratings and Operating Conditions” on page 24 an d in Section 7.0, “AC

Characteristics” on page 29 for operating characteristics wit hin the Extended VCCQ voltag e range.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

26 Order Numbe r: 290701 , Revision: 015

6.0 Electrical Specifications

6.1 DC Current Characteristics

Table 9. DC Current Characteristics (Sheet 1 of 2)

Symbol Parameter (1)

VCCQ= 1.35 V

– 1.8 V (2) VCCQ= 1.8 V

Unit Test Condition Note32/64/128-

Mbit 32/64-Mbit 128-Mbit

Typ Max Typ Max Typ Max

ILI Input Load - TBD - ±1 - ±1 µA VCC = VCCMax

VCCQ = VCCQMax

VIN = VCCQ or GN D 8

ILO Output

Leakage D[15:0] - TBD - ±1 - ±1 µA VCC = VCCMax

VCCQ = VCCQMax

VIN = VCCQ or GN D

130 nm

ICCS VCC Standby

TBDTBD850870

µA

VCC = VCCMax

VCCQ = VCCQMax

CE# = VCC

RST# =VCCQ 9

90 nm

ICCS - - 22 50 - -

130 nm

ICCAPS

APS

TBDTBD850870

µA

VCC = VCCMax

VCCQ = VCCQMax

CE# = VSSQ

RST# =VCCQ

All other inputs =V CCQ or

VSSQ

90 nm

ICCAPS - - 22 50 - -

ICCR Average

VCC

Read

Asynchronous

Page Mode

f=13 MHz TBDTBD3647mA4 Word Read 3

Synchronous

CLK = 40 MHz

TBDTBD613613mABurst length = 4

TBDTBD814814mABurst length = 8

TBD TBD 10 18 11 19 mA Burst length =16

TBD TBD 11 20 11 20 mA Bur s t le ngth = Continuous

Synchronous

CLK = 54 MHz

TBDTBD716716mABurst length = 4

TBD TBD 10 18 10 18 mA Burst le ngth = 8

TBD TBD 12 22 12 22 mA Burst le ngth = 16

TBD TBD 13 25 13 25 mA Burs t lengt h = Continuous

ICCR Average

VCC

Read

Synchronous

CLK = 66 MHz

TBD TBD 8 17 - - mA B urst length = 4

3, 4

TBD TBD 11 20 - - mA Burst length = 8

TBD TBD 14 25 - - mA Burst leng th = 16

TBD TBD 16 30 - - mA Burst leng th = Continuous

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 27

ICCW VCC Program TBD TBD 18 40 18 40 mA VPP = VPP1, Prog ram in

Progress 4,5,6

TBD TBD 8 15 8 15 mA VPP = VPP2, Prog ram in

Progress

ICCE VCC Block Erase

TBD TBD 18 40 18 40 mA VPP = VPP1, Block Erase in

Progress 4,5,6

TBD TBD 8 15 8 15 mA VPP = VPP2, Block Erase in

Progress

130nm

ICCWS VCC Program Suspend TBD TBD 8 50 5 25 µA CE# = VCC, Program Sus-

pended 7

90nm

ICCWS TBD TBD 22 50 - - µA

130nm

ICCES VCC Erase Suspend TBD TBD 8 50 5 25 µA CE# = VCC, Eras e Sus-

pended 7

90nm

ICCWS TBD TBD 22 50 - - µA

IPPS

(IPPWS,

IPPES)

VPP Standby

VPP Program Suspend

VPP Erase Susp end TBD TBD 0.2 5 0.2 5 µA VPP <VCC 4

IPPR VPP Read TBD TBD 2 15 2 15 µA VPP ≤ VCC

IPPW VPP Program TBD TBD 0.05 0.10 0.05 0.10 mA

VPP = VPP1, Program in

Progress 5

TBD TBD 8 22 16 37 VPP = VPP2, Progra m in

Progress

IPPE VPP Erase TBD TBD 0.05 0.10 0.05 0.10 mA

VPP = VPP1, Erase in

Progress 5

TBD TBD 8 22 8 22 VPP = VPP2, Erase in

Progress

Notes:

1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25° C.

2. VCCQ = 1.35 V - 1.8 V is av ailable on 130 nm products only.

3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ

specification for details.

4. Sampled , not 100% t est ed.

5. VCC read + pro gra m current is the su m of VCC r ea d an d VCC program currents.

6. VCC read + erase current is the sum of VCC read and VCC erase currents.

7. ICCES is specified with device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.

8. If VIN>VCC the input load current increases to 10 µA max.

9. ICCS is the average current meas ured over any 5 ms time interval 5 μs after a CE# de-asserti on.

10. Refer to section Sec tio n 8.2, “ Autom atic Pow er Sav i ngs (A PS )” on page 51 for ICCAPS me as ureme nt de tail s.

Tabl e 9. DC Curr ent Chara cteristics (Sheet 2 of 2)

Symbol Parameter (1)

VCCQ= 1.35 V

– 1.8 V (2) VCCQ= 1.8 V

Un it Test Cond ition N ote32/64/128-

Mbit 32/64-Mbit 128-Mbit

Typ Max Typ Max Typ Max

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

28 Order Numbe r: 290701 , Revision: 015

6.2 DC Voltage Characteristics

Table 10. DC Voltage Characteristics

Symbol Parameter

VCCQ= 1.35 V –

1.8 V (1) VCCQ= 1.8 V

Unit Test Condition Note

32/64/128-Mbit 32/64-Mbit 128-Mbit

Min Max Min Max Min Max

VIL Input Low 0 0.2 0 0.4 0 0.4 V 2

VIH Inpu t High VCCQ

– 0.2 VCCQ VCCQ

– 0.4 VCCQ VCCQ

– 0.4 VCCQ V2

VOL Output Low - 0.1 - 0.1 - 0.1 V VCC = VCCMin

VCCQ = VCCQMin

IOL = 100 µA

VOH Output High VCCQ

– 0.1 -VCCQ

– 0.1 -V

VCC = VCCMin

VCCQ = VCCQMin

IOH = –100 µA

VPPLK VPP Lo ck- Ou t - 0.4 - 0.4 - 0 .4 V 3

VLKO

VCC Lo ck

(130nm) 1.0 - 1.0 - 1.0 - V 4

VCC Lock

(90nm) 0.7 - 0.7 - - - V

VILKOQ VCCQ Lock TBD - 0.9 - 0.9 - V

Notes:

1. VCCQ = 1.35 V - 1.8V is available on 130 nm devices only.

2. VIL can undershoot to –1.0 V for durations of 2 ns or less and VIH can ov er sh oot to VCCQ+1.0 V for durations of

2 ns or less.

3. VPP <= VPPLK inhibits erase and program operations. Don’t use VPPL and VPPH outside their valid ranges.

4. Bl ock er a se s, prog r ammin g a nd l oc k- bit con f igur a tion s ar e in hibi t ed when V CC<VLKO, and not guaranteed in the

range between VLKOMIN an d VCCMIN, and above VCCMAX.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 29

7.0 AC Characteristics

Table 11. Read Operations - 90 nm Lithography (Sheet 1 of 2)

Symbol

Parameter (1,2)

VCCQ=

1.70 V – 1.95 V Unit Notes

Min Max

Asynchronous Specifi cations

R1 tAVAV Read Cycle Time 60 - ns 7,8

R2 tAVQV Address to Output Valid - 60 ns 7,8

R3 tELQV CE# Low to Output Valid - 60 ns 7,8

R4 tGLQV OE# Low to Output Valid - 20 ns 4

R5 tPHQV RST# High to Output Valid - 150 ns

R6 tELQX CE# Low to Output Low-Z 0 - ns 5

R7 tGLQX OE# Low to Output Low-Z 0 - ns 4,5

R8 tEHQZ CE# High to Output High-Z - 14 ns 5

R9 tGHQZ OE# High to Output High-Z - 14 ns 4,5

R10 tOH CE# (OE#) High to Output Low-Z 0 - ns 4,5

R11 tEHEL CE# Pulse Width High 14 - ns 6

R12 tELTV CE# Low to WA IT Val id - 11 ns 6

R13 tEHTZ CE# High to WAIT High-Z - 11 ns 5,6

Latchi ng Sp ecif ic at ions

R101 tAVVH Address Setup to ADV# High 7 - ns

R102 tELVH CE# Low to ADV# High 10 - ns

R103 tVLQV ADV# Low to Outp ut Valid - 6 0 ns 7,8

R104 tVLVH A DV# Pulse Width Low 7 - ns

R105 tVHVL ADV# Pulse Wid th High 7 - ns

R106 tVHAX Address Hold from ADV# High 7 - ns 3

R108 tAPA Page Address Access T ime - 20 ns

Clock Sp ec ifi c ations

R200 fCLK CLK Frequency - 66 MHz

R201 tCLK CLK Period 15 - ns

R202 tCH/L CLK High or Low Time 3.5 - ns

R203 tCHCL CLK Fall or Rise Time - 3 ns

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

30 Order Numbe r: 290701 , Revision: 015

1. See Figure 20, “AC Input/Output Reference Waveform” on page 49 for timing meas urements an d

maximum allowable input slew rate.

2. AC sp ecificat ion s assume the data bus voltage is less than or equal to VCCQ when a read operatio n is

initiated.

3. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing speci fic ation is

satisfied first.

4. OE# m ay be de laye d by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV.

5. Sample d, not 100 % t es te d.

6. Applies only to subs equ ent sy nchronous reads.

7. Duri ng the initi al ac c ess of a sy nc h r on ou s bu r st read, data fro m the fir s t wo rd ma y begin to be driv en

onto the data bus as early as the first clock edge after tAVQV.

8. All the precedin g specifications appl y to all densities.

Synchronous Specifications

R301 tAVCH Address Valid Setup to CLK 7 - ns

R302 tVLCH ADV# Low Setup to CLK 7 - ns

R303 tELCH CE# Low Setup to CLK 7 - ns

R304 tCHQV CLK to Output Valid - 11 ns 8

R305 tCHQX Outp ut Hold fr o m CLK 3 - ns

R306 tCHAX Address Hol d from CLK 7 - ns 3

R307 tCHTV CLK to WAIT Valid - 11 ns 8

Table 11. Read Operations - 90 nm Lithography (Sheet 2 of 2)

Symbol

Parameter (1,2)

VCCQ=

1.70 V – 1.95 V Unit Notes

Min Max

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 31

Table 12. Read Operations - 130 nm Lithography (Sheet 1 of 2)

Symbol

Parame ter (1,2)

VCCQ=

1.35 V – 1.8 V VCCQ=

1.70 V – 2.24 V

Unit Notes

-65 -85 -60 -80

Min Max Min Max Min Max Min Max

Asynchronous Specifi cations

R1 tAVAV Read Cycle Time 65 - 85 - 60 - 80 - ns 7,8

R2 tAVQV Ad dres s to O ut p ut Valid - 65 - 85 - 60 - 8 0 ns 7 ,8

R3 tELQV CE# Low to O utp ut Val id - 65 - 85 - 60 - 8 0 ns 7 ,8

R4 tGLQV OE# Low to Output Valid - 25 - 30 - 20 - 25 ns 4

R5 tPHQV RST# High to Output Valid - 1 50 - 150 - 150 - 150 n s

R6 tELQX CE# L ow to Output Low-Z 0 - 0 0 - 0 ns 5

R7 tGLQX OE# Low to Output Low-Z 0 - 0 0 - 0 - ns 4,5

R8 tEHQZ CE# High to Output High-Z - 17 - 20 - 14 - 17 ns 5

R9 tGHQZ OE# High to Output High-Z - 14 - 14 - 14 - 14 ns 4,5

R10 tOH CE# (OE#) High to Output Low-Z 0 - 0 0 - 0 - ns 4,5

R11 tEHEL CE # Pulse Wid th High - 14 - 14 - 14 - 14 ns 6

R12 tELTV CE# Low to WAIT Valid - 14 - 20 - 11 - 14 ns 5,6

R13 tEHTZ CE# High to WAIT High-Z 14 - 20 - 14 - 14 - ns 6

Latching Specifications

R101 tAVVH Address Setup to ADV# High 7 - 7 - 7 - 7 - ns

R102 tELVH CE# Low to ADV# High 10 - 10 - 10 - 10 - ns

R103 tVLQV ADV# Low to Output Valid - 65 - 85 - 60 - 80 ns 7,8

R104 tVLVH ADV# Pulse Widt h Low 7 - 7 - 7 - 7 - ns

R105 tVHVL ADV# Puls e Width High 7 - 7 - 7 - 7 - ns

R106 tVHAX Address Hold from ADV# High 7 - 7 - 7 - 7 - ns 3

R108 tAPA Page Address Access Time - 25 - 30 - 20 - 25 ns

Clock Sp ec ifi c at i on s

R200 fCLK CLK Frequency - 54 - 40 - 66 - 54 MHz

R201 tCLK CLK Period 18.5 - 25 - 15 - 18.5 - ns

R202 tCH/L CLK High or Low Time 4.5 - 9.5 - 3.5 - 4.5 - ns

R203 tCHCL CLK Fall or Rise Time -3-3-3-3ns

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

32 Order Numbe r: 290701 , Revision: 015

Note: For all numb er e d no te r ef erenc es in thi s table, re fer to the notes in Tabl e 11, “Read Operation s - 90 nm

Lithography” on page 29.

S yn chro nou s Spec ific ati ons

R301 tAVCH Address Valid Setup to CLK 7 - 7 - 7 - 7 - ns

R302 tVLCH ADV# Low Setup to C LK 7 - 7 - 7 - 7 - ns

R303 tELCH CE# Low Setup to CLK 7 - 7 - 7 - 7 - ns

R304 tCHQV CLK to Output Valid - 14 - 20 - 11 - 14 ns 8

R305 tCHQX Output Hold from CLK 3 - 3 - 3 - 3 - ns

R306 tCHAX Addr ess Hold fr om CLK 7 - 7 - 7 - 7 - ns 3

R307 tCHTV CLK to WAIT Valid - 14 - 20 - 11 - 14 ns 8

Table 12. Read Op eration s - 130 nm Lithogra phy (Sheet 2 of 2)

Symbol

Parameter (1,2)

VCCQ=

1.35 V – 1.8 V VCCQ=

1.70 V – 2.24 V

Unit Notes

-65 -85 -60 -80

MinMaxMinMaxMinMaxMinMax

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 33

Notes:

1. WAIT shown asserted (RCR[10]=0)

2. ADV# assumed to be driven to VIL in this waveform

Figure 6. Asynchronous Read Operation W avefo rm

Valid

Address

High Z

Valid

Output

R10

Address [A]

CE# [E]

OE# [G]

WE# [W]

Data [D/Q]

RST# [P]

High Z

WAIT [T]

High Z

Note 1

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

34 Order Numbe r: 290701 , Revision: 015

Figure 7. Latched Asynchrono us Read Operatio n Waveform

High Z Valid

Output

Valid

Address

Data [Q]

WE# [W]

OE# [G]

CE# [E]

A[MAX:2] [A]

ADV# [V]

RST# [P]

R102

R104

R10

R103

R101

R105 R106

A[1:0] [A]

Valid

Address

Valid

Address

Valid

Address

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 35

Note: WA IT shown asserted (RCR[10] = 0).

Figure 8. P age-Mod e Read Op erati on Waveform

R105

High Z Valid

Output Valid

Output

Valid

Address

Valid

Address Valid

Address

R102

R104

ADV# [V]

CE # [E]

OE# [G]

WE# [W]

Data [D/Q]

RST# [P]

A[MAX:2 ] [A]

A[1:0] [A]

R101

R106

R103

R108

R10R5

High Z

WAIT [T]

High Z

Note 1

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

36 Order Numbe r: 290701 , Revision: 015

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 86 describes how to in sert clock cycles during the initial

access.

2. W A I T (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data.

3. This waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a CE# de-

assertion after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted (low)

WAIT signal w ould have remained asserted (low) as long as CE# is asserted (lo w).

Figure 9. Single Synchrono us Read -Array Op erati on Waveform

R12

R13

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 37

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 86 describes how to insert clock cycles during the initial

access.

2. WAIT (s hown asserted; RCR[10] = 0) can be configured to assert either during, or one data cycle be fore, valid data.

Figure 10. S ynch ro nous 4-Word Burst Read Operation Waveform

R12

R11

R13

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

38 Order Numbe r: 290701 , Revision: 015

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 86 describes how to in sert clock cycles during the initial

access.

2. W A I T (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data

(assumed wait delay of two clocks, for example).

Figure 11 . WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform

R12

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 39

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 86 describes how to insert clock cycles during the initial

access.

2. WAIT shown asserted (RCR[10]=0).

Figure 12. WAIT Sign al in Synchron ou s Non-Re ad Array Op erati on Wave form

R12

R13

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

40 Order Numbe r: 290701 , Revision: 015

Note: Du ring Burst Suspend, Cl ock signal can be held high or low.

Figure 13. Burst S uspend

Q0 Q1 Q1 Q2

R304R304

R13

R12

R9R4R9R4

R8R3

R106

R101

R105R105

R1R1

R305R305R305R304

CLK

Addre ss [A ]

ADV#

CE # [ E]

OE# [G]

WAIT [T]

WE# [W]

ATA [D/Q]

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 41

7.1 AC Write Characteristics

Ta ble 13. AC Writ e Chara cteristics - 90 nm Lithography

# Sym Parameter (1,2)

VCCQ =

1.70 V – 1.95 V Unit Notes

Min Max

W1 tPHWL (tPHEL) RST# High Recovery to WE# (CE#) Low 150 - ns 3

W2 tELWL (tWLEL) CE# (WE#) Setup to WE# (CE#) Low 0 - ns

W3 tWLWH (tELEH) WE# (CE#) Write Pulse Width Low 40 - ns 4

W4 tDVWH (tDVEH) Data Setup to WE# (CE#) High 40 - ns

W5 tAVWH (tAVEH) Address Setup to WE# (CE#) High 40 - ns

W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 - ns

W7 tWHDX (tEHDX) Da ta Hold from WE # (CE #) High 0 - ns

W8 tWHAX (tEHAX) A ddress Hold from WE# (CE#) High 0 - ns

W9 tWHWL (tEHEL) WE# (CE#) Pulse Width High 20 - ns 5,6,7

W10 tVPWH (tVPEH) VPP Setup to WE# (CE#) High 200 - ns 3

W11 tQVVL VPP Hold from Va lid SR D 0 - ns 3 ,8

W12 tQVBL WP# Hold from Valid SRD 0 - ns 3,8

W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High 200 - ns 3

W14 tWHGL (tEHGL) Write Recovery before Read 0 - ns

W16 tWHQV WE# High to Valid Data tAVQV

+20 -ns3,6,10

W18 tWHAV WE# High to Address Valid 0 - ns 3,9,10

W19 tWHCV WE# High to CLK Valid 12 - ns 3,10

W20 tWHVH WE# High to ADV# High 12 - ns 3,10

W21 tVHWL ADV# High to WE# Low <21 ns 11

W22 tCHWL CLK to WE# Low <21 ns 11

W27 tWHEL WE# High to CE# Low 0

W28 tWHVL WE# High to ADV# Low 0

Notes:

1. Write t imin g characteristics during erase suspend are the same as during w rite-only operat ions.

2. A write operation can be terminated with either CE# or WE#.

3. Sampled , not 100% t est ed.

4. Write puls e width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or

WE# high (whiche v er occurs first). Hence, tWLWH = t ELEH = tWLEH = tELWH.

5. Write puls e width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE#

low (whichever is last). Hence, tWLWH = tEHEL = tWHEL = tEHWL.

6. Syste m de signe r s shoul d t ak e this into acco un t and may inse rt a so f twa re No- Op instr u ctio n to delay the firs t

read after issuing a command.

7. For commands other than resume commands.

8. VPP should be held at VPP1 or VPP2 until block erase or program success is determined.

9. A p pli ca b l e du rin g as ync hr o no us reads follow in g a wr ite .

10. tWHCH/L OR tWHVH must be me t wh en tra ns iti on in g fr om a wr ite cy cle to a syn ch ron ou s bu rst r ead. t WHCH/L and

tWHVH both refer to the address latching ev ent (either the ri sing/falling clock edge o r the rising ADV# edge,

whichever occurs first).

11. The specifications tVHWL and tCHWL can be ignored if there is no cl ock to ggli ng during the wr ite bus cyc le.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

42 Order Numbe r: 290701 , Revision: 015

Table 14. AC Write Characteristics - 130 nm Lithography

# Sym Parameter (1,2)

VCCQ =

1.35 V – 1.8 V VCCQ =

1. 70 V – 2.24 V

Unit Notes

-65 -85 -60 -80

Min Max Min Max Min Max Min Max

W1 tPHWL (tPHEL)RST# High Recovery to WE#

(CE#) Low 150 - 150 - 150 - 150 - ns 3

W2 tELWL (tWLEL)CE# (WE#) Setup to WE# (CE#)

Low 0-0-0-0-ns

W3 tWLWH (tELEH)WE# (CE#) Write Pulse Width

Low 50 - 60 - 40 - 60 - ns 4

W4 tDVWH (tDVEH) Data Setup to W E# (C E#) High 50 - 60 - 40 - 60 - ns

W5 tAVWH (tAVEH)Address Setup to WE# (CE#)

High 50 - 60 - 40 - 60 - ns

W6 tWHEH

(tEHWH)CE# (WE#) Hold from WE#

(CE#) High 0-0-0-0-ns

W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High 0 - 0 - 0 - 0 - ns

W8 tWHAX (tEHAX)Address Hold fr om WE# (CE #)

High 0-0-0-0-ns

W9 tWHWL (tEHEL) W E# ( C E# ) Puls e Width H igh 2 0 - 25 - 2 0 - 2 5 - n s 5,6 ,7

W10 tVPWH (tVPEH) VPP S etup to WE# ( CE#) High 200 - 200 - 200 - 200 - ns 3

W11 tQVVL VPP Hold from Valid SRD 0 - 0 - 0 - 0 - ns 3,8

W12 tQVBL WP# Hold from Valid SRD 0-0-0-0-ns3,8

W13 tBHWH (tBHEH) WP# Setup to WE# (C E#) High 200 - 200 - 200 - 200 - ns 3

W14 tWHGL (tEHGL)Write Recovery before Read 0-0-0 - 0-ns

W16 tWHQV W E# H ig h to Valid Da ta tAVQV

+ 25 -tAVQV

+ 55 -tAVQV

+20 -tAVQV

+50 - ns 3,6,10

W18 tWHAV WE# High to Address Valid 0-0-0-0-ns3,9,10

W19 tWHCV WE# High to CLK Valid 16 - 20 - 12 - 20 - ns 3 ,10

W20 tWHVH WE# High to ADV# High 16 - 20 - 12 - 20 - ns 3,10

Notes: For all numbered note references in this table, refer to the notes in Table 13, “AC Write Characteristics - 90 nm

Lithography” on page 41.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 43

Notes:

1. VCC power-up an d standby.

2. Write Program or Erase Setup command.

3. Write valid address and data (for program) or Erase Confirm command.

4. Automated program/erase delay.

5. Read Status Register data (SRD) to determine program/erase operation completion.

6. OE# and CE# mu st be asserted and WE# must be deasse rted for read operat ions.

7. CLK is ignored. (but may be kept active/toggling)

Figure 14. Write Operati on s Waveform

Note 1 Note 2 Note 3 Note 4 Note 5

Address [A]

Valid

Address Valid

Address

CE# (WE #) [E(W)]

Note 6

OE# [ G]

WE# (CE#) [W(E) ]

RST# [P]

W11

W12

R105

VPP [V]

PPH

PPLK

WP# [B]

Data [Q]

Data In Valid

SRD

ADV# [V]

W16W1

W10

W13

W14

R101

R106

Data In

Valid

Address

Note 6

R104

W5 W18

W19

W20

CLK [C]

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

44 Order Numbe r: 290701 , Revision: 015

Figure 15. Asynchrono us Read to Write Op erati on Waveform

Figure 16. Asynchrono us Write to Read Operation

Q D

W4R10

W3W3

R9R4

R8R3

W8W5

R2 R1

ddres s [ A]

CE# [E}

OE# [ G]

WE# [ W]

Data [D/Q]

RST# [P]

D Q

R2W7

W14

W18W3W3

R10W6W2

R1R1W8W5

ddress [A]

CE # [ E }

WE# [ W]

OE# [G]

Data [D/Q ]

RST# [ P ]

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 45

Figure 17. S ynch ro nous Read to Write Operation

Latency Count

Q D D

R13

R305

R304

R307R12

W15

W19

W9W3W3

W6R11R11

R303

W20

R104R104R106

R102

R105R105

W18

R101 R2

R306

R302

R301

CL K [C]

d d re ss [A]

ADV# [V]

CE# [E]

OE# [ G]

WE#

WAIT [T]

Data [D/Q]

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

46 Order Numbe r: 290701 , Revision: 015

Figure 18. Synchron ou s Write To Read Operation

Latenc y C ount

D Q Q

R304

R305

R304

R307R12

W18

W19W3W3

R11 R303

R11

W20 R104R106

R104

R306W8W5

R302

R301 R2

CLK

ddre ss [ A]

ADV#

CE# [ E }

WE# [W ]

OE# [G ]

WAIT [T ]

Data [D/Q]

RST # [P]

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 47

7.2 Erase and Progr am Times

Ta ble 15. Erase an d Progr am Times

Operation Symbol Parameter Description (1) Notes VPP1 VPP2 Unit

Typ Max Typ Max

Erasing and Suspending

Erase Time W500 t ER S / PB 4-K w o rd P ara m eter B lo ck 2,3 0. 3 2. 5 0. 25 2.5 s

W501 tERS/MB 32-Kword Main Block 2,3 0.7 4 0.4 4 s

Suspend

Latency W600 tSUSP/P Pro gram Suspend 2 5 10 5 10 µs

W601 tSUSP/E Eras e S us p en d 2 5 2 0 5 2 0 µs

Programming

Program

Time

W200 tPROG/W Single Word 2 12 150 8 130 µs

W201 tPROG/PB 4-Kword Parameter Block 2,3 0.05 .23 0.03 0.07 s

W202 tPROG/MB 32-Kword Main Block 2,3 0.4 1.8 0.24 0.6 s

Enhanced Factory Programming (5)

Program

W400 tEFP/W Single Word 4 N/A N/A 3.1 16 µs

W401 tEFP/PB 4 -Kwo rd Paramet er B lo ck 2,3 N/ A - 15 - ms

W402 tEFP/MB 32-Kword Main Block 2,3 N/A - 120 - ms

Operation

Latency

W403 tEFP/SETUP EFP Setup - N/A - 5 µs

W404 tEFP/TRAN Program to Verify Transition N/A N/A 2.7 5.6 µs

W405 tEFP/VERIFY Verify N/A N/A 1.7 130 µs

Notes:

1. Unless noted otherwise, all parameters are measured at TA = +25 °C and no mi na l voltag es , an d the y ar e sam p led , no t

100% tested.

2. Excludes external system-level overhead.

3. Exact results may vary based on system overhead.

4. W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming

within a new word-line.

5. Some EFP performance degradation may occur if block cycling exceeds 10.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

48 Order Numbe r: 290701 , Revision: 015

7.3 Res et Spe cif ica tio ns

Table 16. Reset Specifications

# Symbol Parameter (1) Notes Min Max Unit

P1 tPLPH RST # Low to Reset during Re ad 1, 2, 3, 4 100 - ns

P2 tPLRH RST# to 1, 3, 4, 5 - µs

RS T# to Reset duri ng 1, 3, 4, 5 - µs

P3 tVCCPH VCC Power Valid to Reset 1,3,4,5,6 60 - µs

Notes:

1. Th ese specifications are val id for all product versions (pac kages and spe eds).

2. Th e device may reset if tPLPH< tPLPHMin, but this is not guaranteed.

3. Not applicable if RST# is tied to VCC.

4. Sa mple d, but not 100% teste d.

5. If RST# is tied to VCC, the device is not ready until tVCCPH occurs after when VCC ≥ VCCMin.

6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC ≥

VCCMin.

Figure 19. Reset Operations Waveforms

(

A) Reset during

read mode

(

B) Reset during

pr ogram or block erase

≤

(

C) Reset during

pr ogram or block erase

≥

RST# [P]

Abort

Complete

Abort

Complete

VCC

(

D) VC C P o wer -up to

RST# high

P1 R5

P2 R5

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 49

7.4 AC I/O Test Conditions

Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.

Worst case speed cond itio ns are when VCC = VCCMin.

Note: See Table 16 on page 48 for component values.

Figure 20. AC Inpu t/Outpu t Reference Waveform

CCQ

/2 V

CCQ

Test Points

Input Outpu

Figure 21. Transi ent Equival ent Tes ting Load Circ uit

Device

Under Test

CCQ

Out

Ta bl e 17 . Test Config urat io n Com ponent Val ues for Wors t Case Speed C ondit io ns

Test Conf i gura tion CL (pF) R1 (kΩ)R

2 (kΩ)

-- 30 13.5 13.5

-- 30 16.7 16.7

Note: CL includes jig capacitance.

Figure 22. Clock Inpu t AC Waveform

CL K [C] VIH

VIL

R203R202

R201

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

50 Order Numbe r: 290701 , Revision: 015

7.5 Device Capacitance

TA = +25 °C, f = 1 MHz

Symbol Parameter§Typ Max Unit Condition

CIN Input Capacitance 6 8 pF VIN = 0.0 V

COUT Output Capacitance 8 12 pF VOUT = 0.0 V

CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V

§Sampled, not 100% tested.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 51

8.0 Power and Reset Specifications

Intel® Wireless Flash Memory (W18) devices have a layered approach to power savings that can

significantly reduce overall system power consumption. The APS feature reduces power

consumption when the device is selecte d but id le . If CE# is deassert ed , the me mory enters its

standby mode, w he re current consumpti on is even l ower. A s serti ng RST# provides curre nt savings

simil ar to standby mode. The combi nation of th ese fe atu res ca n minim iz e memo ry pow er

consumption, and therefore, overall system power consumption.

8.1 Activ e Power

With CE# at VIL and RS T# at VIH, the device is in th e acti ve mode. Refer to Section 6.1, “DC

Curr ent Chara ct eristics” on page 26, for I CC va lu es. Wh en the device is in “a ct ive ” s ta te, it

consume s the most power from the sy stem. Minimizing devic e acti ve current therefore reduce s

syste m powe r consum ption, especiall y in bat tery-powered appl ic at ions.

8.2 Aut omatic Powe r Savings (APS)

Automa ti c Power Saving (AP S) provi des low-pow er op era ti on during a read’s active state . During

APS mode, ICCAPS is the average current measured over any 5 ms time interval 5 µs after the

followi ng eve nts happen:

•There is no internal sense activity;

•CE# is asserted;

•The address lines are quiescent, and at VSSQ or VCCQ.

OE# may be asserted during APS.

8.3 Standby Power

With CE# at VIH and the dev ice in re ad mode, t he flas h memory i s in standby mode, which dis ables

most dev ice cir cui try a nd sub stantially redu ces powe r consum ption. Output s are placed in a hi gh-

impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or

program operations, the devic e co nti nues the operati on and cons um es corresponding acti ve power

until th e operati o n is complete. I CCS is the average current measured over any 5 ms time interval 5

µs after a CE# de-as serti on.

8.4 Power-Up/Down Characteristics

The devic e i s prote ct ed agai ns t a cc identa l bl ock erasure or programming during p ower t ransitions.

Powe r supp ly seque nc ing is not requi red if VCC, VCCQ, and VPP are c onne ct ed tog et her; so it

doesn’t matter whe the r VPP or VCC powers-up first. If VCCQ and /o r V PP are not connected to the

syste m suppl y, then VCC should attain VCCMIN before applyi ng VCCQ and VPP. Device i nputs

should not be driven before supply voltage = VCCMIN. Power sup ply trans it ion s shoul d only oc cur

when RS T# is low.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

52 Order Numbe r: 290701 , Revision: 015

8.4.1 System Reset and RST#

The use of RST# during system reset is important with automated program/erase devices because

the syste m expects to read from the flash memory when it comes out of reset. If a CPU rese t occurs

without a flash memory reset , proper CP U initia lizat ion wi ll not occ ur bec ause the flash me mo ry

ma y be providi ng status information instead of array data. To a ll ow proper CP U/fl ash initi aliza ti on

at sys te m reset, conne ct RST# to th e system CPU RESET # signa l.

Syst em designers must guar d agai n st spu r io us writes w h en VCC volta ges ar e ab ove VLKO.

Bec ause both WE# and CE # must be lo w for a command wri te, driving eit her signa l to VIH inhibit s

writes to the device. The CUI architecture provides additional protection because alteration of

memory contents can only occur after successful completion of the two-s tep command sequences.

The device is also disabled unti l RS T# is brought to VIH, regardless of its con trol input states . By

holdi ng the devi ce in reset (RS T# co nne cted to sys te m PowerGood) during pow er -up/down ,

inva li d bus condit ions during power-up can be masked, providing yet anoth er level of memory

protection.

8.4.2 VCC, VPP, and RST# Transitions

The CUI latches commands issued by system soft ware and is not altere d by VPP or CE # transi tions

or WSM actions. Read-array mode is its power-up default state after exit from reset mode or after

VCC transitions above VLKO (Lockout voltage ). After co mpl eting program or block eras e

opera tions (ev en after VP P transitions below VPPLK) , t he Re ad Arr ay co mma nd m us t re set t he C UI

to read-array mode if flash memory arra y ac ces s is desired.

8.5 P ower Supply Decoupling

Whe n the devi ce is acces sed, ma ny int ernal co ndit ions change. Circu its are ena ble d to ch ar ge

pumps and switch voltages. This internal activity produces transient noise. To minimize the effect

of this tra ns ie nt noi se, device de cou pli ng ca pac it ors are required. Transient curre nt magni tudes

depend on the device outputs’ capacitive and inductive loading. Two-line control and proper

dec oupling capacitor sel ec tio n sup press es the se tra nsie nt vol ta ge pe aks. Each fla s h devi ce shou ld

have a 0.1 µF ceramic capacitor connected between each power (VCC, VCCQ, VPP), a nd ground

(VSS, VSSQ ) signal. High-freque ncy, inhe ren tly low-inductance capa ci tors s houl d be as close as

pos sible to package signals.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 53

9.0 Bus Operations Overview

This section provides an overview of device bus operations. The Intel® Wirel ess Flash M em ory

(W18) fa mi ly inclu des an on-c hip WSM to manage block era s e and program al gorit hm s. Its

Comm and User Interface (CUI) allows mi nimal proce s s or overh ea d with RAM-like interface

tim ings. Devic e comm and s are writ te n to the CUI using standard microproc ess or ti mings .

9.1 Bus Operations

Bus cycle s to/f rom th e W1 8 device conform to standard microprocessor bus operations. Table 18

summarizes the bus operations and the logic levels that must be applied to the device’s control

signal inputs .

9.1.1 Reads

Devic e read o perati ons are pe rform ed by placing the desir ed address on A[22 :0] and a s serti ng CE#

and OE#. ADV# must be low, and WE# and RST# must be high. All read operations are

indep ende nt of th e voltage level on VPP.

CE#-l ow sele cts the devi ce and enabl es its int ern al circuit s . OE#- low or WE#-low determine

whethe r DQ[ 15:0] are outputs or inputs, res pecti vel y. OE# and WE# must not be low at the same

time - inde termi nat e de vice ope rat ion will re sult.

In asynchronous-page m ode , the rising edge of ADV# can be used to latch the addre ss. If only

asynchr onous read mode is u sed, ADV# can be tied to ground. CLK is not used in asynchronous-

page mode a nd sh ould be tied high.

In synchronous-burst mo de, ADV# is used to latch th e ini ti al addre ss - either on the risi ng edge of

ADV# or the rising (or falling) edge of CLK with ADV# low, whichever occurs first. CLK is used

in synchronous-burst mode to increment the internal address counter, and to output read data on

DQ[15:0].

Each devi ce part ition ca n be placed in an y of severa l re ad sta tes:

Table 18 . B us Operations Sum mary

Bus Operation RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0] Notes

Read

Asynchronous VIH X L L L H Asserted Output

Synchronous VIH Running L L L H Driven Output 1

Burs t Suspend VIH Halted X L H H Active Output

Write VIH X L L H L Asserted Input 2

Output Disable VIH X X L H H Asserted High-Z 3

Standby VIH X X H X X High-Z High-Z 3

Reset VIL X X X X X High-Z High-Z 3,4

Notes:

1. WAIT is only valid during synch ronous array-read operations.

2 . Re fer to the Table 20, “Bus Cycle Definitions” on page 58 for valid DQ[15:0] during a write operation.

3. X = Don’t Care (H or L).

4. RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

54 Order Numbe r: 290701 , Revision: 015

•Read Array: Re tur ns flash array data fro m t he a ddr es s ed l ocation .

•Read Identifier (ID): Returns manufacturer ID and device ID codes, block lock status, and

prote ction regi ster data. Rea d Identifier informa tion can be acc essed from any 4-M bit partitio n

base address.

•CFI Query: Returns Common Flash Interface (CFI) informat ion . CFI information can be

accessed starting at 4-Mbit partition base addresses.

•Read Status Register: Ret urns S t at us Regi ster (SR) data from the address ed pa rti tio n.

The appropriate CUI command must be written to the partition in order to place it in the desired

read stat e (see Table 19, “Command Codes and Descriptions” on page 56). Non-array r ea d

opera ti ons (Rea d ID, CFI Q uery, and Read Status Regis te r) exe cute as single synchronous or

asynchronous read cy cl es. WAIT is asserted thr oughout non-arra y read opera ti ons.

9.1.2 Writes

Devic e write operations are perform ed by pl ac ing th e desi red ad dress on A[22:0] and ass erting

CE# a nd WE#. OE# and RST# mus t be high. Dat a to be w rit ten at the de sired address is placed on

DQ[15:0]. ADV# must be held lo w throughout the write cycle or it can be toggle d to latch the

addre s s. If ADV# is held low, the address and data are latc he d on the rising edge of WE#. CLK is

not us ed during w rit e ope rat ion s, and is ign ored ; it can be either fre e-ru nning or halted a t VIL or

VIH. All write ope rat ions are async hronous.

Table 19, “Command Co des and Descriptions” on page 56 shows th e av ail ab le de v ice comman ds.

Appendix A , “Write State Mach ine Stat es” on page 93 prov ide s inform at ion on m oving betwe en

different device operations by using CUI comm ands.

9.1.3 Output Disable

Whe n OE# is deas serte d, devi ce output s DQ[15 :0] are disabled and placed in a high-impedance

( High-Z) st ate.

9.1.4 Burst Suspend

The Burs t Susp end feat ure a llo ws the sy stem to tempo rari ly sus pend a syn chro nous -burst read

opera ti on. Thi s can b e usef ul if t he sys te m nee ds to acces s anot her de vi ce on the same address and

dat a bus as the flash during a burst-rea d operati on.

Syn chronous-bur st accesses c an be suspen ded during the ini ti al la te ncy (before da ta is received) or

afte r the device has output da ta . W hen a burst access is suspended, int ernal array sensing continu es

and an y previ ous ly latc he d inte rna l data is ret ai ned .

Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#

rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it

is at VIH or VIL. To resume the burst access , OE # is reassert ed and CLK is restarted. Subs eque nt

C LK ed ges r es u me the b ur st sequence where it le ft off.

Within th e dev ice, CE# gates WAIT. There fore , duri ng Burs t Sus pe nd WAIT is still driven. This

can cause contention with another device attempting to control the system’s READY signal during

a Burst Sus pend. Systems using th e Burst Sus pe nd f eature sho uld not conne ct the device’s WAIT

signal directly to the system’ s READY signal. Refer to Figure 13, “Burst Suspend” on page 40.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 55

9.1.5 Standby

De-ass ert ing CE# d esel ec ts the de vic e and places it in standby mode , s ubs ta nti al ly reducing d evi ce

power consumption. I n s ta ndby mode , outputs are placed in a hi gh-impedance sta te indepen dent of

OE#. If dese lect ed duri ng a program or erase algorit hm, the device shall consume activ e power

until the program or erase operation completes.

9.1.6 Reset

The devic e enters a reset m ode whe n RST# is ass ert ed. In reset mode, interna l circui try is tur ned

off and ou tput s are plac ed in a high-i mpedance state.

After returning from reset, a time tPHQV is require d unti l outp uts are valid, and a delay (tPHWV) is

required before a write sequence can be initiated. After this wake-up interval, normal operation is

restore d. The devic e de faul ts to read-array mode, the Status Regist er is set to 80h, and the

Configuration Register defaults to async hronous page-mo de reads .

If RST# is asserte d during an era s e or program operation, the operat ion a borts and the mem ory

contents a t t he aborted block or ad dress a re i nvalid. See Figure 19, “R ese t Operations Wa ve forms”

on page 48 for detailed info rmati on rega rding reset timings .

Like any automated device, it is import ant to assert RST# during system reset. When the sy stem

comes out of reset, th e process or exp ec ts to read from the flash me mor y arra y. Automated flash

memorie s provide status infor matio n wh en read during progra m or erase operatio ns. If a CPU reset

occur s with no fla sh mem ory rese t, prope r CPU initi al iz at ion may not occu r becaus e the fla sh

memory ma y be prov idi ng stat us inform ation instead of array da ta. Intel fla sh me mor ies al low

proper CPU ini tiali za ti on foll ow ing a system res et through the use of the RS T# input. In this

appli cation, RST# is controll ed by th e sam e CPU reset sig nal .

9.2 Device C o mmands

The device’s on-chip WSM manages erase and program algorithms. This local CPU (WSM)

contro ls the device’s in-system re ad, p rogram, and erase ope rations . Bus cycles to or from the flash

memory conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#, and ADV#

contro l signa ls dicta te data flow int o and out of the devic e. WAIT informs the CPU of valid data

during burs t read s. Tab le 18, “Bus Operat ions S ummary” on page 53 summa riz es bus opera ti ons.

Devic e ope rat ions are sele ct ed by writ ing speci fic com mands into the devic e’s CUI. Table 19,

“Com ma nd Code s and Descri pti ons ” on page 56 lists al l possible command codes and

descriptions. Tabl e 20, “Bus Cycle Definit ions” on page 58 lists command definitions. Because

co mman d s a r e partitio n - s p ecifi c, it is impor tant to issue w r ite commands within t h e tar g et addr ess

range.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

56 Order Numbe r: 290701 , Revision: 015

Table 19. Command Codes and Descri ptions (Sheet 1 of 2)

Operation Code Device

Command Description

Read

FFh Read Array Places selected partition in Read Array mode.

70h Read Status

Places selected partition in Status Register read mode. After issuing this

command, reading from the partition outputs SR data on DQ[15:0]. A partition

automatically enters this mo de after issuing the Program or Erase comm and.

90h Rea d Iden tifier Places the selected partition in Read ID mode. Device reads from partition

addresses output manufacturer/device codes, Configuration Register data, block

lock status, or protection register data on DQ[15:0].

98h CFI Q uery Puts t he ad dressed partition in CFI Query mode. Device reads from the par tition

addresses ou tput CFI i nformation on DQ[7:0].

50h Clear Status

The WSM can set the Status Register’s block lock (SR[1]), VPP (SR[3]), program

(SR[4]), and erase (SR[5]) status bits, but it cannot clear them. SR[5:3,1] can

only be cleared by a device reset or throug h the Clear St atus Register command.

Program

40h Word Program

Setup

This preferred p rogram command’s first cycle prepares the C UI fo r a program

operation. The second cycle latches address and data, and executes the WSM

program algorithm at this location. St atus register updates occur when CE# or

OE# is to ggled. A Read Ar ray c ommand is required to read ar ray data after

programming.

10h Alternate Set up Equivalent to a Pr ogram Setup command (40h) .

30h EFP Setup

This program command activates EFP mode. The first write cycl e sets up the

command . If the second cycle is an EFP Confir m command ( D0h), subsequent

wr ites provide program data. All other c ommands ar e ignored after EFP mode

begins.

D0h EFP Confi r m If the fir st comma nd was E FP S etu p (30 h) , t he CUI l at ches t h e ad dre ss a nd dat a,

and prepares the device for EFP mod e.

Erase

20h Erase Setup

This command prepare s the CUI for Block Erase. The device erase s the b lock

addressed by the Erase C onfirm command. If the next c omman d is not Erase

Confirm, the CUI sets S ta tus Register bits SR[5:4] to indicate command

sequence error and places the partition in the read Status Register mode.

D0h Erase Confirm

If the first c ommand was Erase Setup (20h), the CUI latches address and data ,

and erases the block indicated by the erase confirm cycle address. During

program o r erase, the partition responds only to Read Status Register, Program

Suspend, and Erase Suspend command s. CE# or OE# toggle updates Status

Re gi ster da ta.

Suspend B0h Program

Suspend or

E ras e S us p en d

This command, issued at any device address, suspends the currently executing

program o r erase operation. Status register data indicates the operation was

successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend)

and SR[7] are set. T he WSM remain s in the suspende d state regardless of

control signal states (except R ST#) .

D0h Suspend

Resume This command, issued a t any device address, resumes the suspended progr am

or erase operation.

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Order Number: 290701, Revisio n: 015 57

Block Locki ng

60h Lock Set up Th is command prepares the CUI l ock configura tion. If the next comma nd is not

Lock Block, Unlock Block, or Lock-Down, the CUI sets SR[5:4] to indicate

c omman d sequ ence e rror.

01h Lock Block If the previous command was Lock Setup (60 h), th e CUI locks the addressed

block.

D0h Unlock Block If the previous command was Lock Setup (60h), the CUI latches the address and

unlocks the addressed block. If previously locked-down, the operation has no

effect.

2Fh Lock-Down If the previous command was Lock Setup (60h), the CUI latches the address and

locks -down the addressed block.

Protection C0h Protection

Program

Setup

Th is c omma nd prep a res th e CU I for a pro t ecti on re gist er pro gra m op er ati on . The

s econ d cycl e latc hes address a nd data, and starts the WSM’s protection re gister

program or lock algor ithm. Tog glin g CE# or O E# updates the flas h Status

command.

Configuration

60h Configuration

Setup

This c ommand pre pares the CUI for device configuration. If Set Co nfiguration

sequence error.

03h Set

Configuration

If the previous command was Configuration Setup (60h), t he CUI latches the

address and writes the data from A[15:0] into the configuration r egi ster.

Subs equen t read operations access array data.

Note: Do not use unassigned commands. I ntel reserves the right t o redefine these codes f or futur e functions.

Table 19. Command Codes and Descriptions (Sheet 2 of 2)

Operation Code Device

Command Description

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Table 20. Bus Cycle Definitions

Operation Command Bus

Cycles

First Bus Cycle Second Bus Cy cle

Oper Addr1Data2,3 Oper Addr1Data2,3

Read

Read Array/Reset ≥1WritePnA FFhRead

Read

Address Array

Data

Read Identifier ≥ 2 Write PnA 90h Read PBA+IA IC

CFI Query ≥ 2 Write PnA 98h Read PBA+QA QD

Rea d Status Re gi st er 2 Writ e PnA 70h R e ad PnA SR D

Cle ar Stat us Re gi st er 1 Writ e XX 50 h

Program

and

Erase

Block Erase 2 Write BA 20h Wr ite BA D0h

Word Program 2 Write WA 40h/10h Write WA WD

EFP >2 Write WA 30h Write WA D0h

Program/E ras e Suspend 1 Write XX B0h

Program/E ras e Resume 1 Write XX D0h

Lock

Lock Block 2 Write BA 60h Write BA 01h

Unlock Block 2 Wr ite BA 60h Write BA D0h

Lock-Down Block 2 Write BA 60h Write BA 2Fh

Protection

Protection Program 2 Write PA C0h Write PA PD

Lock Protection Program 2 Write LPA C0h Write LPA FFFDh

Configuration Set Configuration Register 2 Write CD 60h Write CD 03h

Notes:

1. Fi rst -cyc le co mma nd ad dr esse s sh ou l d be t he same as t h e ope r atio n’s tar ge t add res s. Exam pl es: the f irs t-c ycl e a dd res s

for the Read Identifier command should be the same as the Identification code address (IA); the first-cycle address for

the Word Progr am co mmand should be th e same a s the word ad dress (WA) to be program med; the first-cycle addr ess

for the Erase/Pr ogram Suspend command should be th e same as the address within the block to be suspended; etc.

XX = Any v alid address within the device.

IA = Identification code address.

BA = Bl ock Address. Any addre s s within a specific block.

LPA = Lock Protection Address is obtained from the CFI (through the CFI Query command). The Intel Wireless Flash

Memory family’s LPA is at 0080h.

PA = User programmable 4-wor d protection address.

PnA = Any address within a specif ic p artition.

PBA = Part ition Base Address. The very fi rst address of a particular p artition.

QA = CFI code address.

WA = Word address of memory location to be written.

2. SRD = Status register data.

WD = Data to be written at location WA.

IC = Identifier code data.

PD = User programmable 4-word protection data.

QD = Query code data on DQ[7:0].

CD = Conf igu ration register co de data presen ted on devi ce addresses A[15:0]. A[MAX:16] ad dress bits can select any

partition. See Table 28, “Read Configuration Register Descriptions” on page 84 for Configuration Register bits

descriptions.

3. Commands other than those shown above are reserved by Intel for future device imp lemen tations and sh oul d not be

used.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 59

9.3 Command Sequencing

Wh en issu ing a 2- cycle write seq uence to the fla sh device , a r ead operation i s allo we d to occur

between the two write cycles. The setup phase of a 2-cycle write sequence places the addressed

parti ti on int o read-s tatus mode , so if the same partit ion is read before the second “confirm” write

cycl e is issued, Status Regist er da ta will be retur ned. Rea ds from ot her parti tions, however, can

return actual array data assuming the addressed partition is already in read-array mode. Figure 23

and Figure 24 illustrate these two conditions.

By contrast, a writ e bus cycle may not interrupt a 2-cycle write sequence. Doing so causes a

command se que nce error to appe ar in the Status Regist er. Figure 25 illustrates a command

sequence error.

Figure 23. Nor m al Write and Read Cycles

Figure 24. I nterleavi ng a 2-Cycle Writ e Seque nce with an Arra y Read

Partition A Partition A Pa rtiti o n A

20h

D0h FFh

Blo c k Era s e Se t up Block Erase Confirm Read Array

ddress [A]

WE# [W]

OE# [G]

Data [Q]

Partiti on B

Par t ition A

Partition B

Partition A

FFh

20h

Array Data

D0h

R ead Array Erase Set up Bus R ead Erase C onfirm

ddre ss [A]

WE# [W ]

OE# [G]

Data [Q]

Figure 25. Improper Command Sequencing

Parti tion X

Partiti on Y

Parti tio n X

Partition X

20h FFh D0h SR Data

Address [A]

WE# [ W]

OE# [G]

Data [D/Q]

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10.0 Read Operations

The device supports two read modes - asynchronous page and synchronous burst mode.

Async hronous page mode is the defaul t read mo de after devic e powe r-up or a reset. The Read

Configuratio n Register (RCR) must be configure d to en abl e synch ronous burs t reads of the flash

memory array (see Section 14.0 , “Set Read Configurati on Regi s ter ” on page 84).

Each partit io n of t h e device can be in any o f four read st ates: R ead Ar r ay, R ead Identifie r, R ead

S tatus or CFI Que ry. Upon power -up , or af ter a reset, all part itions of the de vice default t o the Read

Array state. To change a partition’ s read state, the appropriate read command must be written to the

de vice (s e e Sec ti on 9.2, “De vic e Com ma nds” on page 55).

The following sections describe device read modes and read states in detail.

10.1 Asynchronous Page Read Mode

Fol lowi ng a de vic e powe r-up or reset, asyn chro nous page mod e is the defau lt read m ode a nd all

part iti ons are set to Read Array. How ever, to perform array reads after any ot her devic e ope rat ion

(e. g. write ope rat ion), the Read Array comma nd must be issu ed in ord er to read from the flash

memory array.

Note: Asynchronous page -m ode re ads can only be performed when Read Conf igura ti on Register bit

RCR [ 1 5] is set ( see Section 14. 0, “Se t Read Configuration Register” on page 84).

To perform an a synchronous page mode re ad, a n address is driven ont o A [MA X:0], and CE #, OE#

and ADV# are asserted. WE# and RST# must be deasserted. WAIT is asserted during

asynchronous page m ode. ADV# can be driven high to latch the addre s s , or it must be held low

throughout the read cycle. CLK is not used for asyn chronous page-m ode reads, and is ignored. If

only asynchronous reads are to be perform ed, CLK should be tied to a valid VIH lev el, WAIT

signal can be fl o ated and ADV# must be tied to gr ou nd. Array data is driven onto DQ[15:0] afte r

an initial access time tAVQV delay. (see Section 7. 0, “AC Chara ct eri s tics ” on page 29).

In asynchronous page mo de, f our data words are “sense d” sim ult aneously from the flas h memory

array and loaded into an internal page buffer. The buffer word corresponding to the initial address

on A[ MAX:0] is driv en onto DQ[15: 0] after the initi al access delay. Address bits A[MAX: 2] select

the 4-w ord pag e. Address bit s A[ 1:0] dete rmine which wo rd of the 4-w ord pa ge is output from the

data buffer at any given time.

10.2 Synchronous Bu rst Read Mode

To perform a synchron ous burst- read, an initial ad dress is drive n onto A[M AX :0 ], an d CE# and

OE# are asserted. WE# and RST# must be deasserted. ADV# is asserted, and then deass ert ed to

lat ch the add ress . Alt ern at ely, ADV# can rema in asserted throughout th e burst a cc ess , in which

case the address is latched on the next valid CLK edge after ADV# is asserted. See Secti on 14. 0,

“Set Read Configuration Register” on page 84

Du ring synchronous array and non-a rray read mode s, the first word is output from the data buf f er

o n th e next valid CL K ed g e a f ter the i n itial acce s s laten cy delay (s ee Section 14.2, “Firs t Access

Latency Count (RCR[ 13:11])” on page 86). Subse quent data is output on valid CLK edge s

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Order Number: 290701, Revisio n: 015 61

following a minimum delay. However, for a synchronous non-array read, the same word of data

will be output on success ive clock edges until the burst length requirements are satisfied. See

Secti on 7.0 , “AC Characteristic s ” on page 29

10.3 Read Array

The Read Array command places (or resets) the partition in read-array mode and is used to read

data from the flash memory array. Upon initial device power-up, or after reset (RST# transitions

from VIL to VIH), all partitions default to asynchronous read-array mode. To read array data from

th e f lash dev ice , f irst write t he R ead Ar r ay comman d (FFh) to th e CUI an d spec if y the desir ed

word address. Then read from that addre ss. If a par tition is already in rea d-ar ray m ode , issuing the

Read Arra y com mand is not re quired to read from that partit ion .

If the Read Array c ommand is writt en to a parti ti on tha t is erasing or programming, the devic e

present s invalid da ta on the bus until the program or erase opera tio n comple te s. Afte r the pro gram

or era s e fini s hes in tha t partition, valid arra y data ca n then be re ad. If an E rase S us pe nd or Program

Suspe nd com mand s us pends th e WSM, a subseque nt Re ad Array command places the addressed

parti ti on in read-a rray mode . Th e Read Array command f unct ions independently of VPP.

10.4 Read Identifier

The Read Ide nti fie r mode outputs the manufac tur er/ devi ce ide nti fier, block loc k stat us , prot ecti on

regist er cod es, and Configuration Regi s te r data. The identifier informa ti on is cont ained within a

separa te me m ory s pa ce on the de vic e and can be ac ces s ed a lo ng the 4-Mbit partition a ddress range

suppl ie d by the Read Identifie r command (90h) addre ss. Re ads from add ress es in Table 21 retri eve

ID informa ti on. Issui ng a Read Iden tifier command to a parti tio n that is progra mm ing or erasing

places that partition’s outputs in read ID mode while the partition continues to program or erase in

the background.

Tabl e 21. Device Identification Codes (Sheet 1 of 2)

Item Address1

Data Description

Base Offset

Manufacturer ID Partition 00h 0089h Intel

Device ID Partition 01h

8862h 32-Mbit TPD

8863h 32-Mbit BPD

8864h 64-Mbit TPD

8865h 64-Mbit BPD

8866h 128-Mbit TPD

8867h 128-Mbit BPD

Block Lock Status(2) Block 02h D0 = 0 Block is unlocked

D0 = 1 Block is locked

Block Lock-D own St atus(2) Block 02h D1 = 0 Block is not locked-down

D1 = 1 Block is locked down

Configuration Reg ister Pa rtition 05h Register Data

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10.5 CFI Query

Thi s devic e co nta ins a sepa rate CFI query database that acts as an “on-chip datasheet.” The CFI

inform ation wi thi n this device ca n be access e d by issui ng the Re ad Query command and supplying

a specific address. The address is constructed from the base address of a partition plus a particular

offset corresponding to the desired CFI field. Appendix B, “C ommon F la sh Inter face (CFI)” o n

page 96 shows acce s sible CF I fields and their address offs ets.

Issui ng the R ead Que ry command to a parti tion that is prog ramming o r erasing puts that pa rtitio n in

read query mode while the partition continues to program or erase in the background.

10.6 Re ad Status Register

The devi ce ’s S ta tus Register displ ays program and erase ope rat ion sta tus. A partition’s stat us can

b e r ead after wr iting the Read Stat u s R eg ister comman d to an y locati on with in th e partiti on ’s

addre s s range . Re ad-status mode is the defaul t read mode foll ow ing a Prog ram, E rase, or Loc k

Bloc k com mand s eque nc e. Sub seque nt single reads from that part it ion wil l return it s status unt il

anot her va li d com mand is wr itten.

The read -stat us mode sup ports single synchronous and single async hronous reads only; it doesn’t

sup port burst reads. The first falli ng ed ge of OE# or CE # latche s and update s S ta tus Reg iste r dat a.

The operation doesn’t affect other partitions ’ modes. Because the Status Register is 8 bits wide,

only DQ [7:0] contains valid S t at us Regi ster da ta ; DQ [15:8] contains zeros. See Table 22, “Status

Regi s ter Defini ti ons ” on page 63 and Table 23, “Status Register Descriptions” on page 63.

Each 4-M bi t part it ion c ontains it s own Status Regis ter. Bits SR[6:0 ] are unique to each par tition,

but SR[7], the De vice WSM S t at us (DWS) bit , pe rtains to the ent ire devi ce . SR[7] provides

program and erase status of the entire devi ce . By contra s t, the Partit ion WS M Sta tus (P WS) bi t,

SR[0], provides program and erase status of the addressed par tition only. Status register bits

SR[6:1] present information about partition-specific program, erase, suspend, VPP, and bloc k-lo ck

states. Table 24, “ S t at us Regi s te r Devi ce W SM a nd P a rti tio n Write St at us Descri pti on” on page 63

presents descript ions of DWS (S R[7]) and PWS (SR[0]) combi nat io ns.

Protection Register Lock Status Partition 80h Lock Data

Protection Register P artition 81h - 88h Register Data Multiple reads required to read

the entire 128-bit Pr ote c tion

Notes:

1. Th e address is construc ted from a base address pl us an offs et. For example, to read t he Block Lock

Status for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), i.e.

0F8002h. Then exa mine bit 0 of the data to determine if the block is locked.

2. S ee Section 13.1.4, “Block Lock Status ” o n pa ge 79 for valid lock status.

Table 21. Device Identi fication Codes (Sheet 2 of 2)

Item Address1

Data Description

Base Offset

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Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 63

Table 22. Status Register Definitions

DWS ESS ES PS VPPS PSS DPS PWS

76543210

Table 23. St atu s Register Descriptions

Bit Name State Description

7DWS

Device WSM Status 0 = Device WSM is Busy

1 = Device WSM is Ready

SR [7] indicates erase or pr ogram completion in the

device. SR[6:1] are invalid while SR[7] = 0. See Table

24 for valid S R[7] and SR[0] c ombinations.

6ESS

Erase Suspend Status 0 = Erase in progress/completed

1 = Er ase suspended

After issuing an Eras e Suspend command, the WSM

halts and sets SR[7] and SR[6]. SR[6] remains set until

the device receives an Erase Resume command.

5ES

E ras e Status 0 = Erase succes sful

1 = Erase error SR[5] is set if an attempted erase failed. A Command

Sequence Error is indicated when SR[7,5:4] are set.

4PS

Progr am Status 0 = Program successful

1 = Program error SR[ 4] is set if the WSM faile d to pro gra m a word.

3VPPS

VPP St atus 0 = VPP OK

1 = VPP l ow detec t, operation aborted

The WSM indicates the VPP level after program or

er ase co mple te s. SR[3] do es not pro vide con tin uous

VPP feed back and i s n’t gua ranteed when VPP ≠ VPP1/2.

2PSS

Program Suspend

Status

0 = Program in progress/completed

1 = Prog ra m susp ende d

After receiving a Program Suspend command, the

WSM halts execution and sets SR[7] and SR[2]. They

remain set until a Resume command is received.

1DPS

Dev ic e Pr ot ec t Status

0 = Unlocked

1 = Abort ed erase/program attempt on

locked block

If an erase or program operation is attempted to a

locked block (if WP# = VIL), the WSM sets SR[1] and

aborts the operat ion.

0PWS

Partition Write Status

0 = This partition is busy, but only if

SR[7]=0

1 = Another partition is busy, but only if

SR[7]=0

Add r ess ed pa r tit io n is er asin g or pro gr am min g. In EF P

mode, SR[0] indicates that a data-stream word has

fi ni sh ed pr og ramm in g or ve rify ing de pe ndin g on th e

particular EFP phase. See Table 24 for valid SR[7] and

SR[0] co m bin at io ns .

Table 24. St atu s Register Device WSM and Partition Write St atus Description

DWS

(SR[7]) PWS

(SR[0]) Description

The addressed p artition is performing a program/er ase opera tion.

EFP: device has fi nish ed programming or verifying data, or i s ready for data.

A partition other than the one currently addressed i s performing a pr ogram/erase operation.

EFP: the device is either programming or verifying data.

No program /erase operation is in progress in any par tition. Erase and Progr am suspend bits (SR[6,2])

indicate whether other partitions are suspended.

EFP: the device has exited EFP mode.

Won’t occur in standard program or erase modes.

EFP: this combin ation doe s not occur.

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10.7 C lea r Statu s Reg ist er

The Clear Status Register command clears the Status Register and leaves all partition output states

unchanged. The WSM can set all Status Register bit s and clear bits SR[7:6,2,0]. Because bits

SR[ 5,4 ,3, 1] i ndicate various error condi ti ons , the y c an only be cle are d by the Cl ea r Status Re gister

command. By allowing system software to reset these bits, several operations (such as

cum ula ti vel y progra mm in g several addresses or er asing multipl e bl ocks in sequence) can be

performed before re ad ing t he Status Re giste r to de termine error occ urre nce . If an er ror is de tecte d,

the S ta tus Register must be cleared before beginning an othe r com mand or s eque nc e. Device re set

(RST# = VIL) also clea rs the St at us Regi s ter. This command func ti ons independently of VPP.

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11.0 Program Operations

11.1 Word Program

When the Wor d Pro g r am co mman d is issue d, the WSM execu tes a seq uence of in ter n ally timed

events to progra m a word a t the desire d addr ess and ver ify that th e bits are sufficie ntl y

programmed. Programming the flash array changes specifically addressed bits to 0; 1 bits do not

change th e memo r y ce ll co nt ents .

Progr am mi ng can occur in only one partition a t a time. A ll othe r pa rti tio ns must be in either a re ad

mode or erase suspend mode . Onl y one parti tio n can be in erase susp end m ode at a time .

The St at us Regi ster can be examin ed for program progres s by readi ng any address within the

parti tion that is b usy progr amming. Ho wever , whi le most S tatus Regi ster b its are partiti on-speci fic,

the Device WSM Status bit, SR[7], is device- spec ifi c; tha t is, if th e St at us R egis te r is rea d f rom any

other part ition, SR [7] indicat es program st atus of the ent ire device. This pe rmits the s ystem CPU to

monitor program progre ss whil e readi ng the statu s of other par tit ion s.

CE# or OE# tog gle (during polli ng) upda te s the Status Registe r. Several commands can be issued

to a partition tha t is programming: Read Status Regi s te r, Program Suspend, Read Ide nti fie r, and

Read Que ry. The Read Array command can also be issued, but the read data is indeterm inate.

After programming completes, three S ta tus Re giste r bit s can signify various poss ibl e err or

condi tio ns . SR[4] ind ic ates a program fa ilu re if set. If SR[3] is set, the WSM couldn’t execute the

Word Program command becaus e VPP was outside accept abl e limi ts. If SR[1] is set, the program

was aborted because the WSM attempted to program a locked block.

After the Status Register data is examined, clear it with the Clear Status Register command before

a ne w command is i ssue d. The partit ion remains in S tatus Re gis t er mode u nti l a not her command is

writte n to that pa rti tio n. Any co mmand can be issued aft er th e Status Register in dic at es program

completion.

If CE# is deass erted w hile the device is p rogrammin g, the dev ices wil l not ente r standby mode u ntil

the progr am opera ti on comple te s .

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11 .2 Factory Programming

The standard factory programming mode uses the same commands and algorithm as the Word

Pro gram mod e (40h/ 10h). Whe n VPP is at VPP1, prog ram and erase cu rren ts are drawn through

VC C. If V P P is dri ven by a logi c si gna l, VPP1 must re main abo ve the VPP1Min v alue to perfo rm in -

system flash modifications. When VPP is connected to a 12 V power supply, the device draws

program and erase current directly from VPP. This eliminates the need for an external switching

transistor to control the VPP voltage. Figure 35 , “Exa mp les of VP P P ower Supply Configurations”

on page 8 3 shows exam ple s of flash pow er supply usage in various configurations .

Figu re 26 . Word Program Fl owchart

Suspend

Program

Loop

Start

Write 40h,

Word Address

Write Data

Word Address

Read Status

SR[7] =

Full Program

Status Check

(if desired)

Program

Complete

FULL PROGRAM STATUS CHECK PROCEDURE

Suspend

Program

Read Status

Program

Successful

SR[3] =

SR[1] =

SR[4] =

Yes

Range

Error

Device

Protect Error

Program

Error

WO RD PROGRAM PROCEDURE

SR[3] MUST be cleared before the WSM will allow further

program attempts

Only the Clear Staus Register command clears SR[4:3,1].

If an error is detected, clear the status register before

attempting a program retry or other error recovery.

Standby

Bus

Operation Command

Check SR[3]

1 = V

error

Check SR[4]

1 = Data program error

Comments

Repeat for subsequent programming operations.

Full status register check can be done after each program or

after a sequence of program operations.

Comments

Bus

Operation Command

Data = 40h

Addr = Location to program (WA)

Write Program

Setup

Data = Data to program (WD)

Addr = Location to program (WA)

Write Data

Read SRD

Toggle CE# or OE# to update SRD

Read

Check SR[7]

1 = WSM ready

0 = WSM busy

Standby

Standby Check SR[1]

1 = Attempted program to locked block

Program aborted

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The 12-V VPP mode enhances programming performance during the short time period typically

found in manufacturing proce s ses ; howe ver, it is not intended for extende d use.1 2 V may be

appli ed to VPP during program and erase oper ations as sp ecified in Section 5.0, “Maxim um

Ratings and Operating Condit ions” on page 24. VPP may be connected to 12 V for a total of tPPH

hours maximum. Stressing th e dev ice beyond these limits may cause perm anent da ma ge .

11 .3 Enh an c ed Fact or y Pro gr am (E FP)

EFP substa nti al ly improves device programming performance throu gh a number of enh anc ements

to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm

elimin at es the traditi ona l overhead delays of t he conventional word program mode in both th e host

program m ing s yste m an d the flash devi ce . Change s to the conventi onal word programming

flowcha rt a nd int erna l WSM rout ine were deve lope d because of today's beat-r at e-sensitive

manu facturing e nvironments; a balance between progra mming s peed and cyclin g perform ance was

attained.

The host pro gram m er writ es dat a to the dev ice and c hecks the Status Regis te r to determine wh en

the data ha s comp leted pro gramming. This modi fic at ion essen ti all y cuts write bus cycl es in half.

Fol lowin g each int ernal program pulse , the WSM inc rements the device's addre s s to the next

physi cal l ocation. Now, programming e quipm e nt c an sequent ially stream program da ta thro ughout

an entire block without havi ng to set up and pre s ent each new ad dress . In combina tio n, th ese

enhan ce ments reduce much of the host program m er ove rhe ad, enabli ng more of a data stre aming

approach to device programming.

EFP further spe eds up programming by perfo rmi ng int ern al code ve rifi ca ti on. With this, PROM

program m ers ca n rely on the devic e to verify th at it has been progra m med properly. From the

device s ide, E FP stre amli nes int ernal overhead by eliminating the delays previously associ at ed to

swit ch volta ges bet w ee n progra mm in g and ve rify levels at each mem ory-word location.

EFP cons ists of four phases: setup, prog ram, ve rify and exit. Refe r to F igure 27, “Enhanced

Facto ry Pro gram Flowchart” on page 70 for a detai le d grap hic al representation of how to

implement EFP.

11.3.1 EFP Requirements and Considerations

EFP Requirements

Ambien t te mperature: TA = 2 5 °C ± 5 °C

VCC within specified operating range

VPP within specified VPP2 range

Target block unlocked

E FP Cons ide rat ion s

Block cyclin g bel ow 100 er ase cy cles 1

RWW not supported2

EFP programs one bl ock at a tim e

EFP canno t be suspended

Notes:

1. Reco mme nded fo r op t imum p er for ma nc e. S om e deg r adat io n i n pe rfo r man ce may

occur if this limit is exceeded, but the internal algorithm will continue to work

properly.

2. Code o r data cannot be read from anothe r p artition during EFP.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

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11.3.2 Setup

After receivin g the E FP Set up (30h) a nd EFP Confirm (D0h) co mmand sequence, SR[7] transitions

fr om a 1 to a 0 in dic at ing th at the WSM is busy w ith EFP algori thm start up. A dela y before

che cki ng SR [7] is requ ire d to allow the WSM time to perform al l of its setups and checks (VPP

lev el and block lock s ta tus). If an error is detec te d, S t at us R egi ster bit s SR[4], SR[3], and/ or S R[1]

are set and EFP ope rat ion term ina te s .

Note: After the EFP S etup and Confirm command s equence, reads from the device automatically output

S ta tus Register da ta . Do not issue the Rea d S t atu s Register comman d; it will be interpreted as data

to progra m a t WA0.

11.3.3 Program

After setup comp letion, the host pr ogramming system must c heck SR[0] to determ ine “data -stream

ready" status (SR[0]=0). Each subsequent write after this is a program-data write to the flash array.

Each ce ll withi n the mem ory word to be programmed to 0 receives one WSM pul se; addit iona l

puls es, if required, occ ur i n the verify pha se. SR[0]=1 ind icate s tha t t he WSM is busy ap plyi ng the

program pulse.

The hos t programmer must poll the device's S tatus Re gister for the "program d one" state a fte r each

data-stream write. SR[0]=0 indicates that the appropriate cell(s) within the accessed memory

loc ation have received their si ngl e WSM program pulse, and that the dev ic e is now ready for the

next wor d. Alt hough the host m ay ch ec k full status for errors at any time, it is only neces sary on a

block basis, after EFP exit.

Ad dress es mu st rem ai n withi n the tar ge t block. Supplying an address outside the targ et block

immediately terminates the program phas e; the WSM then en te rs the EFP veri fy pha se.

The address can either hold constant or it can increment. The device compares the incoming

addre s s to tha t stored from the setup phase (WA0); if they m atc h, the WSM programs the new data

wo rd at the next sequential memory lo ca tio n. If they dif fer, the WSM jumps to the new addres s

location.

The program phase conclud es when th e host programming syst em wr ites to a different block

address , and data supplied must be FFFFh. Upon program phase comple tio n, the devi ce enters the

EFP verify phase.

11.3.4 Verify

A high perc ent ag e of the flash bi ts progra m on the first W SM puls e. However, for those cel ls tha t

do not completely progra m on their fir st attem pt, EFP int erna l verifi ca ti on ide nti fie s them and

appl ie s addit iona l pul s es as requi red .

The verify phase is identical in flow to the program phase, except that instead of programming

incoming data, the WSM compares the verify-stream data to that which was previously

programmed into the block. If the data comp are s corre ctl y, the host progr am mer proceeds to the

next wor d. If not, the hos t waits while the WSM appli es an ad dit iona l pul se(s).

The host programmer must reset it s initial veri fy-w ord ad dress to the same start ing locati on

supplied during the program phase. It then reissues each data word in the same order as during the

progra m phase . Like pro gramming, the h ost may write eac h subsequent data w ord to WA0 or it may

increment up through the block addresses.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 69

The verification phase concludes when the interfacing programmer writes to a different block

addres s; data supplied mus t be FFFFh. Upon completion of the verify phase, the device enters the

EFP exit phase.

11.3.5 Exit

SR[7] =1 ind ic ates that the device has retur ned to normal ope rat ing c onditions. A full status check

shoul d be performed at this time to ensure the entire bl ock pro gram m ed succ essfully. Aft er EFP

exit , any valid CU I com mand ca n be issued.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

70 Order Numbe r: 290701 , Revision: 015

Figure 27. Enhanced Factory Program Flowchart

EFP Setup EFP Program EFP Verify

EFP Exit

1. WA

= first Word Address to be programm ed w ithin the target block. The BBA (Block Base

Address) must remain constant throughout the program phase data stream; WA can be held

constant at the first address location, or it can be written to sequence up through the addresses

w ithin the block. Writing to a BBA not equal to that of the block currently being written to

term inates th e E F P p rog ram p hase, and in stru cts the dev ice to enter th e E F P v erify p hase.

2. For proper verification to occur , the verify data stream must be presented to th e device in the

same sequence as that of the program p hase data stream. Writing to a BBA not equal to WA

terminates the EFP verify phase, and instructs the device to exit EFP .

3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive

additional program-pulse attempts during the EFP verify phase. The device will report any

program failure by setting SR[4]=1; this check can be performed during the full status check after

EFP has been exited for that bl ock, an d wil l indicate an y error w it hin t h e entire d ata stream.

Comments

Bus

State

Repeat for subsequent operations.

After EFP exit, a Full Status Check can

d et e rmine if any program erro r occurred.

See the Fu ll S tat u s Check p rocedure in t h e

Word Prog ram flowchart.

Write

Standby

Read

Write

(note 2)

Read

Standby

Write

Read

Standby

EFP

Setup

Program

Done?

Exit

Program

Phase

Last

Data?

Exit

Verify

Phase

EFP

Exited?

Write EFP

Confirm

Read

Standby EFP

Setup

Done?

Read

Standby Verify

Stream

Ready?

Write Unlock

Block

Write

(note 1)

Standby Last

Data?

Standby

(note 3) Verify

Done?

SR[0]=1=N

Wri te D a ta

Address = WA

Last

Data?

Write FFFFh

Address

≠

BBA

Program

Done?

Read

Status Register

SR[0]=0=Y

SR[0]=1=N

Wri te D a ta

Address = WA

Verify

Done?

Last

Data?

Read

Status Register

Write FFFFh

Address

≠

BBA

Verify Stream

Ready?

Read

Status Register

SR[7]=0=N

Fu ll S t at u s Ch eck

Procedure

Operation

Complete

Read

Status Register

EFP

Exited?

SR[7]=1=Y

SR[0]=1=N

Start

Write 30h

Address = WA

= 12V

Unlock B lock

Wri te D 0 h

Address = WA

EFP Setup

Done?

Read

Status Register

SR[7]=1=N

Exit

EFP Program EFP Verify EFP ExitEFP Setup

ENHANCED FACTORY PROGRAMMING PROCEDURE

Comments

Bus

State

Data = 30h

Address = WA

Data = D0h

Address = WA

Status Register

Check S R[ 7]

0 = EF P read y

1 = EF P not ready

= 12V

Unlock b lock

Check S R[ 0]

0 = Program done

1 = Program not done

Status Register

Data = FFFFh

Ad dress not within same

BBA

Data = Data to program

Address = WA

Device automaticall y

increment s ad dress.

Comments

Bus

State

Data = Word to verify

Address = WA

Status Register

Device automaticall y

increment s ad dress.

Data = FFFFh

Ad dress not within same

BBA

Status Register

Check S R[ 0]

0 = Ready for verify

1 = Not ready for verify

Check S R[ 0]

0 = Verify done

1 = Verify not done

Status Register

Check S R[ 7]

0 = Exit not finished

1 = Exit comp l eted

Check V

& Lock

errors (S R [ 3, 1 ] )

Data Stream

Ready?

Read

Status Register

SR[0] =0=Y

SR[7]=0=Y

SR[0]=1=N

Standby

Read

Data

Stream

Ready?

Check S R[ 0]

0 = Ready for dat a

1 = Not ready for dat a

Status Register

SR[0]=0=Y

SR[0] =0=Y

EFP setup time

Standby EFP setup time

Standby Error

Condition

Check

If SR[7] = 1:

Check SR[3,1]

SR[3] = 1 = V

error

SR[1] = 1 = locked block

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 71

12.0 Program and Erase Operations

12.1 Progr am/Erase Su spend and Resume

The Progra m Sus pe nd and E rase Sus pe nd com ma nds hal t an in-progress progra m or erase

opera tio n. Th e comm and can be issued at any device address. The partition c orre sp onding to the

command’s addr ess remain s in its previ ous st at e. A suspen d com ma nd allows dat a to be access ed

from memo ry loc at ions othe r tha n the one being programmed or the block being erase d.

A progr am operation ca n be suspended only to perfo rm a read operation. An erase operati on can be

suspended to perform either a program or a read operation within any block, except the block that

is erase suspended. A program command nes ted within a suspended erase can subsequently be

suspe nded to read yet anothe r loc at ion. O nce a program or eras e proc ess start s, the Su sp end

command r eques ts tha t the WSM suspe nd the program or erase sequenc e at prede te rm ine d point s

in the algorithm. The partition that is actually suspended continues to output Status Register data

after the Suspen d command is written. An ope ration is s uspended whe n status bi ts SR[7 ] and SR[6]

and/or SR[2] are set.

To read data from blocks within the partition (other than an erase-suspended block), you can write

a Read Array com m and. Block era s e cannot res ume unti l the progra m ope rat io ns init iat ed during

erase suspend are complete. Read Array, Read Status Register , Read Identifier (ID), Read Query,

and Program Resume are valid commands during Program or Erase Suspend. Additionally, Clear

S ta tus Register, Program, Pr ogra m Sus pen d, E rase Res um e, Lock Bloc k, Unl ock Bloc k, a nd Lock-

Down Bl ock ar e valid c ommands during erase sus pe nd.

To read data from a block in a partition that is not program ming or erasing, the operation does not

need to be suspended. If the other parti tion is already in Read Array, ID, or Query mode, issuing a

vali d address ret urns correspond ing data. If t he other part ition is not in a rea d mode , one of the re ad

commands must be issued to the partition before data can be read.

During a suspe nd, CE# = VIH pla ces the de vice in stan dby s tate, whic h re duces active c urrent. VPP

must remai n at its progra m level and WP# must rema in unc hanged while in suspend mode.

A resume co mmand ins truc ts the WSM to con tin ue progr am mi ng or eras ing an d clears S t at us

Regist er bit s SR[2] (or SR[ 6]) and SR[7]. The Resume command can be writt en to any partit ion.

When rea d at the partitio n that is program ming or erasing , the devic e outputs data corre spondi ng to

th e p artit io n’s last mode. If Status Re gist er error bit s are s et, the S tatus Reg ister can be clea red

before issuing the next instruction. RST# must remain at VIH. See Figure 28, “Program Suspend /

Resume Flow ch art ” on page 72, and Figure 2 9, “Era se Su sp end / Res ume Fl owchart” on page 73.

If a suspended pa rtition was placed in R ead Array, Read Sta tus Registe r, ID, or Query mode during

the sus pe nd, the device rem a ins in that mod e a nd outputs da ta corresponding to that m ode after the

program or era se operati on is resum ed . Afte r resum ing a suspended operati on, issue the re ad

command appropriate to the read operation. To read status after resuming a suspended operation,

issue a Read Sta tus Register comm and (70h) to ret urn the suspe nded partition to statu s mode.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

72 Order Numbe r: 290701 , Revision: 015

Figure 28. Program Suspen d / Resum e Flowc hart

Read Status

SR.7 =

SR.2 =

Write FFh

Susp Partition

Read Arra y

Data

Program

Completed

Done

Reading

Write FFh

P gm'd P art ition

Write D0h

Any Address

Program

Resumed Read Array

Data

Yes

PR OGRA M SU SP EN D / RE SUME PR O C ED U R E

Write Program

Resume Data = D0h

Addr = Suspende d b lock (BA)

Bus

Operation Command Comments

Write Program

Suspend Data = B0h

Addr = Block to suspen d (BA)

Standby Ch eck SR. 7

1 = WSM ready

0 = WSM busy

Standby Ch eck SR. 2

1 = Program suspended

0 = Program completed

Write Read

Array

Data = FFh

Addr = Any address within the

suspended partition

Read Read array data from block other than

the one b eing programmed

Read

Status register data

Toggle CE# or OE# to update Status

Addr = Suspende d b lock (BA)

PGM_SUS.WM

Start

Write B0h

Any Address

Program Suspend

Read Status

Program Resume Read Array

Read Array

Write 70h

Sa me Pa rtition

Write Read

Status Data = 70h

Addr = Same partition

If the suspende d partition was placed in Read Array mode:

Write Read

Status

Return partition to Status mode:

Data = 7 0h

Addr = Same partition

Write 70h

Sa me Pa rtition

Read Status

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 73

12.2 Block Eras e

The 2-cycl e bl ock er ase c omman d sequence, consisti ng of Era se Setup (2 0h) and Erase Confirm

(D0h) , initi at es one bl ock erase at the add ress ed bl ock . Only on e partit ion can be in an eras e mode

at a time; other part it ion s must be in a read mode. The Era se Confirm command internally latches

the address of the block to be erased. Erase forces all bits within the block to 1. SR[7] is cleared

while th e er ase exec u tes.

Figure 29. Erase S usp end / Resume Flowch art

Erase

Completed

Write FFh

Erased Par titi on

Read Array

Data

Read

Program

Loop

Read Array

Data

Yes

Start

Write B0h

Any Addres s

Read Status

SR.7 =

SR.6 =

Write D0h

Any Addres s

Erase R e sumed

Read or

Program?

Done?

Write

Standby

Write

Erase

Suspend

Read Array

or Program

Program

Resume

Data = B0h

Addr = Any address

Data = F Fh or 4 0 h

Addr = Block to program or read

Check SR .7

1 = WSM ready

0 = WSM busy

Check SR .6

1 = Erase suspended

0 = Erase completed

Data = D 0 h

Addr = Any address

Bus

Operation Command Comments

Read Status register data. T oggle CE# or

OE# to update Status register

Addr = Same partiti on

Read or

Write Read ar r ay or program data from /to

block other than the one being erased

ERASE SUSPEND / RESUME PROCEDURE

ERAS_SUS.WM

Write 70h

Same Partition

Write Read

Status Data = 70h

Addr = Same partiti on

Erase Re sume

Erase Suspend

Read Status

Read Array

Write 70h

Same Partition

Read Status

If the suspended partition was placed in

Read Array mode or a Program Loop:

Write Read

Status

Return partition to Status mode:

Data = 70h

Addr = Same partiti on

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

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After writing the Erase Confirm command, the selected partition is placed in read Status Regi s ter

mode and rea ds perfo rme d to t hat par tit ion ret urn the current sta tus data. The addre ss gi ven during

the Erase Confirm command does not need to be the sam e address used in the Eras e Setu p

command. So, if the Eras e Confirm command is given to partition B, then the selected block in

p ar titi on B w ill be erased even if the Erase S etup co mman d was to p arti tion A.

The 2-cycle e rase seque nce cann ot be inte rrupted wi th a bus wri te ope ration. For example, an Eras e

Setup command must be immediately fol lowed by the Erase Confirm com mand in order to exec ute

properly. If a different command is issued between the setup and confirm commands, the partition

is placed in read-status mode, the Status Register signals a command sequence error, and all

su bseq u ent erase comm ands to that partiti o n ar e ignored u n til th e Status R eg ister is cl eared.

The CPU can det ect blo ck eras e co mpl et ion by anal yzi ng SR [7] of tha t par tition. If an er ror bit

(SR[5,3,1]) was flagged, the Status Register can be cleared by issuing the Clear Status Register

com ma nd bef ore atte mp tin g the next ope rat ion. The partition remains in re ad- stat us mode until

anot her c ommand is writt en to its CUI. Any CU I instru ct ion can foll ow aft er eras ing comp le tes.

The C U I ca n be set to re ad - ar ra y mo d e to pr e vent ina d ve rte n t St at u s Reg i s t er reads.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 75

12.3 Read-Whil e-Write and Read -While-Erase

The Intel® Wireless Flash Memory (W18) supports flexible multi-partition dual-operation

archite ct ure. By dividin g the fla s h m em ory into many s ep ara te part it ion s, the device can rea d from

one partit ion whil e programing or erasi ng in ano the r part ition; henc e the terms , RWW and RWE.

Both of the se feature s grea tl y enhance dat a stora ge performance.

Figure 30. Bl ock Erase Flow cha rt

SR[3,1]

must

be cleared before the WSM will allow further

erase attempts.

Only the Clear Status Register command clear s SR[5:3,1].

If an error is detected, clear the Status register before

attempting an erase retry or other error recovery.

Start

FULL ERASE STATUS CHECK PROCEDURE

Repe at for subse quent block erasures.

Full status register check can be done after each block erase

or after a sequence of block erasures.

Suspend

Erase

0Yes

Suspend

Erase

Loop

Write 20h

Block Address

Write D0h and

Block Address

Read Status

SR[7] =

Full Eras e

Status Check

(if desired)

Block Erase

Complete

Read Status

Block Erase

Successful

SR[1] = Erase of

Locked Block

Aborted

BLOCK ERASE P ROCEDU RE

Bus

Operation Command Comments

Write Block

Erase

Setup

Data = 20h

Addr = Block to be erased (BA)

Write Erase

Confirm D ata = D0h

Addr = Block to be erased (BA)

Read Read SRD

Toggle CE# or OE# to update SRD

Standby Check SR[7]

1 = WSM ready

0 = WSM busy

Bus

Operation Command Comments

SR[3] = V

Range

Error

SR[5:4] = Command

Sequence Error

SR[5] = Block Erase

Error

Standby Check SR[3]

1 = V

error

Standby Check SR[5:4]

Both 1 = C ommand sequence error

Standby Check SR[5]

1 = Block erase error

Standby Check SR[1]

1 = Attempted erase of locked block

Erase aborted

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

76 Order Numbe r: 290701 , Revision: 015

The product doe s not support simultaneous program and erase operations. Attempting to perform

opera ti ons such as the s e results in a command seq uence e rror. Only one partiti on can be

programming or era s ing wh ile an othe r partition is re adi ng. However, one pa rti tio n ma y be in e rase

suspe nd mode while a second pa rtition i s perfo rming a pro gram op eration, and yet another p artition

is e xec uti ng a rea d c om ma nd. Table 19, “Command C ode s and D e scriptions” on page 56 describes

the command codes available for all functions.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 77

13.0 Security Modes

The In tel W irel ess Flash Mem ory offe rs both hardware and sof tware s ecurity fe atures to prot ect the

flash dat a. The software security feature is used by executing the Lock Block command. The

hardware security feature is used by executing the Lock-Down Block command and by assert ing

the WP# sign al .

Refer to Figu r e 3 1, “Block Locki n g Stat e D iag r am” on pa g e 78 for a state diagram of the flash

security features. Also see Figure 32, “Locking Operations Flowchart” on page 80.

13.1 Block Lock Operations

Indivi dual ins tant bl ock lo cki ng protects code and data by allowing any block to be locke d or

unloc ked wit h no latency. This loc kin g schem e of fers two levels of prot ectio n. Th e first allows

soft ware -onl y cont rol of blo ck lo cki ng (us eful for frequ ent ly ch ang ed data bl ocks), wh il e the

second r equires ha rdware i nteraction be fore lo cking can be changed (pr otect s infrequentl y changed

code blocks ).

The following sections discuss the locking system operation. The term “state [abc]” specifies

locking states; for example, “state [001],” where a = WP# value, b = block lock-down status bit

D1, and c = Block Lock St atus Regi st er bi t D0. Figu re 31, “Blo ck Lo cki ng State Diagram” on

page 78 defines possible locking states .

The following summarize s the locki ng func tio nal ity.

•All blocks power-up in a locked state.

•Unlock c omm an ds can unlock these blocks, and lock comman ds can lock them a gai n.

•The Lock-D own comman d lo ck s a bl ock an d prev ents it fr o m be in g un locked w h en W P# is

asserted.

— Locked-down blocks can be unlocked or locked with commands as long as WP# is

deasserted.

— The lock-down status bit is cleared only when the device is reset or powered-down.

Bl o ck lock regis ters ar e not affe cted by the VPP level. The y may be mo difi ed and rea d eve n if VPP

≤ VPPLK.

Each bloc k’s locking st atus can be set to locked , unl ocke d, and lock-dow n, as described in the

followi ng sections. See Figure 32, “L ocki ng Operations Flowc hart ” on pa ge 80.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

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13.1.1 Lock

All blo cks defa ult to locked (state [x01]) after ini tia l powe r-up or reset. Locked blo cks are full y

prote ct ed from al terat ion. Atte mp te d progra m or eras e ope rat ions to a locked block w il l return an

error in SR[1 ]. Unlo cke d bloc ks can be locked by using the Lock Block command sequence.

Si mila rly, a locked blo ck’s status can be change d to unl ock ed or lock-down using the appropriate

sof tware comma nds .

13.1.2 Unlock

Un loc ked blocks (s ta te s [x00] and [110]) c an be p r ogra mmed or erased. All unlocke d blocks re turn

to the locked s tate when the device is re set or powe red-down. An unlocke d blo ck’s status can be

cha nged to the locked or loc ked -dow n s tate usin g the appropriate software comm a nds . A locked

block can be unlocked by writing the Unlock Block command sequence if the block is not locked-

down.

13.1.3 Lock-Down

Loc ked-down blocks (s ta te [011]) offer the user an addit iona l l eve l of wr ite prot ec ti on bey ond that

of a re gular locke d block. A bloc k that is lock ed-down ca nnot have it ’ s s tate changed b y software if

WP# i s assert ed. A l ocked or unl ocked block c an be loc ked-down by writ ing the Lock-Do wn Block

command sequence. If a block was set to locked-down, then later changed to unlocked, a Lock-

Figure 31. Block Loc king State Diagram

[X00]

[X01]

ower-Up/Reset

Unlocked

Locked

[011]

[111] [110]

Locked-

Down4,5

Software

Locked

[011]

Hardware

Locked5

Unlocked

WP# Har dware Control

Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.

2. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to

this block. D1 = ‘1’, Lock-down has been issued to this block.

3. D0 indicat es bl ock l ock stat us. D0 = ‘0’, block is un locked. D0 = ‘ 1’, block is l ocked

4. Loc ked-down = H ardware + Softw are locked.

5. [011] states should be tracked by system software to determine difference between

Har dware Locked and Locked-Down states .

Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)

Software Block Lock-Down (0x60/0x2F)

WP# hardware control

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 79

Down c om ma nd s houl d be is su ed pr ior a s serti ng W P # w il l put tha t bl oc k bac k to the locked -down

state . When WP # is deasserted, locked-dow n blocks are change d to the lock ed sta te and can then

be unlocked by the Unlock Block command.

13.1.4 Block Lock Status

Every block’s lock status can be read in read identifier mode. To enter this mode, issue the Read

Identifier command to the device. Subsequent reads at BBA + 02h will output that block’s lock

status. F or exa m ple , t o read the block lock stat us of bloc k 10, the address sent to t he de vic e should

be 50002h (for a top-pa ram e te r devi ce ). The lowe st two data bit s of the read data, D Q1 and DQ 0,

repre sent the lock status. D Q0 indicates t he block loc k s ta tus. It is set by the Loc k Block c ommand

and clear ed by the Bloc k U nloc k comma nd. It is also set when enteri ng the loc k-dow n sta te . DQ1

indicates lock-down status and is set by the Lock-Down command. The lock-down status bit

cannot be cleared by software–only by device reset or power-down. See Table 25.

13.1 .5 Lock Duri ng Erase Su spe nd

Block lock configurations can be performed during an eras e suspend operation by using the

standa rd loc king command sequenc es to unl ock, lock, or lock-down a bl ock. Thi s feat ure is useful

when another block requires immediate updating.

To change block lo cki ng during an era s e operat ion, first write the Erase Sus pe nd com mand. After

checking SR[6] to determine the erase operation has suspended, write the desired lock command

sequence to a block; the lock status will be changed. After completing lock, unlock, read, or

program operations, resume the erase opera ti on w ith the Erase Resu me comma nd (D 0h).

If a block is locked or l ocke d-down during a susp ende d era se of th e sam e bl ock, the loc king statu s

bits cha nge immedi at el y. When the eras e operat ion is resum ed, it wi ll comp let e normally.

Locking operation s cannot occ ur during p rogra m sus pend. Appendix A, “Write State Machine

Stat es” on pa ge 93 shows valid c omm an ds during e rase sus pe nd.

13.1.6 Status Register Error Checking

Using nested locking or program command sequences during erase suspend can introduce

ambiguity into St atu s Register results.

Becaus e locking changes require 2-cycle comm and sequ enc es, for exa mpl e, 60h foll ow ed by 01h

to lock a block, following the Configuration Setup command (60h) with an invali d command

produce s a command sequ ence error (SR[5: 4]=1 1b) . If a Lo ck Block comma nd error occurs during

erase su s p en d , th e device sets SR[ 4 ] and SR[5] to 1 ev en af ter th e er ase is r esum ed . When er ase is

Table 25. Write Protection Truth Table

VPP WP# RST # Write Protection

XXV

IL Device inaccessible

VIL XV

IH Word program and block erase prohibited

IL VIH All lock-down blocks locked

IH VIH All lock-down blocks can be unlocked

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

80 Order Numbe r: 290701 , Revision: 015

com ple te , possibl e er rors during the e rase c anno t be detecte d from the Status Regis te r bec ause of

the previous locking command error. A similar situation occurs if a program operation error is

n ested w ithin an eras e susp end.

13.1.7 WP# Lock-Down Control

The Write Protect s igna l, W P #, adds an a ddit ion al la yer of block secu rit y. WP# only affects bl ock s

tha t once had th e Lock-Dow n command writt en to them. Afte r the lock-dow n s ta tus bit is set for a

bloc k, a sse rti ng WP# forc es tha t blo ck into the lock -down s ta te [011] and prevents it f rom being

unloc ked. After WP# is deassert ed, the block ’s st at e revert s to locked [111] and so ftwa re

com mands can the n unlock the blo ck (for erase or progra m operati ons) and subse quently re-l ock it.

On ly dev ice rese t or power-dow n can clear the loc k-dow n s tatus bit and render W P# inef fective.

13.2 Protection Register

The Intel Wirel ess Fla s h M e mor y includes a 128-bit Protection R egi s te r. This protection register is

used to inc re ase sys te m securit y and for ident ifi ca ti on purpos e s . The protect ion register value can

ma tch the flash com pone nt to the syste m’s CPU or ASIC to prevent devic e substi tut ion.

The lower 64 bits within the protection register are programmed by Intel with a unique number in

each fla s h devi ce. Th e uppe r 64 OTP bits with in the prote ct ion register are left for the custome r to

program. Once programmed, the customer segme nt can be lo cked to pre vent further programming.

Figure 32. Locking Op erati ons Flowchart

Optional

Start

Write 60h

Block Address

Write 90h

BBA + 02 h

Read Block Lock

Status

Locking

Change?

Lock Change

Complete

Write 01,D0,2Fh

Block Address

Write FFh

Partition Address

Yes

Write

(Optional)

Read

(Optional)

Standby

(Optional)

Write

Lock

Setup

Lock,

Un lock, or

Lockdown

Confirm

Read ID

Plane

Block Lo ck

Status

Read

Array

Data = 60h

Addr = Bl ock to lock/unlock/lock-down (BA)

Data = 01h (Lock block)

D0h (Unlock block)

2Fh (Lockdown block)

Addr = Bl ock to lock/unlock/lock-down (BA)

Data = 90h

Addr = BBA + 02h

Block Lock status data

Addr = BBA + 02h

Confirm locking change on DQ[1:0].

(See Block Locking State Transitions Table

for valid combinations.)

Data = FFh

Addr = Any address in same partition

Bus

Operation Command Comments

LOCKING OPERAT IONS PROCEDURE

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 81

Note: T he ind ivi dual bits of the user segmen t of the prote ction re gis ter are OTP, not the regis ter in total.

The user may prog ram each O TP bit indiv idua ll y, one at a time, if desired. Aft er the prote ct ion

re g ister is loc ked, ho w ever, the entire us er s eg men t is l o cked and no mor e use r bi ts can b e

programmed.

The protec ti on reg is ter shares some of the same interna l fl ash resources as the paramet er pa rti ti on.

Therefore, RWW is only allowe d bet w een the prote ct ion re giste r and mai n part iti ons. Table 26

describes the operations allowed in the protection register, parameter partition, and main partition

during RWW and RWE.

13.2.1 Reading the Protection Register

Writing the Re ad Identifie r command allows the pro tecti on registe r data to be rea d 16 bits at a ti me

from addresses shown in Table 21, “Device Identification Codes” on page 61. The protection

regist er is rea d from the Read Ide nti fie r comma nd and can be read in any parti tio n.Writing the

Read Arra y comma nd re turns the devi ce to read-a rray mode.

13.2.2 Programing the Protection Register

The Prot ec ti on P rogra m c om ma nd should be issu ed on ly a t th e pa ramet er (t op or bottom) part iti on

followe d by the data to be prog ram med at the specifi ed loca ti on. It progra ms the upper 64 bi ts of

the pro tecti on register 16 bi ts at a time . Table 21, “Device Id ent ifi ca ti on Code s ” on pa ge 61 shows

allow ab le addresses. See al s o Figure 33, “Protection Regis te r Prog ram m ing Flowchart” on

page 82. Issui ng a Prot ec tio n Prog ram comma nd out side t he reg iste r’s address space re su lts in a

S ta tus Regi s te r error (SR[4]=1).

Ta ble 26. Simultaneous Operations Allowed with the Protection Register

Protection

Parameter

Partition

Array Data

Main

Partitions Description

Read See

Description Write/Erase Whi le p r ogra mmi ng or e r as ing i n a ma in p art iti on , the p r otec ti on r eg is ter ca n be

read from any other partition. Reading the parameter partition data is not

allowed if the protection register is being read from addresses within the

parameter partition.

See

Description Read Write/Erase W hil e programm ing or erasing in a ma in pa rtition, read operations are allowed

in the parameter partition. Accessing the protection registers from parameter

partition addresses is not allowed.

Read Read Write/Erase While programming or eras ing i n a m ain partition, read operations a re allowed

in the parameter partition. Accessing the protection registers in a partition that

is different from the one being programmed o r e rased, and als o different from

the parameter partition, is allowed.

Write No Access

Allowed Read W hile programming the protection r egister, reads are o nly a llowed in the other

main partitions. Access to the parameter partition is not allowed. This is

becau s e programming of the prot ection register can o nly occur in the

parameter partition, so it will exist in status mode.

No Access

Allowed Write/Erase Read While progr amming or e rasing the parameter partition, reads of the protection

registers are not allowed in any partition. Reads in other main partitions are

supported.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

82 Order Numbe r: 290701 , Revision: 015

13.2.3 Lo cki ng the Protectio n Regis ter

PR-LK.0 is programmed to 0 by Intel to protect the unique device number. PR-LK.1 can be

programmed by the user to lock the user port ion (u pper 64 bits) of the prote ct ion regis ter (S ee

Fi gure 34, “Prot ecti on Register Locking“). This bit is set using the Protection Program command

to progra m “ FFFDh” into PR-L K.

After PR-LK reg iste r bits are programmed (l ocked), the protection re gis t er’s st ored values ca n’t be

cha nged. Protec tion Program commands writ ten to a locked sec tion result in a S tatus Re gister error

(SR [4]=1, SR[5]=1).

Figure 33. Protection Register Programming Flowchart

FULL STATUS CHECK PROCEDURE

Protection Program operations ad dresses must be within the

protection register address space. Addresses outside thi s

space will return an error.

Repeat for subsequent programming operations.

Full status register check can be done after each program or

after a sequence of program operations.

SR[3] MUST be cleared before t he WSM will allow further

program attempts.

Only the Clear Staus Register command clears SR[4:3,1].

If an error is detected, clear the status register before

attempting a program retry or other error recovery.

Yes

1,1

1,0

1,1

PROTECTION REGISTER PROGRAMMING PROCEDURE

Start

Write C0h

Addr=Prot addr

Write Protect.

Address / Data

Read Status

SR[7] = 1?

Full Status

Check

(if desired)

Program

Complete

Read SRD

Program

Successful

SR[4:3] =

SR[4,1] =

Range Error

Programming Error

Locked-Register

Program Aborted

Standby

Bus

Operation Command

SR[1] SR[3] SR[4]

011V

Error

0 0 1 Protection regis ter

program error

Comments

Write

Standby

Protection

Program

Setup

Protection

Program

Data = C0h

Addr = Protection address

Data = Data to program

Addr = Protection address

Check SR[7]

1 = WS M Ready

0 = WSM Busy

Bus

Operation Command Comments

Read Read SRD

Toggle CE# or OE# to update SRD

Standby 1 0 1 Register locked;

Operation aborted

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 83

13.3 VPP Protection

The Intel® Wireless Flash Memory (W18) provides in-system program and erase at VPP1. Fo r

factory programming, it also includes a lo w-cost, backward-co mpa ti ble 12 V prog ram ming

feature.(S ection 11.2, “Facto ry Pr ogra mm ing” on page 66) Th e EFP f eatur e can also be used to

greatly im prove factory progra m performance as explaine d in Section 11.3, “Enhanced Factory

Progr am (EFP)” on pag e 67.

In addit ion to the flexi ble block lock ing, holding the VPP pro gramming voltage low can provi de

absolut e ha rdw are wr ite prote ct ion of all flash-device block s. If VPP is b elow VPPLK, program or

erase operations result in an error displayed in S R[3]. (See F igure 35.)

Note: If th e VCC supply can sink adequate current, you can use an appropriately valued resistor.

Figure 34. Protection Register Lo cking

0x84

0x88

0x85

0x81

0x80 PR Lock Register 0

User-Programmable

In tel Fac tory -Pr ogramme d

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure 35. Exam ples of V PP Power Supply Conf iguration s

•

12 V fa st pr ogramming

•

Absolute write protection with V

≤

PPLK

Syst em sup ply

(Note 1)

VCC

VPP

12 V supply

•

Low vol t a ge and 12 V fas t pr ogram m ing

Syst em sup ply

12 V supply

•

Low-voltage programming

•

Absolute write protection via logic signal

System supply

Prot# (logic signal)

•

Low-voltage programming

System supply

≤

10K

VCC

VPP

VCC

VPP

VCC

VPP

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

84 Order Numbe r: 290701 , Revision: 015

14.0 Set Read Configuration Register

The Set Read Configuration Register (RCR) command sets the burst order, frequency

confi guration, burst len gth, and ot her param et er s.

A two-bus cy cl e command seque nce initiate s thi s operation. The R ead Configurat ion Registe r data

is placed on the lower 16 bits of the addre s s bus (A[15:0]) during both bus cycl es. The Set Read

Configuratio n Re giste r command is wr i tt en a long with th e c onfi guration data (on the addres s bus ).

Thi s is follow e d by a secon d write that confi rm s th e operat ion an d aga in pre sents the Rea d

Confi guratio n Registe r data on the address bus . The Read Confi gurati on Register da ta is la tched on

the rising edg e of AD V#, CE #, or WE# (whi che ver occur s firs t). This comm and funct ions

inde pendently of the applie d VPP voltage. Afte r exe cut ing this comma nd, the devic e re turn s to

rea d-array mode . The Re ad Confi gurati on Regi ster’ s c ontent s can be examined by writ ing the Re ad

Ident ifi er c omm an d and then rea din g loca ti on 05h. See Table 27 and Table 28.

Table 27. Read Co nfiguratio n Register Summ ary

Read Mode

Res’d

First Access

Latency Count

WAIT Polarity

Data Outpu t Con fig

WAIT Config

Burst Seq

Clock Config

Res’d

Burst Wrap

Burst Length

RM R LC2 LC1 LC0 WT DOC WC BS CC R R BW BL2 BL1 BL0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Table 28. Read Co nfiguration Register Descr iptions (Sheet 1 of 2)

Bit Name Description1Notes

15 RM

Read Mode 0 = Synchro nous Bur st Reads Enabled

1 = Asynchronous Reads Enabl ed (De fault ) 2

14 RReserved 5

13-11 LC[2:0]

First Access Latency

Count

001 = Reserved

010 = Code 2

011 = Code 3

100 = Code 4

101 = Code 5

111 = Reserved (Default) 6

10 WT

WAIT Signal Polarity 0 = WAIT signal is asserted low

1 = WAIT signal is asse rt ed high (D efault ) 3

9DOC

Data Output

Configuration

0 = Hold Data for One Clock

1 = Hold Data for T wo Clock (Default) 6

8WC

WAIT Configuration 0 = W AIT Asserted During Delay

1 = W AIT Asserted One Data Cycle before Delay (Default) 6

7BS

Burst Sequence 1 = Linear Burst Order (Default)

6CC

Clock

Configuration

0 = Burst Sta rts and Data Output on Falling Clock Edge

1 = Burst Sta rts and Data Output on Rising Clock Edge

(Default)

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 85

5RReserved 5

4RReserved 5

3BW

Burst Wrap

0 = Wrap bursts within burst length set by CR[2:0]

1 = Don’t wrap accesses within burst length set by

CR[2:0].(Default)

2-0 BL[2:0]

Bur st Length

001 = 4-Word Burst

010 = 8-Word Burst

011 = 16-Word Burst

111 = Continuous Burst (Default)

Notes:

1. Undocumented combinations of bits are reserved by Intel for future implementations.

2. Synchronous and p age read mode con fi gurat ions affect read s from main bloc ks and parameter

blocks. Status Regist er and configurat io n reads support single read cycles. RCR[1 5]=1 disabl es

configuration set by RCR[14:0].

3. Data is not ready when WAIT is asserted.

4. Set the synchronous burst length. In asynchronous page mode, the page size equals four words.

5. Set all reserved Read Configuration Register bits to zero.

6. Sett ing th e Read C onfig urati on Regi ster for synchron ous bu r st-mode wi th a latency co unt of 2

(RCR[13:1 1 ] = 010), data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before

delay (RCR[8] =1) is not supported.

Table 28. Read Configuration Register Descriptions (Sheet 2 of 2)

Bit Name Description1Notes

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

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14.1 Read Mode (RCR[15])

All par tit ion s support two high-performance read config urat ions: synchronous burs t mo de and

asynchronous page m ode (de fau lt) . RCR[15] sets the read confi gura ti on to one of these mode s.

S tatus register , query, a nd ide ntifier m odes s upport o nly async hronous and si ngle-sync hronou s read

operations.

14.2 First Access Latency Count (RCR[13:11])

The First Acce s s Lat ency Count (RCR[13:11]) configurat ion tell s the devic e how many cl ocks

must elapse from ADV# de-assertion (VIH) before the first data word s hould be drive n onto its da ta

p ins. The inp u t clo ck freq uen cy d eterm in es t his val ue. See Table 28, “Read Configu ration Regis ter

Des cri pti ons ” on page 84 for laten cy values. F igure 36 shows data outpu t laten cy from ADV#

ass ert ion for di fferent latenci es. Refe r to Section 14.2.1, “Latency Count Settings” on page 87 for

Latency Code Settings.

Note: Other Fir st Access Lat ency Configurat ion settings ar e reserved .

)

Figure 36. First Access Laten cy Conf iguration

Code 5

Code 4

Code 3

Code 2

Valid

Address

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Address [A]

ADV# [V]

CLK [C]

D[1 5:0] [Q]

Figu re 37. Word Bou nd ary

0123456789ABCDEF

16 Word Boundary

Word 0 - 3 Word 4 - 7 Word 8 - B Word C - F

4 Word Boundary

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 87

Note: The 1 6- wor d boun dary is the en d of the devic e sense word-line.

14.2.1 Latency Count Settings

Notes: 1) RCR bits[9:8] must be set to 0 for latency count of 2.

Table 29. Latency Count Setting for VCCQ = 1.7 V - 1.95 V (90 nm lithogra phy )

VCCQ = 1.7 - 1.95 V Unit

tAVQV/tCHQV (60ns/11ns)

Latency Count Settings 2134, 5

Frequency Support < 40 < 61 < 66 MHz

Table 30. Latency Count Setting for VCCQ = 1.7 V - 2.24 V (130 nm lithogr aphy)

VCCQ = 1.7 - 2.24 V Unit

tAVQV/tCHQV (60ns/11ns) tAVQV/tCHQV (80ns/14ns)

Latency Count

Settings 2 3 4, 5 2 3 4, 5

Frequency

Support < 40 < 61 < 66 < 30 < 45 < 54 MH z

Ta bl e 31 . La te nc y C ou nt S et tings for V CCQ = 1.35 V - 1.8 V (130 nm lithography)

VCCQ = 1.35 V - 1.8 V Unit

tAVQV/tCHQV (65ns/14ns) tAVQV/tCHQV (85ns/20ns)

Latency Count

Settings 2 3, 4, 5 2 3, 4, 5

Frequency

Support < 39 < 54 < 30 < 40 MHz

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

88 Order Numbe r: 290701 , Revision: 015

14.3 WAIT Signal Polarity (RCR[10])

I f th e WAI T bit is clear ed (RC R [ 10]=0 ) , the n WAIT is co n fig ured to be as sert ed low. This means

tha t a 0 on the WA IT signal indicates that data is not ready and the da ta bus conta ins inva li d dat a.

Conversely, if RCR[10] is set, then WAIT is asserted hi gh. In either cas e, if WAIT is deasserted,

then data is ready and valid. WAIT is asserted during asynchronous page mode reads.

14.4 WAIT Si gnal Fun cti on

The WAIT signal ind icates data val id when the de vic e is ope rat ing in synchronous mode

(RCR[15]=0), and when add ress ing a partiti on tha t is curr ently in re ad-array mode. The WAIT

si gnal is only “d easse rte d” when d ata is val id on the bus.

Whe n th e de vic e i s oper at ing i n s ync hronous non-re ad- arra y m ode, such as re ad st at us , re ad ID , or

read q ue r y, WA I T is set to an “ass er t ed ” state as d eter m ined by R CR [ 1 0 ]. Se e Figure 12, “WAIT

Si gna l in Synch ronous N on-Re ad Array O pera ti on Wave form ” on page 39.

Whe n t he device i s operating in asynchronous page m ode or asynchronous single word read mode ,

WAIT is set to an “asserted” state as determined by RCR[10]. See Figure 8, “Page-Mode Read

Op era tio n Wave form ” on pag e 35, and Figure 6, “Asynchronous Read Operation Waveform” on

page 33.

Fro m a syste m per spec tiv e, the WAIT signal is in the asserte d s tate (bas ed on RCR[10]) when the

device is operating in s ynchronous non-read-array mode (such as Read ID, Read Query, or Read

S tatus), or if the device i s operati ng in a synchronous mode (RCR [15]= 1). In t hese cases, the sys tem

sof tware should i gnore (ma sk ) t he WAIT signal, beca us e it does not conve y a ny usefu l information

about the validity of what is appearing on the data bus.

Figure 38. Example: Latency Count Setting at 3

AMAX-0 (A)

DQ15-0 (D/Q)

CLK (C)

CE# (E)

ADV# (V)

R103

Valid

Output Valid

Output

High Z

tADD-DELAY tDATA

1nd0st 2rd 3th 4th

Valid Addre ss

Code 3

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 89

14.5 Data Hold (RCR[9])

The Da ta Output Confi guratio n (DOC) bit (RCR[ 9]) deter mines whe ther a data wo rd remains valid

on the data bus for one or two clock cyc le s. The proce s s or’s minimum data set -up ti me and the

flash memory’s clock-to-data outp ut delay dete rmi ne whethe r one or two cloc ks are neede d.

A DOC set at 1-cl ock data hold corre sponds to a 1-clo ck data cycle; a DO C se t at 2 -clock data hold

corre sponds to a 2-clo ck data cycle . The setting of thi s configura tion bit depe nds on the system and

CPU characteristics. For clarification, see Figure 39, “Data Output Configuration with WAIT

Sig nal Dela y” on pag e 90.

A method for determ ini ng thi s configuration setti ng is sho wn belo w.

To set the device at 1-clock data hold for subsequent reads, the following condition must be

satisfied:

tCHQV ( ns) + tDATA (n s) ≤ One CLK Period (ns)

As an example, use a clock frequency of 66 MHz and a clock period of 15 ns. Assume the data

output hold time is one clock. A pply this data to the formula above for the subsequent reads:

11 ns + 4 ns ≤ 15 ns

This eq uation is sati sfied, and dat a output will be ava ilable and val id at every cloc k period . If tDATA

is long, hol d for two cycle s .

Dur ing p age-m o d e reads, the initial access time can be determine d b y th e formula:

tADD- DEL AY (ns) + tDATA (ns) + tAVQV (ns)

Subse quent reads in page mode are defi ned by:

tAPA (ns) + tDATA (ns) (minimum time)

Table 32. WAIT Signal Conditions

CONDITION WAIT

CE# = VIH

CE# = VIL

Tri-State

Active

OE# No-Effect

Syn chronous Array Read Active

Syn chronous Non-Arra y Rea d Asse rted

All Asy nchronous Read and all Write Asse rte d

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flash M em ory (W18) Datasheet

90 Order Numbe r: 290701 , Revision: 015

Note: W AIT shown asserted high (RCR[10]=1).

14.6 WAIT Dela y ( RCR[8])

The WAIT configu rat ion bi t (RCR[8]) controls WAIT signa l delay behavi or for al l synchronous

rea d-array modes. Its setting depends on the system and CPU cha racte ristics. The WAIT can be

ass ert ed eithe r during, or one data cycle befo re, a valid out put.

In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-, 8-, 16-, or continuous-word

burs t mode, a n output delay may occ ur when a burst se quence cro sses its fi rst device-r ow bound ary

(16-w ord bounda ry). If the burst start a ddress is 4-wor d boundary aligned, the dela y does not occur.

If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read

sequence. The WAIT signal informs the system of this delay.

14.7 Burst Sequence (RCR[7])

The burs t sequence speci fie s the sy nchronous-bur st mo de da ta order (see Table 33, “Se que nce and

Burs t Length” on page 91). When operating in a linear burst mode , either 4-, 8-, or 16-word burs t

length with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the device may incur an

output delay when the burst sequen ce cross es the firs t 16-word bo unda ry. (See Figure 37, “Word

Boundary” on pa ge 86 for word boundary desc ript ion.) This d epe nds on the sta rti ng address. If the

st art ing address is aligned to a 4-word b oundary, there is no d elay. I f the st art ing address is the end

of a 4-word bou nda ry, the outp ut delay is one cloc k cycle less tha n the First Access Latency Co unt;

this is the worst-case delay. The delay take s pl ac e only onc e, and only if th e burst sequence cros s es

a 16-wo rd boun dary. The WAIT pin in forms the system of t his dela y. For timing dia grams of WAIT

f u n ctionality, see these f igures:

•Figure 9, “Single Synchronous Read-Array Operation Waveform” on page 36

•Figure 10, “Synchronous 4-Word Burst Read Operation Waveform” on page 37

Figu re 39. Data Output Co nfi gurat io n wi th WAIT Sign a l Del ay

DQ15-0 [Q ]

CLK [C]

Valid

Output Valid

Output

DQ15-0 [Q ] Valid

Output

1 CLK

Data Hold

WAIT (CR.8 = 1)

WAIT (CR.8 = 0)

tCHQV

WAIT (CR.8 = 0)

WAIT (CR.8 = 1)

2 CL K

Data Hold

tCHTL/H

Note 1

Valid

Output

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 91

•Figure 11, “WAIT Functi onal it y for EOW L (End-of-Word Line) Cond ition Waveform” on

page 38

14.8 Clock Edge (RCR[6])

Configuring the valid clock edge enables a flexible memory interface to a wide range of burs t

CPUs. Clock configuration sets the device to start a burst cycle, output data, and assert WAIT on

the clock ’s ris ing or fa lling edge.

Table 33. Sequence and Burst Length

Start Addr. (Dec)

Burst Addressing Sequence (Decimal)

4-W ord Burst

RCR[2:0]=001b 8-Word Burst

RCR[2:0]=010b 16-Word Burst

RCR[2:0]=011b Continuous Burst

RCR[2:0]=111b

Linear Linear Linear Linear

Wra p (RCR[3]=0)

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...

1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3...14-15-0 1-2-3-4-5-6-7-...

2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4...15-0-1 2-3-4-5-6-7-8-...

3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5...15-0-1-2 3-4-5-6-7-8-9-...

44-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3 4-5-6-7-8-9-10...

55-6-7-0-1-2-3-4 5-6-7...15-0-1...4 5-6-7-8-9-10-11...

66-7-0-1-2-3-4-5 6-7-8...15-0-1...5 6-7-8-9-10-11-12-...

77-0-1-2-3-4-5-6 7-8-9...15-0-1...6 7-8-9-10-11-12-13...

...

14 14-15-0-1...13 14-15-16-17-18-19-20-...

15 15-0-1-2-3...14 15-16-17-18-19-...

No-Wrap (RCR[3]=1)

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...

1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3...15-16 1-2-3-4-5-6-7-...

2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4...16-17 2-3-4-5-6-7-8-...

3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5...17-18 3-4-5-6-7-8-9-...

44-5-6-7-8-9-10-11 4-5-6...18-19 4-5-6-7-8-9-10...

55-6-7-8-9-10-11-12 5-6-7...19-20 5-6-7-8-9-10-11...

66-7-8-9-10-11-12-13 6-7-8...20-21 6-7-8-9-10-11-12-...

77-8-9-10-11-12-13-14 7-8-9...21-22 7-8-9-10-11-12-13...

...

14 14-15...28-29 14-15-16-17-18-19-20-...

15 15-16...29-30 15-16-17-18-19-20-21-...

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

92 Order Numbe r: 290701, Revision: 015

14.9 Burst Wrap (RCR[3])

The burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within the burst-

length boundary or whether they cross word-length boundaries to perform linear accesses. No-

wrap mode (RCR[3]= 1) enable s WAIT to hold off the syste m proc ess or, as it does in the

continuous burst mode, until valid data is available. In no-wrap mode (RCR[3]=0), the device

opera te s similarly to co nti nuous li nea r burst mo de but consum es less power du ring 4-, 8-, or 16-

word bursts.

For example, if RCR[3]=0 (wrap mode) and RCR[2:0] = 1h (4-word burst), possible linear burst

sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.

If RCR[3]= 1 (no-w ra p mod e) and RCR[2:0] = 1h (4-word burst leng th), then pos sible line a r burs t

sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR[3]=1 not only enables limited non-

ali gne d sequential bursts , but also redu ce s powe r by minim iz ing th e num ber of inte rnal read

operations.

Sett ing RCR[2:0] bits for con tin uous lin ea r burs t mod e (7h) also ach iev es the above 4-w ord burs t

sequences. However, significa ntl y more pow er may be cons ume d. The 1-2-3-4 seque nce, for

exa mple, consume s power durin g the initial acce ss, again during th e internal pipe line lookup as the

proce s so r rea ds word 2, and possibl y again, depending on system timing, near the end of the

seque nce as the devic e pipelines the next 4-word seque nce. RCR[3]= 1 whi le in 4-word burst mode

(no-wrap mode) reduces this excess power consumption.

14.10 Burst Length (RCR[2:0])

The Burst Len gth bit (BL[2 :0]) sele cts the number of w ords the device out puts in s ynchronous re ad

access of the flash mem ory arra y. The burst lengths are 4-word, 8-word, 16-word, a nd cont inu ous

word.

Conti nuous-burst accesses are linea r only, and do not wrap within any wor d l engt h boundarie s (s e e

Table 33, “Sequen ce and Burst Len gth” on page 91). When a burst cycle be gins, the devi ce outputs

synchronous burst data until it reaches the end of the “burstable” address space.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 93

Appendix A Write State Machine States

This ta ble shows the com ma nd stat e tr ansit ion s bas ed on incoming comman ds . Only one part it ion

can be active ly programming or eras ing at a time .

Figure 40. Write State Mach ine — Next State Table (Sheet 1 of 2)

Chip

Next State after Command Input

Read

Array(3) Program

Setup(4,5) Erase

Setup(4,5)

Enhanced

Factory

Pgm

Setup(4)

BE Confirm,

P/E Resume,

ULB

Confirm(9)

Program/

Erase

Suspend

Read

Status

Clear

Status

Read

ID/Query

(FFH) (10H/40H) (20H) (30H) (D0H) (B0H) (70H) (50H) (90H, 98H

)

Ready Ready Program

Setup Erase

Setup EFP

Setup Ready

Lock/CR Setup Ready (Lock Error) Ready Ready (Lock Error)

Setup OTP Busy

Busy

Setup Program Busy

Busy Progr am Busy Pgm Susp Program Busy

Suspend Progra m Suspend Pgm Bu sy Program Suspend

Setup Ready (Error) Erase Busy Ready (Error)

Busy Erase Busy Erase Susp Erase Busy

Suspend Erase

Suspend

Pgm in

Eras e

Susp Setup Erase Suspend Eras e Busy Erase Suspend

Setup Program in Erase Suspend Busy

Busy Program in Erase Suspend Bus y Pgm Susp in

Erase Susp

Program in Erase Suspend Busy

Suspend Program Suspend in Erase Suspend Pgm in Erase

Susp Busy

Program Suspend in Erase Suspend

Erase Suspend (Lock Error) Erase Susp Erase Suspend

(Lock Error)

Setup Ready (Error) EFP Busy Ready (Error)

EFP Busy

(7)

EFP Verify

Verify Busy

(7)

Output

Next State after Command Input

Status

ID/Query

Write State Machine (WSM) Next State Table

Outp ut Next State Table(1)

Lock/CR Setup,

Lock/CR Setup in Erase Susp

OTP Busy

Current Chip

State(8)

Ready,

Pgm Busy,

Pgm Suspend,

Erase Busy,

Erase Suspend,

Pgm In Erase Susp Busy,

Pgm Susp In Erase Susp

Pgm Setup,

Erase Setup,

OTP Setup,

Pgm in Erase Susp Setup,

EFP Setup,

EFP Busy,

Verify Busy

Lock/CR Setup in Erase

Suspend

Erase

Program

Program in

Erase Suspend

OTP

Enhanced

Factory

Program

Output

does not

change

Array(3) Status Output does not change Status

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

94 Order Numbe r: 290701, Revision: 015

Notes:

1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command

address.

A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued.

Each parti ti on stays in its last ou tput st ate ( Array, ID/CFI or St atus) until a new command change s it . The next WSM state

does not depend on the partition's output state.

For example, if par tition #1's output state i s Read Array and parti tion #4's output state is Read Sta tus, every read fr om

parti tion #4 (without issuing a ne w comm and) outputs t he Status r egis ter .

Figure 40. Write State Machine — Next State Tab le (Sheet 2 of 2)

Chip

Next State after Command Input

Lock,

Unlock,

Lock-down,

CR set u p(5)

OTP

Setup(5)

Lock

Block

Confirm(9)

Lock-

Down

Block

Confirm(9)

Write CR

Confirm(9)

Enhanced

Fact Pgm

Exit (blk add

<> WA0)

Illegal

commands or

EFP data(2)

(60H) (C0H) (01H) (2FH) (03H) (XXXXH) (other code s)

Ready Lock/CR

Setup OTP

Setup Ready

Lock/CR Setup Ready (Lock Error) Ready Ready Ready Ready (Lock Error)

Setup OTP Busy

Busy Ready

Setup P rogram Busy N/A

Busy Program Busy Ready

Suspend Program Suspend

Setup Ready (Error)

Busy Er ase Busy Erase Busy Ready

Suspend Lock/CR

Setup in

Erase Susp Erase Suspend

Setup Program in Erase Suspend Busy

Busy Program in Erase Suspend Busy Erase

Suspend

Suspend Program Suspend in Erase Suspend

Er ase Suspend

(Lock Error)

Erase Susp Erase Susp Erase Susp Erase Suspend (Lock Error)

Setup Ready (Error)

EFP Busy

(7) EFP Verify

EFP Busy

(7)

EFP Verify

Verify Bus y

(7) Ready

EFP Verify

(7) Ready

Output

Next State after Command Input

Status

Status Array Status

Write State Machine (WSM) Next State Table

Output Next State Table(1)

Program

Erase

Program in

Erase Suspend

Current Chip

State(8)

OTP

Lock/CR Setup in Erase

Suspend

Enhanced

Factory

Program

Output does

not change

Output does

not change

WSM

Operation

Completes

N/A

Output does not change ArrayStatus

Pgm Setup,

Erase Setup,

OTP Setup,

Pgm in Erase Susp Setup,

EFP Setup,

EFP Busy,

Verify Busy

Lock/CR Setup,

Lock/CR Setup in Erase Susp

OTP Busy

Ready,

Pgm Busy,

Pgm Suspend,

Erase Busy,

Erase Suspend,

Pgm In Erase Susp Busy ,

Pgm Susp In Erase Susp

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 95

2. Illeg al com m ands are tho s e not defined in t he command set.

3. All partit ions default to Read Arr ay mode at po wer-up. A Read Array com mand issued to a busy partit ion results in

undermined data when a partition address is read.

4. B oth cy cle s of 2 cyc le s comm an ds sh ould be issu ed to the sa me p arti tion add res s. If the y are i ssu ed to di ff e rent p art iti on s,

the second write determines the active partition. Both partitions will output status information when read.

5. If the WSM is active, both cycles of a 2 cycle com man d are ignored. This differs from p r evious Intel devi ces.

6. The Cl ear Statu s command clears Stat us Registe r error bits except when the W SM is running (Pgm Busy, Era s e Busy,

Pgm Busy In Erase Suspend, OTP Busy, EFP modes) o r s uspended (Erase Suspend, Pg m Suspend, Pgm Suspend In

Er ase Suspend).

7. EFP writes ar e allow ed on ly when S tatus Reg ister bit SR.0 = 0. EF P is busy if Block Address = a ddress at EF P Confirm

command. Any other commands are treated as data.

8. The "current state" is that of the WSM, not the partition.

9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then

mo ve to the Read y State.

10. In Erase suspe nd, the only valid tw o cycle commands ar e "Progra m Word", "Lock/U nlock/Lockdown Block", and "CR

Write". Both cycles of other two cycle commands ("OEM CAM program & confirm", "Program OTP & confirm", "EFP Setup

& confirm", "Erase setup & confirm") will be ignored. In Program suspend or Program suspend in Erase suspend, both

cy cles of a ll tw o cycle commands will be ignor ed.

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

96 Order Numbe r: 290701, Revision: 015

Appendix B Common Flash Interface (CFI)

Thi s appendix defines the data stru ct ure or “d ataba se” re turned by the Common Flas h Interfac e

(CF I) Qu ery comm an d. Sys te m softwa re should parse this structure to gain cri ti ca l infor ma ti on

such as block si ze, de ns it y, x8/x16, and elect ric al speci fic at ion s. O nce this inf ormati on has been

obta ine d, the softwa re wil l know w hic h comm and set s to use to enable f lash write s, bloc k era ses,

and oth erwise control the flash com pone nt. The Query is par t of an overal l spec ifi ca tio n for

multiple command set and control interface descriptions called Common Flash Interface, or CFI.

B.1 Query Structure Output

The Query dat ab ase allows s ys tem software to obtain infor mati on for cont rolling the flash device.

This section describes the device’s CFI-compliant interface that allows access to Query data.

Qu ery da ta are present ed on the lowest-order dat a outputs (DQ 0-7) onl y. The num erica l offset

val ue is the addre s s rela tiv e to the maximum bu s wid th support ed by th e dev ice. On this fam ily of

devi ce s, the Query table devi ce start ing a ddre ss is a 10h, which is a word addre ss for x16 devic es.

For a word-wide (x16) device, the first two Query-structure byte s , ASCII “Q” and “R,” a ppea r on

the low byte at w ord ad dress es 10h and 11h. This CF I-co mpl ia nt de vic e ou tput s 00h da ta on upper

b y tes. The device o u tp uts AS CI I “Q ” in the low b y te (DQ0-7) an d 00h in the high byt e (DQ8-15).

At Query addresses conta ini ng two or mor e byte s of inform at ion, the lea s t signi fic ant data byte is

presented at t he lower ad dress , and the mos t si gni fic ant da ta byte is pre sented at the higher add ress .

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suf fix h as bee n droppe d. In addit ion, since the upper byte of word-wi de de vic es is al ways

“00h, ” the leadi ng “00 ” has be en dropp ed from the table not at ion an d only th e lower byte valu e is

sho wn . Any x16 de vic e out puts ca n be assum ed to have 00h on the upper byte in this mode.

Table 34. Su mm ary of Qu ery Struc ture Ou tput as a Function of Device and Mode

Device Hex

Offset Hex

Code ASCII

Value

Device Addresses

00010 51 “Q”

00011 52 “R”

00012 59 “Y”

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 97

B.2 Quer y Struc tu re Over vi ew

The Que ry comma nd ca us es the flash co mponent to display th e Common Flas h Inte rfa ce (CFI)

Query structure or “database.” The structure sub-sections and address locations are summarized

below.

Table 36. Query Structure

Notes:

1. R efe r to the Q u ery Struct ure Out pu t sec tion an d o ff set 28 h fo r th e de tai led def ini tio n o f of fse t a ddre ss as

a fu nc t ion of devi ce bus wi dt h and mo de.

2. BA = B lock Addre ss beginning l ocation (i .e., 0800 0h is bloc k 1’s beginning location when th e block siz e

is 32K-word).

3. O ffset 15 defin es “P” which p oints to th e Primary Intel-spec ific Exten ded Query Table.

B.3 Block Status Register

The Block Stat us R egi s ter indi cate s whe ther an erase ope ration complete d succ ess fully or wheth er

a given block is locked or ca n be acce sse d for flash program /er a se operations.

Ta ble 35. Exam ple of Qu ery Structure Outp ut of x16 and x8 Devices

W ord Addres si ng Byte Addres s ing

Offset Hex Code Value Offset Hex Code Value

AX - A0D16 - D0AX - A0D7 - D0

00010h 0051 “Q” 00010h 51 “Q”

00011h 0052 “R” 00011h 52 “R”

00012h 0059 “Y” 00012h 59 “Y”

00013h P ID LO P rVend or 0 0013h P ID LO P rVendor

00014h P IDHI ID # 00014h P IDLO ID #

00015h PLO P rVe ndor 00015h P IDHI ID #

00016h PHI TblAdr 00016h ... ...

00017h A ID LO AltVendor 00017h ... ...

00018h A IDHI ID # 00018h ... . ..

Offset

Su b-Sect ion N ame

Description

(1)

00000h Manufacturer Code

00001h Device Code

(BA+2)h

(2)

Bl oc k Status r eg i s ter

Block -specif ic information

00004-Fh Reserved Reserved for vendor-specific information

00010h CFI query identification string Command set ID and vendor data offset

0001Bh System interface information Device tim ing & voltage information

00027h Device geometr y defini tion Flash device layout

P(3) Primary Intel-specific Extended Query Table V endo r-de fi ned ad ditional inf or m ation specific

to th e Pr imary Ve ndor Al gorit hm

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

98 Order Numbe r: 290701, Revision: 015

B loc k Era se S tatu s (BS R. 1) al lows sy stem sof twa re to de te rmin e the succ ess of th e last b loc k era se

opera ti on. BSR .1 can be used jus t after power-up to ve rify that the VCC supply wa s not

accidentally remove d during an era s e ope ration.

Table 37. Block Status Register

Notes:

1. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size

is 32K-word).

B.4 CFI Query Identification String

The Ident ifi ca tio n String provide s verifi cati on tha t the component supports the Comm on Fla sh

Inte rfac e spe cif icati on. I t also indic at es the speci ficat ion ve rs ion a nd sup port ed ve ndor-spe cifie d

command set(s).

Offset

Length

Description

Add.

Value

(BA+2)h

(1)

1 Block Lock Status Reg ist er BA+2 --0 0 or --01

B A+2 (bit 0) : 0 or 1

B A+2 (bit 1) : 0 or 1

BSR 2–7: Reserv ed for fu ture use BA+2 (bi t 2–7): 0

BSR.0 Block lock status

0 = Unl ocked

1 = Locked

BSR.1 Block lock- down status

0 = Not locked down

1 = Locked down

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revisio n: 015 99

Ta ble 39. System In terface Information

Table 38. CFI Identification

Offset Length Description Addr. Hex

Code Value

10h 3 Query-un ique AS CII str ing “ Q RY” 10:

11:

12:

--51

--52

--59

“Q”

“R”

“Y”

13h 2 Primary vendor command set and control interface ID code.

16-bit ID code for vendor-specific algorithms. 13:

14: --03

--00 —

15h 2 Ext ended Quer y Table primary algorithm address 15:

16: --39

--00 —

17h 2 Alter nate vendor comm and s et and control int erface ID code.

0000h means no second vendor-s pecified al gorithm exi sts. 17:

18: --00

--00 —

19h 2 Secondary algorithm Extended Query Table address.

0000h means none ex ists. 19:

1A: --00

--00 —

Offset Length Description Add.

Hex

Code Valu

1Bh 1 1B: --17 1.7V

1Ch 1 1C: --19 1.9V

1Dh 1 1D: --B4 11.4

1Eh 1 1E: --C6 12.6

1Fh 1

“n” such that typical single word program time-out = 2

µ- sec

1F: --04 16µs

20h 1

“n” such that typ ical max . buffer write time-o ut = 2

µ-sec

20: --00 NA

21h 1

“n” such that typical block erase time-out = 2

m-sec

21: --0A 1s

22h 1

“n” such that typical full chip erase time-out = 2

m-sec

22: --00 NA

23h 1

“n” such that m aximum word program time-o ut = 2

ti me s typical

23: --04 256µ

24h 1

“n” such tha t maxim um buf fer write time - out = 2

ti me s typical

24: --00 NA

25h 1

“n ” such that maxim um bl ock er ase time-o ut = 2

times typical

25: --03 8s

26h 1

“n” such that maximum chip erase time-out = 2

times typical

26: --00 NA

VCC logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

VCC logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

VPP [programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

VPP [programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

100 O rder Numbe r: 290701 , Revision: 015

B.5 Device Geometry Definition

Table 40. Device Geometry Definition

Offset Length Description

Code

27h 1

“n” such that device size = 2

in number of bytes

27:

See table below

76543210

28h 2 ————x64x32x16x828:--01x16

15 14 13 12 11 10 9 8

————————29:--00

2Ah 2

“n” such that max imum number of bytes in writ e buffer = 2

2A:

--00

2B: --00

2Ch 1 2C:

2Dh 4 Erase Bloc k Region 1 Inf ormation 2D:

bits 0–15 = y, y+1 = number of identical-siz e erase blocks 2E:

bits 16–31 = z, region erase block (s) size are z x 256 by tes 2F:

30:

31h 4 Erase Block Region 2 Info rmation 31:

bits 0–15 = y, y+1 = number of identical-siz e erase blocks 32:

bits 16–31 = z, region erase block (s) size are z x 256 by tes 33:

34:

35h 4 Res erved for future erase block region information 35:

36:

37:

38:

See table below

Number of erase block regions (x) within device :

1. x = 0 means no erase blocking; the device erases in bulk

2. x specifies the number of device regions with one or

more cont iguous same-size erase blocks.

3. Symm etricall y block ed partitions have one bloc king region

Flash device interface code as si gnment:

"n" such that n+1 specifies the bit field that repres ents the flash

device width capabilities as described in the table:

Address

32 Mbit

–B

–T

–B

–T

–B

–T

27: --16 --16 --17 --17 --18 --18

28: --01 --01 --01 --01 --01 --01

29: --00 --00 --00 --00 --00 --00

2A: --00 --00 --00 --00 --00 --00

2B: --00 --00 --00 --00 --00 --00

2C: --02 --02 --02 --02 --02 --02

2D: --07 --3E --07 --7E --07 --FE

2E: --00 --00 --00 --00 --00 --00

2F: --20 --00 --20 --00 --20 --00

30: --00 --01 --00 --01 --00 --01

31: --3E --07 --7E --07 --FE --07

32: --00 --00 --00 --00 --00 --00

33: --00 --20 --00 --20 --00 --20

34: --01 --00 --01 --00 --01 --00

35: --00 --00 --00 --00 --00 --00

36: --00 --00 --00 --00 --00 --00

37: --00 --00 --00 --00 --00 --00

38: --00 --00 --00 --00 --00 --00

64 Mbit

128 M bi t

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revision: 015 101

B.6 Intel- Specific Exte nded Query Table

Table 41. Primary Vendor-Sp ecific Extended Query

Offset

(1)

Length

Description

Hex

P = 39h

(Optional flash features and commands)

Add.

Code

Value

(P+0)h 3 Primary extended query table 39: --50 "P"

(P+1)h Unique ASCII string “PRI“ 3A: --52 "R"

(P+2)h 3B: --49 "I"

(P+3)h 1 Major version number, ASCII 3C: --31 "1"

(P+4)h 1 Minor version number, ASCII 3D: --33 "3"

(P+5)h 4 Optional feature and command support (1=yes, 0=no) 3E: --E6

(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 3F: --03

(P+7)h “1” then another 31 bit field of Optional features follows at 40: --00

(P+8)h the end of the bit–30 field. 41: --00

bit 0 Chip erase supported bit 0 = 0 No

bit 1 Suspend erase supported bit 1 = 1 Yes

bit 2 Suspend program supported bit 2 = 1 Yes

bit 3 Legacy lock/unlock supported bit 3 = 0 N o

bit 4 Queued erase supported bit 4 = 0 No

bit 5 Instant individual block locking supported bit 5 = 1 Yes

bit 6 Protection bits supported bit 6 = 1 Yes

bit 7 Pagemode read supported bi t 7 = 1 Yes

bit 8 Synchronous read supported bit 8 = 1 Yes

bit 9 Simultaneous operations support ed bi t 9 = 1 Yes

(P+9)h 1 42: --01

bit 0 Program supported after erase suspend bit 0 = 1 Yes

(P+A)h 2 Block status register mask 43: --03

(P+B)h bits 2–15 are Reserved; undefined bit s are “0” 44: --00

bit 0 Block Lock-Bit Stat us regist er active bit 0 = 1 Yes

bit 1 Block Lock-Down Bit Stat us active bit 1 = 1 Yes

(P+C)h 1 45: --18 1.8V

(P+D)h 1 46: --C0 12.0

Supported functions after suspend: read Array, Status, Query

Other supported operati ons are:

bits 1–7 reserved; undefined bits are “0”

VCC logic supply highest perf o rm ance program/erase voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

VPP optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

102 O rder Numbe r: 290701 , Revision: 015

Table 43. Burst Read Information for Non-muxe d Devi ce

Table 44. Partition and Erase-block Region Information

Table 42. Protection Register Information

Offset

P = 39h Lengt

hDescription

(Opt iona l Fl as h Fea t ur e s an d Co mm an ds) Add. Hex

Code Value

(P + E)h 1 Number of P r otectuib R egis ter fields in JEDEC ID space.

“00h” indicates that 256 protection fields are available. 47: --01 1

(P + E)h

(P + 10)h

(P + 11)h

(P + 12)h

Pr otec ti on Fi eld 1: P rotection Descrip tion

This field describes user-available One Time

Programmable (OTP) Protection Register bytes, Some

are p r e-pr ogramm ed wi th device-u niqu e seria l numb er s.

Others are user-programmable. Bits are 0-15 point to the

Pr otecti on Registe r lock by te, the section’s first byte. The

following bytes are factory pre-programmed and user-

programmable:

•bits 0-7 = Lock/bytes JEDEC-plane physical low address

•bites 8-15 = Lock/bytes JEDEC-plane physical hig h address

•bits 16-23 = “n” such that 2n = factory pre-programmed bytes

•bit s 24- 31 = “n” such that 2n = user -programmable bytes

48:

49:

4A:

4B:

--80

--00

--03

80h

00h

8 byte

Offset

(1)

Length

Description

Hex

P = 39h

(O ption a l flash features and commands)

Add.

Code

Value

(P+13)h 1 4C: --03 8 byt

(P+14)h 1 4D: --04 4

(P+15)h 1 4E: --01 4

(P+16)h 1 Synchronous mode read capability configuration 2 4F: --02 8

(P+17)h 1 Synchronous mode read capability configuration 3 50: --03 16

(P+18)h 1 Synchronous mode read capability configuration 4 51: --07 Con

Page Mode Read capability

bits 0–7 = “n” such that 2n H EX value re pr e sen t s the nu m ber of

read-pag e bytes . S e e off s et 28h fo r devic e word wid th to

dete r m i ne pag e- mode da t a output wi dth. 00h i n dic ates no

read page buffer.

Nu m ber of sy nch r on ous m ode read c onfigu r ation fields t h at

foll ow. 00h indicates no burs t capabi li ty.

Synchronous mode read capability configuration 1

Bits 3–7 = Rese r ve d

bits 0–2 “n” s uch t ha t 2 n+1 HEX value represents the

maximu m nu mber of continuous synchronous r eads when

the de vic e i s c onfigur ed f or its m axim um wo r d wi dth. A value

of 07h indicates that the device is capable of continuous

line ar bu r s t s t h at wil l ou tput data un t il the internal burst

coun ter reaches the end of the device’s bursta ble addr ess

space. This field’s 3-bit value can be written directly to the

Read Configu r ation R eg ister bit s 0– 2 i f the dev ice is

configured for its maximum wor d wid th. See offset 28h for

wo rd wi dth t o deter mi n e t h e burst data outpu t wi dth.

Offset

(1)

See table below

P = 39h

Description

Address

Bottom

Top

(O ption a l flash features and commands)

Len

Bot Top

(P+19)h (P+19)h 1 52: 52:Number of device hardw ar e-partiti on regi ons wit hin the de vice.

x = 0: a single hardware partition device (no fields follow).

x specifies the number of device partition regions containing

one or more contiguous erase block regions.

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revision: 015 103

Table 45. Partition Region 1 Information

Offset

(1)

See table below

P = 39h

Description

Address

Bottom

Top

(O ption a l flash features and commands)

Len

Bot Top

(P+1A)h (P+1A)h Nu m b er of identica l par titions wit hin t h e part ition re gion 2 53: 53:

(P+1B)h (P+1B)h 54: 54:

(P+1C)h (P+1C)h 1 55: 55:

(P+1D)h (P+1D)h 1 56: 56:

(P+1E)h (P+1E)h 1 57: 57:

(P+1F)h (P+1F)h 1 58: 58:

(P+2 0) h (P+ 20)h P ar tition Regio n 1 E ras e B l ock Ty pe 1 Infor mation 4 59: 59:

(P+2 1) h (P+ 21) h bi t s 0– 15 = y, y+1 = nu m ber of ide nti c al- s ize er as e bloc k s 5A: 5A :

(P+22)h (P+22)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 5B: 5B:

(P+23)h (P+23)h 5C: 5C:

(P+24)h (P+24)h P ar tition 1 (E ras e Bloc k Ty pe 1) 25D:5D:

(P+25)h (P+25)h Mini m um bloc k er as e c yc les x 100 0 5E: 5E:

(P+26)h (P+26)h 1 5F: 5F:

(P+27)h (P+27)h 1 60: 60:

(P+2 8) h Par tition Regio n 1 E ras e Block Ty pe 2 Informat io n 4 61 :

(P+2 9) h bi ts 0– 15 = y, y+1 = nu m ber of ide nti c al- s ize er as e bloc k s 62 :

(P+ 2A)h bits 16– 31 = z, reg ion era se block(s) size are z x 256 by tes 63:

(P+ 2B)h ( bottom paramet er device only) 64:

(P+2C)h

Partition

(Erase block Type 2)

65:

(P+2 D )h Mini m um bloc k er as e c yc les x 1000 66:

(P+2E)h 167:

(P+2F)h 168:

Simult aneo us pr ogram or erase oper ations allowed in other

partit ions while a partiti on in th is reg io n is in Prog ram m od e

bits 0–3 = nu m ber of sim u l tan eous Pr ogram op er a t ion s

bits 4–7 = nu m ber of sim u l tan eous Er as e op er ation s

Simult aneo us pr ogram or erase oper ations allowed in other

partit ions while a partiti on in th is reg io n is in Eras e m od e

bits 0–3 = nu m ber of sim u l tan eous Pr ogram op er a t ion s

bits 4–7 = nu m ber of sim u l tan eous Er as e op er ation s

Nu m ber of pro gr a m or er a se op er a t ion s al l ow ed in a pa r t i t ion

bits 0–3 = nu m ber of sim u l tan eous Pr ogram op er a t ion s

bits 4–7 = nu m ber of sim u l tan eous Er as e op er ation s

P arti tio n 1 ( er a s e bloc k Ty pe 1) bits per c ell; i nternal E CC

bits 0–3 = bi t s per cell in er a s e r egio n

bi t 4 = reserved for “internal ECC used” (1=yes, 0=no)

bi ts 5– 7 = reserve for future use

Partition 1 (erase block Type 1) page mode and synchronous

mode capabilities defined in Table 10.

bit 0 = pa ge-m ode host reads per mi tted (1=ye s , 0= no)

bit 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = s yn chrono us ho s t wri t e s permit ted ( 1= ye s, 0=no )

bits 3–7 = reserved for future use

P arti tio n 1 ( Er a se bl ock Ty pe 2) bi ts per cel l

bits 0–3 = bi t s per cell in er a s e r egio n

bi t 4 = reserved for “internal ECC used” (1=yes, 0=no)

bi ts 5– 7 = reserve for future use

P arti tio n 1 ( E ras e bloc k Type 2) pag emode an d syn c hr o nous

mode capabilities defined in Table 10

bit 0 = pa ge-m ode host reads per mi tted (1=ye s , 0= no)

bit 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = s yn chrono us ho s t wri t e s permit ted ( 1= ye s, 0=no )

bits 3–7 = reserved for future use

Types of erase block regions in this Partition Region.

x = 0 = no erase blocking; the Partition Region erases in bulk

x = number of er as e bloc k r egions w/ co nti g uous s ame-s ize

erase blocks. Symmetrically blocked partiti ons hav e one

blocking region. Partition size = (Type 1 blocks)x(Type 1

block sizes) + (Typ e 2 blocks)x(Type 2 block sizes) +…+

(Type n blocks)x(Type n block sizes)

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

104 O rder Numbe r: 290701 , Revision: 015

Notes:

1. The variable P is a pointer which is defined at CFI offs et 15h.

2. TPD - Top parameter device; BPD - Bottom parameter device.

3. Par ti tion: Each pa rtitio n is 4-Mbit in si ze. It can co ntain ma in blocks O R a com binat ion of both main and

parameter bloc ks.

4. Partition Region: Symmetrical partitions form a partition region. There are two partition regions: A

c ontains all the parti tions that ar e m ade up of main blocks o nly; B co ntains the par tition made up of the

parameter and t he mai n blocks.

Table 46. Pa rtition and Erase Block Region Informati on

Address

32 Mbit

–B

–T

–B

–T

–B

–T

52: --02 --02 --02 --02 --02 --02

53: --01 --07 --01 --0F --01 --1F

54: --00 --00 --00 --00 --00 --00

55: --11 --11 --11 --11 --11 --11

56: --00 --00 --00 --00 --00 --00

57: --00 --00 --00 --00 --00 --00

58: --02 --01 --02 --01 --02 --01

59: --07 --07 --07 --07 --07 --07

5A: --00 --00 --00 --00 --00 --00

5B: --20 --00 --20 --00 --20 --00

5C: --00 --01 --00 --01 --00 --01

5D: --64 --64 --64 --64 --64 --64

5E: --00 --00 --00 --00 --00 --00

5F: --01 --01 --01 --01 --01 --01

60: --03 --03 --03 --03 --03 --03

61: --06 --01 --06 --01 --06 --01

62: --00 --00 --00 --00 --00 --00

63: --00 --11 --00 --11 --00 --11

64: --01 --00 --01 --00 --01 --00

65: --64 --00 --64 --00 --64 --00

66: --00 --02 --00 --02 --00 --02

67: --01 --06 --01 --06 --01 --06

68: --03 --00 --03 --00 --03 --00

69: --07 --00 --0F --00 --1F --00

6A: --00 --01 --00 --01 --00 --01

6B: --11 --64 --11 --64 --11 --64

6C: --00 --00 --00 --00 --00 --00

6D: --00 --01 --00 --01 --00 --01

6E: --01 --03 --01 --03 --01 --03

6F: --07 --07 --07 --07 --07 --07

70: --00 --00 --00 --00 --00 --00

71: --00 --20 --00 --20 --00 --20

72: --01 --00 --01 --00 --01 --00

73: --64 --64 --64 --64 --64 --64

74: --00 --00 --00 --00 --00 --00

75: --01 --01 --01 --01 --01 --01

76: --03 --03 --03 --03 --03 --03

64Mbit 128Mbit

Intel® Wireless Flash Memory (W18)

Datasheet Intel® Wireless Flash Memory (W18) 07-Dec-2005

Order Number: 290701, Revision: 015 105

Appen dix C Ordering Informati on

Figure 41. VF BGA Ordering Information

ackage:

E = VF BGA, Leaded

H = VF BGA, Pb-free

roduct Li ne Desi gnat or :

or all I nt el F l as h P roduct s

evi ce Densi t y:

20 = 3 2 Mbit

40 = 6 4 Mbit

28 = 128Mbit

Product Fam i l y:

W 18 = Intel

Wireless Flas

Memory

Param et er Locat i on:

T = Top Paramet er

B = Bottom Parameter

Proces s Identi f ier:

C = 180 nm

D = 130 nm

E = 90 nm

A ccess Sp eed (ns)

(60,80)

G E 2 8 F 6 4 0 W 1 8 T E 6 0

Fig ure 42. S C S P Orderi ng Inform ati on

ackage:

D = S C SP , Le ad ed

F = SCSP, Pb-Free

roduct Li ne:

8F = F l as h Onl y

lash Den si ty:

= N o die

= 12 8 M bi t

roduct Family Desi gnator :

= Intel

Wireless Flash Memory

Voltage:

= 1.8 Volt I/ O

Bal lout I ndi cat or:

Q= QUA D+

Parameter Location

T = Top P arameter

B = Bottom Parameter

Devi ce Detai ls :

0 = Initial Version

Fla sh 1 &

Fla sh 3 &

Fla sh 1

Fla sh 2

Fla sh 3

Fla sh 4

R D 4 8 F 3 0 0 0 W 0 Y B Q 0

Intel® Wir eless Flash M emory (W18)

07-Dec-2005 Intel® Wireless Flas h Memor y (W18) Datasheet

106 O rder Numbe r: 290701 , Revision: 015

§ §

Table 47. W18 Fami l y: Available Produc t Ordering I nform ati on

I/O

Voltage

(V) F las h Densit y

Package

Pa rt Numbe r

Size (mm) Ballout

Name Ballout

Type

1.8

32 Mbit 9x7.7x1.0 VF BGA

Leaded

GE28F320W18TD60

GE28F320W18BD60

GE28F320W18TE60

GE28F320W18BE60

Lead Free

PH28F320W18TD60

PH28F320W18BD60

PH28F320W18TE60

PH28F320W18BE60

64 Mbit 9x7.7x1.0 VF BGA

Leaded

GE28F640W18TD60

GE28F640W18BD60

GE28F640W18TE60

GE28F640W18BE60

GE28F640W18TD80

GE28F640W18BD80

Lead Free

PH28F640W18TD60

PH28F640W18BD60

PH28F640W18TE60

PH28F640W18BE60

128 M bit

9x11x1.0 VF BGA Leaded GE28F128W18TD60

GE28F128W18BD60

Lead Free PH28F128W18TD60

PH28F128W18BD60

10x8x1.2 SCSP Leaded RD48F3000W0YTQ0

RD48F3000W0YBQ0

Lead Free PF48F3000W0YTQ0

PF48F3000W0YBQ0