LT3029
1
3029fa
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Dual 500mA/500mA
Low Dropout, Low Noise,
Micropower Linear Regulator
The LT
®
3029 is a dual, micropower, low noise, low drop-
out linear regulator. The device operates either with a
common input supply or independent input supplies for
each channel, over an input voltage range of 1.8V to 20V.
Each output supplies up to 500mA of output current with
a typical dropout voltage of 300mV. Quiescent current is
well controlled in dropout. With an external 10nF bypass
capacitor, output noise is only 20μVRMS over a 10Hz to
100kHz bandwidth. Designed for use in battery-powered
systems, the low 55μA quiescent current per channel makes
it an ideal choice. In shutdown, quiescent current drops to
less than 1μA. Shutdown control is independent for each
channel, allowing for fl exible power management.
The LT3029 optimizes stability and transient response with
low ESR ceramic output capacitors, requiring a minimum
of only 3.3μF. The regulator does not require the addition
of ESR, as is common with other regulators.
Internal circuitry provides reverse-battery protection,
reverse-current protection, current limiting with foldback
and thermal shutdown. The device is available as an
adjustable output voltage device with a 1.215V reference
voltage. The LT3029 is offered in the thermally enhanced
16-lead MSOP and 16-lead, low profi le (4mm × 3mm ×
0.75mm) DFN packages.
2.5VIN to 1.5V/1.8V Application
n Output Current: 500mA per Channel
n Low Dropout Voltage: 300mV
n Low Noise: 20μVRMS (10Hz to 100kHz)
n Low Quiescent Current: 55μA per Channel
n Wide Input Voltage Range: 1.8V to 20V (Common or
Independent Input Supply)
n Adjustable Output: 1.215V Reference Voltage
n Very Low Quiescent Current in Shutdown: <1μA per
Channel
n Stable with 3.3μF Minimum Output Capacitor
n Stable with Ceramic, Tantalum or Aluminum
Electrolytic Capacitors
n Reverse-Battery and Reverse Output-to-Input
Protection
n Current Limit with Foldback and Thermal Shutdown
n Tracking/Sequencing Capability: Compatible with
LTC292X Power Supply Tracking ICs
n Thermally Enhanced 16-Lead MSOP and 16-Lead
(4mm × 3mm) DFN Packages
n General Purpose Linear Regulator
n Battery-Powered Systems
n Microprocessor Core/Logic Supplies
n Post Regulator for Switching Supplies
n Tracking/Sequencing Power Supplies
Dropout Voltage vs Load Current
VOUT1
1.8V
500mA
VOUT2
1.5V
500mA
237k
1%
10nF 3.3μF
113k
1%
3029 TA01
OUT2
ADJ2
BYP2
GND 237k
1%
10nF 3.3μF
54.9k
1%
OUT1
ADJ1
BYP1
LT3029
IN1
VIN
2.5V
3.3μF
SHDN1
IN2
SHDN2
OUTPUT CURRENT (mA)
0
DROPOUT VOLTAGE (mV)
400
350
300
250
200
150
100
50
0400
3029 TA01b
100 200 300 500
50 450
150 250 350
TJ = 25°C
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LT3029
2
3029fa
ABSOLUTE MAXIMUM RATINGS
IN1, IN2 Pin Voltage ................................................±22V
OUT1, OUT2 Pin Voltage .........................................±22V
Input-to-Output Differential Voltage ........................±22V
ADJ1, ADJ2 Pin Voltage ............................................±9V
BYP1, BYP2 Pin Voltage ........................................±0.6V
SHDN1 , SHDN2 Pin Voltage ..................................±22V
Output Short-Circuit Duration .......................... Indefi nite
(Note 1)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
ADJ1
SHDN1
IN1
IN1
IN2
IN2
SHDN2
ADJ2
BYP1
NC
OUT1
OUT1
GND
OUT2
OUT2
BYP2
TOP VIEW
DE PACKAGE
16-LEAD
(
4mm s 3mm
)
PLASTIC DFN
TJMAX = 125°C, θJA = 38°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB GND
ADJ1
SHDN1
IN1
IN1
IN2
IN2
SHDN2
ADJ2
BYP1
NC
OUT1
OUT1
GND
OUT2
OUT2
BYP2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
MSE PACKAGE
16-LEAD PLASTIC MSOP
17
GND
TJMAX = 125°C (LT3029E/LT3029I, LT3029MP), θJA = 37°C/W, θJC: 5°C/W TO 10°C/W
TJMAX = 150°C (LT3029H), θJA = 37°C/W, θJC: 5°C/W TO 10°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB GND
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3029EDE#PBF LT3029EDE#TRPBF 3029 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3029IDE#PBF LT3029IDE#TRPBF 3029 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3029EMSE#PBF LT3029EMSE#TRPBF 3029 16-Lead Plastic MSOP –40°C to 125°C
LT3029IMSE#PBF LT3029IMSE#TRPBF 3029 16-Lead Plastic MSOP –40°C to 125°C
LT3029HMSE#PBF LT3029HMSE#TRPBF 3029 16-Lead Plastic MSOP –40°C to 150°C
LT3029MPMSE#PBF LT3029MPMSE#TRPBF 3029 16-Lead Plastic MSOP –55°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3029EDE LT3029EDE#TR 3029 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3029IDE LT3029IDE#TR 3029 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3029EMSE LT3029EMSE#TR 3029 16-Lead Plastic MSOP –40°C to 125°C
LT3029IMSE LT3029IMSE#TR 3029 16-Lead Plastic MSOP –40°C to 125°C
LT3029HMSE LT3029HMSE#TR 3029 16-Lead Plastic MSOP –40°C to 150°C
LT3029MPMSE LT3029MPMSE#TR 3029 16-Lead Plastic MSOP –55°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Operating Junction Temperature (Notes 2, 12)
LT3029E ............................................. –40°C to 125°C
LT3029I .............................................. –40°C to 125°C
LT3029H ............................................ –40°C to 150°C
LT3029MP.......................................... –55°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
(MSOP Only) ..................................................... 300°C
LT3029
3
3029fa
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3029 is tested and specifi ed under pulse load conditions
such that TJ ≈ TA. The LT3029E is 100% tested at TA = 25°C. Performance
of the LT3029E over the full –40°C to 125°C operating junction
temperature range is assured by design, characterization and correlation
with statistical process controls. The LT3029I is guaranteed over the full
–40°C to 125°C operating junction temperature range. The LT3029MP is
100% tested and guaranteed over the –55°C to 125°C operating junction
temperature range. The LT3029H is tested at 150°C operating junction
temperature. High junction temperatures degrade operating lifetimes.
Operating lifetime is derated at junction temperatures greater than 125°C.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Notes 3, 11) ILOAD = 500mA l1.8 2.3 V
ADJ1, ADJ2 Pin Voltage (Notes 3, 4, 9) VIN = 2V, ILOAD = 1mA
2.3V < VIN < 20V, 1mA < ILOAD < 500mA (E, I, MP)
2.3V < VIN < 20V, 1mA < ILOAD < 500mA (H)
l
l
1.203
1.191
1.173
1.215
1.215
1.215
1.227
1.239
1.239
V
V
V
Line Regulation (Note 3) ΔVIN = 2V to 20V, ILOAD = 1mA l0.5 5 mV
Load Regulation (Note 3) VIN = 2.3V, ΔILOAD = 1mA to 500mA
VIN = 2.3V, ΔILOAD = 1mA to 500mA (E, I, MP)
VIN = 2.3V, ΔILOAD = 1mA to 500mA (H)
l
l
2.5 6
15
32
mV
mV
mV
Dropout Voltage
VIN = VOUT(NOMINAL)
(Notes 5, 6, 11)
ILOAD = 10mA
ILOAD = 10mA l
0.11 0.18
0.25
V
V
ILOAD = 50mA
ILOAD = 50mA l
0.16 0.22
0.31
V
V
ILOAD = 100mA
ILOAD = 100mA l
0.2 0.25
0.34
V
V
ILOAD = 500mA
ILOAD = 500mA l
0.3 0.36
0.46
V
V
GND Pin Current (per Channel)
VIN = VOUT(NOMINAL)
(Notes 5, 7)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 250mA
ILOAD = 500mA
l
l
l
l
l
l
55
90
1.1
2
4.3
10
150
250
2
3.5
8
16
μA
μA
mA
mA
mA
mA
Output Voltage Noise COUT = 10μF, CBYP = 10nF, ILOAD = 500mA,
BW = 10Hz to 100kHz
20 μVRMS
ADJ1/ADJ2 Pin Bias Current ADJ1, ADJ2 (Notes 3, 8) 30 100 nA
Shutdown Threshold VOUT = Off to On
VOUT = On to Off
l
l0.20
0.45
0.40
1.1 V
V
SHDN1/SHDN2 Pin Current (Note 10) VSHDN1, VSHDN2 = 0V
VSHDN1, VSHDN2 = 20V
l
l
0
0.6
0.5
3
μA
μA
Quiescent Current in Shutdown (per Channel) VIN = 6V, VSHDN1 = 0V, VSHDN2 = 0V 0.01 0.1 μA
Ripple Rejection VIN = 2.715V (Avg), VRIPPLE = 0.5VP-P,
fRIPPLE = 120Hz, ILOAD = 500mA
55 67 dB
Current Limit (Note 9) VIN = 7V, VOUT = 0V
VIN = 2.3V, ΔVOUT = –0.1V l520
1.5 A
mA
Input Reverse Leakage Current VIN = –20V, VOUT = 0V l1mA
Reverse Output Current VOUT = 1.215V, VIN = 0V 0.5 10 μA
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 2)
Note 3: The LT3029 is tested and specifi ed for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
Note 4: Maximum junction temperature limits operating conditions. The
regulated output voltage specifi cation does not apply for all possible
combinations of input voltage and output current. When operating at
maximum input voltage, limit the output current range. When operating at
maximum output current, limit the input voltage range.
Note 5: To satisfy minimum input voltage requirements, the LT3029 is
tested and specifi ed for these conditions with an external resistor divider
(two 243k resistors) for an output voltage of 2.437V. The external resistor
divider adds 5μA of DC load on the output.
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specifi ed output current. In dropout, the
output voltage equals: VIN – VDROPOUT.
LT3029
4
3029fa
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Dropout Voltage Guaranteed Dropout Voltage
Dropout Voltage vs Temperature Quiescent Current (per Channel)
ELECTRICAL CHARACTERISTICS
Note 7: GND pin current is tested with VIN = 2.437V and a current source
load. This means the device is tested while operating in its dropout region
or at the minimum input voltage specifi cation. This is the worst-case
GND pin current. The GND pin current decreases slightly at higher input
voltages. Total GND pin current equals the sum of output 1 and output 2
GND pin currents.
Note 8: ADJ1/ADJ2 pin bias current fl ows into the pin.
Note 9: The LT3029 contains current limit foldback circuitry. See the
Typical Performance Characteristics for current limit as a function of the
VIN – VOUT differential voltage.
Note 10: SHDN1/SHDN2 pin current fl ows into the pin.
Note 11: The LT3029 minimum input voltage specifi cation limits dropout
voltage under some output voltage/load conditions. See the curve of
Minimum Input Voltage in the Typical Performance Characteristics.
Note 12: The LT3029 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature exceeds the maximum operating junction temperature when
overtemperature protection is active. Continuous operation above the
specifi ed maximum operating junction temperature may impair device
reliability.
OUTPUT CURRENT (mA)
500
450
400
350
300
250
200
150
100
50
0
DROPOUT VOLTAGE (mV)
3029 G01
0 50 100 150 200 250 300 350 400 450 500
TJ = 150°C
TJ = 25°C
TJ = 125°C
TJ = –55°C
OUTPUT CURRENT (mA)
500
450
400
350
300
250
200
150
100
50
0
GUARANTEED DROPOUT VOLTAGE (mV)
3029 G02
0 50 100 150 200 250 300 350 400 450 500
TJ = 150°C
TJ = 25°C
= TEST POINTS
TEMPERATURE (°C)
500
450
400
350
300
250
200
150
100
50
0
DROPOUT VOLTAGE (mV)
3029 G03
–75 –50 –25 0 25 50 75 100 125 150 175
IL = 500mA
IL = 100mA
IL = 250mA
IL = 50mA
IL = 10mA
IL = 1mA
TEMPERATURE (°C)
QUIESCENT CURRENT (μA)
3029 G04
–75 –50 –25 0 25 50 75 100 125 150 175
VIN = 6V
RL = 243k, IL = 5μA
150
125
100
75
50
25
0
VSHDN = VIN
TJ = 25°C, unless otherwise noted.
LT3029
5
3029fa
ADJ1 or ADJ2 Pin Voltage Quiescent Current (per Channel)
TYPICAL PERFORMANCE CHARACTERISTICS
GND Pin Current (per Channel) GND Pin Current (per Channel)
GND Pin Current vs ILOAD
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
TEMPERATURE (°C)
ADJ PIN VOLTAGE (V)
3029 G05
–75 –50 –25 0 25 50 75 100 125 150 175
IL = 1mA
1.239
1.233
1.227
1.221
1.215
1.209
1.203
1.197
1.191
INPUT VOLTAGE (V)
160
140
120
100
80
60
40
20
0
QUIESCENT CURRENT (μA)
3029 G06
0246810 12 14 16 18 20
TJ = 25°C
RL = 243k
VOUT = 1.215V
VSHDN = VIN
VSHDN = 0V
INPUT VOLTAGE (V)
GND PIN CURRENT (mA)
3029 G07
01234567 8910
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TJ = 25°C
FOR VOUT = 1.215V
RL = 24.3Ω, IL = 50mA
RL = 1.215kΩ, IL = 1mA
RL = 121.5Ω, IL = 10mA
INPUT VOLTAGE (V)
GND PIN CURRENT (mA)
3029 G08
01234567 8910
16
14
12
10
8
6
4
2
0
TJ = 25°C
FOR VOUT = 1.215V
RL = 2.43Ω, IL = 500mA
RL = 12.15Ω, IL = 100mA
RL = 4.05Ω, IL = 300mA
OUTPUT CURRENT (mA)
GND PIN CURRENT (mA)
3029 G09
0 50 100 150 200 250 300 350 400 450 500
TJ = 25°C
VIN = VOUT(NOMINAL) + 1V
16
14
12
10
8
6
4
2
0
TEMPERATURE (°C)
SHDN PIN THRESHOLD (V)
3029 G10
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
IL = 1mA
–75 –50 –25 0 25 50 75 100 125 150 175
TJ = 25°C, unless otherwise noted.
LT3029
6
3029fa
TYPICAL PERFORMANCE CHARACTERISTICS
Current Limit
TEMPERATURE (°C)
CURRENT LIMIT (A)
3029 G16
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VIN = 7V
VOUT = 0V
–75 –50 –25 0 25 50 75 100 125 150 175
Current Limit
INPUT VOLTAGE (V)
CURRENT LIMIT (A)
3029 G15
0246810 12 14 16 18 20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VOUT = 0V
TJ = 150°C
TJ = 25°C
TJ = –55°C
TJ = 125°C
SHDN1 or SHDN2 Pin
Input Current ADJ1 or ADJ2 Pin Bias Current
TEMPERATURE (°C)
SHDN PIN INPUT CURRENT (μA)
3029 G13
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VSHDN = 20V
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
ADJ PIN BIAS CURRENT (nA)
3029 G14
–75 –50 –25 0 25 50 75 100 125 150 175
150
135
120
105
90
75
60
45
30
15
0
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
SHDN1 or SHDN2 Pin
Input Current
TEMPERATURE (°C)
SHDN PIN THRESHOLD (V)
3029 G11
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–75 –50 –25 0 25 50 75 100 125 150 175
IL = 1mA
IL = 500mA
SHDN PIN VOLTAGE (V)
SHDN PIN INPUT CURRENT (μA)
3029 G12
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0246810 12 14 16 18 20
TJ = 25°C
TJ = 25°C, unless otherwise noted.
LT3029
7
3029fa
Reverse Current Input Ripple Rejection
Input Ripple Rejection Input Ripple Rejection
Minimum Input Voltage Channel-to-Channel Isolation
TEMPERATURE (°C)
REVERSE CURRENT (μA)
3029 G17
300
270
240
210
180
150
120
90
60
30
0
VIN = 0V
VADJ = VOUT = 1.215V
IADJ FLOWS INTO ADJ PIN TO GND PIN
IOUT FLOWS INTO OUT PIN TO IN PIN
–75 –50 –25 0 25 50 75 100 125 150 175
IADJ
IOUT
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
100 1k 10k 100k 1M 10M
3029 G18
10
40
50
60
70
80
30
20
10
0
90
100 TJ = 25°C
IL = 500mA
VIN = VOUT(NOMINAL) +1V + 50mVRMS RIPPLE
CBYP = 0 COUT = 10μF
COUT = 3.3μF
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
100 1k 10k 100k 1M 10M
3029 G19
10
40
50
60
70
80
30
20
10
0
90
100
TJ = 25°C
IL = 500mA
VIN = VOUT(NOMINAL) +1V + 50mVRMS RIPPLE
COUT = 10μF
CBYP = 0.01μF
CBYP = 1000pF
CBYP = 100pF
TEMPERATURE (°C)
RIPPLE REJECTION (dB)
3029 G20
100
90
80
70
60
50
40
30
20
10
0
VIN = VOUT(NOMINAL) + 1.5V + 0.5VP-P RIPPLE
f = 120Hz
IL = 500mA
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
MINIMUM INPUT VOLTAGE (V)
3029 G21
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–75 –50 –25 0 25 50 75 100 125 150 175
IL = 1mA
IL = 500mA
VOUT = 1.215V
FREQUENCY (Hz)
CHANNEL-TO-CHANNEL ISOLATION (dB)
100 1k 10k 100k 1M 10M
3029 G22
10
40
50
60
70
80
30
20
10
0
90
100
GIVEN CHANNEL IS TESTED WITH 50mVRMS
SIGNAL ON OPPOSING CHANNEL, BOTH
CHANNELS DELIVERING FULL CURRENT
TJ = 25°C
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
LT3029
8
3029fa
OUTPUT NOISE SPECTRAL DENSITY (μV/Hz)
FREQUENCY (kHz)
0.01
0.1
10
3029 G25
1
VOUT = 5V
VOUT = VADJ
TJ = 25°C
COUT = 10μF
CBYP = 0
IL = 500mA
0.01 1 10 1000.1
FREQUENCY (kHz)
OUTPUT NOISE SPECTRAL DENSITY (μV/Hz)
0.01 1 10 100
3029 G26
0.1
10
1
0.1
0.01
VOUT = 5V
VOUT =VADJ
TJ = 25°C
COUT = 10μF
IL = 500mA
CBYP =
100pF
CBYP = 0.01μF
CBYP = 1000pF
CBYP (pF)
10
80
OUTPUT NOISE (μVRMS)
100
120
160
140
100 1000 10000
3029 G27
60
40
20
0
VOUT = 5V
VOUT = 1.215V
TJ = 25°C
COUT = 10μF
IL = 500mA
fBW = 10Hz TO 100kHz
Channel-to-Channel Isolation Load Regulation
TYPICAL PERFORMANCE CHARACTERISTICS
Output Noise Spectral Density Output Noise Spectral Density
RMS Output Noise
vs Bypass Capacitor
RMS Output Noise
vs Load Current
TEMPERATURE (°C)
LOAD REGULATION (mV)
3029 G24
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–75 –50 –25 0 25 50 75 100 125 150 175
ΔIL = 1mA TO 500mA
LOAD CURRENT (mA)
0.01
OUTPUT NOISE (μVRMS)
160
140
120
100
80
60
40
20
0
0.1 1 10010
3029 G28
VOUT = 5V
VOUT =VADJ
VOUT = 5V
VOUT =VADJ
TJ = 25°C
COUT = 10μF
C
BYP = 0
C
BYP = 10nF
50μs/DIV
VOUT1
50mV/DIV
VOUT2
50mV/DIV
3029 G23
COUT1 = 10μF
COUT2 = 10μF
CBYP1 = CBYP2 = 0.01μF
ΔIL1 = 50mA TO 500mA
ΔIL2 = 50mA TO 500mA
VIN = 6V, VOUT1 = VOUT2 = 5V
TJ = 25°C, unless otherwise noted.
LT3029
9
3029fa
1ms/DIV
VOUT
100μV/DIV
3029 G29
COUT = 10μF
IL = 500mA
VOUT = 5V
10Hz to 100kHz Output Noise,
CBYP = 0pF
10Hz to 100kHz Output Noise,
CBYP = 100pF
10Hz to 100kHz Output Noise,
CBYP = 1000pF
10Hz to 100kHz Output Noise,
CBYP = 0.01μF
1ms/DIV
VOUT
100μV/DIV
3029 G30
COUT = 10μF
IL = 500mA
VOUT = 5V
1ms/DIV
VOUT
100μV/DIV
3029 G31
COUT = 10μF
IL = 500mA
VOUT = 5V
1ms/DIV
VOUT
100μV/DIV
3029 G32
COUT = 10μF
IL = 500mA
VOUT = 5V
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
LT3029
10
3029fa
200μs/DIV
200mV/DIV
250mA/DIV
VOUT DEVIATION
LOAD CURRENT DEVIATION
3029 G33
VIN = 6V
CIN = 10μF
COUT = 10μF
IL = 100mA
TJ = 25°C
VOUT = 5V
20μs/DIV
50mV/DIV
250mA/DIV
VOUT DEVIATION
LOAD CURRENT DEVIATION
3029 G34
VIN = 6V
CIN = 10μF
COUT = 10μF
IL = 100mA
TJ = 25°C
VOUT = 5V
1ms/DIV
VOUT
1V/DIV
SHDN
VOLTAGE
2V/DIV
3029 G35
VIN = 2.5V
COUT = 10μF
RL = 3Ω
IL = 500mA
VOUT = 1.5V
1ms/DIV
VOUT
1V/DIV
SHDN
VOLTAGE
2V/DIV
3029 G36
VIN = 2.5V
COUT = 10μF
RL = 3Ω
IL = 500mA
VOUT = 1.5V
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response, CBYP = 0pF Transient Response, CBYP = 0.01μF
Start-Up Time from Shutdown,
CBYP = 0pF
Start-Up Time from Shutdown,
CBYP = 0.01μF
TJ = 25°C, unless otherwise noted.
LT3029
11
3029fa
PIN FUNCTIONS
BYP1/BYP2 (Pin 1/Pin 8): Bypass. Use the BYP1/BYP2
pins to bypass the reference of the LT3029 regulator and
achieve low output noise performance. Internal circuitry
clamps the BYP1/BYP2 pins to ±0.6V (one VBE) from
ground. A small capacitor from the corresponding output
to this pin bypasses the reference to lower the output
voltage noise. Using a maximum value of 10nF reduces
the output voltage noise to a typical 20μVRMS over a 10Hz
to 100kHz bandwidth. If not used, this pin must be left
unconnected.
NC (Pin 2): No Connect. This pin is not connected to
any internal circuitry. It may be fl oated, tied to VIN or tied
to GND.
OUT1/OUT2 (Pins 3, 4/Pins 6, 7): Output. The outputs
supply power to the loads. A minimum 3.3μF output ca-
pacitor prevents oscillations on each output. Applications
with large output load transients require larger values of
output capacitance to limit peak voltage transients. See
the Applications Information section for more on output
capacitance and reverse output characteristics.
GND (Pin 5, 17): Ground. The exposed pad (Pin 17) of
the DFN and MSOP packages is an electrical connection
to GND. To ensure proper electrical and thermal perfor-
mance, solder Pin 17 to the PCB ground and tie directly
to Pin 5. Connect the bottom of the output voltage setting
resistor divider directly to GND (Pin 5) for optimum load
regulation performance.
IN1/IN2 (Pins 13, 14/Pins 11, 12): Inputs. The IN1/IN2
pins supply power to each channel. The LT3029 requires
a bypass capacitor at the IN1/IN2 pins if located more
than six inches away from the main input fi lter capacitor.
Include a bypass capacitor in battery-powered circuits,
as a battery’s output impedance rises with frequency. A
bypass capacitor in the range of 1μF to 10μF suffi ces. The
LT3029’s design withstands reverse voltages on the IN pins
with respect to ground and the OUT pins. In the case of
a reversed input, which occurs if a battery is plugged in
backwards, the LT3029 acts as if a diode is in series with
its input. No reverse current fl ows into the LT3029 and no
reverse voltage appears at the load. The device protects
itself and the load.
SHDN1 /SHDN2 (Pin 15/Pin 10): Shutdown. Pulling the
SHDN1 or SHDN2 pin low puts its corresponding LT3029
channel into a low power state and turns its output off. The
SHDN1 and SHDN2 pins are completely independent of
each other, and each SHDN pin only affects operation on
its corresponding channel. Drive the SHDN1 and SHDN2
pins with either logic or an open collector/drain with pull-up
resistors. The resistors supply the pull-up current to the
open collectors/drains and the SHDN1 or SHDN2 current,
typically less than 1μA. If unused, connect the SHDN1 and
SHDN2 to their corresponding IN pins. Each channel will
be in its low power shutdown state if its corresponding
SHDN pin is not connected.
ADJ1/ADJ2: (Pin 16/Pin 9) Adjust Pin. These are the error
amplifi er inputs. These pins are internally clamped to ±9V.
A typical input bias current of 30nA fl ows into the pins
(see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature
in the Typical Performance Characteristics section). The
ADJ1 and ADJ2 pin voltage is 1.215V referenced to ground
and the output voltage range is 1.215V to 19.5V.
LT3029
12
3029fa
The LT3029 is a dual 500mA/500mA low dropout regulator
with independent inputs, micropower quiescent current
and shutdown. The device supplies up to 500mA from each
channel’s output at a typical dropout voltage of 300mV.
The two regulators share a common GND pin and are
thermally coupled. However, the two inputs and outputs of
the LT3029 operate independently. Each channel can be
shut down independently, but a thermal shutdown fault
on either channel shuts off the output on both channels.
The addition of a 10nF reference bypass capacitor lowers
output voltage noise to 20μVRMS over a 10Hz to 100kHz
bandwidth. Additionally, the reference bypass capacitor
improves transient response of the regulator, lowering
the settling time for transient load conditions. The low
operating quiescent current (55μA per channel) drops to
less than 1μA in shutdown. In addition to the low quies-
cent current, the LT3029 regulator incorporates several
protection features that make it ideal for use in battery-
powered systems. Most importantly, the device protects
itself against reverse input voltages. Current limiting with
foldback necessitates a minimum load current of 20μA
for input/output voltage differentials of more than 10V to
keep the output regulated.
Adjustable Operation
Each of the LT3029’s channels has an output voltage range
of 1.215V to 19.5V. Figure 1 illustrates that output voltage
is set by the ratio of two external resistors. The device
regulates the output to maintain the corresponding ADJ
pin voltage at 1.215V referenced to ground. R1’s current
equals 1.215V/R1. R2’s current equals R1’s current plus
the ADJ pin bias current. The ADJ pin bias current, 30nA at
25°C, fl ows through R2 into the ADJ pin. Use the formula
in Figure 1 to calculate output voltage. Linear Technology
recommends that the value of R1 be less than 243k to
minimize errors in the output voltage due to the ADJ pin bias
current. In shutdown, the output turns off and the divider
current is zero. Curves of ADJ Pin Voltage vs Temperature
and ADJ Pin Bias Current vs Temperature appear in the
Typical Performance Characteristics section.
APPLICATIONS INFORMATION
Figure 1. Adjustable Operation
IN1/IN2
3029 F01
C
LT3029
OUT1/OUT2
VIN
VOUT
ADJ1/ADJ2
GND R1
R2
Linear Technology tests and specifi es each LT3029 channel
with its ADJ pin tied to the corresponding OUT pin for a
1.215V output voltage. Specifi cations for output voltages
greater than 1.215V are proportional to the ratio of desired
output voltage to 1.215V:
VOUT
1.215V
For example, load regulation on either output for an output
current change of 1mA to 500mA is typically –2.5mV at
VOUT = 1.215V. At VOUT = 2.5V, load regulation is:
2.5V
1.215V •(−2.5mV) =−5.14mV
Table 1 shows 1% resistor divider values for some com-
mon output voltages with a resistor divider current of
approximately 5μA.
Table 1. Output Voltage Resistor Divider Values
VOUT
(V)
R1
(k)
R2
(k)
1.5 237 54.9
1.8 237 113
2.5 243 255
3 232 340
3.3 210 357
5 200 619
VOUT =1.215V 1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟+IADJ
()
R2
()
VADJ =1.215V
IADJ =30nA AT 25°C
OUTPUT RANGE = 1.215V TO 19.5V
LT3029
13
3029fa
APPLICATIONS INFORMATION
Bypass Capacitance and Low Noise Performance
Using a bypass capacitor connected between a channel’s
BYP pin and its corresponding OUT pin signifi cantly low-
ers LT3029 output voltage noise, but is not required in
all applications. Linear Technology recommends a good
quality low leakage capacitor. This capacitor bypasses
the regulator’s reference, providing a low frequency noise
pole. A 10nF bypass capacitor introduces a noise pole that
decreases output voltage noise to as low as 20μVRMS.
Using a bypass capacitor provides the added benefi t of
improving transient response. With no bypass capacitor,
and a 10μF output capacitor, a 100mA to 500mA load step
settles to within 1% of its fi nal value in approximately
100μs. With the addition of a 10nF bypass capacitor and
evaluating the same load step, output voltage excursion
stays within 1% (see Transient Response in the Typical
Performance Characteristics section). Using a bypass
capacitor makes regulator start-up time proportional to
the value of the bypass capacitor. For example, a 10nF
bypass capacitor and 10μF output capacitor slow start-up
time to 15ms.
Output Capacitance and Transient Response
The LT3029 design is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stabil-
ity, most notably with small capacitors. Linear Technology
recommends a minimum output capacitor of 3.3μF with
an ESR of 3Ω, or less, to prevent oscillations. The LT3029
is a micropower device, and output transient response is
a function of output capacitance. Larger values of output
capacitance decrease the peak deviations and provide
improved transient response for larger load current
changes.
Ceramic capacitors require extra consideration. Manufac-
turers make ceramic capacitors with a variety of dielectrics,
each with different behavior across temperature and
applied voltage. The most common dielectrics specify
the EIA temperature characteristic codes of Z5U, Y5V,
X5R and X7R. Z5U and Y5V dielectrics provide high C-V
products in a small package at low cost, but exhibit strong
voltage and temperature coeffi cients, as shown in Figures
2 and 3. When used with a 5V regulator, a 16V 10μF Y5V
capacitor can exhibit an effective value as low as 1μF to
2μF for the applied DC bias voltage and over the operat-
ing temperature range. X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and
is available in higher values.
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3029 F02
20
0
–20
–40
–60
–80
–100 04810
26 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
3029 F03
–25 0 50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
Figure 2. Ceramic Capacitor DC Bias Characteristics
Figure 3. Ceramic Capacitor Temperature Characteristics
LT3029
14
3029fa
APPLICATIONS INFORMATION
Exercise care even when using X5R and X7R capacitors;
the X5R and X7R codes only specify operating temperature
range and maximum capacitance change over temperature.
Capacitance change due to DC bias (voltage coeffi cient)
with X5R and X7R capacitors is better than with Y5V and
Z5U capacitors, but can still be signifi cant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as case size increases.
Linear Technology recommends verifying expected versus
actual capacitance values at operating voltage in situ for
an application.
Voltage and temperature coeffi cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
Figure 4’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
VOUT
500μV/DIV
3029 F04
100ms/DIV
COUT = 10μF
CBYP = 0.01μF
ILOAD = 500mA
Thermal Considerations
The LT3029’s power handling capability limits the maximum
rated junction temperature (125°C, LT3029E/LT3029I/
LT3029MP or 150°C, LT3029H). Two components comprise
the power dissipated by each channel:
1. Output current multiplied by the input/output voltage
differential: (IOUT)(VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
(IGND)(VIN).
Ground pin current is found by examining the GND Pin
Current curves in the Typical Performance Characteristics
section.
Power dissipation for each channel equals the sum of the
two components listed above. Total power dissipation for
the LT3029 equals the sum of the power dissipated by
each channel.
The LT3029’s internal thermal shutdown circuitry protects
both channels of the device if either channel experiences
an overload or fault condition. Activation of the thermal
shutdown circuitry turns both channels off. If the overload
or fault condition is removed, both outputs are allowed
to turn back on. For continuous normal conditions, do
not exceed the maximum junction temperature rating of
125°C (LT3029E/LT3029I/LT3029MP) or 150°C (LT3029H).
Carefully consider all sources of thermal resistance from
junction-to-ambient, including additional heat sources
mounted in proximity to the LT3029. For surface mount
devices, use the heat spreading capabilities of the PC board
and its copper traces to accomplish heat sinking. Copper
board stiffeners and plated through-holes can also spread
the heat generated by power devices.
The following tables list thermal resistance as a function
of copper area in a fi xed board size. All measurements
were taken in still air on a four-layer FR-4 board with 1oz
solid internal planes, and 2oz external trace planes with a
total board thickness of 1.6mm. For further information
on thermal resistance and using thermal information, refer
to JEDEC standard JESD51, notably JESD51-12.
LT3029
15
3029fa
APPLICATIONS INFORMATION
Table 2. DE Package, 16-Lead DFN
COPPER AREA THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*BACKSIDE BOARD AREA
2500mm22500mm22500mm236°C/W
1000mm22500mm22500mm237°C/W
225mm22500mm22500mm238°C/W
100mm22500mm22500mm240°C/W
*Device is mounted on topside.
Table 3. MSE Package, 16-Lead MSOP
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*BACKSIDE
2500mm22500mm22500mm235°C/W
1000mm22500mm22500mm236°C/W
225mm22500mm22500mm237°C/W
100mm22500mm22500mm239°C/W
*Device is mounted on topside.
The junction-to-case thermal resistance (θJC), measured
at the Exposed Pad on the back of the die, is 4.3°C/W for
the DFN package, and 5°C/W to 10°C/W for the MSOP
package.
Calculating Junction Temperature
Example: Channel 1’s output voltage is set to 1.8V. Chan-
nel 2’s output voltage is set to 1.5V. Each channel’s input
voltage is 2.5V. Each channel’s output current range is
0mA to 500mA. The application has a maximum ambient
temperature of 50°C. What is the LT3029’s maximum
junction temperature?
The power dissipated by each channel equals:
I
OUT(MAX)(VIN – VOUT) + IGND(VIN)
where for each output:
IOUT(MAX) = 500mA
VIN = 2.5V
IGND at (IOUT = 500mA, VIN = 2.5V) = 8.5mA
So, for output 1:
P = 500mA (2.5V – 1.8V) + 8.5mA (2.5V) = 0.37W
For output 2:
P = 500mA (2.5V – 1.5V) + 8.5mA (2.5V) = 0.52W
The thermal resistance is in the range of 35°C/W to 40°C/W,
depending on the copper area. So, the junction temperature
rise above ambient temperature approximately equals:
(0.37W + 0.52W) 39°C/W = 34.7°C
The maximum junction temperature then equals the maxi-
mum ambient temperature plus the maximum junction
temperature rise above ambient temperature, or:
T
JMAX = 50°C + 34.7°C = 84.7°C
Protection Features
The LT3029 regulator incorporates several protection fea-
tures that make it ideal for use in battery-powered circuits.
In addition to the normal protection features associated
with monolithic regulators, such as current limiting and
thermal limiting, the device protects itself against reverse
input voltages and reverse voltages from output to input.
The two regulators have independent inputs, a common
GND pin and are thermally coupled. However, the two
channels of the LT3029 operate independently. Each
channel’s output can be shut down independently, and
a fault condition on one output does not affect the other
output electrically, unless the thermal shutdown circuitry
is activated.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
each output of the LT3029. For normal operation, do not
allow the junction temperature to exceed 125°C (LT3029E/
LT3029I/LT3029MP) or 150°C (LT3029H). The typical ther-
mal shutdown temperature threshold is 165°C and the
circuitry incorporates approximately 5°C of hysteresis.
Each channel’s input withstands reverse voltages of 22V.
Current fl ow into the device is limited to less than 1mA
(typically less than 100μA) and no negative voltage appears
at the respective channel’s output. The device protects
both itself and the load against batteries that are plugged
in backwards.
The LT3029 incurs no damage if either channel’s output
is pulled below ground. If the input is left open-circuit, or
grounded, the output can be pulled below ground by 22V.
The output acts like an open circuit, and no current fl ows
from the output. However, current fl ows in (but is limited
by) the external resistor divider that sets the output voltage.
LT3029
16
3029fa
APPLICATIONS INFORMATION
The LT3029 incurs no damage if either ADJ pin is pulled
above or below ground by 9V. If the input is left open
circuit or grounded, the ADJ pins perform like an open
circuit down to –1.5V, and then like a 1.2k resistor down
to –9V when pulled below ground. When pulled above
ground, the ADJ pins perform like an open circuit up to
0.5V, then like a 5.7k resistor up to 3V, then like a 1.8k
resistor up to 9V.
In situations where an ADJ pin connects to a resistor
divider that would pull the pin above its 9V clamp volt-
age if the output is pulled high, the ADJ pin input current
must be limited to less than 5mA. For example, assume
a resistor divider sets the regulated output voltage to
1.5V, and the output is forced to 20V. The top resistor of
the resistor divider must be chosen to limit the current
into the ADJ pin to less than 5mA when the ADJ pin is
at 9V. The 11V difference between the OUT and ADJ pins
divided by the 5mA maximum current into the ADJ pin
yields a minimum top resistor value of 2.2k.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled
to ground, pulled to some intermediate voltage or is left
open-circuit. Current fl ow back into the output follows the
curve shown in Figure 5.
If either of the LT3029’s IN pins is forced below its cor-
responding OUT pin, or the OUT pin is pulled above its
corresponding IN pin, input current for that channel typi-
cally drops to less than 2μA. This occurs if the IN pin is
connected to a discharged (low voltage) battery, and either
a backup battery or a second regulator circuit holds up
the output. The state of that channel’s SHDN pin has no
effect on the reverse output current if the output is pulled
above the input.
Overload Recovery
Like many IC power regulators, the LT3029 has safe
operating area (SOA) protection. The safe area protec-
tion decreases current limit as input-to-output voltage
increases and keeps the power transistor inside a safe
operating region for all values of input-to-output voltage.
The protective design provides some output current at
all values of input-to-output voltage up to the specifi ed
maximum operational input voltage of 20V.
When power is fi rst applied, as input voltage rises, the
output follows the input, allowing the regulator to start-up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents.
With a high input voltage, an event can occur wherein
removal of an output short will not allow the output to
recover. The event occurs with a heavy output load when
the input voltage is high and the output voltage is low.
Common situations occur immediately after the removal
of a short-circuit or if the shutdown pin is pulled high after
the input voltage has already been turned on. The load line
intersects the output current curve at two points creating
two stable output operating points for the regulator. With
this double intersection, the input power supply may need
to be cycled down to zero and brought up again to make
the output recover.
Figure 5. Reverse Output Current
OUTPUT VOLTAGE (V)
REVERSE CURRENT (mA)
3029 F05
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
TJ = 25°C
VIN = 0V
VADJ = VOUT
IADJ FLOWS INTO ADJ PIN TO GND PIN
IOUT FLOWS INTO OUT PIN TO IN PIN
0123456789
IADJ
IOUT
LT3029
17
3029fa
PACKAGE DESCRIPTION
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.15 REF
1.70 ± 0.05
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE16) DFN 0806 REV Ø
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
3.30 ±0.05
3.30 ±0.10
0.45 BSC
0.23 ± 0.05
0.45 BSC
LT3029
18
3029fa
PACKAGE DESCRIPTION
MSOP (MSE16) 0608 REV A
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16
161514131211 10
12345678
9
9
18
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
0.50
(.0197)
BSC
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 p 0.102
(.112 p .004)
2.845 p 0.102
(.112 p .004)
4.039 p 0.102
(.159 p .004)
(NOTE 3)
1.651 p 0.102
(.065 p .004)
1.651 p 0.102
(.065 p .004)
0.1016 p 0.0508
(.004 p .002)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.280 p 0.076
(.011 p .003)
REF
4.90 p 0.152
(.193 p .006)
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev A)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35
REF
LT3029
19
3029fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 3/11 Added Overload Recovery section to Applications Information 16
LT3029
20
3029fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 0311 REV A • PRINTED IN USA
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VIN: 2.1V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD < 1μA,
Low Noise: < 40μVRMS, “A” Version Stable with Ceramic Capacitors;
DD, TO220-5, SOT223, S8 and TSSOP Packages
LT1964 200mA, Low Noise Micropower,
Negative LDO
VIN: –1.9V to –20V, VOUT(MIN) = –1.22V, VDO = 0.34V, IQ = 30μA, ISD = 3μA,
Low Noise: <30μVRMS, Stable with Ceramic Capacitors, ThinSOT Package
LT1965 1.1A, Low Noise LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.20V, VDO = 0.31V, IQ = 0.5mA, ISD < 1μA,
Low Noise: <40μVRMS, Stable with Ceramic Capacitors; 3mm × 3mm DFN,
MS8E, DD-Pak and TO-220 Packages
LT3020 100mA, Low Voltage VLDO VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.15V, IQ = 120μA, ISD < 3μA;
3mm × 3mm DFN and MS8 Packages
LT3021 500mA, Low Voltage VLDO VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.16V, IQ = 120μA, ISD < 3μA;
5mm × 5mm DFN and SO8 Packages
LT3023 Dual 100mA, Low Noise,
Micropower LDO
VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 40μA, ISD < 1μA;
DFN and MS10E Packages
LT3024 Dual 100mA/500mA, Low Noise,
Micropower LDO
VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 60μA, ISD < 1μA;
DFN and TSSOP-16E Packages
LTC3025 300mA, Low Voltage Micropower VLDO VIN: 0.9V to 5.5V, Low IQ: 54μA, Low Noise < 80μVRMS, 45mV Dropout Voltage;
2mm × 2mm 6-Lead DFN Package
LTC3026 1.5A, Low Input Voltage VLDO VIN: 1.14V to 5.5V, Low IQ: 950μA, Low Noise < 110μVRMS, 100mV Dropout Voltage;
10-Lead 3mm × 3mm DFN and MS10E Packages
LT3027 Dual 100mA, Low Noise, Micropower
LDO with Independent Inputs
VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 50μA, ISD < 1μA;
DFN and MS10E Packages
LT3028 Dual 100mA/500mA, Low Noise, Micropower
LDO with Independent Inputs
VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.32V, IQ = 60μA, ISD < 1μA;
DFN and TSSOP-16E Packages
LT3080/
LT3080-1
1.1A, Parallelable, Low Noise LDO VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Low Noise < 40μVRMS, 300mV Dropout Voltage
(2-Supply Operation), Current-Based Reference with 1-Resistor VOUT Set, Directly
Parallelable (No Op Amp Required), Stable with Ceramic Capacitors;
TO-220, SOT-223, MS8E and 3mm × 3mm DFN Packages
ThinSOT is a trademark of Linear Technology Corporation.
VOUT1
1.8V
500mA
VOUT2
1.5V
500mA
237k
1%
10nF 3.3μF
113k
1%
3029 TA02
OUT2
ADJ2
BYP2
GND 237k
1%
10nF 3.3μF
54.9k
1%
OUT1
ADJ1
BYP1
LT3029
LTC2923
IN1
VCC
3.3μF
SHDN1
IN2
SHDN2
SDO
FB2
GND
RAMP
GATE
FB1
ON
TRACK1
RAMPBUF
TRACK2
2.5V
3.3V
3.3μF
63.4k
1%
54.9k
1%
90.9k
1%
113k
1%
0.1μF
3.3V
CGATE
0.1μF
ON
OFF
1M
Coincident Tracking Supply Application
10ms/DIV
VOUT1
VOUT2
500mV/DIV
3029 TA02b
