EMIF08-LCD04M16 8-line L-C IPADTM, EMI filter and ESD protection in Micro QFN Features High cut off frequency low-pass filter: FC = 400 MHz at -6 dB High efficiency in EMI filtering: better than -35 dB from 900 MHz to 2 GHz Very low PCB space consuming with plastic micro-package 3.3 x 1.35 mm Very thin package: 0.55 mm High efficiency in ESD (IEC 61000-4-2 level 4) High reliability offered by monolithic integration High reducing of parasitic elements through integration Micro QFN 3.3 x 1.35 16L Figure 1. Device configuration Low-pass Filter 0000 Input Output ECOPACK(R)2 compliant component Complies with the following standards IEC 61000-4-2 level 4: - 15 kV (air discharge) - 8 kV (contact discharge) GND Where EMI filtering in ESD sensitive equipment is required: LCD and camera for mobile phones Computers and printers Communication systems MCU boards GND Description Applications GND The EMIF08-LCD04M16 is a 8-line inductorcapacitor (LC) EMI filter designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences requiring a large bandwidth. This filter includes an ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up 15 kV contact discharge. TM: IPAD is a trademark of STMicroelectronics. November 2009 Doc ID 15673 Rev 2 1/10 www.st.com 10 Electrical characteristics 1 EMIF08-LCD04M16 Electrical characteristics Table 1. Absolute maximum ratings (Tamb = 25 C) Symbol Parameter Value Unit 15 kV VPP ESD discharge IEC 61000-4-2, contact discharge Top Operating temperature range -40 to 85 C Tj Maximum junction temperature 125 C -55 to 150 C Tstg Storage temperature range Figure 2. Electrical characteristics (definitions) I Symbol VBR IRM VRM VCL Rd IPP IR T VF Table 2. = = = = = = = = = IF V VCL VBR VRM IRM IR IPP Electrical characteristics (Tamb = 25 C) Symbol Test conditions Min. Typ. Max. Unit VBR IR = 1 mA 6 - - V IRM VRM = 3 V per line - - 100 nA Inductance - 12 - nH VR = 3 V DC, F = 1 MHz, Vosc = 30 mV 17 18 19 pF R Parasitic resistance of the inductance 9 12.5 20 FC 50 source and 50 load termination at -6 dB - 400 - MHz L Cline 2/10 Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Breakdown current Voltage temperature coefficient Forward voltage drop Doc ID 15673 Rev 2 EMIF08-LCD04M16 Figure 3. 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 Electrical characteristics S21 attenuation measurements Figure 4. Analog crosstalk measurements dB I2 I3 I4 I5 I6 I7 I8 - O2 #1 O3 #1 O4 #1 O5 #1 O6 #1 O7 #1 O8 #1 F/Hz F/Hz 100k Figure 5. 1M 10M 100M 1G ESD response to IEC 61000-4-2 (+15 kV air discharge) Figure 6. ESD response to IEC 61000-4-2 (-15 kV air discharge) 5V/Div 5V/Div C2 IN IN C2 C3 OUT OUT C3 Figure 7. 2V/Div 2V/Div Line capacitance versus applied voltage C(pF) 35 30 25 20 15 10 5 VR(V) 0 0 1 2 3 Doc ID 15673 Rev 2 4 5 3/10 Ordering information scheme 2 EMIF08-LCD04M16 Ordering information scheme Figure 8. Ordering information scheme EMIF EMI Filter Number of lines Information xxx = application zz = version Package Mxx = Micro QFN - xx leads 4/10 Doc ID 15673 Rev 2 yy - xxxzz Mxx EMIF08-LCD04M16 3 Package information Package information Epoxy meets UL94, V0 Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Table 3. Micro QFN 3.3x1.35 16L dimensions Dimensions TOP VIEW D Ref. INDEX AREA (D/2 x E/2) Millimeters Inches Min. Typ. Max. Typ. Max. A 0.45 0.50 0.55 0.018 0.020 0.022 A1 0.00 0.02 0.05 b 0.15 0.20 0.25 0.006 0.008 E Min. 0.00 0.0008 0.002 SIDE VIEW A1 A BOTTOM VIEW e INDEX AREA (D/2 x E/2) 1 b 8 EXPOSED PAD PIN # 1 ID E2 9 16 D2 L Figure 9. K Footprint 0.40 - - 0.13 0.010 D - 3.30 D2 2.65 2.80 E - 1.35 E2 0.25 0.40 e - 0.40 - - 0.016 - k 0.20 - - 0.008 - - L 0.15 0.25 2.90 0.104 0.110 - - 0.053 0.50 0.010 0.016 0.35 0.006 0.010 0.114 0.020 0.014 Figure 10. Marking 0.20 0.45 0.40 0.85 1.75 XX WW YP 2.80 Dot: Pin 1 XX: Marking WW: Assembly week Y: Assembly year P: Assembly plant 3.00 Note: Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Doc ID 15673 Rev 2 5/10 Recommendation on PCB assembly EMIF08-LCD04M16 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 11. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ----- 1.5 T LxW Aspect Area = ---------------------------- 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 m b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 12. Recommended stencil window position 4 m 4 m 14 m 422 m 450 m T=100 m 192 m 14 200 m m 2800 m 400 m 280 m 60 m Footprint 2000 m 60 m 400 m 6/10 400 m Doc ID 15673 Rev 2 Stencil window Footprint EMIF08-LCD04M16 4.2 4.3 4.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. "No clean" solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 m. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Doc ID 15673 Rev 2 7/10 Recommendation on PCB assembly 4.5 EMIF08-LCD04M16 Reflow profile Figure 13. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting Temperature (C) 260C max 255C 220C 180C 125 C 2C/s recommended 2C/s recommended 6C/s max 6C/s max 3C/s max 3C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 8/10 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 15673 Rev 2 EMIF08-LCD04M16 5 Ordering information Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF08-LCD04M16 JA(1) QFN 6.74 mg 3000 Tape and reel 1. The marking can be rotated by 90 to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision Changes 20-May-2009 1 Initial release. 10-Nov-2009 2 Updated Features on page 1. Added Figure 2 on page 2. Doc ID 15673 Rev 2 9/10 EMIF08-LCD04M16 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10 Doc ID 15673 Rev 2