K4M28163PD-R(B)G/S CMOS SDRAM 8Mx16 Mobile SDRAM 54CSP (VDD/VDDQ 1.8V/1.8V, TCSR & PASR & DS) Revision 1.3 December 2002 Rev. 1.3 Dec. 2002 K4M28163PD-R(B)G/S CMOS SDRAM 2M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION * 1.8V power supply. The K4M28163PD is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 * LVCMOS compatible with multiplexed address. bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control * Four banks operation. * MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). * EMRS cycle with address key programs. with the use of system clock, and I/O transactions are possible on every clock cycle. Range of operating frequencies, program- * All inputs are sampled at the positive going edge of the system high performance memory system applications. mable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and clock. * Burst read single-bit write operation. ORDERING INFORMATION Part No. * Special Function Support. Max Freq. K4M28163PD-R(B)G/S1L -. PASR (Partial Array Self Refresh). -. TCSR (Temperature Compensated Self Refresh) -. DS (Driver Strength) * DQM for masking. 105MHz(CL=3) Interface Package *1 LVCMOS K4M28163PD-R(B)G/S15 66MHz(CL=2/3)*2 54 CSP Pb (Pb Free) -R(B)G : Low Power, Operating Temp : -25 C ~ 85 C. -R(B)S : Super Low Power, Operating Temp : -25 C ~ 85C. * Auto refresh. Notes : 1. In case of 40MHz Frequency, CL1 can be supported. 2. In case of 33MHz Frequency, CL1 can be supported. * 64ms refresh period (4K cycle). * Extended Temperature Operation (-25C ~ 85 C). * 54balls CSP( -RXXX -Pb, -BXXX -Pb Free). FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter 2M x 16 2M x 16 2M x 16 DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 2M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE LDQM UDQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.3 Dec. 2002 K4M28163PD-R(B)G/S CMOS SDRAM Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > E1 54Ball(6x9) CSP 9 8 7 6 5 4 3 2 1 1 2 3 7 8 9 A V SS DQ15 VSSQ V DDQ DQ0 VD D B B DQ14 DQ13 V DDQ VSSQ DQ2 DQ1 C C DQ12 DQ11 VSSQ V DDQ DQ4 DQ3 D D DQ10 DQ9 V DDQ VSSQ DQ6 DQ5 D D1 e A E E DQ8 NC V SS VD D LDQM DQ7 F F UDQM CLK CKE CAS RAS WE G NC A11 A9 BA0 BA1 CS H A8 A7 A6 A0 A1 A10 J J V SS A5 A4 A3 A2 VD D D/2 G H E E/2 *2: Top View A Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A 11 Address BA0 ~ BA 1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable *1: Bottom View L(U)DQM Data Input/Output Mask < Top View*2 > DQ 0 ~ 15 Data Input/Output A1 Max. 0.20 Pin Name Encapsulant b z V DD /VSS Power Supply/Ground V DDQ /VSSQ Data Output Power/Ground #A1 Ball Origin Indicator SAMSUNG Week K4M28163PD-XXXX [Unit:mm] Symbol Min Typ Max A 0.90 0.95 1.00 A1 0.30 0.35 0.40 E - 8.10 - E1 - 6.40 - D - 9.30 - D1 - 6.40 - e - 0.80 - b 0.40 0.45 0.50 z - - 0.10 Rev. 1.3 Dec. 2002 K4M28163PD-R(B)G/S CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V I N, V OUT -1.0 ~ 2.6 V Voltage on VD D supply relative to Vss V DD , V DDQ -1.0 ~ 2.6 V TSTG -55 ~ +150 C Power dissipation PD 1 W Short circuit current I OS 50 mA Storage temperature Notes : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25C to 85 C) Parameter Symbol Min Typ Max Unit VD D 1.65 1.8 1.95 V V DDQ 1.65 1.8 1.95 V Input logic high voltage VI H 0.8 x V DDQ 1.8 V DDQ + 0.3 V 1 Input logic low voltage VIL -0.3 0 0.3 V 2 Output logic high voltage VO H VDDQ - 0.2 - - V IO H = -0.1mA Output logic low voltage V OL - - 0.2 V I OL = 0.1mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 2.2V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -1.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V V IN VDDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V V OUT V DDQ. CAPACITANCE (VDD = 1.8V, TA = 23C, f = 1MHz, V REF =0.9V 50 mV) Pin Symbol Min Max Unit CCLK 2.0 4.0 pF CIN 2.0 4.0 pF Address CADD 2.0 4.0 pF D Q0 ~ DQ15 COUT 3.5 6.0 pF Clock RAS, CAS, WE, CS, CKE, DQM Note Rev. 1.3 Dec. 2002 K4M28163PD-R(B)G/S CMOS SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85C) Parameter Symbol Operating Current (One Bank Active) Precharge Standby Current in power-down mode I CC1 Burst length = 1 tRC t R C(min) IO = 0 mA ICC2 P CKE V IL (max), tCC = 10ns Precharge Standby Current in non power-down mode I CC2NS Active Standby Current in non power-down mode (One Bank Active) -1L -15 35 30 0.3 IC C 2PS CKE & CLK V IL (max), tCC = ICC2 N Active Standby Current in power-down mode Version Test Condition ICC3 P I CC3NS Note mA 1 mA 0.3 CKE V IH (min), CS V IH (min), tCC = 10ns Input signals are changed one time during 20ns CKE V IH (min), CLK VIL (max), tCC = Input signals are stable 5.5 mA 1 CKE V IL (max), tCC = 10ns 1.5 IC C 3PS CKE & CLK V IL (max), tCC = ICC3 N Unit mA 1 CKE V IH (min), CS V IH (min), tCC = 10ns Input signals are changed one time during 20ns CKE V IH (min), CLK VIL (max), tCC = Input signals are stable 12 mA 6 mA Operating Current (Burst Mode) I CC4 IO = 0 mA Page burst 4Banks Activated tC C D = 2CLKs 50 40 mA 1 Refresh Current I CC5 tRC tR C(min) 85 75 mA 2 Max 45C Max 85C C 4 Banks 160 200 2 Banks 140 160 1 Bank 130 140 4 Banks 100 140 2 Banks 80 100 1 Bank 70 80 TCSR Range -R(B)G Self Refresh Current I CC6 CKE 0.2V -R(B)S 3 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4M28163PD-R(B)G** 4. K4M28163PD-R(B)S** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL =V DDQ /V SSQ). Rev. 1.3 Dec. 2002 K4M28163PD-R(B)G/S AC OPERATING TEST CONDITIONS CMOS SDRAM (V DD = 1.8V 0.15V, TA = -25C to 85C) Parameter Value Unit 0.9 x VDDQ / 0.2 V 0.5 x V DDQ V tr/tf = 1/1 ns Output timing measurement reference level 0.5 x V DDQ V Output load condition See Fig. 2 AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time 1.8V Vtt=0.5 x VDDQ 13.9K 50 V OH (DC) = VDDQ -0.2 , IO H = -0.1mA V OL (DC) = 0.2V, IOL = 0.1mA Output 10.6K Output Z0=50 30pF 30pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted .) Parameter Version Symbol -1L -15 Unit Note Row active to row active delay tR R D(min) 19 30 ns 1 RAS to CAS delay tR C D(min) 28.5 30 ns 1 tR P(min) 28.5 30 ns 1 tR A S(min) 60 60 ns 1 Row precharge time Row active time tRAS (max) 100 90 us Row cycle time tR C(min) ns 1 Last data in to row precharge tR D L(min) 2 90 CLK 2,3 Last data in to Active delay tDAL (min) tRDL + tRP - 3 Last data in to new col. address delay tC D L(min) 1 CLK 2 2 Last data in to burst stop tBDL (min) 1 CLK Auto refresh cycle time tARFC (min) 105 ns Exit self refresh to write command tSRFX (min) 120 ns tC C D(min) 1 CLK 4 ea 5 Col. address to col. address delay Number of valid output data CAS latency=3 2 CAS latency=2 1 CAS latency=1 0 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 1.3 Dec. 2002 K4M28163PD-R(B)G/S CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted.) Parameter -1L Symbol Min CAS latency=3 CLK cycle time CAS latency=2 tC C 15 tSAC CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 tO H CAS latency=1 Min Unit Note ns 1 ns 1,2 ns 2 Max 15 1000 25 CAS latency=3 CAS latency=2 Max 9.5 CAS latency=1 CLK to valid output delay - 15 15 1000 30 7 9 8 9 20 24 2.5 2.5 2.5 2.5 2.5 2.5 CLK high pulse width tC H 3.5 3.5 ns 3 CLK low pulse width tC L 3.5 3.5 ns 3 Input setup time tSS 3.0 4.0 ns 3 Input hold time tSH 1.5 2.0 ns 3 CLK to output in Low-Z tSLZ 1 1 ns 2 CAS latency=3 CLK to output in Hi-Z CAS latency=2 tSHZ CAS latency=1 7 9 8 9 20 24 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Note : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Rev. 1.3 Dec. 2002 K4M28163PD-R(B)G/S CMOS SDRAM SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X L H H H X X H H L BA0,1 L H H X X X Bank Active & Row Addr. H X L L H H X V Read & Column Address Auto Precharge Disable H X L H L H X V Write & Column Address Auto Precharge Disable H X L H L L X V H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H H X X X L V V V Auto Precharge Enable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Clock Suspend or Active Power Down L DQM H No Operation Command H H X X H X X X L H H H X A11, A9 ~ A 0 Note 1, 2 3 3 3 3 Row Address L Column Address (A 0 ~ A8) H L Precharge Power Down Mode Exit A10 /AP Column Address (A 0 ~ A8) H X V L X H 4 4, 5 4 4, 5 6 X X X X X X V X X X 7 (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Notes : 1. OP Code : Operand Code A 0 ~ A 11 & BA 0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode. 4. BA0 ~ BA1 : Bank select addresses. If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). Rev. 1.3 Dec. 2002