AN221D04-DEVLP - Anadigm, Inc.

DS030600-U002a - 1 -

AN221E02 Datasheet

Entry Level, Dynamically Reconfigurable

FPAA With Enhanced I/O

www.anadigm.com

DS030600-U002a - 2 -

Disclaimer

Anadigm reserves the right to make any changes without further notice to any products herein. Anadigm makes no

warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does

Anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims

any and all liability, including with out limitation consequential or incidental damages. "Typical" parameters can and

do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer

application by customer's technical experts. Anadigm does not in this document convey any license under its patent

rights nor the rights of others. Anadigm software and associated products cannot be used except strictly in

accordance with an Anadigm software license. The terms of the appropriate Anadigm software license shall prevail

over the above terms to the extent of any inconsistency.

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 3 -

PRODUCT AND ARCHITECTURE OVERVIEW

The AN221E02 device is a low-cost, entry-level version of the

Anadigmvortex FPAA. The device consists of a two fully

Configurable Analog Blocks (CABs), surrounded by a fabric of

programmable interconnect resources. Each device has two

configurable I/Os and two dedicated outputs – which allows for

maximum flexibility to the system designer.

These devices can be configured both in the static and in the

dynamic mode.

Using the on-chip LUT, these devices also accommodate

nonlinear functions such as sensor response linearization and

arbitrary waveform synthesis. In addition, the AN221E04 devices

allow designers to implement an integrated 8-bit analog-to-digital

converter on the FPAA, eliminating the potential need for an

external converter.

Packaged in a standard 44-pin TQFP package, these devices

maintain pin compatibility with the larger FPAA devices (i.e. the

AN221E04); allowing designers the ability to migrate up the

density curve

Figure 1: Architectural overview of the AN221E02 device

With dynamic reconfigurability, the functionality of the

AN221E02 can be reconfigured in-system by the designer or

on-the-fly by a microprocessor. A single AN221E02 can thus

be programmed to implement multiple analog functions

and/or to adapt on-the-fly to maintain precision operation

despite system degradation and aging.

PRODUCT FEATURES

• Two CABs, Two configurable I/O, two dedicated

outputs

• Static and Dynamic reconfiguration

• 256 Byte Look-Up Table (LUT) for linearization and

arbitrary signal generation

• 8-bit SAR analog–to–digital converter

• Fully differential architecture

o SNR Broadband 80dB

o SNR Narrowband (audio) 100dB

• Total Harmonic Distortion (THD): 80dB

• Fully differential I/O buffering with options for single ended

to differential conversion

• Low input offset through chopper stabilized amplifiers

o DC offset <100µV

• 4:1 Input multiplexer

• Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM

dependent)

• Package: 44-pin QFP (10x10x2mm)

o Lead pitch 0.8mm

• Supply voltage: 5V

ORDERING CODES

AN221E02-QFPSP Dynamically reconfigurable FPAA

Sample Pack

AN221E02-QFPTY Dynamically reconfigurable FPAA

Tray (96 pcs)

AN221E02-QFPTR Dynamically reconfigurable FPAA

Tape and Reel (1000 pcs)

AN221D04-EVAL Anadigmvortex Evaluation Kit

APPLICATIONS

• Intelligent sensor modules

• Tunable filters

• Programmable analog front-end to DSPs

• Self-calibrating systems

• Compensation for aging of system components

• Dynamic recalibration of remote systems

• Ultra-low frequency signal conditioning

• Custom analog signal processing

[For more detailed information on the features of the AN221E02 device,

please refer to the Anadigmvortex Silicon User Manual coming soon.]

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 4 -

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter Symbol Min Typ Max Unit Comment

DC Power Supplies AVDD(2)

BVDD

DVDD

-0.5 - 5.5 V V AVSS, BVSS, DVSS and SVSS all

held to 0.0 V a

xVDD to xVDD Offset -0.5 0.5 V Ideally all supplies should be at the

same voltage

Package Power Dissipation Pmax 25°C

Pmax 85°C --

1.8

0.73 WStill air, No heatsink, 4 layer board,

44 pins. θja = 55°C/W

Analog and Digital Input Voltage Vinmax Vss-0.5 - Vdd+0.5 V

Ambient Operating Temperature Top -40 - 85 °C

Storage Temperature Tstg -65 150 °C

aAbsolute Maximum DC Power Supply Rating - The failure mode is non-catastrophic for Vdd of up to 7 volts, but will cause reduced

operating life time. The additional stress caused by higher local electric fields within the CMOS circuitry may induce metal migration,

oxide leakage and other time/quality related issues.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit Comment

DC Power Supplies AVDD(2)

BVDD

DVDD

4.75 5.00 5.25 V AVSS, BVSS, DVSS and SVSS all

held to 0 V

Analog Input Voltage. Vina VMR-1.9 - VMR+1.9 V VMR is 2.0 volts above AVSS

Digital Input Voltage Vind 0 - DVDD V

Junction Temp Tj -40 - 125 °C Assume a package θja = 55°C/W b

bIn order to calculate the junction temperature you must first empirically determine the current draw (total Idd) for the design. Once the

current consumption established then the following formula can be used; Tj = Ta + Idd x Vdd x 55 °C/W, where Ta is the ambient

temperature. The worst case θja of 55 °C/W assumes no air flow and no additional heatsink of any type.

General Digital I/O Characteristics (Vdd = 5v +/- 10%, -40 to 85 deg.C)

Parameter Symbol Min Typ Max Unit Comment

Input Voltage Low Vih 0 - 30 - % of DVDD

Input Voltage High Vil 70 - 100 - % of DVDD

Output Voltage Low Vol 0 - 20 - % of DVDD

Output Voltage High Voh 80 - 100 - % of DVDD

Input Leakage Current Iil - - ±1.0 µA All pins except DCLK

Input Leakage Current Iil - ±12.0 - µA DCLK if a crystal is connected and

the on-chip oscillator is used

Max. Capacitive Load Cmax - - 10 pF The maximum load for a digital

output is 10 pF // 10 Kohm

Min. Resistive Load Rmin 10 - - Kohm The maximum load for a digital

output is 10 pF // 10 Kohm

DCLK Frequency Fmax - - 40 MHz For MODE = 1, Max DCLK is

16 MHz

ACLK Frequency Fmax - - 40 MHz Divide down to <8 MHz prior to use

as a CAB clock

Clock Duty Cycle - 45 - 55 % All clocks

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 5 -

Detailed Digital I/O Interface Characteristics: Vdd = 5.0volts

LCCb

Parameter Symbol Min Typ Max Unit Comment

Output Voltage Low Vol Vss - 150 mV Load 20pF//50Kohm to Vss

Output Voltage High Voh 4.5 - Vdd V Load 20pF//50Kohm to Vss

Max. Capacitive Load Cmax - - 20 pF Maximum load 20 pF // 50 Kohm

Min. Resistive Load Rmin 50 - - Kohm Maximum load 20 pF // 50 Kohm

Current Sink Isnkmax - - 15 mA LCCb pin shorted to Vdd

Current Source Isrcmax - - 4 mA LCCb pin shorted to Vss

CFGFLG, ACTIVATE

Parameter Symbol Min Typ Max Unit Comment

Input Voltage Low Vil 0 30 % % of DVDD

Input Voltage High Vih 70 100 % % of DVDD

Output Voltage Low Vol Vss - 85 mV Pin load =

Internal pullup + 20pF//50K to Vss

Output Voltage High Voh 4.5 - Vdd V Pin load =

Internal pullup + 20pF//50K to Vss

Output Voltage Low

Vol Vss - 200 mV

Pin Load =

External 5K ohm pullup +

20pF//50K to Vss

Output Voltage High

Voh 4.5 - Vdd V

Pin Load =

External 5Kohm pullup +

20pF//50K to Vss

Max. Capacitive Load Cmax - - 50 pF Maximum load 50 pF // 50 Kohm

Min. Resistive Load Rmin 50 - - Kohm Maximum load 50 pF // 50 Kohm

Current Sink Isnkmax - - 2.5 mA Pin shorted to Vdd

Current Source Isrcmax - - 200 µA Pin shorted to Vss

External Resistive Pullup Rpullupext 5 7.5 10 Kohm Use only if internal pullup is

deselected

ERRb

Parameter Symbol Min Typ Max Unit Comment

Input Voltage Low Vil 0 30 % % of DVDD

Input Voltage High Vih 70 100 % % of DVDD

Output Voltage Low Vol Vss - 50 mV

Output Voltage High Voh 4.9 - Vdd V

Max. Capacitive Load Cmax - - 50 pF Maximum load 50 pF // 50 Kohm

Min. Resistive Load Rmin 50 - - Kohm Maximum load 50 pF // 50 Kohm

Current Sink Isnkmax - - 10 mA

Current Source Isrcmax - - 0 µA

External Resistive Pullup Rpullupext 10 10 10 Kohm

DCLK,Mode,DIN,EXECUTE,PORb,CS1b,CS2b

Parameter Symbol Min Typ Max Unit Comment

Input Voltage Low Vil 0 - 30 % % of DVDD

Input Voltage High Vih 70 - 100 % % of DVDD

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 6 -

OUTCLK/SPIMEM,DOUTCLK

Parameter Symbol Min Typ Max Unit Comment

Output Voltage Low Vol 0 - 20 % % of DVDD

Output Voltage High Voh 80 - 100 % % of DVDD

Max. Capacitive Load Cmax - - 50 pF Maximum load 50 pF // 50 Kohm

Min. Resistive Load Rmin 10 - - Kohm Maximum load 50 pF // 50 Kohm

Current Sink Isnkmax - - 17 mA

Current Source Isrcmax - - 4 mA

ACLK/SPIP

Parameter Symbol Min Typ Max Unit Comment

Input Voltage Low Vil 0 - 30 % % of DVDD

Input Voltage High Vih 70 - 100 % % of DVDD

Output Voltage Low Vol 0 - 20 % % of DVDD

Output Voltage High Voh 80 - 100 % % of DVDD

Max. Capacitive Load Cmax - - 50 pF Maximum load 50 pF // 50 Kohm

Min. Resistive Load Rmin 10 - - Kohm Maximum load 50 pF // 50 Kohm

Current Sink Isnkmax - - 15 mA

Current Source Isrcmax - - 4 mA

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 7 -

Analog Inputs General

Parameter Symbol Min Typ Max Unit Comment

High Precision Input Range cVina 0.5 - 3.5 V VMR +/- 1.5v

Standard precision Input Range dVina 0.1 - 3.9 V VMR +/- 1.9v

High Precision

Differential Input c Vdiffina 0 - +/-3.0 V Common mode voltage = 2 V

Standard Precision

Differential Input d Vdiffina 0 - +/-3.8 V Common mode voltage = 2 V

Common Mode

Input Range Vcm 1.8 2.0 2.2 V

Input Offset Vos - 5 15 mV Non-chopper stabilized input

Input Frequency

Fain 0 <2 8 MHz

Max value is clock, CAM and input

stage dependant. Input frequency

is limited to approx <2MHz due to

CAM signal processing which is

based on sampled data

architectures.

c. High precision operating range provides optimal linearity and dynamic range.

d. Standard precision operating range provides maximum dynamic range and reduced linearity.

Input Differential Amplifier ON and Filter OFF

Parameter Symbol Min Typ Max Unit Comment

Input Range Vina

Vdiffina See analog input above Usable input range will be reduced

by the effective gain setting

Gain Setting Ginamp 16 - 128

Gain Accuracy - 1.0 2.5 %

Gain Drift (Temperature, Supply

Voltage zand Time) Dist - - 1.0 %

Equivalent Input Offset Voltage

Vos - 3 12 mV

Non-chopper stabilized input

When the input amplifier and filter

are used in combination Vos

contribution comes only from the

input amplifier

Offset Voltage Temperature

Coefficient Voffsettc - 1 10 µV/°C from -40°C to 125°C

Input Frequency cFain 0 - 2 MHz

Input Frequency dFain 0 <2 8 MHz

Power Supply Rejection Ratio PSRR 65 - - dB d.c. Amp Gain =16

a.c. See graphs page 18

Common Mode Rejection Ratio CMRR - 67 - dB

Large Signal Harmonic Distortion Dist - -65 - dB 0.4v p-p Differential input at 660Hz

Gain setting = 16

Input Resistance Rin 10 - Mohm

Input Capacitance Cin - 5.0 pF

Input Referred Noise Figure

NF - 0.1 - µV/sqrtHz

Input cell Gain = 16

Applies to audio frequency range

(400Hz to 30KHz).

See graphical data on page 18

Signal-to Noise Ratio and

Distortion SINAD - 75 - dB

Input signal = 285 mV p-p diff,

audio frequency range

See graphical data on page 18

Spurious Free Dynamic Range SFDR - 73 - dB Input signal = 100 mV p-p diff

See graphical data on page 18

c. High precision operating range provides optimal linearity and dynamic range.

d. Standard precision operating range provides maximum dynamic range and reduced linearity.

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 8 -

Input Differential Chopper Amplifier on and Filter OFF

Parameter Symbol Min Typ Max Unit Comment

Input Range Vina

Vdiffina See analog input above Usable input range will be reduced

by the effective gain setting

Gain Setting Ginamp 16 - 128

Gain Accuracy - 1.0 2.5 %

Gain Drift, (Temperature, Supply

Voltage and Time) --1.0 %

Chopper Frequency Clock Range

Fch Fc/260100 - >250 KHz

Fc = master clock frequency

Set Fch as slow as possible

Fch > 250KHz will result in some

signal attenuation

Equivalent Input Offset Voltage

Vos - <100 200 µV

Chopper stabilized amplifier

The maximum value of 200µV is

guaranteed by production test

This is a tester limitation

Offset Voltage Temperature

Coefficient Voffsettc - 0.5 2.0 µV/°C from -40°C to 125°C

Power Supply Rejection Ratio PSRR 65 - - dB d.c.

a.c. See graphs on page 18

Common Mode Rejection Ratio CMRR - 102 - dB

Large Signal Harmonic Distortion Dist - -40 - dB

0.4v p-p Differential input at

660Hz

Gain setting = 16

Input Frequency

Fain 0 Fch/20 Fch/2 KHz

Fch=Chopper clock frequency

The chopper frequency and

input frequency should be

chosen such that subsequent

low pass filtering can remove the

chopper stage frequency

elements

Input Resistance Rin 10 - Mohm Input to filter or chopper

Input Capacitance Cin - 5.0 pF

Input Referred Noise Figure

NF - 0.09 - µV/sqrtHz

Input cell Gain = 16

Applies to Audio frequency

range Chopper clock Fch =

250KHz

See graphical data on page 18

Signal-to Noise Ratio and

Distortion SINAD - 75 - dB

Input signal = 285 mV p-p

differential,

Audio frequency range

See graphical data on page 18

Spurious Free Dynamic Range

SFDR - 74 - dB

Input signal =100 mV p-p

differential

See graphical data on page 18

Input Differential Amplifier OFF and Filter ON

Parameter Symbol Min Typ Max Unit Comment

Input Range Vina

Vdiffina See analog input above

Equivalent Input Offset Vos - 8 32 mV Non-chopper stabilized input,

Filter corner frequency =470KHz

Offset Voltage Temperature

Coefficient Voffsettc - 0.05 I 1.0 II mV/°C

from -40°C to 125°C

I. measured at filter corner=470Khz

II. maximum at Filter corner=76KHz

Input Frequency

Fain - - - MHz

Input filter frequency will define the

maximum frequency

Input filter is recommended to be

>30x higher than the max input

frequency, for 80dB distortion

performance

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 9 -

Common Mode Rejection Ration CMRR - 60 - dB

Power Supply Rejection Ratio PSRR 68 - - dB d.c.

a.c. See graphical data on page 19

Large Signal Harmonic Distortion Dist - -82 - dB 4v p-p Differential input at 660Hz

Filter corner frequency 470KHz

Input Low Pass Filter (Anti-Alias)

Corner Frequency Settings Ffiltcorner 76 - 470 KHz

Input Resistance Rin 10 - - Mohm Input to filter or chopper

Input Capacitance Cin - 5.0 pF

Input Referred Noise Figure

NF - 0.17 - µV/sqrtHz

Input cell filter corner Fc = 470KHz

Applies to Audio frequency range

See graphical data on page 18

Signal-To Noise Ratio and

Distortion SINAD - 84 - dB

Input signal = 1400 mV p-p diff,

Audio frequency range

See graphical data on page 18

Spurious Free Dynamic Range SFDR - 90 - dB Input signal =1400 mV p-p differential

See graphical data on page 18

Input Differential Voltage Mode, Amplifier OFF, Filter OFF and Unity Gain Stage ON

Parameter Symbol Min Typ Max Unit Comment

Input Range Vina

Vdiffina See analog input above V

Equivalent Input Offset Vos - 5 15 mV Non-chopper stabilized input

Offset Voltage Temperature

Coefficient Voffsettc - 20 50 µV/°C from -40°C to 125°C

Input Frequency Fain - - 1.0 MHz Gain Bandwidth limited by input

impedance

Power Supply Rejection Ratio PSRR 60 - - dB d.c.

a.c. See graphs on page 18

Common Mode Rejection Ratio CMRR - 60 - dB

Large Signal Harmonic Distortion Dist - -80 - dB 4v p-p Differential input at 660Hz

Large Signal Harmonic Distortion Dist - -80 - dB 3v p-p single ended signal at 660Hz

Input Resistance Rin - 126 - Kohm Input to unity gain stage

Input Capacitance Cin - 2.0 5.0 pF

Input Referred Noise Figure NF - 0.16 - µV/sqrtHz Applies to Audio frequency range

See graphical data on page 18

Signal-To Noise Ratio and

Distortion SINAD - 84 - dB

Input signal = 1400 mV p-p diff,

Audio frequency range

See graphical data on page 18

Spurious Free Dynamic Range SFDR - 90 - dB Input signal =1400 mV p-p differential

See graphical data on page 18

Input Differential Voltage Mode, Amplifier OFF, Filter OFF and Unity Gain Stage OFF

Parameter Symbol Min Typ Max Unit Comment

Input Range Vina

Vdiffina See analog input above V

Equivalent Input Offset Vos N/A N/A N/A mV See CAM Op Amp

Offset Voltage Temperature

Coefficient Voffsettc N/A N/A N/A µV/°C See CAM Op Amp.

from -40°C to 125°C

Input Frequency Fain - - 8 MHz Dependant upon CAM

Power Supply Rejection Ratio PSRR N/A N/A N/A dB See CAM Op Amp

Large Signal Harmonic Distortion Dist - -85 - dB See CAM Op Amp

Input Resistance

Rin - - - Mohm

Input to CAM directly (Input cell

bypass mode). This variable is

influenced by CAB capacitor size,

CAB clock frequency and CAB

architecture

Input Capacitance

Cin - - - pF

Input to CAM directly (Input cell

bypass mode)

This variable is influenced by CAB

capacitor size, CAB clock frequency

and CAB architecture

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 10 -

Analog Outputs

(See “Output Cell” section in the AN120E04/AN220E04 user manual for more details)

Parameter Symbol Min Typ Max Unit Comment

High Precision Output Range cVouta 0.5 - 3.5 V VMR +/- 1.5v

Standard Precision Output

Range dVouta 0.1 - 3.9 V VMR +/- 1.9v

High Precision

Differential Output c Vdiffouta - - +/-3.0 V Common mode voltage = 2 V

Standard precision

Differential Output d Vdiffouta - - +/-3.8 V Common mode voltage = 2 V

Common Mode

Voltage Vcm 1.9 2.0 2.1 V

c. High precision operating range provides optimal linearity and dynamic range.

d. Standard precision operating range provides maximum dynamic range and reduced linearity.

Output Voltage Mode and Filter ON, Corner Frequency 470KHz

Parameter Symbol Min Typ Max Unit Comment

Input Range Vina

Vdiffina See analog input above V

Equivalent Input Offset Vos - 5 15 mV

Offset Voltage Temperature

Coefficient Voffsettc 0.05 I 1.0 II mV/°C

from -40°C to 125°C

I measured at filter corner: 470Khz

II maximum at filter corner: 76KHz

Output Frequency

Faout - - - MHz

Output filter frequency will define

the maximum frequency

Input filter is recommended to be

>30x higher then the max input

frequency, for good distortion

performance

Power Supply Rejection Ratio PSRR 60 - - dB d.c.

a.c. See graphical data on page 19

Large Signal Harmonic Distortion Dist - -82 - dB 4v p-p Differential input at 660Hz

Filter corner frequency 470KHz

Input Low Pass Filter (Anti-Alias)

Corner Frequency Settings Ffiltcorner 76 - 470 KHz

Output Load c e Rload 0.1 - - Mohm

Output Load c e Cload - - 50 pF

Output Load d e

Rload 1 10 - Kohm

Additional loading causes internal

voltage drops across output stage

and series resistances

The output stage has a small

signal output impedance of approx

10ohm

Output Load d e Cload - - 100 pF

Common Mode Rejection Ratio CMRR - 56 - dB

Input Referred Noise Figure

NF - 0.22 - µV/sqrtHz

Output filter corner fc = 470KHz

Applies to Audio frequency range

See graphical data on page 18

Signal-To Noise Ratio and

Distortion SINAD - 82 - dB

Input signal = 1400 mV p-p diff,

Audio frequency range

See graphical data on page 18

Spurious Free Dynamic Range SFDR - 90 - dB Input signal =1400 mV p-p diff

See graphical data on page 18

c. High precision operating range provides optimal linearity and dynamic range.

d. Standard precision operating range provides maximum dynamic range and reduced linearity.

e. The maximum load for an analog output is 50 pF // 100 Kohms. This load maybe with respect to analog ground VMR or AVSS.

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 11 -

Output Voltage Mode and Filter Off (Bypass Mode)

Parameter Symbol Min Typ Max Unit Comment

Input Range Vina

Vdiffina See analog input above V

Equivalent Input Offset Vos N/A N/A N/A mV See CAM Op Amp

Offset Voltage Temperature

Coefficient Voffsettc N/A N/A N/A mV/°C See CAM Op Amp

Output Frequency c e Faout - - 4 MHz

Output Frequency d f

Faout - - 8 MHz

The realizable output frequency is

limited to approx <2MHz due to

CAM signal processing which is

based on sampled data

architectures.

Power Supply Rejection Ratio PSRR N/A N/A N/A dB See CAM Op Amp

Large Signal Harmonic Distortion Dist - -85 - dB

Output Load Rload N/A N/A N/A Mohm See CAM Op Amp

Output Load Cload N/A N/A N/A pF See CAM Op Amp

c. High precision operating range provides optimal linearity and dynamic range.

d. Standard precision operating range provides maximum dynamic range and reduced linearity.

e. The maximum load for an analog output is 50 pF // 100 Kohms. This load maybe with respect to analog ground VMR or AVSS.

f. The maximum load for an analog output is 100 pF // 100 Kohms. This load must be differential and with respect to analog ground(VMR).

VMR (Voltage Mid Rail) and VREF (Reference Voltage) Ratings

Parameter Symbol Min Typ Max Unit Comment

VMR Output Voltage Vvmr 1.925 2.01 2.075 V At 25°C, Vdd=5.00 volts

VREF+ Output Voltage Vref+ 3.4 3.51 3.6 V At 25°C, Vdd=5.00 volts

VREF- Output Voltage Vref- 0.45 0.505 0.55 V At 25°C, Vdd=5.00 volts

Output Voltage Deviation

VREF+, VMR, VREF- Vrefout - 0.5 1 % Over process and supply voltage

corners

Voltage Temperature

Coefficient

VREF+, VMR, VREF-

Vreftc - - - - See typical graphical data below

-40°C to 125°C f

Power Supply Rejection Ratio,

VMR PSSR 60 - - dB

Power Supply Rejection Ratio

Vref+ and Vref- PSSR 75 - - dB

Start Up Time Tstart - - 1 ms Assuming recommended

capacitors

V+ref vs temperature

3.490

3.495

3.500

3.505

3.510

-50 0 50 100 150

Tchip (C)

Volts

VMR vs temperature

1.990

1.995

2.000

2.005

2.010

-50 0 50 100 150

Tchip (C)

Volts

Vref- vs temperature

0.490

0.495

0.500

0.505

0.510

-50 0 50 100 150

Tchip (C)

Volts

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 12 -

CAB (Configurable Analog Block) Differential Operational Amplifier

Parameter Symbol Min Typ Max Unit Comment

High Precision Input/Output

Range cVinouta 0.5 - 3.5 V VMR +/- 1.5v

Standard Precision Input/Output

Range dVinouta 0.1 - 3.9 V VMR +/-1.9v

High Precision.

Differential Input/Output c Vdiffioa - - +/-3.0 V Common mode voltage = 2 V

Standard Precision

Differential Input/Output d Vdiffioa - - +/-3.8 V Common mode voltage = 2 V

Common Mode Input Voltage

Range d Vcm 0 2.0 4 V

Common Mode Output Voltage

Range Vcm 1.9 2.0 2.1 V

Equivalent Input Voltage Offset. Voffset 0.1 5 15 mV

Some CAMs (Configurable

Analog Modules) can inherently

compensate

Offset Voltage Temperature

Coefficient Voffsettc - 1 10 µV/°C

from -40°C to 125°C some

CAMs (Configurable Analog

Modules) can inherently

compensate

Power Supply Rejection Ratio PSSR - 80 - dB

Variation between CAMs is

expected because of variations

in architecture

Common Mode Rejection Ratio

CMRR - 77 - dB

Example 1 GainInv CAM

CAM clock = 1MHz

CAM parameter settings

Gain = 1

Common Mode Rejection Ratio

CMRR - 60 - dB

Example 2 Filterbiquad

Setting = Low pass filter

CAM clock = 1MHz

CAM parameter settings

Gain = 1,

Corner frequency = 50KHz

Quality Factor = 0.707

Differential Slew Rate, Internal Slew - 50 - V/µsec Applicable when the OpAmp

load is internal to the FPAA

Differential Slew Rate, External Slew - 10 - V/µsec

Applicable when the OpAmp

driving signal out of the FPAA

package

Unity Gain Bandwidth,

Full Power Mode. UGB - 50 - MHz

Applicable when sourcing and

loading the OpAmp with a load

internal to the FPAA

Input Impedance, Internal Rin 10 - - Mohm

Output Impedance, Internal Rout - - - Ohms

The OpAmp output is designed

to drive all internal nodes, these

are dominantly capacitive loads

Output Impedance, External Rout - - - Ohms

Output to an FPAA output pin

(ouput cell bypass mode). This

variable is influenced by CAB

capacitor size, CAB clock

frequency and CAB architecture

Output Load, External c e Rload 0.1 - - Mohm

Output Load, External c e Cload - - 50 pF

Output Load, External d e f

Rload 1 10 - Kohm

Additional loading causes

internal voltage drops across

output stage and series

resistances

The output stage has a small

signal output impedance of

approx 10ohm

Output Load, External d e f Cload - - 50 pF

Noise Figure g

Noise - 0.13 - µV/sqrtHz

Example1 GainInv CAM

CAM clock = 1MHz

Gain = 1

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 13 -

Signal-To Noise Ratio and

Distortion g

SINAD - 80 - dB

Input signal=1400 mV p-p

differential

Audio frequency range

Example. GainInv CAM

CAM clock = 1MHz

Gain = 1

Spurious Free Dynamic Range g

SFDR - 92 - dB

Input signal=1400 mV p-p

differential,

Audio frequency range

Example. GainInv CAM

CAM clock = 1MHz

Gain = 1

c. High precision operating range provides optimal linearity and dynamic range.

d. Standard precision operating range provides maximum dynamic range and reduced linearity.

e. The maximum load for an analog output is 50 pF || 100 Kohms. This load may be with respect to analog ground VMR or AVSS.

f. Using the FPAA with CAB Op Amp’s driving directly off-chip, requires care, full characterization of the performance of each application

circuit by the circuit designer is necessary.

g. This specification parameter can only be characterized when a circuit topology is configured onto the CAB differential amplifier architecture.

The figure provided here is an representative on the performance of one specific CAM, as specified in the comments.

The idealized open loop gain plot is provided for

information only. This information is associated with the

FPAA in full power mode of operation. The FPAA

operation amplifier open loop gain cannot be observed

nor used when associated with external connections to

the device. Internal reprogrammable routing impedances

and switched capacitor circuit architecture using this

operational amplifier limit the effective usable bandwidth

of a circuit realized in the FPAA to less than 2MHz.

Idealized CAB Op Amp, Open Loop Gain [dB]

-20

-10

0.1 10 1000 100000

Frequency (KHz)

Open Loop Gain (dB)

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 14 -

CAB (Configurable Analog Block) Differential Comparator

Parameter Symbol Min Typ Max Unit Comment

Input Range, Internal Vina 0.1 - 3.9 V

Input Range, External Vina 0.0 - Vdd V

Differential Input, Internal Vdiffina - - +/-3.8 V Common mode voltage = 2 V

Differential Input, External Vdiffina +/- 0.0 - +/- Vdd V

Common Mode Output Voltage

Range, Internal cVcm 1.9 2.0 2.1 V

Common Mode Input Voltage

Range, External c Vcm 0 2.0 4 V

Common Mode Input Voltage,

External d Vcm 0 - 5 V The comparator will function

correctly

Differential Output Voutdiff - - +/-5 V

Single Pin Output (Ox1P) Vout 0 - 5 V

Input Voltage Offset Voffcomp - 2 10 mV Zero hysterisis

Offset Voltage Temperature

Coefficient Voffsettc - 1 10 µV/°C from -40°C to 125°C,

Zero Hysterisis

Setup Time, Internal Tsetint - - 125 nsec

Setup Time, External Tsetext - - 500 nsec

Delay Time Tdelay _Td+25 - 1_Td+25 nsec Td = 1/Fc

Fc = master clock frequency

Output Load

Rload 10 - - Kohm

Applies if comparator drive off

chip with output cell in bypass

mode

Output Load

Cload - - 50 pF

Applies if comparator drive off

chip with output cell in bypass

mode

Differential Variable Reference

Voltage Settings CompVref 0 - +/-4.0 V

Differential Hysteresis Hysta1 - Voffcomp - mV Hysteresis setting = zero

Differential Hysteresis Hysta2 - 20 - mV Hysteresis setting = 10mV

Differential Hysteresis Hysta3 - 40 - mV Hysteresis setting = 20mV

Differential Hysteresis Hysta4 - 80 - mV Hysteresis setting = 40mV

Hysteresis Setting Accuracy Hystb - 25 - %

Hysteresis Temperature

Coefficient Hysttc1 - 5 - µV/°C Hysteresis setting = zero

Hysteresis Temperature

Coefficient Hysttc2 - 50 - µV/°C Hysteresis setting = 10mV

Hysteresis Temperature

Coefficient Hysttc3 - 100 - µV/°C Hysteresis setting = 20mV

Hysteresis Temperature

Coefficient Hysttc4 - 200 - µV/°C Hysteresis setting = 40mV

c. High precision operating range provides optimal linearity and dynamic range.

d. Standard precision operating range provides maximum dynamic range and reduced linearity.

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 15 -

ESD Characteristics

Pin Type Human

Body

Model

Machine

Model

Charged

Device

Model

Digital Inputs 4000V 250V 4kV

Digital Outputs 4000V 250V 4kV

Digital Bidirectional 4000V 250V 4kV

Digital Open Drain 4000V 250V 4kV

Analog Inputs 2000V 200V 4kV

Analog Outputs 1500V 100V 4kV

Reference Voltages 1500V 100V 4kV

The AN221E02 is an ESD (electrostatic discharge)

sensitive device. Electrostatic charges as high as 4000V

readily accumulate on the human body and test equipment

and can discharge without detection. Although the

AN221E02 device features proprietary ESD protection

circuitry, permanent damage may occur on devices

subjected to high-energy electrostatic discharges.

Therefore, proper ESD precautions are recommended to

avoid performance degradation or loss of functionality.

Power Consumption – Low Power Mode

Parameter Symbol Min Typ Max Unit Comment

Minimum Power 1a Idd - 0.2 - mA Vdd=5.00 volts, Tj=25°C

Low Power Nominal 50%

Power1b Idd - 25 30 mA Vdd=5.00 volts, Tj=25°C

Low Power Maximum Power1c Idd - 42 47 mA Vdd=5.00 volts, Tj=25°C

Temperature Coefficient - - -2 -10 µA/°C

1a. External clock, all analog function disabled, memory active.

1b FPAA active elements – Two core op-amps (low power mode), one comparator, one input (bypass mode), one output filter and

differential to single-ended converter (low power mode).

1c. FPAA active elements – Four core op-amps (low power mode), two comparators (one using SAR), two inputs (bypass mode), two output

filters and two differential to single-ended converters (low power mode).

Power Consumption – Full Power Mode

Parameter Symbol Min Typ Max Unit Comment

Full Power Mode Minimum Power 2a Idd - 1.5 - mA Vdd=5.00 volts, Tj=25°C

Full Power Mode Nominal 50% Power2b Idd - 80 90 mA Vdd=5.00 volts, Tj=25°C

Full Power Mode Maximum Power2c Idd - 150 160 mA Vdd=5.00 volts, Tj=25°C

2a. AN220E04 Crystal Oscillator, all analog functions disabled, memory active.

2b. FPAA active elements – Two core op-amps, one comparator, one input filter and chopper amplifier, one output filter and differential to

single-ended converter.

2c. FPAA active elements – Four core op-amps, two comparators (one using SAR), two Input filters and two chopper amplifiers, two output

filters and two differential to single-ended converters.

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 16 -

PINOUT

Numb

Name

Type Comments

1 I2PA Analog IN+

2 I2NA Analog IN-

3 O1P Analog OUT+

4 O1N Analog OUT-

5 AVSS Analog Vss

6 AVDD Analog Vdd

7 O2P Analog OUT

8 O2N Analog OUT

9 I1P Analog IN+

10 I1N Analog IN-

11 NC Not Connected

12 NC Not Connected

13 SHIELD Analog Vdd Low noise Vdd bias for capacitor array n-wells

14 AVDD2 Analog Vdd Analog power

15 VREFMC Vref Attach filter capacitor for VREF-

16 VREFPC Vref Attach filter capacitor for VREF+

17 VMRC Vref Attach filter capacitor for VMR (Voltage Main Reference)

18 BVDD Analog Vdd Analog power for bandgap Vref Generators

19 BVSS Analog Vss Analog ground for bandgap Vref Generators

Digital IN In multi-device systems...

0, Ignore incoming data (unless currently addressed)

1, Pay attention to incoming data (watching for address)

20 CFGFLGb

Digital OUT 0, Device is being configured

Z, Device is not being configured (if internal pullup is selected)

21 CS2b Digital IN 0, Chip is selected

1, Chip is not selected

Digital IN

(during config)

0, Allow configuration to proceed

1, Hold off configuration

22 CS1b

Digital IN

(after config)_

Passes read-back data through to LCC_B pin

23 DCLK Digital IN

24 SVSS Digital Vss Digital ground - substrate tie

25 MODE Digital IN 0, Synchronous serial interface

1, SPI EPROM Interface

Digital IN MODE = 0, analog clock < 40 MHz26 ACLK / SPIP

Digital OUT MODE = 1, SPI EPROM or serial EPROM clock

Digital OUT During power-up, sources SPI EPROM initialization command string27 OUTCLK /

SPIMEM Digital OUT After power-up, sources any of the four internal analog clocks

28 DVDD Digital Vdd

29 DVSS Digital Vss

30 DIN Digital IN Serial configuration data input

31 LCCb Digital OUT 1, Local configuration is needed. Once configuration is completed, it is a registered version of

CS1b or if the device is addressed for read, it serves as serial data out port

Digital IN

(monitored OUT)

0, Initiate reset

1, No action

32 ERRb

Digital OUT 0, Error condition

Z, No error condition (external pullup required)

33 ACTIVATE Digital IN 0, Hold off completion of configuration

Rising Edge, Allow completion of configuration

O.D. Output 0, device has not yet completed primary configuration

Z, Device has completed primary configuration (if internal pullup is selected)

Digital OUT A buffered version of DCLK.34 DOUTCLK /

TEST Digital IN (Factory reserved test input. Float if unused)

35 PORb Digital IN 0, Chip held in reset state

Rising edge, re-initiates power on reset sequence

To initiate a POR reset cycle, the minimum pulse width required on the PORb pin is 25ns.

36 EXECUTE Digital IN 0, No action

1, Transfer shadow RAM into configuration RAM

37 NC Not Connected

38 NC Not Connected

39 I2PD Analog IN+

40 I2ND Analog IN-

41 I2PC Analog IN+

42 I2NC Analog IN-

43 I2PB Analog IN+

44 I2NB Analog IN-

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 17 -

MECHANICAL AND HANDLING

The AN221E02 comes in the industry standard 44 lead QFP package.

Dry pack handling is recommended. The package is qualified to MSL3 (JEDEC Standard, J-STD-020A, Level 3). Once the device is

removed from dry pack, 30°C at 60% humidity for not longer than 168 hours is the maximum recommended exposure prior to solder

reflow. If out of dry pack for longer than this recommended period of time, then the recommended bake out procedure prior to solder

reflow is 24 hours at 125°C.

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 18 -

Distortion, SINAD and SNR Measurements

The following plots give an indication of the Distortion, SINAD and SNR for some representative CAMs.

INPUT CELL UGB SNR, DSTN, SINAD

-100

-80

-60

-40

-20

100

120

0.7 1.4 2.8 5.6 7.0

INPUT [Vp-p]

[dB]

SNR[dB]

SINAD[dB]

DISTN[dB]

INPUT CELL LOW PASS FILTER SNR, DSTN,

SINAD

-100

-80

-60

-40

-20

100

120

0.7 1.4 2.8 5.6 7.0

INPUT [Vp-p]

[dB]

SNR[dB]

SINAD[dB]

DISTN[dB]

INPUT CELL AMPLIFIER SNR,DSTN,SINAD

Measured with Inputcell Gain G = 16

Same results for Input Amplifier and

Chopper Amplifier stage, If the signal

from the chopper Amplifier is correctly

filtered before measurement.

-100.00

-80.00

-60.00

-40.00

-20.00

0.00

20.00

40.00

60.00

80.00

100.00

0.08 0.14 0.21 0.28 0.35 0.42 0.49

INPUT [Vp-p]

[dB]

SNR[dB]

SINAD[dB]

DISTN[dB]

Output Cell SNR, DSTN, SINAD

-100

-80

-60

-40

-20

100

120

0.7 1.4 2.8 3.5 5.6 7.0

INPUT [Vp-p]

[dB]

SNR[dB]

SINAD[dB]

DISTN[dB]

GAININV CAM SNR, DSTN, SINAD

This graph shows the typical performance

of an FPAA CAB when configured with a

CAM in this example GainInv CAM

Input signal=1400 mV p-p differential,

CAM clock = 1MHz CAM parameter settings Gain = 1

-120

-100

-80

-60

-40

-20

100

0.7 1.4 2.8 3.5 5.6 7.0

INPUT [Vp-p]

[dB]

SNR[dB]

SINAD[dB]

DISTN[dB]

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 19 -

Power Supply Rejection Ratio (PSRR) Measurements

The following plots give an indication of the PSRR for some representative CAMs.

AVDD to Power Supply (PS): 5v +/- 0.25v sinusoidal waveform (100 kHz to 1 MHz)

INPUT AMP PSRR [dB]

20.00

30.00

40.00

50.00

60.00

70.00

80.00

DC 100 1KHz 10KHz 100KHz 1MHz

INPUT LPF PSRR [dB]

20.00

30.00

40.00

50.00

60.00

70.00

80.00

DC 15 50 100 1KHz 10KHz100KHz1MHz

VMR, Vref+, Vref- PSRR [dB]

20.00

30.00

40.00

50.00

60.00

70.00

80.00

90.00

100.00

DC 100 1KHz 10KHz 100KHz 1MHz

PSRR_VMR [dB]

PSRR_VREFP [dB]

OUTPUT Voltage Mode + LPF PSRR [dB]

20.00

30.00

40.00

50.00

60.00

70.00

80.00

DC 100 1KHz 10KHz 100KHz 1MHz

GAININV_1MHz PSRR [dB]

100

DC 50 100 1KHz 10KHz 100KHz 1MHz

GAININV_4MHz PSRR [dB]

100

100 1KHz 10KHz 100KHz 1MHz

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 20 -

The following is provided for information only, as and when additional characterization data is collected ‘noise measurements’

will be added formally to the datasheet.

Noise and Distortion Observations

The following plots give an indication of the noise characteristics of Anadigm®’s AN221E02 FPAA device.

These were done using a simple set-up and in many cases reflect the noise limit of the setup. Actual device noise margins are

expected to be better.

Signal and Noise for the Input Cell (input signal - 50mVp-p differential to the FPAA at 10 kHz)

Signal and Noise for the Output Cell (with a differential input 4V p-p, 660Hz)

Input gain stage set at X16

Input anti-aliasing filter set off

Input chopper amplifier set off

nal to Noise: -92 dB

at 376KHz

3Hz BW

: -1

KHz

Hz BW

Voltage output mode (including filter) ON

Output smoothing filter set at fC = 470 kHz

AN221E02 Datasheet – Entry Level, Dynamically Reconfigurable FPAA With Enhanced I/O

DS030600-U002a - 21 -

Measured THD for input and output cells (with a differential input 4V p-p, 660Hz)

Settings Distortion in dB

Input cell with anti-aliasing filter set at fC = 470 kHz 81.6

Output cell with differential to single ended converter and output smoothing filter set at fC = 470 kHz 82

Signal and Noise for a representative CAM – Gaininv CAM (input signal of 700mV p-p differential at 10 kHz)

nal to Noise: 108 dB, at 528 kHz, 3Hz BW

s above, zoom to lower fre

uenc

THD for a representative CAM –

Gaininv CAM (with a differential

input 4V p-p, 660Hz)

CAM Clock

Frequency

Distortion

(dB)

250 KHz 80.00

1 MHz 72.83

2 MHz 69.22

4 MHz 73.48